1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
|
/*
* Copyright (C) 2012 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_IRQFLAGS_H
#define __ASM_IRQFLAGS_H
#ifdef __KERNEL__
#include <asm/ptrace.h>
#ifndef CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS
#include <linux/irqchip/arm-gic-v3.h>
/*
* CPU interrupt mask handling.
*/
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
unsigned long pmr = 0xef;
asm volatile(
"mrs %0, daif // arch_local_irq_save\n"
"msr daifset, #2\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%1\n"
"dsb sy"
: "=r" (flags)
: "r" (pmr)
: "memory");
return flags;
}
static inline void arch_local_irq_enable(void)
{
unsigned long pmr = 0xf0;
asm volatile(
"msr daifclr, #2 // arch_local_irq_enable\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%0\n"
"dsb sy"
:
: "r" (pmr)
: "memory");
}
static inline void arch_local_irq_disable(void)
{
unsigned long pmr = 0xef;
asm volatile(
"msr daifset, #2 // arch_local_irq_disable\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%0\n"
"dsb sy"
:
: "r" (pmr)
: "memory");
}
/*
* Save the current interrupt enable state.
*/
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile(
"mrs %0, daif // arch_local_save_flags"
: "=r" (flags)
:
: "memory");
return flags;
}
/*
* restore saved IRQ state
*/
static inline void arch_local_irq_restore(unsigned long flags)
{
unsigned long pmr = 0xf0;
asm volatile(
"msr daif, %0 // arch_local_irq_restore\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%1\n"
"dsb sy"
:
: "r" (flags), "r" (pmr)
: "memory");
}
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
return flags & PSR_I_BIT;
}
#else /* CONFIG_IRQFLAGS_GIC_MASKING */
#include <linux/irqchip/arm-gic-v3.h>
/*
* CPU interrupt mask handling.
*/
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags, masked = ICC_PMR_EL1_MASKED;
asm volatile(
"// arch_local_irq_save\n"
"mrs_s %0, " __stringify(ICC_PMR_EL1) "\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%1\n"
//"dsb sy\n"
: "=&r" (flags)
: "r" (masked)
: "memory");
return flags;
}
static inline void arch_local_irq_enable(void)
{
unsigned long unmasked = ICC_PMR_EL1_UNMASKED;
asm volatile(
"// arch_local_irq_enable\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%0\n"
"dsb sy\n"
:
: "r" (unmasked)
: "memory");
}
static inline void arch_local_irq_disable(void)
{
unsigned long masked = ICC_PMR_EL1_MASKED;
asm volatile(
"// arch_local_irq_disable\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%0\n"
//"dsb sy\n"
:
: "r" (masked)
: "memory");
}
/*
* Save the current interrupt enable state.
*/
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile(
"// arch_local_save_flags\n"
"mrs_s %0, " __stringify(ICC_PMR_EL1) "\n"
: "=r" (flags)
:
: "memory");
return flags;
}
/*
* restore saved IRQ state
*/
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile(
"// arch_local_irq_restore\n"
"msr_s " __stringify(ICC_PMR_EL1) ",%0\n"
"dsb sy\n"
:
: "r" (flags)
: "memory");
}
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
return !(flags & ICC_PMR_EL1_G_BIT);
}
#endif /* CONFIG_IRQFLAGS_GIC_MASKING */
#define local_fiq_enable() asm("msr daifclr, #1" : : : "memory")
#define local_fiq_disable() asm("msr daifset, #1" : : : "memory")
#define local_async_enable() asm("msr daifclr, #4" : : : "memory")
#define local_async_disable() asm("msr daifset, #4" : : : "memory")
/*
* save and restore debug state
*/
#define local_dbg_save(flags) \
do { \
typecheck(unsigned long, flags); \
asm volatile( \
"mrs %0, daif // local_dbg_save\n" \
"msr daifset, #8" \
: "=r" (flags) : : "memory"); \
} while (0)
#define local_dbg_restore(flags) \
do { \
typecheck(unsigned long, flags); \
asm volatile( \
"msr daif, %0 // local_dbg_restore\n" \
: : "r" (flags) : "memory"); \
} while (0)
#define local_dbg_enable() asm("msr daifclr, #8" : : : "memory")
#define local_dbg_disable() asm("msr daifset, #8" : : : "memory")
#endif
#endif
|
