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path: root/arch/arm/kernel/perf_event_cpu.c
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/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */
#define pr_fmt(fmt) "CPU PMU: " fmt

#include <linux/bitmap.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/irqdesc.h>

#include <asm/cputype.h>
#include <asm/irq_regs.h>
#include <asm/pmu.h>

/* Set at runtime when we know what CPU type we are. */
static struct arm_pmu *cpu_pmu;

/*
 * Despite the names, these two functions are CPU-specific and are used
 * by the OProfile/perf code.
 */
const char *perf_pmu_name(void)
{
	if (!cpu_pmu)
		return NULL;

	return cpu_pmu->name;
}
EXPORT_SYMBOL_GPL(perf_pmu_name);

int perf_num_counters(void)
{
	int max_events = 0;

	if (cpu_pmu != NULL)
		max_events = cpu_pmu->num_events;

	return max_events;
}
EXPORT_SYMBOL_GPL(perf_num_counters);

#ifdef CONFIG_SMP
/*
 * Workaround logic that is distributed to all cores if the PMU has only
 * a single IRQ and the CPU receiving that IRQ cannot handle it. Its
 * job is to try to service the interrupt on the current CPU. It will
 * also enable the IRQ again if all the other CPUs have already tried to
 * service it.
 */
static void cpu_pmu_do_percpu_work(struct irq_work *w)
{
	struct pmu_hw_events *hw_events =
	    container_of(w, struct pmu_hw_events, work);
	struct arm_pmu *cpu_pmu = hw_events->percpu_pmu;

	/* Ignore the return code, we can do nothing useful with it */
	cpu_pmu->handle_irq(0, cpu_pmu);

	if (atomic_dec_and_test(&cpu_pmu->remaining_irq_work))
		enable_irq(cpu_pmu->muxed_spi_workaround_irq);
}

/*
 * Issue work to the other CPUs. Must be called whilst we own the
 * hotplug locks.
 */
static void cpu_pmu_queue_percpu_work(struct arm_pmu *cpu_pmu)
{
	int cpu;

	atomic_add(num_online_cpus() - 1, &cpu_pmu->remaining_irq_work);

	for_each_online_cpu(cpu) {
		struct pmu_hw_events *hw_events =
		    per_cpu_ptr(cpu_pmu->hw_events, cpu);

		if (cpu == smp_processor_id())
			continue;

		/*
		 * We assume that the IPI within irq_work_queue_on()
		 * implies a full memory barrier making the value of
		 * cpu_pmu->remaining_irq_work visible to the target.
		 */
		if (!irq_work_queue_on(&hw_events->work, cpu))
			if (atomic_dec_and_test(&cpu_pmu->remaining_irq_work))
				enable_irq(cpu_pmu->muxed_spi_workaround_irq);
	}
}

void cpu_pmu_muxed_spi_workaround_worker(struct work_struct *work)
{
	struct arm_pmu *cpu_pmu =
	    container_of(work, struct arm_pmu, muxed_spi_workaround_work);

	get_online_cpus();
	cpu_pmu_queue_percpu_work(cpu_pmu);
	put_online_cpus();
}

/*
 * Called when the main interrupt handler cannot determine the source
 * of interrupt. It will deploy a workaround if we are running on an SMP
 * platform with only a single muxed SPI.
 *
 * The workaround disables the interrupt and distributes irqwork to all
 * other processors in the system. Hopefully one of them will clear the
 * interrupt...
 */
static irqreturn_t cpu_pmu_handle_irq_none(int irq_num, struct arm_pmu *cpu_pmu)
{

	if (irq_num != cpu_pmu->muxed_spi_workaround_irq)
		return IRQ_NONE;

	disable_irq_nosync(cpu_pmu->muxed_spi_workaround_irq);

	if (try_get_online_cpus()) {
		cpu_pmu_queue_percpu_work(cpu_pmu);
		put_online_cpus();
	} else {
		/*
		 * There is a CPU hotplug operation in flight making it
		 * unsafe for us to queue the percpu work. The PMU is
		 * already silenced so we'll leave it like that and
		 * schedule some work to tidy things up.
		 *
		 * Taking this code path should be very rare which is
		 * good because the latencies involved here are way to
		 * long for good profiling.
		 */
		schedule_work(&cpu_pmu->muxed_spi_workaround_work);
	}

	return IRQ_HANDLED;
}

static int cpu_pmu_muxed_spi_workaround_init(struct arm_pmu *cpu_pmu)
{
	struct platform_device *pmu_device = cpu_pmu->plat_device;
	int cpu;

	for_each_possible_cpu(cpu) {
		struct pmu_hw_events *hw_events =
		    per_cpu_ptr(cpu_pmu->hw_events, cpu);

		init_irq_work(&hw_events->work, cpu_pmu_do_percpu_work);
	}

	INIT_WORK(&cpu_pmu->muxed_spi_workaround_work,
		  cpu_pmu_muxed_spi_workaround_worker);
	atomic_set(&cpu_pmu->remaining_irq_work, 0);
	cpu_pmu->muxed_spi_workaround_irq = platform_get_irq(pmu_device, 0);

	return 0;
}

static void cpu_pmu_muxed_spi_workaround_term(struct arm_pmu *cpu_pmu)
{
	cpu_pmu->muxed_spi_workaround_irq = 0;
}
#else /* CONFIG_SMP */
static int cpu_pmu_muxed_spi_workaround_init(struct arm_pmu *cpu_pmu)
{
	return 0;
}

static void cpu_pmu_muxed_spi_workaround_term(struct arm_pmu *cpu_pmu)
{
}

static irqreturn_t cpu_pmu_handle_irq_none(int irq_num, struct arm_pmu *cpu_pmu)
{
	return IRQ_NONE;
}
#endif /* CONFIG_SMP */

/* Include the PMU-specific implementations. */
#include "perf_event_xscale.c"
#include "perf_event_v6.c"
#include "perf_event_v7.c"

static void cpu_pmu_enable_percpu_irq(void *data)
{
	int irq = *(int *)data;

	enable_percpu_irq(irq, IRQ_TYPE_NONE);
}

static void cpu_pmu_disable_percpu_irq(void *data)
{
	int irq = *(int *)data;

	disable_percpu_irq(irq);
}

static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
{
	int i, irq, irqs;
	struct platform_device *pmu_device = cpu_pmu->plat_device;
	struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;

	irqs = min(pmu_device->num_resources, num_possible_cpus());

	irq = platform_get_irq(pmu_device, 0);
	if (irq >= 0 && irq_is_percpu(irq)) {
		on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
		free_percpu_irq(irq, &hw_events->percpu_pmu);
	} else {
		for (i = 0; i < irqs; ++i) {
			if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
				continue;
			irq = platform_get_irq(pmu_device, i);
			if (irq >= 0)
				free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, i));
		}

		cpu_pmu_muxed_spi_workaround_term(cpu_pmu);
	}
}

static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
{
	int i, err, irq, irqs;
	struct platform_device *pmu_device = cpu_pmu->plat_device;
	struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;

	if (!pmu_device)
		return -ENODEV;

	irqs = min(pmu_device->num_resources, num_possible_cpus());
	if (irqs < 1) {
		pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
		return 0;
	}

	irq = platform_get_irq(pmu_device, 0);
	if (irq >= 0 && irq_is_percpu(irq)) {
		err = request_percpu_irq(irq, handler, "arm-pmu",
					 &hw_events->percpu_pmu);
		if (err) {
			pr_err("unable to request IRQ%d for ARM PMU counters\n",
				irq);
			return err;
		}
		on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
	} else {
		for (i = 0; i < irqs; ++i) {
			err = 0;
			irq = platform_get_irq(pmu_device, i);
			if (irq < 0)
				continue;

			/*
			 * If we have a single PMU interrupt that we can't shift,
			 * assume that we're running on a uniprocessor machine and
			 * continue. Otherwise, continue without this interrupt.
			 */
			if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
				pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
					irq, i);
				continue;
			}

			err = request_irq(irq, handler,
					  IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
					  per_cpu_ptr(&hw_events->percpu_pmu, i));
			if (err) {
				pr_err("unable to request IRQ%d for ARM PMU counters\n",
					irq);
				return err;
			}

			cpumask_set_cpu(i, &cpu_pmu->active_irqs);
		}

		/*
		 * If we are running SMP and have only one interrupt source
		 * then get ready to share that single irq among the cores.
		 */
		if (nr_cpu_ids > 1 && irqs == 1) {
			err = cpu_pmu_muxed_spi_workaround_init(cpu_pmu);
			if (err)
				return err;
		}
	}

	return 0;
}

/*
 * PMU hardware loses all context when a CPU goes offline.
 * When a CPU is hotplugged back in, since some hardware registers are
 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 * junk values out of them.
 */
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
			  void *hcpu)
{
	struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);

	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
		return NOTIFY_DONE;

	if (pmu->reset)
		pmu->reset(pmu);
	else
		return NOTIFY_DONE;

	return NOTIFY_OK;
}

static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
{
	int err;
	int cpu;
	struct pmu_hw_events __percpu *cpu_hw_events;

	cpu_hw_events = alloc_percpu(struct pmu_hw_events);
	if (!cpu_hw_events)
		return -ENOMEM;

	cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
	err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
	if (err)
		goto out_hw_events;

	for_each_possible_cpu(cpu) {
		struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
		raw_spin_lock_init(&events->pmu_lock);
		events->percpu_pmu = cpu_pmu;
	}

	cpu_pmu->hw_events	= cpu_hw_events;
	cpu_pmu->request_irq	= cpu_pmu_request_irq;
	cpu_pmu->free_irq	= cpu_pmu_free_irq;

	/* Ensure the PMU has sane values out of reset. */
	if (cpu_pmu->reset)
		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);

	/* If no interrupts available, set the corresponding capability flag */
	if (!platform_get_irq(cpu_pmu->plat_device, 0))
		cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

	return 0;

out_hw_events:
	free_percpu(cpu_hw_events);
	return err;
}

static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
{
	unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
	free_percpu(cpu_pmu->hw_events);
}

/*
 * PMU platform driver and devicetree bindings.
 */
static struct of_device_id cpu_pmu_of_device_ids[] = {
	{.compatible = "arm,cortex-a17-pmu",	.data = armv7_a17_pmu_init},
	{.compatible = "arm,cortex-a15-pmu",	.data = armv7_a15_pmu_init},
	{.compatible = "arm,cortex-a12-pmu",	.data = armv7_a12_pmu_init},
	{.compatible = "arm,cortex-a9-pmu",	.data = armv7_a9_pmu_init},
	{.compatible = "arm,cortex-a8-pmu",	.data = armv7_a8_pmu_init},
	{.compatible = "arm,cortex-a7-pmu",	.data = armv7_a7_pmu_init},
	{.compatible = "arm,cortex-a5-pmu",	.data = armv7_a5_pmu_init},
	{.compatible = "arm,arm11mpcore-pmu",	.data = armv6mpcore_pmu_init},
	{.compatible = "arm,arm1176-pmu",	.data = armv6_1176_pmu_init},
	{.compatible = "arm,arm1136-pmu",	.data = armv6_1136_pmu_init},
	{.compatible = "qcom,krait-pmu",	.data = krait_pmu_init},
	{},
};

static struct platform_device_id cpu_pmu_plat_device_ids[] = {
	{.name = "arm-pmu"},
	{.name = "armv6-pmu"},
	{.name = "armv7-pmu"},
	{.name = "xscale-pmu"},
	{},
};

static const struct pmu_probe_info pmu_probe_table[] = {
	ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init),
	ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init),
	ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init),
	ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init),
	ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init),
	ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init),
	XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init),
	XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init),
	{ /* sentinel value */ }
};

/*
 * CPU PMU identification and probing.
 */
static int probe_current_pmu(struct arm_pmu *pmu)
{
	int cpu = get_cpu();
	unsigned int cpuid = read_cpuid_id();
	int ret = -ENODEV;
	const struct pmu_probe_info *info;

	pr_info("probing PMU on CPU %d\n", cpu);

	for (info = pmu_probe_table; info->init != NULL; info++) {
		if ((cpuid & info->mask) != info->cpuid)
			continue;
		ret = info->init(pmu);
		break;
	}

	put_cpu();
	return ret;
}

static int cpu_pmu_device_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	const int (*init_fn)(struct arm_pmu *);
	struct device_node *node = pdev->dev.of_node;
	struct arm_pmu *pmu;
	int ret = -ENODEV;

	if (cpu_pmu) {
		pr_info("attempt to register multiple PMU devices!\n");
		return -ENOSPC;
	}

	pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
	if (!pmu) {
		pr_info("failed to allocate PMU device!\n");
		return -ENOMEM;
	}

	cpu_pmu = pmu;
	cpu_pmu->plat_device = pdev;

	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
		init_fn = of_id->data;
		ret = init_fn(pmu);
	} else {
		ret = probe_current_pmu(pmu);
	}

	if (ret) {
		pr_info("failed to probe PMU!\n");
		goto out_free;
	}

	ret = cpu_pmu_init(cpu_pmu);
	if (ret)
		goto out_free;

	ret = armpmu_register(cpu_pmu, -1);
	if (ret)
		goto out_destroy;

	return 0;

out_destroy:
	cpu_pmu_destroy(cpu_pmu);
out_free:
	pr_info("failed to register PMU devices!\n");
	kfree(pmu);
	return ret;
}

static struct platform_driver cpu_pmu_driver = {
	.driver		= {
		.name	= "arm-pmu",
		.pm	= &armpmu_dev_pm_ops,
		.of_match_table = cpu_pmu_of_device_ids,
	},
	.probe		= cpu_pmu_device_probe,
	.id_table	= cpu_pmu_plat_device_ids,
};

static int __init register_pmu_driver(void)
{
	return platform_driver_register(&cpu_pmu_driver);
}
device_initcall(register_pmu_driver);