aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/omap34xx.dtsi
blob: 4f6b2d5b1902e96114f12b1f8bd7d15ba0b9819e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
/*
 * Device Tree Source for OMAP34xx/OMAP35xx SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/media/omap3-isp.h>

#include "omap3.dtsi"

/ {
	cpus {
		cpu@0 {
			/* OMAP343x/OMAP35xx variants OPP1-5 */
			operating-points = <
				/* kHz    uV */
				125000   975000
				250000  1075000
				500000  1200000
				550000  1270000
				600000  1350000
			>;
			clock-latency = <300000>; /* From legacy driver */
		};
	};

	ocp {
		omap3_pmx_core2: pinmux@480025d8 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x480025d8 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		isp: isp@480bc000 {
			compatible = "ti,omap3-isp";
			reg = <0x480bc000 0x12fc
			       0x480bd800 0x017c>;
			interrupts = <24>;
			iommus = <&mmu_isp>;
			syscon = <&scm_conf 0xdc>;
			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
			#clock-cells = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};
};

&ssi {
	status = "ok";

	clocks = <&ssi_ssr_fck>,
		 <&ssi_sst_fck>,
		 <&ssi_ick>;
	clock-names = "ssi_ssr_fck",
		      "ssi_sst_fck",
		      "ssi_ick";
};

/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"