From 2a13096ac7da07a1bfc9d91fc4a982020e7ded2b Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 1 Feb 2019 13:02:29 +0530 Subject: platform/x86: intel_pmc_core: Include Reserved IP for LTR Recently introduced commit "platform/x86: intel_pmc_core: Show Latency Tolerance info <51337cd94d18184601ac0fb4cf1a02b8bbabc3d7> skipped the LTR from a reserved IP. Though this doesn't cause any functional issue but it is needed for the consumers of "ltr_ignore" as the index printing for "ltr_show" is missing. For example, w/o this change, a user that wants to ignore LTR from ME would do something like echo 5 > ltr_ignore but the index for ME is 6. Printing a reserved IP helps to properly calculate LTR ignore offsets. Cc: "David E. Box" Cc: Srinivas Pandruvada Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 2 ++ drivers/platform/x86/intel_pmc_core.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'drivers/platform/x86') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 125461ca2927..835ed6d333bf 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -108,6 +108,7 @@ static const struct pmc_bit_map spt_ltr_show_map[] = { {"SATA", SPT_PMC_LTR_SATA}, {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE}, {"XHCI", SPT_PMC_LTR_XHCI}, + {"Reserved", SPT_PMC_LTR_RESERVED}, {"ME", SPT_PMC_LTR_ME}, /* EVA is Enterprise Value Add, doesn't really exist on PCH */ {"EVA", SPT_PMC_LTR_EVA}, @@ -276,6 +277,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { {"SATA", CNP_PMC_LTR_SATA}, {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, {"XHCI", CNP_PMC_LTR_XHCI}, + {"Reserved", CNP_PMC_LTR_RESERVED}, {"ME", CNP_PMC_LTR_ME}, /* EVA is Enterprise Value Add, doesn't really exist on PCH */ {"EVA", CNP_PMC_LTR_EVA}, diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 1a0104d2cbf0..0680ca397b57 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -46,6 +46,7 @@ #define SPT_PMC_LTR_SATA 0x368 #define SPT_PMC_LTR_GBE 0x36C #define SPT_PMC_LTR_XHCI 0x370 +#define SPT_PMC_LTR_RESERVED 0x374 #define SPT_PMC_LTR_ME 0x378 #define SPT_PMC_LTR_EVA 0x37C #define SPT_PMC_LTR_SPC 0x380 @@ -156,6 +157,7 @@ enum ppfear_regs { #define CNP_PMC_LTR_SATA 0x1B68 #define CNP_PMC_LTR_GBE 0x1B6C #define CNP_PMC_LTR_XHCI 0x1B70 +#define CNP_PMC_LTR_RESERVED 0x1B74 #define CNP_PMC_LTR_ME 0x1B78 #define CNP_PMC_LTR_EVA 0x1B7C #define CNP_PMC_LTR_SPC 0x1B80 -- cgit v1.2.3