From 79fc72d6d3ab4ee08068fe39c199aab2e677daaa Mon Sep 17 00:00:00 2001 From: Boojin Kim Date: Sat, 26 Jun 2010 16:36:43 +0900 Subject: ARM: S5P: Bug fix on external interrupt for S5P SoCs This patch fixes bug on eint type set function, s5p_irq_eint_set_type(). In the IRQ_TYPE_EDGE_FALLING case, S5P_EXTINT_FALLEDGE is right instead of S5P_EXTINT_RISEEDGE Signed-off-by: Boojin Kim Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/irq-eint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index e56c8075df97..f36cd3327025 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -71,7 +71,7 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) break; case IRQ_TYPE_EDGE_FALLING: - newvalue = S5P_EXTINT_RISEEDGE; + newvalue = S5P_EXTINT_FALLEDGE; break; case IRQ_TYPE_EDGE_BOTH: -- cgit v1.2.3 From 154d62e4cdec9eb9271cf57f9d1f57c79c4f4e18 Mon Sep 17 00:00:00 2001 From: MyungJoo Ham Date: Sat, 26 Jun 2010 17:21:50 +0900 Subject: ARM: S5PV210: Correct clock register properties 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were defined incorrectly. 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc, sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their twins defined in struct clk init_clocks_disable[] and struct clk init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK register to avoid the duplicated clock problem described below. NOTE: Duplicated Clock Problem Please note that each clock definition should access different control register; otherwise, the system may suffer lockups. For example, if we have two clock definitions "a" and "b" which access the same register (and the shift value). Then, when we do: module A clk = clk_get("a"); clk->clk_enable(clk); module B (context switch) clk = clk_get("b"); clk->clk_enable(clk); do something with clk. clk->clk_disable(clk); module A (context switch) do something with clk * At this point, the system may hang. Therefore, there should be no clock definitions with the same contol register/shift. If we need to create "aliases", then, creating child clocks sharing the clock should be fine. 3. Corrected other sclk_* shift values and access registers. Signed-off-by: MyungJoo Ham Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: minor title and message fix] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv210/clock.c | 115 +++++++++++++++++++++++------------------- 1 file changed, 62 insertions(+), 53 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 154bca4abc09..af91fefef2c6 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); } +static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); +} + static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .id = -1, @@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = { .id = 0, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<4), + .ctrlbit = (1 << 5), }, { .name = "i2s_v32", .id = 1, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<4), - } + .ctrlbit = (1 << 6), + }, }; static struct clk init_clocks[] = { @@ -429,25 +434,25 @@ static struct clk init_clocks[] = { .id = 0, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<7), + .ctrlbit = (1 << 17), }, { .name = "uart", .id = 1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<8), + .ctrlbit = (1 << 18), }, { .name = "uart", .id = 2, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<9), + .ctrlbit = (1 << 19), }, { .name = "uart", .id = 3, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<10), + .ctrlbit = (1 << 20), }, }; @@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = { .clk = { .name = "sclk_dac", .id = -1, - .ctrlbit = (1 << 10), - .enable = s5pv210_clk_ip1_ctrl, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 2), }, .sources = &clkset_sclk_dac, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, @@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = { .clk = { .name = "sclk_hdmi", .id = -1, - .enable = s5pv210_clk_ip1_ctrl, - .ctrlbit = (1 << 11), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_sclk_hdmi, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, @@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", .id = 0, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 4), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 24), }, .sources = &clkset_sclk_audio0, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, @@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", .id = 1, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 5), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 25), }, .sources = &clkset_sclk_audio1, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, @@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", .id = 2, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 6), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 26), }, .sources = &clkset_sclk_audio2, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, @@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 0, - .ctrlbit = (1<<17), - .enable = s5pv210_clk_ip3_ctrl, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 12), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, @@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 1, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 18), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 13), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, @@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 2, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 19), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 14), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, @@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 3, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 20), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 15), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, @@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mixer", .id = -1, - .enable = s5pv210_clk_ip1_ctrl, - .ctrlbit = (1 << 9), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 1), }, .sources = &clkset_sclk_mixer, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, @@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 0, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 24), + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 2), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, @@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 1, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 25), + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 3), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, @@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 2, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 26), + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 4), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, @@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_cam", .id = 0, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 3), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, @@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_cam", .id = 1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 4), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, @@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimd", .id = -1, - .enable = s5pv210_clk_ip1_ctrl, - .ctrlbit = (1 << 0), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 5), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, @@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 0, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1 << 16), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 8), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, @@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 1, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1 << 17), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 9), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, @@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 2, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1 << 18), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 10), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, @@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 3, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1 << 19), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 11), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, @@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_csis", .id = -1, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 31), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 6), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, @@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_spi", .id = 0, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 12), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 16), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, @@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_spi", .id = 1, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 13), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 17), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, @@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_pwi", .id = -1, - .enable = &s5pv210_clk_ip4_ctrl, - .ctrlbit = (1 << 2), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 29), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, @@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_pwm", .id = -1, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 23), + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 19), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, -- cgit v1.2.3 From 6b34f498fe8a918978ddba2bc82a9bd6a883e1fb Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 22 Jun 2010 15:45:26 +0900 Subject: ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XX This patch fixes the following compilation problem if only NCP machine is selected: arch/arm/mach-s3c64xx/s3c6410.c: In function 's3c6410_map_io': arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function 's3c6410_default_sdhci2' And also adds missed 's3c6400_default_sdhci2'. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: minor title fix and added comments] Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/sdhci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 13f9fb20900a..2e263a8bb2ef 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -166,8 +166,10 @@ static inline void s3c6410_default_sdhci2(void) { } #else static inline void s3c6410_default_sdhci0(void) { } static inline void s3c6410_default_sdhci1(void) { } +static inline void s3c6410_default_sdhci2(void) { } static inline void s3c6400_default_sdhci0(void) { } static inline void s3c6400_default_sdhci1(void) { } +static inline void s3c6400_default_sdhci2(void) { } #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ -- cgit v1.2.3 From 4164acaf096fb92b67cdbde6b454dda773aa953b Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 21 Jun 2010 14:21:54 +0530 Subject: ARM: S5P6442: Fix PLL setting announce message. The S5P6442 PLL setting announce message incorrectly displays S5P6440 as the SoC. Change it to S5P6442. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p6442/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c index 3aadbf42c112..087e57f20ad5 100644 --- a/arch/arm/mach-s5p6442/clock.c +++ b/arch/arm/mach-s5p6442/clock.c @@ -294,7 +294,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void) mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); - printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", + printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld", apll, mpll, epll); clk_fout_apll.rate = apll; -- cgit v1.2.3 From f50b8bc707988e2543f884d3030199868ca0f48f Mon Sep 17 00:00:00 2001 From: Hyuk Lee Date: Thu, 10 Jun 2010 12:40:39 +0900 Subject: ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0 This patch fixes on wrong function name in include/plat/sdhci.h for Samsung. The 's5pc100_default_sdhci0()' function should be chnaged to 's5pv210_default_sdhci0()'. Because 's5pv210_default_sdhci0()' must be pair. Signed-off-by: Hyuk Lee Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/sdhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 2e263a8bb2ef..016674fa20dd 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -241,7 +241,7 @@ static inline void s5pv210_default_sdhci0(void) s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; } #else -static inline void s5pc100_default_sdhci0(void) { } +static inline void s5pv210_default_sdhci0(void) { } #endif /* CONFIG_S3C_DEV_HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC1 -- cgit v1.2.3