From 10314e09d044296bc50dec831aa85b3ae1acedf0 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 27 Apr 2018 08:43:14 +0200 Subject: riscv: add swiotlb support All RISC-V platforms today lack an IOMMU. However, legacy PCI devices sometimes require DMA-memory to be in the low 32 bits. To make this work, we enable the software-based bounce buffers from swiotlb. They only impose overhead when the device in question cannot address the full 64-bit address space, so a perfect fit. This patch assumes that DMA is coherent with the processor and the PCI bus. It also assumes that the processor and devices share a common address space. This is true for all RISC-V platforms so far. [changelog stolen from an earlier patch by Palmer Dabbelt that did the more complicated swiotlb wireup before the recent consolidation] Signed-off-by: Christoph Hellwig Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/riscv/Kconfig') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c4488ce8c2fa..274bc064c41f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -114,6 +114,7 @@ config ARCH_RV64I select HAVE_FTRACE_MCOUNT_RECORD select HAVE_DYNAMIC_FTRACE select HAVE_DYNAMIC_FTRACE_WITH_REGS + select SWIOTLB endchoice -- cgit v1.2.3