From b48b3a390629945f5a131b210931416cf243f58d Mon Sep 17 00:00:00 2001 From: Steven Miao Date: Wed, 29 Jan 2014 12:25:39 +0800 Subject: From: Paul Walmsley blackfin: bf60x: clock: return 0 upon error from clk_round_rate() clk_round_rate() should return 0 upon an error, rather than returning a negative error code. This is because clk_round_rate() is being changed to return an unsigned return type rather than a signed type, since some clock sources can generate rates higher than (2^31)-1 Hz. Signed-off-by: Paul Walmsley Signed-off-by: Steven Miao --- arch/blackfin/mach-bf609/clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/mach-bf609') diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c index dab8849af884..13644ed25489 100644 --- a/arch/blackfin/mach-bf609/clock.c +++ b/arch/blackfin/mach-bf609/clock.c @@ -120,6 +120,7 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); + unsigned long clk_get_rate(struct clk *clk) { unsigned long ret = 0; @@ -131,7 +132,7 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { - long ret = -EIO; + long ret = 0; if (clk->ops && clk->ops->round_rate) ret = clk->ops->round_rate(clk, rate); return ret; -- cgit v1.2.3 From cccdfcf728e2f322e8986a39bc02bf5aaa8fe8a7 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 4 Dec 2013 13:51:38 +0800 Subject: blackfin: bf609: update the anomaly list to Nov 2013 Signed-off-by: Sonic Zhang --- arch/blackfin/mach-bf609/include/mach/anomaly.h | 54 ++++++++++++++++++++----- 1 file changed, 44 insertions(+), 10 deletions(-) (limited to 'arch/blackfin/mach-bf609') diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h index 7a07374308ac..696786e9a531 100644 --- a/arch/blackfin/mach-bf609/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h @@ -23,11 +23,11 @@ /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ #define ANOMALY_16000003 (1) /* The EPPI Data Enable (DEN) Signal is Not Functional */ -#define ANOMALY_16000004 (1) +#define ANOMALY_16000004 (__SILICON_REVISION__ < 1) /* Using L1 Instruction Cache with Parity Enabled is Unreliable */ -#define ANOMALY_16000005 (1) +#define ANOMALY_16000005 (__SILICON_REVISION__ < 1) /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ -#define ANOMALY_16000006 (1) +#define ANOMALY_16000006 (__SILICON_REVISION__ < 1) /* DDR2 Memory Reads May Fail Intermittently */ #define ANOMALY_16000007 (1) /* Instruction Memory Stalls Can Cause IFLUSH to Fail */ @@ -49,19 +49,53 @@ /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_16000017 (1) /* RSI Boot Cleanup Routine Does Not Clear Registers */ -#define ANOMALY_16000018 (1) +#define ANOMALY_16000018 (__SILICON_REVISION__ < 1) /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ -#define ANOMALY_16000019 (1) +#define ANOMALY_16000019 (__SILICON_REVISION__ < 1) /* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ -#define ANOMALY_16000020 (1) +#define ANOMALY_16000020 (__SILICON_REVISION__ < 1) /* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */ -#define ANOMALY_16000021 (1) +#define ANOMALY_16000021 (__SILICON_REVISION__ < 1) /* Boot Code Fails to Enable Parity Fault Detection */ -#define ANOMALY_16000022 (1) +#define ANOMALY_16000022 (__SILICON_REVISION__ < 1) +/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */ +#define ANOMALY_16000023 (__SILICON_REVISION__ < 1) +/* Spurious Fault Signaled After Clearing an Externally Generated Fault */ +#define ANOMALY_16000024 (1) +/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */ +#define ANOMALY_16000025 (1) /* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */ -#define ANOMALY_16000027 (1) +#define ANOMALY_16000027 (__SILICON_REVISION__ < 1) +/* Default SPI Master Boot Mode Setting is Incorrect */ +#define ANOMALY_16000028 (__SILICON_REVISION__ < 1) +/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */ +#define ANOMALY_16000027 (__SILICON_REVISION__ < 1) /* Interrupted Core Reads of MMRs May Cause Data Loss */ -#define ANOMALY_16000030 (1) +#define ANOMALY_16000030 (__SILICON_REVISION__ < 1) +/* Incorrect Default USB_PLL_OSC.PLLM Value */ +#define ANOMALY_16000031 (__SILICON_REVISION__ < 1) +/* Core Reads of System MMRs May Cause the Core to Hang */ +#define ANOMALY_16000032 (__SILICON_REVISION__ < 1) +/* PPI Data Underflow on First Word Not Reported in Certain Modes */ +#define ANOMALY_16000033 (1) +/* CNV1 Red Pixel Substitution feature not functional in the PVP */ +#define ANOMALY_16000034 (__SILICON_REVISION__ < 1) +/* IPF0 Output Port Color Separation feature not functional */ +#define ANOMALY_16000035 (__SILICON_REVISION__ < 1) +/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */ +#define ANOMALY_16000036 (__SILICON_REVISION__ < 1) +/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */ +#define ANOMALY_16000037 (__SILICON_REVISION__ < 1) +/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */ +#define ANOMALY_16000038 (__SILICON_REVISION__ < 1) +/* CGU_STAT.PLOCKERR Bit May be Unreliable */ +#define ANOMALY_16000039 (1) +/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */ +#define ANOMALY_16000040 (1) +/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */ +#define ANOMALY_16000041 (1) +/* Instruction Cache Failure When Parity Is Enabled */ +#define ANOMALY_16000042 (__SILICON_REVISION__ == 1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) -- cgit v1.2.3 From 1b6012394bec5dc653d495245c5495db08f817f6 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 4 Dec 2013 15:27:47 +0800 Subject: blackfin: Support L1 SRAM parity checking feature on bf60x Move code for the SEC faults from the IRQ hanlders into IRQ actions. refine bfin fault routine handle Signed-off-by: Sonic Zhang Signed-off-by: Steven Miao --- arch/blackfin/mach-bf609/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/blackfin/mach-bf609') diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig index b0fca44110b0..6584190faeb8 100644 --- a/arch/blackfin/mach-bf609/Kconfig +++ b/arch/blackfin/mach-bf609/Kconfig @@ -17,6 +17,12 @@ config SEC_IRQ_PRIORITY_LEVELS Divide the total number of interrupt priority levels into sub-levels. There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. +config L1_PARITY_CHECK + bool "Enable L1 parity check" + default n + help + Enable the L1 parity check in L1 sram. A fault event is raised + when L1 parity error is found. comment "System Cross Bar Priority Assignment" -- cgit v1.2.3