From 0a8c265c165b671ab5607c118f1c5cb57b68ccb9 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:22 -0600 Subject: arm: dts: qcom: Add idle states device nodes for 8974 Add allowable C-States for each cpu using the cpu-idle-states node. Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index a200883f7fed..819a6f407e70 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -25,6 +25,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu1: cpu@1 { @@ -38,6 +39,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu3: cpu@3 { @@ -64,6 +67,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { @@ -71,6 +75,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- cgit v1.2.3