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This is a multi_v7_defconfig derived configuration with extra settings
applied to make it possible to run with an android userspace.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently the sti drm driver forcible applies O_RDWR when it exports
a prime handle. This is because it was not previously possible for
user requests to create the fd with O_RDWR passed into drivers.
This is a cleanup to remove this code. This change has obvious impact
upon the userspace which must change the flags passed to
DRM_IOCTL_PRIME_HANDLE_TO_FD. However at present only a tiny handful of
developers run this userspace and, if they don't complain, nobody else
will.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently msm does not implement gem_prime_mmap. Without this it is not
possible to draw onto a dma-buf from userspace (making its very hard to
implement the Android rendering model).
Fixing this is just a matter of adding a little boilerplate.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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gem_prime_map is not currently described in the DRM manual, lets document
it.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently DRM_IOCTL_PRIME_HANDLE_TO_FD rejects all flags except
(DRM|O)_CLOEXEC making it hard for the userspace to generate a file
descriptor that can be used by mmap().
It is easy to relax the restriction and allow read/write permissions.
This should be safe because the flags are seldom touched by drm; mostly
they are passed verbatim to dma_buf calls.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently if the user passes an invalid value on the kernel command line
then the kernel will crash during argument parsing. On most systems this
is very hard to debug because the console hasn't been initialized yet.
This is a regression due to commit 51e158c12aca ("param: hand arguments
after -- straight to init") which, in response to the systemd debug
controversy, made it possible to explicitly pass arguments to init. To
achieve this parse_args() was extended from simply returning an error
code to returning a pointer. Regretably the new init args logic does not
perform a proper validity check on the pointer resulting in a crash.
This patch adds a validity check. Should the check fail then no arguments
will be passed to init but this is normal in the sense that no error
recovery is performed by the parser.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: stable@vger.kernel.org
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To properly support sysrq on uartDM hardware we need to properly
handle break characters. With the DM hardware the fifo can pack 4
characters at a time, where a break is indicated by an all zero
byte. Unfortunately, we can't differentiate between an all zero
byte for a break and an all zero byte of data, so try and do as
best we can. First unmask the RX break start interrupt and record
the interrupt when it arrives. Then while processing the fifo,
detect the break by searching for an all zero character as long
as we recently received an RX break start interrupt. This should
make sysrq work fairly well.
Cc: Frank Rowand <frank.rowand@sonymobile.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently the magic SysRq functions are accessed by sending a break.
Unfortunately some networked serial proxies makes is difficult to send
a break meaning SysRq functions cannot be reached. We avoid this problem
by allowing the (fairly unlikely) sequence of ^B^R^K characters to
emulate a real break.
This approach is very nearly as robust as normal sysrq/break handling
because all trigger recognition happens during interrupt handling however
to emulate a break we must enter the ISR four times (instead of twice) and
manage an extra byte of state.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
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Currently forcing the video mode from the kernel command line (for example
video=HDMI-A-1:1280x720-16@60) does not correctly set the number of bits
per pixel. This is due to a rather aggressive override in
msm_fbdev_create(). This is a particular problem for Android bring up
because the software EGL fallbacks don't support 32bpp.
Since the overrides are actually the default values anyway then this
problem can be trivially fixed by removing the overrides completely.
Change was tested by dd'ing a test image to /dev/fb0 with no video=
(still 32bpp), video=1920x1080-32@60, video=1920x1080-24@60 and
video=1920x1080-16@60 .
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: David Airlie <airlied@linux.ie>
Cc: Rob Clark <robdclark@gmail.com>
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* tracking-qcomlt-dt:
arm: dts: qcom: Add idle state device nodes for 8064
arm: dts: qcom: Add idle states device nodes for 8084
arm: dts: qcom: Add idle states device nodes for 8974
arm: dts: qcom: Update power-controller device node for 8064 Krait CPUs
arm: dts: qcom: Add power-controller device node for 8084 Krait CPUs
arm: dts: qcom: Add power-controller device node for 8974 Krait CPUs
ARM: DT: apq8064: Add Support for SD Card Detect for ifc6410 board
ARM: dts: qcom: Add necessary DT data for Krait cpufreq
WIP: ARM: DT: ifc6410 : add lvds panel
WIP: ARM: DT: APQ8064: Add iommu
ARM: DT: APQ8064: Add MDP support
ARM: DT: ifc6410: add wlan node with reset line.
ARM: DT: apq8064: Add pmic gpio node
ARM: DT: apq8064: add pci support
ARM: DT: apq8064: Add SATA controller support.
ARM: DT: apq8064: Add USB OTG support
ARM: DT: apq8064: Add usb host support.
ARM: DT: apq8064: add rpm support
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* tracking-qcomlt-cpuidle:
qcom: scm: fix compliation error.
qcom: cpuidle: Add cpuidle driver for QCOM cpus
qcom: spm: Add Subsystem Power Manager driver
qcom: scm: scm_set_warm_boot_addr() to set the warmboot address
ARM: qcom: Move scm-boot files to drivers/soc and include/soc
ARM: qcom: Add SCM warmboot flags for quad core targets.
ARM: qcom: scm: Add atomic SCM APIs
ARM: qcom: scm: Move the scm driver to drivers/soc/qcom
ARM: qcom: scm: Add logging of actual return code from scm call
ARM: qcom: scm: Flush the command buffer only instead of the entire cache
ARM: qcom: scm: Get cacheline size from CTR
ARM: qcom: scm: Fix incorrect cache invalidation
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* tracking-qcomlt-cpufreq:
cpufreq:qcom: covert to use cpufreq-dt
cpufreq: Add module to register cpufreq on Krait CPUs
clk: qcom: Add Krait clock controller driver
clk: qcom: Add KPSS ACC/GCC driver
clk: qcom: Add support for Krait clocks
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add MSM8960/APQ8064's HFPLLs
clk: qcom: Add HFPLL driver
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
clk: Avoid sending high rates to downstream clocks during set_rate
clk: Add safe switch hook
clk: divider: Make generic for usage elsewhere
ARM: Add Krait L2 register accessor functions
clk: Add __clk_mux_determine_rate_closest
clk: mux: Split out register accessors for reuse
clk: mux: Add unregistration API
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* tracking-qcomlt-iommu:
iommu: qcom: fix compiler warnings.
WIP: qcom-iommu-v0 (v3)
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* tracking-qcomlt-pmic-gpio:
pinctrl: qcom: fix compiler errors.
pinctrl:qcom:ssbi: Enable gpio mode
pinctrl: qcom: ssbi-pmic: promote driver to sub system level
pinctrl: Introduce pinctrl driver for Qualcomm SSBI PMIC's
mfd: pm8921: Expose pm8xxx_read_irq_status
pinctrl: Qualcomm SPMI PMIC MPP pin controller driver
pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver
pinctrl: Device tree bindings for Qualcomm PMIC MPP block
pinctrl: Device tree bindings for Qualcomm PMIC GPIO block
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* tracking-qcomlt-pcie:
pci: qcom: move device init to subsys_initcall_sync
pci: qcom: add msi support
pci: qcom: Add support to external phy reference clk.
pci: qcom: remove static declaration of functions.
pci: qcom: Add regulator support
pci: qcom: move dt parsing code out of probe
pci: qcom: fix unused variable warning.
pci: qcom: fix a typo in reset gpio
PCI: qcom: Add support for pcie controllers on IPQ8064
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* tracking-qcomlt-fixes:
defconfig: qcom: add qcom specific configs.
clk: qcom: Fix duplicate rbcpr clock name
arm: vfp: Bounce undefined instructions in vectored mode
ARM: vfp: Fix VFPv3 hwcap detection on CPUID based cpus
ARM: vfp: Workaround bad MVFR1 register on some Kraits
iommu:msm: fix compilation error.
fixup: ATAG MEM fixup loader for Qualcomm devices
ARM: multi_v7_defconfig: Add QCOM specific drivers
mfd: ssbi: promote the driver to subsys level
arm: Fix DEBUG_LL for multi-platform kernels (without PL01X)
arm: Seperate DEBUG_UART_PHYS from DEBUG_LL on EP93XX
arm: sa1100: Migrate DEBUG_LL macros to shared directory
arm: netx: Migrate DEBUG_LL macros to shared directory
arm: omap1: Migrate debug_ll macros to use 8250.S
arm: ks8695: Migrate debug_ll macros to shared directory
arm: Remove DEBUG_LL_UART_NONE
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* tracking-qcomlt-dma:
dt/bindings: dmaengine: qcom_bam_dma: Add compatible string for BAM v1.3.0
dmaengine: qcom_bam_dma: Add BAM v1.3.0 support
dmaengine: qcom_bam_dma: Generalize BAM register offset calculations
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* tracking-qcomlt-wlan:
ARM:qcom: Add WLAN reset support
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* tracking-qcomlt-sdcc:
mmc: mmci: fix mmci_post_request
mmc: core: fix prepared requests while doing bkops
mmc: mmci: Support any block sizes for ux500v2 and qcom variant
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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There is a duplication in a clock name for apq8084 platform that causes
the following warning: "RBCPR_CLK_SRC" redefined
Resolve this by adding a MMSS_ prefix to this clock and making its name
coherent with msm8974 platform.
Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
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Recent 3.18 changed cpufreq-generic to cpufreq-dt, so convert the driver
to use the the latest cpufreq-dt naming.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Add ARM common idle state device bindings for cpuidle support in
APQ8064.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Add allowable C-States for each cpu using the cpu-idle-states node.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Add allowable C-States for each cpu using the cpu-idle-states node.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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This changes muxes in gpio26 pin to function as gpio and adds support
for sd card detect for apq8064 based IFC6410 board.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
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Add the necessary DT nodes and data so we can probe the cpufreq
driver on MSM devices with Krait CPUs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds MDP node to APQ8064 dt.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds wlan node with platform specfic reset gpio line.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds pmic gpio node to the device tree, this node is
necessary for devices like wlan to control reset gpio.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds PCIE support to APQ8064, tested on IFC6410 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds AHCI based SATA controller support to APQ8064.
Tested on IFC6410 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds USB OTG support on USB1 of APQ8064 SOC.
Tested on IFC6410 with ethernet gadget.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds device tree nodes to support two usb hosts on APQ8064
SOC.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds rpm node to apq8064 dt as rpm would be used by other
devices for regulator support.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch fixes compilation error if CONFIG_DEBUG_FORCE_WEAK_PER_CPU is
enabled. This is possible wirh randomconfig, so fix it before it blows
off.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures, to provide the
C-State information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest of low power mode sequence and brings the core
out of low power mode.
The SPM has a set of control registers that configure the SPMs
individually based on the type of the core and the runtime conditions.
SPM is a finite state machine block to which a sequence is provided and
it interprets the bytes and executes them in sequence. Each low power
mode that the core can enter into is provided to the SPM as a sequence.
Configure the SPM to set the core (cpu or L2) into its low power mode,
the index of the first command in the sequence is set in the SPM_CTL
register. When the core executes ARM wfi instruction, it triggers the
SPM state machine to start executing from that index. The SPM state
machine waits until the interrupt occurs and starts executing the rest
of the sequence until it hits the end of the sequence. The end of the
sequence jumps the core out of its low power mode.
Add support for an idle driver to set up the SPM to place the core in
Standby or Standalone power collapse mode when the core is idle.
Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
Original tree available at -
git://codeaurora.org/quic/la/kernel/msm-3.10.git
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Set the warmboot address using an SCM call, only if the new address is
different than the old one.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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The atomic SCM APIs are useful for commands that are guaranteed by the
secure side to be uninterruptable, atomic and SMP safe. The calling
convention use registers for passing parameters and return values between
the secure and non-secure side. Support this interface with
scm_call_atomic[1-2]() functions corresponding to the number of arguments
passed.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Architectural changes in the ARM Linux kernel tree mandate the eventual
removal of the mach-* directories. Move the scm driver to
drivers/soc/qcom and the scm header to include/soc/qcom to support that
removal.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an error occurs we
have no idea what actually failed within the secure environment.
Add a logging statement that will log the actual error code from scm call
allowing us to easily determine what caused the error to occur.
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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