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2015-03-18arm64: Add support for on-demand backtrace of other CPUsdev/arm64_nmi-v4.0Daniel Thompson
Currently arm64 has no implementation of arch_trigger_all_cpu_backtace. The patch provides one for arm64 systems that are built with CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS (i.e. those that have a pseudo-NMI). Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18arm64: irqflags: Automatically identify I bit mis-managementDaniel Thompson
This is self-test code to identify circumstances where the I bit is set by hardware but no software exists to copy its state to the PMR. I don't really expect this patch to be retained much after the RFC stage. However I have included it in this RFC series to document the testing I have done and to allow further testing under different workloads. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18arm64: irqflags: Use ICC sysregs to implement IRQ maskingDaniel Thompson
Currently irqflags is implemented using the PSR's I bit. It is possible to implement irqflags by using the co-processor interface to the GIC. Using the co-processor interface makes it feasible to simulate NMIs using GIC interrupt prioritization. This patch changes the irqflags macros to modify, save and restore ICC_PMR_EL1. This has a substantial knock on effect for the rest of the kernel. There are three reasons for this: 1. The state of the ICC_PMR_EL1_G_BIT becomes part of the CPU context and must be saved and restored during traps. To simplify the additional context management the ICC_PMR_EL1_G_BIT is converted into a fake (reserved) bit within the PSR (PSR_G_BIT). Naturally this approach will need to be changed if future ARM architecture extensions make use of this bit. 2. The hardware automatically masks the I bit (at boot, during traps, etc). When the I bit is set by hardware we must add code to switch from I bit masking and PMR masking. 3. Some instructions, noteably wfi, require that the PMR not be used for interrupt masking. Before calling these instructions we must switch from PMR masking to I bit masking. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18arm64: irqflags: Reorder the fiq & async macrosDaniel Thompson
Separate out the local fiq & async macros from the various arch inlines. This makes is easier for us (in a later patch) to provide an alternative implementation of these inlines. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18irqchip: gic-v3: Reset BPR during initializationDaniel Thompson
Currently, when running on FVP, CPU 0 boots up with its BPR changed from the reset value. This renders it impossible to (preemptively) prioritize interrupts on CPU 0. This is harmless on normal systems but prevents preemption by NMIs on systems with CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS enabled. Many thanks to Andrew Thoelke for suggesting the BPR as having the potential to harm preemption. Suggested-by: Andrew Thoelke <andrew.thoelke@arm.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18printk: Simple implementation for NMI backtracingDaniel Thompson
Currently there is a quite a pile of code sitting in arch/x86/kernel/apic/hw_nmi.c to support safe all-cpu backtracing from NMI. The code is inaccessible to backtrace implementations for other architectures, which is a shame because they would probably like to be safe too. Copy this code into printk, reworking it a little as we do so to make it easier to exploit as library code. We'll port the x86 NMI backtrace logic to it in a later patch. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-18serial: Emulate break using control charactersDaniel Thompson
Currently the magic SysRq functions can accessed by sending a break on the serial port. Unfortunately some networked serial proxies make it difficult to send a break meaning SysRq functions cannot be used. This patch provides a workaround by allowing the (fairly unlikely) sequence of ^B^R^K characters to emulate a real break. This approach is very nearly as robust as normal sysrq/break handling because all trigger recognition happens during interrupt handling. Only major difference is that to emulate a break we must enter the ISR four times (instead of twice) and manage an extra byte of state. No means is provided to escape the trigger sequence (and pass ^B^R^K to the underlying process) however the sequence is proved reasonably pretty collision resistant in practice. The most significant consequence is that ^B and ^B^R are delayed until a new character is observed. The most significant collision I am aware of is with emacs-like backward-char bindings (^B) because the character movement will become lumpy (two characters every two key presses rather than one character per key press). Arrow keys or ^B^B^F provide workarounds. Special note for tmux users: tmux defaults to using ^B as its escape character but does not have a default binding for ^B^R. Likewise tmux had no visual indicator showing the beginning of break sequence meaning delayed the delivery of ^B is not observable. Thus serial break emulation does not interfere with the use of tmux's default key bindings. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-03-17Merge branch 'tracking-ilp32' into merge-linux-linaroAndrey Konovalov
2015-03-17Automatically merging tracking-llvm into merge-linux-linaroAndrey Konovalov
Conflicting files:
2015-03-17Merge branch 'tracking-armlt-juno-cpufreq' into integration-linaro-vexpress64Jon Medhurst
2015-03-17Merge branch 'tracking-armlt-config64' into integration-linaro-vexpress64Jon Medhurst
Conflicts: linaro/configs/vexpress64.conf
2015-03-17Merge branch 'tracking-armlt-arm64' into integration-linaro-vexpress64Jon Medhurst
2015-03-16Merge branch 'tracking-llct-misc-fixes' into merge-linux-linaro-core-trackingAndrey Konovalov
2015-03-16Merge branch 'tracking-linaro-builddeb-tweaks' into ↵Andrey Konovalov
merge-linux-linaro-core-tracking
2015-03-16Merge branch 'tracking-gator' into merge-linux-linaro-core-trackingAndrey Konovalov
2015-03-16Merge branch 'tracking-linaro-android-llct' into ↵Andrey Konovalov
merge-linux-linaro-core-tracking
2015-03-16Merge branch 'tracking-basic-board-configs' into ↵Andrey Konovalov
merge-linux-linaro-core-tracking
2015-03-16Merge branch 'tracking-core-configs' into merge-linux-linaro-core-trackingAndrey Konovalov
2015-03-16ARM: Exynos: Fix build error with thumb2Andrey Konovalov
Add non-global symbols to avoid build failure in thumb2 mode. Exact the same issue and the fix as in [1]; just the variables are different. [1] http://lists.linaro.org/pipermail/linaro-kernel/2014-June/015227.html Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
2015-03-16mailbox: mhu: Initialise all members of struct mbox_clientJon Medhurst
Failure to do so means means we may end up using uninitialised values if new members are added, leading to bugs; as happens with commit 97b0c7bd2e86 (mailbox: add tx_prepare client callback). Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16dts: juno: Add SCPI and cpufreq nodesJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16dts: juno: Add mailbox nodesJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16dts: juno: Add cpu-map nodesJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16scpi: Increase the maximum number of DVFS OPPsFilipe Rinaldi
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16scpi: Add voltage on the DVFS Info commandFilipe Rinaldi
Newer versions of SCP added voltage as one of the parameters in the DVFS Info command. This patch reads the voltage which can be used by CPUFreq and Devfreq. Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: mhu: Update for new version of mailbox patchesJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: mhu: Replace use of devm_request_and_ioremap()Jon Medhurst
This deprecated API is removed in Linux 3.17 Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: Remove all message timeouts and block until they completeJon Medhurst
Neither the mailbox framework nor the scpi_protocol code correctly handle timeouts if a message is subsequently completed by the SCP, in that case they end up accessing no-longer live stack based objects. Even if the code was reworked to fix those issues, we are still left with problems with the scpi protocol because a delayed message response may look like a reply to a later message. To hopefully avoid all these problems this patch removes all timeouts and forces things block until each message completes. Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: mhu: Acknowledge the interrupt only after data is pushedLiviu Dudau
According to the mailbox documentation the controller should ACK the RX only after it has finished pushing the data up the link. Signed-off-by: Punit Agrawal <Punit.Agrawal@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: scpi: Free the mailbox channel when we fail to queue a message.Liviu Dudau
When sending an SCPI command we aquire a channel and queue the message in the mailbox. If the queuing failed we were not releasing the channel hence preventing everyone else from using it. Signed-off-by: Punit Agrawal <Punit.Agrawal@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: Pack SCPI structures used for messages.Liviu Dudau
The System Control Processor expects data sent in the messages to be contiguos. When using unpacked structures to describe the data being transmitted we increase the general size of the message which leads to SCP rejecting our request. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16arm64: topology: Use new name for SCHED_POWER_SHIFTJon Medhurst
Commit ca8ce3d0b1 (sched: Final power vs. capacity cleanups) renamed SCHED_POWER_SHIFT to SCHED_CAPACITY_SHIFT so we need to use that name. Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16cpufreq: Enable big.LITTLE cpufreq driver on arm64Mark Brown
There are arm64 big.LITTLE systems so enable the big.LITTLE cpufreq driver. While IKS is not available for these systems the driver is still useful since it manages clusters with shared frequencies which is the common case for these systems. Long term combining the cpufreq-cpu0 and big.LITTLE drivers may be a more sensible option but that is substantially more complex especially in the case of IKS. Signed-off-by: Mark Brown <broonie@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (cherry picked from commit 4920ab84979d8cd2eb7e3c4fefcc924efabf1cb2) Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16arm64: Add big.LITTLE switcher stubMark Brown
The big.LITTLE cpufreq driver is useful on arm64 big.LITTLE systems even without IKS support since it implements support for clusters with shared clocks (a common big.LITTLE configuration). In order to allow it to be built provide the non-IKS stubs for arm64, enabling cpufreq with all the cores available. It may make sense to make an asm-generic version of these stubs instead but given that there's only likely to be these two architectures using the code and asm-generic stubs also need per architecture updates it's probably more trouble than it's worth. Signed-off-by: Mark Brown <broonie@linaro.org>
2015-03-16[HACK] cpufreq: arm_big_little: Fall back to getting clock from cpu deviceJon Medhurst
The driver in LSK assumes a hard-coded name for cluster clock, as used by vexpress TC2. Modify this to allow also clocks to be obtained from the cpu device; as Juno requires and as seems more like the correct way. Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16cpufreq: arm_big_little: add SPCI interface driverSudeep Holla
On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control including CPU DVFS. SCPI Message Protocol is used to communicate with the SCPI. This patch adds a interface driver for adding OPPs and registering the arm_big_little cpufreq driver for such systems. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16clk: add support for clocks provided by system control processorSudeep Holla
On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Power Interface(SCPI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. This patch adds support for the clocks provided by SCP using SCPI protocol. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: get mhu driver working with new (v7) mailbox frameworkJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: add support for System Control and Power Interface(SCPI) protocolSudeep Holla
This patch add supports for System Control and Power Interface (SCPI) Message Protocol used between the Application Cores(AP) and the System Control Processor(SCP). The MHU peripheral provides a mechanism for inter-processor communication between SCP's M3 processor and AP. SCP offers control and management of the core/cluster power states, various power domain DVFS including the core/cluster, certain system clocks configuration, thermal sensors and many others. This protocol library provides interface for all the client drivers using SCPI to make use of the features offered by the SCP. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16mailbox: add support for ARM Message Handling Unit(MHU) controllerSudeep Holla
This patch adds support for ARM Message Handling Unit(MHU) controller that provides control logic and interrupt generation to support inter-processor communication between the Application Processor and the System Control Processor(SCP). This support is built on the existing common mailbox framework for client/protocol drivers and controller drivers of Inter Processor Communication(IPC). SCP controls most of the power managament on the Application Processors. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16arm64: topology: Provide relative power numbers for coresMark Brown
Provide performance numbers to the scheduler to help it fill the cores in the system on big.LITTLE systems. With the current scheduler this may perform poorly for applications that try to do OpenMP style work over all cores but should help for more common workloads. The current 32 bit ARM implementation provides a similar estimate so this helps ensure that work to improve big.LITTLE systems on ARMv7 systems performs similarly on ARMv8 systems. The power numbers are the same as for ARMv7 since it seems that the expected differential between the big and little cores is very similar on both ARMv7 and ARMv8. In both ARMv7 and ARMv8 cases the numbers were based on the published DMIPS numbers. These numbers are just an initial and basic approximation for use with the current scheduler, it is likely that both experience with silicon and ongoing work on improving the scheduler will lead to further tuning or will tune automatically at runtime and so make the specific choice of numbers here less critical. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16configs: vexpress64: Enable cpufreqJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16arm64: topology: Tell the scheduler about the relative power of coresMark Brown
In heterogeneous systems like big.LITTLE systems the scheduler will be able to make better use of the available cores if we provide power numbers to it indicating their relative performance. Do this by parsing the CPU nodes in the DT. This code currently has no effect as no information on the relative performance of the cores is provided. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16configs: vexpress64: Enable devices used on JunoJon Medhurst
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16vexpress64.conf: enable CONFIG_PREEMPT to workaround boot failureAndrey Konovalov
The workaround to disable CONFIG_CPU_IDLE doesn't work for all the models. Let's use the other one. Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
2015-03-16vexpress64.conf: disable CONFIG_CPU_IDLE to workaround boot failureFathi Boudra
There's a known issue with ARM trusted firmware: CPU idle does not work on the advertised version of the Foundation FVP. Some FVP fixes are required that are not available externally at the time of writing. Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
2015-03-16configs: vexpress64: Enable CPU hotplugJon Medhurst
And up to 8 rather than the default 4 CPUs. Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16configs: vexpress64: Enable CONFIG_COMPATAndrey Konovalov
Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
2015-03-16configs: vexpress: Enable the RTCJon Medhurst
The AEMv8 model supports this, so lets enable it. Signed-off-by: Jon Medhurst <tixy@linaro.org>
2015-03-16configs: vexpress64: Disable CONFIG_SERIO_I8042Jon Medhurst
This defaults to 'y' but produces a kernel oops at boot. Perhaps ARM64 should be added to the long list of architectures excluded in drivers/input/serio/Kconfig. Signed-off-by: Jon Medhurst <tixy@linaro.org>