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Diffstat (limited to 'arch/tile/include/asm/pci.h')
-rw-r--r--arch/tile/include/asm/pci.h22
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 54a924208d3c..dfedd7ac7298 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -17,7 +17,6 @@
#include <linux/dma-mapping.h>
#include <linux/pci.h>
-#include <linux/numa.h>
#include <asm-generic/pci_iomap.h>
#ifndef __tilegx__
@@ -29,7 +28,6 @@ struct pci_controller {
int index; /* PCI domain number */
struct pci_bus *root_bus;
- int first_busno;
int last_busno;
int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
@@ -124,6 +122,11 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
* the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
* devices, we create a separate map region that handles the low
* 4GB.
+ *
+ * This design lets us avoid the "PCI hole" problem where the host bridge
+ * won't pass DMA traffic with target addresses that happen to fall within the
+ * BAR space. This enables us to use all the physical memory for DMA, instead
+ * of wasting the same amount of physical memory as the BAR window size.
*/
#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())
@@ -145,6 +148,10 @@ struct pci_controller {
int pio_mem_index; /* PIO region index for memory access */
+#ifdef CONFIG_TILE_PCI_IO
+ int pio_io_index; /* PIO region index for I/O space access */
+#endif
+
/*
* Mem-Map regions for all the memory controllers so that Linux can
* map all of its physical memory space to the PCI bus.
@@ -154,6 +161,10 @@ struct pci_controller {
int index; /* PCI domain number */
struct pci_bus *root_bus;
+ /* PCI I/O space resource for this controller. */
+ struct resource io_space;
+ char io_space_name[32];
+
/* PCI memory space resource for this controller. */
struct resource mem_space;
char mem_space_name[32];
@@ -166,13 +177,11 @@ struct pci_controller {
/* Table that maps the INTx numbers to Linux irq numbers. */
int irq_intx_table[4];
-
- /* Address ranges that are routed to this controller/bridge. */
- struct resource mem_resources[3];
};
extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
+extern int num_trio_shims;
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
@@ -211,7 +220,8 @@ static inline int pcibios_assign_all_busses(void)
}
#define PCIBIOS_MIN_MEM 0
-#define PCIBIOS_MIN_IO 0
+/* Minimum PCI I/O address, starting at the page boundary. */
+#define PCIBIOS_MIN_IO PAGE_SIZE
/* Use any cpu for PCI. */
#define cpumask_of_pcibus(bus) cpu_online_mask