diff options
Diffstat (limited to 'arch/arm')
698 files changed, 24677 insertions, 20004 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1c5021002fe4..72ad724c67ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -188,6 +188,9 @@ config ARCH_HAS_ILOG2_U64 config ARCH_HAS_BANDGAP bool +config FIX_EARLYCON_MEM + def_bool y if MMU + config GENERIC_HWEIGHT bool default y @@ -268,7 +271,6 @@ config PHYS_OFFSET depends on !ARM_PATCH_PHYS_VIRT default DRAM_BASE if !MMU default 0x00000000 if ARCH_EBSA110 || \ - EP93XX_SDCE3_SYNC_PHYS_OFFSET || \ ARCH_FOOTBRIDGE || \ ARCH_INTEGRATOR || \ ARCH_IOP13XX || \ @@ -277,10 +279,7 @@ config PHYS_OFFSET default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x20000000 if ARCH_S5PV210 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET - default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100 - default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET - default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET - default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET + default 0xc0000000 if ARCH_SA1100 help Please provide the physical address corresponding to the location of main memory in your system. @@ -418,11 +417,14 @@ config ARCH_EP93XX bool "EP93xx-based" select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_REQUIRE_GPIOLIB - select ARCH_USES_GETTIMEOFFSET select ARM_AMBA + select ARM_PATCH_PHYS_VIRT select ARM_VIC + select AUTO_ZRELADDR select CLKDEV_LOOKUP + select CLKSRC_MMIO select CPU_ARM920T + select GENERIC_CLOCKEVENTS help This enables support for the Cirrus EP93xx series of CPUs. @@ -536,6 +538,7 @@ config ARCH_ORION5X select MVEBU_MBUS select PCI select PLAT_ORION_LEGACY + select MULTI_IRQ_HANDLER help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), @@ -1496,6 +1499,7 @@ config HOTPLUG_CPU config ARM_PSCI bool "Support for the ARM Power State Coordination Interface (PSCI)" depends on CPU_V7 + select ARM_PSCI_FW help Say Y here if you want Linux to communicate with system firmware implementing the PSCI specification for CPU-centric power @@ -1700,13 +1704,24 @@ config HIGHPTE consumed by page tables. Setting this option will allow user-space 2nd level page tables to reside in high memory. -config HW_PERF_EVENTS - bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS +config CPU_SW_DOMAIN_PAN + bool "Enable use of CPU domains to implement privileged no-access" + depends on MMU && !ARM_LPAE default y help - Enable hardware performance counter support for perf events. If - disabled, perf events will use software events only. + Increase kernel security by ensuring that normal kernel accesses + are unable to access userspace addresses. This can help prevent + use-after-free bugs becoming an exploitable privilege escalation + by ensuring that magic values (such as LIST_POISON) will always + fault when dereferenced. + + CPUs with low-vector mappings use a best-efforts implementation. + Their lower 1MB needs to remain accessible for the vectors, but + the remainder of userspace will become appropriately inaccessible. + +config HW_PERF_EVENTS + def_bool y + depends on ARM_PMU config SYS_SUPPORTS_HUGETLBFS def_bool y @@ -2005,6 +2020,7 @@ config KEXEC bool "Kexec system call (EXPERIMENTAL)" depends on (!SMP || PM_SLEEP_SMP) depends on !CPU_V7M + select KEXEC_CORE help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index a2e16f940394..0cfd7f947f6b 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -141,6 +141,12 @@ choice depends on ARCH_AT91 depends on SOC_SAMA5 + config AT91_DEBUG_LL_DBGU3 + bool "Kernel low-level debugging on sama5d2" + select DEBUG_AT91_UART + depends on ARCH_AT91 + depends on SOC_SAMA5 + config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" depends on ARCH_BCM2835 @@ -411,6 +417,13 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6SX. + config DEBUG_IMX6UL_UART + bool "i.MX6UL Debug UART" + depends on SOC_IMX6UL + help + Say Y here if you want kernel low-level debugging support + on i.MX6UL. + config DEBUG_IMX7D_UART bool "i.MX7D Debug UART" depends on SOC_IMX7D @@ -1269,6 +1282,7 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ + DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART default 1 depends on ARCH_MXC @@ -1320,6 +1334,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ + DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART default "debug/ks8695.S" if DEBUG_KS8695_UART default "debug/msm.S" if DEBUG_QCOM_UARTDM diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 7a13aebacf81..3f9a9ebc77c3 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -51,10 +51,6 @@ else endif endif -ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y) -OBJS += head-shmobile.o -endif - # # We now have a PIC decompressor implementation. Decompressors running # from RAM should not define ZTEXTADDR. Decompressors running directly diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index bd245d34952d..a0765e7ed6c7 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -57,5 +57,5 @@ extern char * strstr(const char * s1, const char *s2); int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) { - return decompress(input, len, NULL, NULL, output, NULL, error); + return __decompress(input, len, NULL, NULL, output, 0, NULL, error); } diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S deleted file mode 100644 index 22a75259faa3..000000000000 --- a/arch/arm/boot/compressed/head-shmobile.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * The head-file for SH-Mobile ARM platforms - * - * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * Simon Horman <horms@verge.net.au> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifdef CONFIG_ZBOOT_ROM - - .section ".start", "ax" - - /* load board-specific initialization code */ -#include <mach/zboot.h> - - adr r0, dtb_info - ldmia r0, {r1, r3, r4, r5, r7} - - sub r0, r0, r1 @ calculate the delta offset - add r5, r5, r0 @ _edata - - ldr lr, [r5, #0] @ check if valid DTB is present - cmp lr, r3 - bne 0f - - add r9, r7, #31 @ rounded up to a multiple - bic r9, r9, #31 @ ... of 32 bytes - - add r6, r9, r5 @ copy from _edata - add r9, r9, r4 @ to MEMORY_START - -1: ldmdb r6!, {r0 - r3, r10 - r12, lr} - cmp r6, r5 - stmdb r9!, {r0 - r3, r10 - r12, lr} - bhi 1b - - /* Success: Zero board ID, pointer to start of memory for atag/dtb */ - mov r7, #0 - mov r8, r4 - b 2f - - .align 2 -dtb_info: - .word dtb_info -#ifndef __ARMEB__ - .word 0xedfe0dd0 @ sig is 0xd00dfeed big endian -#else - .word 0xd00dfeed -#endif - .word MEMORY_START - .word _edata - .word 0x4000 @ maximum DTB size -0: - /* Failure: Zero board ID, NULL atag/dtb */ - mov r7, #0 - mov r8, #0 @ pass null pointer as atag -2 : - -#endif /* CONFIG_ZBOOT_ROM */ diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..233159d2eaab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \ at91sam9x35ek.dtb dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2.dtb \ + at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ sama5d31ek.dtb \ sama5d33ek.dtb \ @@ -176,6 +177,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-km_kirkwood.dtb \ kirkwood-laplug.dtb \ kirkwood-lschlv2.dtb \ + kirkwood-lswvl.dtb \ + kirkwood-lswxl.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ @@ -211,6 +214,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ @@ -331,6 +335,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb.dtb +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb dtb-$(CONFIG_SOC_LS1021A) += \ @@ -390,6 +396,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-cm-t3530.dtb \ omap3-cm-t3730.dtb \ omap3-devkit8000.dtb \ + omap3-devkit8000-lcd43.dtb \ + omap3-devkit8000-lcd70.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ omap3-gta04a3.dtb \ @@ -409,15 +417,19 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-overo-alto35.dtb \ omap3-overo-chestnut43.dtb \ omap3-overo-gallop43.dtb \ + omap3-overo-palo35.dtb \ omap3-overo-palo43.dtb \ omap3-overo-storm-alto35.dtb \ omap3-overo-storm-chestnut43.dtb \ omap3-overo-storm-gallop43.dtb \ + omap3-overo-storm-palo35.dtb \ omap3-overo-storm-palo43.dtb \ omap3-overo-storm-summit.dtb \ omap3-overo-storm-tobi.dtb \ + omap3-overo-storm-tobiduo.dtb \ omap3-overo-summit.dtb \ omap3-overo-tobi.dtb \ + omap3-overo-tobiduo.dtb \ omap3-pandora-600mhz.dtb \ omap3-pandora-1ghz.dtb \ omap3-sbc-t3517.dtb \ @@ -426,6 +438,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-thunder.dtb \ omap3-zoom3.dtb dtb-$(CONFIG_SOC_TI81XX) += \ + dm8148-evm.dtb \ + dm8148-t410.dtb \ dm8168-evm.dtb dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir5221.dtb \ @@ -438,7 +452,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-nano.dtb \ am335x-pepper.dtb \ am335x-lxm.dtb \ - am335x-chiliboard.dtb + am335x-chiliboard.dtb \ + am335x-wega-rdk.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-duovero-parlor.dtb \ omap4-panda.dtb \ @@ -464,6 +479,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-linkstation-lswtgl.dtb \ + orion5x-lswsgl.dtb \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ @@ -488,7 +505,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ - rk3288-firefly.dtb + rk3288-firefly.dtb \ + rk3288-r89.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-minnie.dtb \ + rk3288-veyron-pinky.dtb \ + rk3288-veyron-speedy.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ @@ -501,11 +523,8 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-smdkv210.dtb \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ - r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ - r8a7778-bockw-reference.dtb \ - r8a7779-marzen.dtb \ - sh73a0-kzm9g.dtb + r8a7778-bockw-reference.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ @@ -516,12 +535,15 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ + r8a7793-gose.dtb \ r8a7794-alt.dtb \ + r8a7794-silk.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_vt.dtb @@ -544,7 +566,9 @@ dtb-$(CONFIG_ARCH_STI) += \ stih416-b2020.dtb \ stih416-b2020e.dtb \ stih418-b2199.dtb -dtb-$(CONFIG_ARCH_STM32)+= stm32f429-disco.dtb +dtb-$(CONFIG_ARCH_STM32)+= \ + stm32f429-disco.dtb \ + stm32429i-eval.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ @@ -554,6 +578,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-hackberry.dtb \ sun4i-a10-hyundai-a7hd.dtb \ sun4i-a10-inet97fv2.dtb \ + sun4i-a10-itead-iteaduino-plus.dts \ sun4i-a10-jesurun-q5.dtb \ sun4i-a10-marsboard.dtb \ sun4i-a10-mini-xplus.dtb \ @@ -601,6 +626,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-ippo-q8h-v1.2.dtb \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ @@ -642,10 +668,11 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ph1-sld3-ref.dtb \ uniphier-ph1-ld4-ref.dtb \ + uniphier-ph1-ld6b-ref.dtb \ uniphier-ph1-pro4-ref.dtb \ - uniphier-ph1-sld8-ref.dtb + uniphier-ph1-sld3-ref.dtb \ + uniphier-ph1-sld8-ref.dtb dtb-$(CONFIG_ARCH_VERSATILE) += \ versatile-ab.dtb \ versatile-pb.dtb @@ -705,6 +732,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ dove-dove-db.dtb \ dove-sbc-a510.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ mt6592-evb.dtb \ mt8127-moose.dtb \ diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 5c42d259fa68..eadbba32386d 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -68,16 +68,26 @@ &lcdc { status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; }; -/ { - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; +&i2c0 { + tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; pinctrl-names = "default", "off"; pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - status = "okay"; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 765be2766eb0..1942a5c8132d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -136,16 +136,29 @@ }; sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-EVM"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <12000000>; + }; }; }; @@ -342,7 +355,7 @@ >; }; - am335x_evm_audio_pins: am335x_evm_audio_pins { + mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -351,6 +364,15 @@ >; }; + mcasp1_pins_sleep: mcasp1_pins_sleep { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ @@ -460,6 +482,7 @@ }; tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; @@ -575,19 +598,21 @@ #include "tps65910.dtsi" &mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&am335x_evm_audio_pins>; + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; - status = "okay"; + status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; }; &tps { diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 156d05efcb70..315bb02c9920 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -141,14 +141,26 @@ }; sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-EVMSK"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <24000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVMSK"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; }; panel { @@ -396,6 +408,15 @@ >; }; + mcasp1_pins_sleep: mcasp1_pins_sleep { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ @@ -462,6 +483,7 @@ }; tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; @@ -661,19 +683,21 @@ }; &mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; - status = "okay"; + status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; }; &tscadc { diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi new file mode 100644 index 000000000000..4d28fc3aac69 --- /dev/null +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am33xx.dtsi" + +/ { + model = "Phytec AM335x phyCORE"; + compatible = "phytec,am335x-phycore-som", "ti,am33xx"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rtc; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + }; +}; + +/* Crypto Module */ +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet0_pins: pinmux_ethernet0 { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + mdio_pins: pinmux_mdio { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins>; + status = "okay"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +/* I2C Busses */ +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0 { + pinctrl-single,pins = < + 0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: pmic@2d { + reg = <0x2d>; + }; + + i2c_eeprom: eeprom@52 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + status = "disabled"; + }; + + i2c_rtc: rtc@68 { + compatible = "rv4162"; + reg = <0x68>; + status = "disabled"; + }; +}; + +/* NAND memory */ +&am33xx_pinmux { + nandflash_pins: pinmux_nandflash { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ + nandflash: nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,cycle2cycle-diffcsen; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <30>; + gpmc,wr-data-mux-bus-ns = <0>; + + elm_id = <&elm>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "xload"; + reg = <0x0 0x20000>; + }; + partition@1 { + label = "xload_backup1"; + reg = <0x20000 0x20000>; + }; + partition@2 { + label = "xload_backup2"; + reg = <0x40000 0x20000>; + }; + partition@3 { + label = "xload_backup3"; + reg = <0x60000 0x20000>; + }; + partition@4 { + label = "barebox"; + reg = <0x80000 0x80000>; + }; + partition@5 { + label = "bareboxenv"; + reg = <0x100000 0x40000>; + }; + partition@6 { + label = "oftree"; + reg = <0x140000 0x40000>; + }; + partition@7 { + label = "kernel"; + reg = <0x180000 0x800000>; + }; + partition@8 { + label = "root"; + reg = <0x980000 0x0>; + }; + }; +}; + +/* Power */ +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "vdig1_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; +}; + +/* SPI Busses */ +&am33xx_pinmux { + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + serial_flash: m25p80@0 { + compatible = "m25p80"; + spi-max-frequency = <48000000>; + reg = <0x0>; + m25p,fast-read; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "xload"; + reg = <0x0 0x20000>; + }; + partition@1 { + label = "barebox"; + reg = <0x20000 0x80000>; + }; + partition@2 { + label = "bareboxenv"; + reg = <0xa0000 0x20000>; + }; + partition@3 { + label = "oftree"; + reg = <0xc0000 0x20000>; + }; + partition@4 { + label = "kernel"; + reg = <0xe0000 0x0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-wega-rdk.dts b/arch/arm/boot/dts/am335x-wega-rdk.dts new file mode 100644 index 000000000000..6431b7db8109 --- /dev/null +++ b/arch/arm/boot/dts/am335x-wega-rdk.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-wega.dtsi" + +/* SoM */ +&i2c_eeprom { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi new file mode 100644 index 000000000000..5e541bd1b45a --- /dev/null +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + model = "Phytec AM335x phyBOARD-WEGA"; + compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; + +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + 0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + 0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + 0x40 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + 0x48 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + 0x4c (PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + 0x50 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + 0x54 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_pins ðernet1_pins>; + dual_emac = <1>; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +/* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 21fcc440fc1a..d23e2524d694 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -103,6 +103,15 @@ #size-cells = <1>; ranges = <0 0x44c00000 0x280000>; + wkup_m3: wkup_m3@100000 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x100000 0x4000>, + <0x180000 0x2000>; + reg-names = "umem", "dmem"; + ti,hwmods = "wkup_m3"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + prcm: prcm@200000 { compatible = "ti,am3-prcm"; reg = <0x200000 0x4000>; @@ -144,6 +153,14 @@ }; }; + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + scm_clockdomains: clockdomains { }; }; @@ -210,7 +227,7 @@ }; uart0: serial@44e09000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; @@ -221,7 +238,7 @@ }; uart1: serial@48022000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; @@ -232,7 +249,7 @@ }; uart2: serial@48024000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; @@ -243,7 +260,7 @@ }; uart3: serial@481a6000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; @@ -252,7 +269,7 @@ }; uart4: serial@481a8000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; @@ -261,7 +278,7 @@ }; uart5: serial@481aa000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; @@ -700,7 +717,7 @@ }; mac: ethernet@4a100000 { - compatible = "ti,cpsw"; + compatible = "ti,am335x-cpsw","ti,cpsw"; ti,hwmods = "cpgmac0"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; @@ -762,14 +779,6 @@ reg = <0x40300000 0x10000>; /* 64k */ }; - wkup_m3: wkup_m3@44d00000 { - compatible = "ti,am3353-wkup-m3"; - reg = <0x44d00000 0x4000 /* M3 UMEM */ - 0x44d80000 0x2000>; /* M3 DMEM */ - ti,hwmods = "wkup_m3"; - ti,no-reset-on-init; - }; - elm: elm@48080000 { compatible = "ti,am3352-elm"; reg = <0x48080000 0x2000>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ade28c790f4b..0447c04a40cc 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -23,6 +23,11 @@ i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; }; @@ -59,6 +64,27 @@ interrupt-parent = <&gic>; }; + scu: scu@48240000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x48240000 0x100>; + }; + + global_timer: timer@48240200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x48240200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&dpll_mpu_m2_ck>; + }; + + local_timer: timer@48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x100>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&dpll_mpu_m2_ck>; + }; + l2-cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; @@ -83,9 +109,19 @@ #size-cells = <1>; ranges = <0 0x44c00000 0x287000>; + wkup_m3: wkup_m3@100000 { + compatible = "ti,am4372-wkup-m3"; + reg = <0x100000 0x4000>, + <0x180000 0x2000>; + reg-names = "umem", "dmem"; + ti,hwmods = "wkup_m3"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + prcm: prcm@1f0000 { compatible = "ti,am4-prcm"; reg = <0x1f0000 0x11000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; prcm_clocks: clocks { #address-cells = <1>; @@ -127,6 +163,14 @@ }; }; + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am4372-wkup-m3-ipc"; + reg = <0x1324 0x44>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + scm_clockdomains: clockdomains { }; }; @@ -308,11 +352,14 @@ }; rtc: rtc@44e3e000 { - compatible = "ti,am4372-rtc","ti,da830-rtc"; + compatible = "ti,am4372-rtc", "ti,am3352-rtc", + "ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "rtc"; + clocks = <&clk_32768_ck>; + clock-names = "int-clk"; status = "disabled"; }; @@ -527,8 +574,11 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, + <&dpll_clksel_mac_clk>; + clock-names = "fck", "cpts", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; status = "disabled"; cpdma_channels = <8>; ale_entries = <1024>; @@ -865,7 +915,12 @@ usb1: usb@48390000 { compatible = "synopsys,dwc3"; reg = <0x48390000 0x10000>; - interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; phys = <&usb2_phy1>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; @@ -889,7 +944,12 @@ usb2: usb@483d0000 { compatible = "synopsys,dwc3"; reg = <0x483d0000 0x10000>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; phys = <&usb2_phy2>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 84aa30c3235a..22038f21f228 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -21,12 +21,11 @@ aliases { display0 = &lcd0; - serial3 = &uart3; }; - vmmcsd_fixed: fixedregulator-sd { + evm_v3_3d: fixedregulator-v3_3d { compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; + regulator-name = "evm_v3_3d"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; @@ -83,17 +82,6 @@ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - /* - * SelLCDorHDMI, LOW to select HDMI. This is not really the - * panel's enable GPIO, but we don't have HDMI driver support nor - * support to switch between two displays, so using this gpio as - * panel's enable should be safe. - */ - enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - panel-timing { clock-frequency = <33000000>; hactive = <800>; @@ -124,6 +112,39 @@ clock-frequency = <12000000>; }; + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM437x-GP-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <12000000>; + }; + }; }; &am43xx_pinmux { @@ -217,7 +238,6 @@ nand_flash_x8: nand_flash_x8 { pinctrl-single,pins = < - 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ @@ -270,7 +290,7 @@ >; }; - lcd_pins: lcd_pins { + display_mux_pins: display_mux_pins { pinctrl-single,pins = < /* GPIO 5_8 to select LCD / HDMI */ 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -409,6 +429,60 @@ 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ >; }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_sleep_pins: mcasp1_sleep_pins { + pinctrl-single,pins = < + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + gpio0_pins: gpio0_pins { + pinctrl-single,pins = < + 0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ + >; + }; + + emmc_pins_default: emmc_pins_default { + pinctrl-single,pins = < + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + >; + }; + + emmc_pins_sleep: emmc_pins_sleep { + pinctrl-single,pins = < + 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ + 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ + 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ + 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ + 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + 0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ + 0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ + >; + }; }; &i2c0 { @@ -455,6 +529,8 @@ regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; }; dcdc6: regulator-dcdc6 { @@ -462,6 +538,8 @@ regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; ldo1: regulator-ldo1 { @@ -521,6 +599,19 @@ }; }; }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */ + AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ + DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ + DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ + }; }; &epwmss0 { @@ -542,7 +633,23 @@ }; &gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins>; status = "okay"; + + p23 { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + /* SelEMMCorNAND selects between eMMC and NAND: + * Low: NAND + * High: eMMC + * When changing this line make sure the newly + * selected device node is enabled and the previously + * selected device node is disabled. + */ + output-low; + line-name = "SelEMMCorNAND"; + }; }; &gpio1 { @@ -558,19 +665,48 @@ }; &gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; status = "okay"; ti,no-reset-on-init; + + p8 { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; }; &mmc1 { status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; + vmmc-supply = <&evm_v3_3d>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; +/* eMMC sits on mmc2 */ +&mmc2 { + /* + * When enabling eMMC, disable GPMC/NAND and set + * SelEMMCorNAND to output-high + */ + status = "disabled"; + vmmc-supply = <&evm_v3_3d>; + bus-width = <8>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_sleep>; + ti,non-removable; +}; + &mmc3 { status = "okay"; /* these are on the crossbar and are outlined in the @@ -651,6 +787,10 @@ }; &gpmc { + /* + * When enabling GPMC, disable eMMC and set + * SelEMMCorNAND to output-low + */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; @@ -790,3 +930,27 @@ }; }; }; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 378344271746..af25801418b4 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -110,6 +110,13 @@ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; }; }; + + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; }; &am43xx_pinmux { @@ -394,6 +401,8 @@ }; &rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; status = "okay"; }; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index c17097d2c167..7da7c2da4af1 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -24,6 +24,13 @@ display0 = &lcd0; }; + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; @@ -32,14 +39,29 @@ }; sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM437x-SK-EVM"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <24000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; + compatible = "simple-audio-card"; + simple-audio-card,name = "AM437x-SK-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; }; matrix_keypad: matrix_keypad@0 { @@ -364,6 +386,15 @@ >; }; + mcasp1_pins_sleep: mcasp1_pins_sleep { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + lcd_pins: lcd_pins { pinctrl-single,pins = < 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ @@ -480,6 +511,7 @@ }; tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x1b>; status = "okay"; @@ -640,8 +672,10 @@ }; &mcasp1 { - pinctrl-names = "default"; + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; status = "okay"; @@ -670,6 +704,8 @@ }; &rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; status = "okay"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 795d68af6df9..86c2dfbe8875 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -14,6 +14,7 @@ #include <dt-bindings/pinctrl/am43xx.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/tlv320aic31xx-micbias.h> / { model = "TI AM43x EPOS EVM"; @@ -31,21 +32,18 @@ enable-active-high; }; + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + lcd0: display { compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; label = "lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - /* - * SelLCDorHDMI, LOW to select HDMI. This is not really the - * panel's enable GPIO, but we don't have HDMI driver support nor - * support to switch between two displays, so using this gpio as - * panel's enable should be safe. - */ - enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - panel-timing { clock-frequency = <33000000>; hactive = <800>; @@ -108,6 +106,38 @@ brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM43-EPOS-EVM"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1LP", "Microphone Jack", + "MIC1RP", "Microphone Jack", + "MIC1LP", "MICBIAS", + "MIC1RP", "MICBIAS", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPL", + "Speaker", "SPR"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3111>; + system-clock-frequency = <12000000>; + }; + }; }; &am43xx_pinmux { @@ -278,7 +308,7 @@ >; }; - lcd_pins: lcd_pins { + display_mux_pins: display_mux_pins { pinctrl-single,pins = < /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -320,6 +350,24 @@ 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ + 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ + >; + }; + + mcasp1_sleep_pins: mcasp1_sleep_pins { + pinctrl-single,pins = < + 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; }; &mmc1 { @@ -399,6 +447,15 @@ regulator-always-on; }; + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "vdcdc4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + dcdc5: regulator-dcdc5 { compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; @@ -441,6 +498,23 @@ touchscreen-size-x = <1024>; touchscreen-size-y = <600>; }; + + tlv320aic3111: tlv320aic3111@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3111"; + reg = <0x18>; + status = "okay"; + + ai31xx-micbias-vg = <MICBIAS_2_0V>; + + /* Regulators */ + HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + SPRVDD-supply = <&vbat>; /* vbat */ + SPLVDD-supply = <&vbat>; /* vbat */ + AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ + DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ + }; }; &i2c2 { @@ -458,7 +532,21 @@ }; &gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; status = "okay"; + + p1 { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; }; &gpio3 { @@ -686,3 +774,21 @@ }; }; }; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index d0c0dfa4ec48..cc88728d751d 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -486,6 +486,15 @@ reg = <0x4238>; }; + dpll_clksel_mac_clk: dpll_clksel_mac_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_m5_ck>; + reg = <0x4234>; + ti,bit-shift = <2>; + ti,dividers = <2>, <5>; + }; + clk_32k_mosc_ck: clk_32k_mosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index a63bf78191ea..3a05b94f59ed 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -580,7 +580,6 @@ vmmc-supply = <&ldo1_reg>; vmmc_aux-supply = <&vdd_3v3>; - pbias-supply = <&pbias_mmc_reg>; bus-width = <4>; cd-gpios = <&gpio6 27 0>; /* gpio 219 */ }; @@ -693,3 +692,7 @@ }; }; }; + +&pcie1 { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 67a0ab0f71e0..e9a381741ce1 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -176,6 +176,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu@c000 { diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index fd4f6fd8a2e8..353c92532e7a 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -81,10 +81,6 @@ pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <100000>; - /* - * The EEPROM located at adresse 54 is needed - * for the boot - DO NOT ERASE IT - - */ expander0: pca9555@20 { compatible = "nxp,pca9555"; @@ -111,6 +107,10 @@ reg = <0x21>; }; + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; }; serial@12000 { @@ -301,9 +301,11 @@ reg_sata0: pwr-sata0 { compatible = "regulator-fixed"; regulator-name = "pwr_en_sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; enable-active-high; regulator-always-on; - + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; }; reg_5v_sata0: v5-sata0 { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 04ecfe6e2bc6..f9f2347d9995 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -143,6 +143,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu@c000 { @@ -450,7 +454,7 @@ }; xor@60800 { - compatible = "marvell,orion-xor"; + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60800 0x100 0x60a00 0x100>; clocks = <&gateclk 22>; @@ -470,7 +474,7 @@ }; xor@60900 { - compatible = "marvell,orion-xor"; + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 28>; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index fc9864f85fc2..dc6efd386dbc 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -104,6 +104,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu@c000 { @@ -325,7 +329,7 @@ }; xor@60800 { - compatible = "marvell,orion-xor"; + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60800 0x100 0x60a00 0x100>; clocks = <&gateclk 22>; @@ -345,7 +349,7 @@ }; xor@60900 { - compatible = "marvell,orion-xor"; + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 28>; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts new file mode 100644 index 000000000000..e8d63afdb135 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -0,0 +1,134 @@ +/* + * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d2.dtsi" + +/ { + model = "Atmel SAMA5D2 Xplained"; + compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x80000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + usb0: gadget@00300000 { + status = "okay"; + }; + + usb1: ohci@00400000 { + num-ports = <3>; + status = "okay"; + }; + + usb2: ehci@00500000 { + status = "okay"; + }; + + apb { + spi0: spi@f8000000 { + status = "okay"; + + m25p80@0 { + compatible = "atmel,at25df321a"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + macb0: ethernet@f8008000 { + phy-mode = "rmii"; + status = "okay"; + }; + + uart1: serial@f8020000 { + status = "okay"; + }; + + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + status = "okay"; + }; + + uart3: serial@fc008000 { + status = "okay"; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + status = "okay"; + + at24@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 22ad7c959103..07f46963335b 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -131,6 +131,15 @@ }; adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; atmel,adc-vref = <3300>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index d782f2926b73..49a59c7e4a5d 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -100,6 +100,15 @@ }; adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ atmel,adc-vref = <3300>; /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index e3cfb9972f54..60edd8baebb8 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -359,6 +359,7 @@ compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; reg = <0xfffffd00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; watchdog { compatible = "atmel,at91rm9200-wdt"; @@ -369,6 +370,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffe00 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; status = "disabled"; }; @@ -378,8 +380,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffa4000 { @@ -388,8 +390,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; i2c0: i2c@fffb8000 { diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 4bc347549102..be9c027ddd97 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -359,11 +359,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -379,8 +381,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffdc000 { @@ -389,8 +391,8 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; pinctrl@fffff400 { @@ -973,6 +975,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index b2c44a07a3d0..ce1e3e94a40c 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -119,8 +119,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>, <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; usb1: gadget@fffa4000 { @@ -820,11 +820,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; }; pit: timer@fffffd30 { @@ -846,6 +848,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index e36d966ef5e8..f1f5fa3a9e6e 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -377,18 +377,20 @@ compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&slow_xtal>; + clock-names = "t0_clk", "slow_clk"; }; rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; }; pinctrl@fffff200 { @@ -902,6 +904,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index cfd7044616d7..27de7dc0f0e0 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" / { model = "Atmel AT91SAM9G15 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 26b0444b0f96..d1d2b400f1c6 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts @@ -8,9 +8,34 @@ */ /dts-v1/; #include "at91sam9g15.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G15-EK"; compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; + }; + }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index e35c2fcf8298..ff4115886f97 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" #include "at91sam9x5_macb0.dtsi" / { diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 641a9bf89ed1..23ec8b13f30a 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9g35.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { @@ -20,6 +21,26 @@ phy-mode = "rmii"; status = "okay"; }; + + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; }; }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 18177f5a7464..18b8b9e29704 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -387,6 +387,7 @@ rstc@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -400,22 +401,23 @@ shdwc@fffffd10 { compatible = "atmel,at91sam9rl-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffd4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; dma: dma-controller@ffffec00 { @@ -498,23 +500,31 @@ }; isi { - pinctrl_isi: isi-0 { - atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ - AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */ - AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ - AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */ - AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ - AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ - AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ - AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ - AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ - AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ - AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ - AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ - AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ - AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ - AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */ - AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>; + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ + AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ + AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ + AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ + AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ + AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ + AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ + AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ + AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ + AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */ }; }; @@ -1067,9 +1077,11 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; clocks = <&isi_clk>; clock-names = "isi_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi>; status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; pwm0: pwm@fffb8000 { @@ -1113,6 +1125,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1247,6 +1260,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffdb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 1375d3362603..d1ae60a855d4 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -63,6 +63,25 @@ i2c0: i2c@fff84000 { status = "okay"; + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; }; i2c1: i2c@fff88000 { @@ -101,6 +120,22 @@ }; pinctrl@fffff200 { + camera_sensor { + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = @@ -155,6 +190,18 @@ status = "okay"; }; + isi@fffb4000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + status = "okay"; + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + }; + }; + }; + pwm0: pwm@fffb8000 { status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 5c2a8c8c8bd4..32bc9a189db0 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -376,6 +376,7 @@ rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -388,6 +389,7 @@ shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; sckc@fffffe50 { @@ -431,16 +433,44 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9n12-hlcdc"; + reg = <0xf8038000 0x2000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; }; dma: dma-controller@ffffec00 { @@ -475,6 +505,49 @@ }; }; + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ + AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ + AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -891,6 +964,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -901,6 +975,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index eab17fcace6d..efa75064d38a 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -128,6 +128,22 @@ }; }; + hlcdc: hlcdc@f8038000 { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + usb1: gadget@f803c000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_vbus_sense>; @@ -161,6 +177,23 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "okay"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + leds { compatible = "gpio-leds"; @@ -194,6 +227,34 @@ }; }; + panel: panel { + compatible = "qd,qd43003c0-40", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + sound { compatible = "atmel,asoc-wm8904"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index c9920c64791c..a0b90aedd3b8 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -121,8 +121,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; mmc0: mmc@fffa4000 { @@ -1018,11 +1018,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -1036,6 +1038,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; @@ -1083,6 +1086,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffe00 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 499cdc81f4c0..d9054e8167b7 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" #include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_can.dtsi" diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 343d32818ca3..fcb67180ea26 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9x35.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { @@ -20,6 +21,25 @@ phy-mode = "rmii"; status = "okay"; }; + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; }; }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index b6c8df8d380e..747d8f070a5c 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -376,11 +376,13 @@ rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -418,16 +420,16 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; dma0: dma-controller@ffffec00 { @@ -1173,6 +1175,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1183,6 +1186,7 @@ compatible = "atmel,at91sam9x5-rtc"; reg = <0xfffffeb0 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi index 485302e8233d..1629db9dd563 100644 --- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi @@ -13,6 +13,137 @@ / { ahb { apb { + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff400 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ + AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ + AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + }; + }; + pmc: pmc@fffffc00 { periphck { lcdc_clk: lcdc_clk { @@ -20,6 +151,14 @@ reg = <25>; }; }; + + systemck { + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi new file mode 100644 index 000000000000..34c089fe0bc0 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi @@ -0,0 +1,101 @@ +/* + * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module + * + * Copyright (C) 2014 Atmel, + * 2014 Free Electrons + * + * Author: Boris Brezillon <boris.brezillon@free-electrons.com> + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c0: i2c@f8010000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <7 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + hlcdc: hlcdc@f8038000 { + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "disabled"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "disabled"; + }; + + panel: panel { + compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts index 49cf59a95572..1e9cd1a8508e 100644 --- a/arch/arm/boot/dts/atlas7-evb.dts +++ b/arch/arm/boot/dts/atlas7-evb.dts @@ -10,6 +10,9 @@ /include/ "atlas7.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + / { model = "CSR SiRFatlas7 Evaluation Board"; compatible = "sirf,atlas7-cb", "sirf,atlas7"; @@ -106,5 +109,20 @@ }; }; }; + + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + rearview_key { + label = "rearview key"; + linux,code = <KEY_CAMERA>; + gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>; + debounce_interval = <100>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi index 3e21311f9514..83449b33de6b 100644 --- a/arch/arm/boot/dts/atlas7.dtsi +++ b/arch/arm/boot/dts/atlas7.dtsi @@ -21,6 +21,10 @@ serial5 = &uart5; serial6 = &uart6; serial9 = &usp2; + spi1 = &spi1; + spi2 = &usp1; + spi3 = &usp2; + spi4 = &usp3; }; cpus { #address-cells = <1>; @@ -53,6 +57,11 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0 29 4>, <0 82 4>; + }; + noc { compatible = "simple-bus"; #address-cells = <1>; @@ -1205,7 +1214,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x18641000 0x18641000 0x3000>, - <0x18620000 0x18620000 0x1000>; + <0x18620000 0x18620000 0x1000>, + <0x18630000 0x18630000 0x10000>; cgum@18641000 { compatible = "sirf,nocfw-cgum"; @@ -1218,6 +1228,15 @@ #clock-cells = <1>; #reset-cells = <1>; }; + pwm: pwm@18630000 { + compatible = "sirf,prima2-pwm"; + #pwm-cells = <2>; + reg = <0x18630000 0x10000>; + clocks = <&car 138>, <&car 139>, <&car 237>, + <&car 240>, <&car 140>, <&car 246>; + clock-names = "pwmc", "sigsrc0", "sigsrc1", + "sigsrc2", "sigsrc3", "sigsrc4"; + }; }; gnssm { @@ -1231,6 +1250,7 @@ <0x18040000 0x18040000 0x1000>, <0x18050000 0x18050000 0x1000>, <0x18060000 0x18060000 0x1000>, + <0x180b0000 0x180b0000 0x4000>, <0x18100000 0x18100000 0x3000>, <0x18250000 0x18250000 0x10000>, <0x18200000 0x18200000 0x1000>; @@ -1314,6 +1334,18 @@ dma-names = "rx", "tx"; status = "disabled"; }; + gmac: eth@180b0000 { + compatible = "snps, dwc-eth-qos"; + reg = <0x180b0000 0x4000>; + interrupts = <0 59 0>, <0 70 0>; + interrupt-names = "macirq", "macpmt"; + clocks = <&car 39>, <&car 45>, + <&car 86>, <&car 87>; + clock-names = "gnssm_rgmii", "gnssm_gmac", + "rgmii", "gmac"; + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "rgmii"; + }; dspub@18250000 { compatible = "dx,cc44p"; reg = <0x18250000 0x10000>; @@ -1338,18 +1370,51 @@ compatible = "arteris, flexnoc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x13000000 0x13000000 0x3000>; + ranges = <0x13000000 0x13000000 0x3000>, + <0x13010000 0x13010000 0x1400>, + <0x13010800 0x13010800 0x100>, + <0x13011000 0x13011000 0x100>; gpum@0x13000000 { compatible = "sirf,nocfw-gpum"; reg = <0x13000000 0x3000>; }; + dmacsdrr: dma-controller@13010800 { + cell-index = <5>; + compatible = "sirf,atlas7-dmac-v2"; + reg = <0x13010800 0x100>; + interrupts = <0 8 0>; + clocks = <&car 127>; + #dma-cells = <1>; + #dma-channels = <1>; + }; + dmacsdrw: dma-controller@13011000 { + cell-index = <6>; + compatible = "sirf,atlas7-dmac-v2"; + reg = <0x13011000 0x100>; + interrupts = <0 9 0>; + clocks = <&car 127>; + #dma-cells = <1>; + #dma-channels = <1>; + }; + sdr@0x13010000 { + compatible = "sirf,atlas7-sdr"; + reg = <0x13010000 0x1400>; + interrupts = <0 7 0>, + <0 8 0>, + <0 9 0>; + clocks = <&car 127>; + dmas = <&dmacsdrr 0>, <&dmacsdrw 0>; + dma-names = "tx", "rx"; + }; }; mediam { compatible = "arteris, flexnoc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x16000000 0x16000000 0x00200000>, + ranges = <0x15000000 0x15000000 0x00600000>, + <0x16000000 0x16000000 0x00200000>, + <0x17000000 0x17000000 0x10000>, <0x17020000 0x17020000 0x1000>, <0x17030000 0x17030000 0x1000>, <0x17040000 0x17040000 0x1000>, @@ -1360,6 +1425,13 @@ <0x17070200 0x17070200 0x100>, <0x170A0000 0x170A0000 0x3000>; + multimedia@15000000 { + compatible = "sirf,atlas7-video-codec"; + reg = <0x15000000 0x10000>; + interrupts = <0 5 0>; + clocks = <&car 102>; + }; + mediam@170A0000 { compatible = "sirf,nocfw-mediam"; reg = <0x170A0000 0x3000>; @@ -1386,6 +1458,8 @@ nand@17050000 { compatible = "sirf,atlas7-nand"; reg = <0x17050000 0x10000>; + pinctrl-names = "default"; + pinctrl-0 = <&nd_df_pmx>; interrupts = <0 41 0>; clocks = <&car 108>, <&car 112>; clock-names = "nand_io", "nand_nand"; @@ -1416,6 +1490,14 @@ bus-width = <8>; }; + jpeg@17000000 { + compatible = "sirf,atlas7-jpeg"; + reg = <0x17000000 0x10000>; + interrupts = <0 72 0>, + <0 73 0>; + clocks = <&car 103>; + }; + usb0: usb@17060000 { cell-index = <0>; compatible = "sirf,atlas7-usb"; @@ -1826,7 +1908,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x13100000 0x13100000 0x20000>, - <0x10e10000 0x10e10000 0x10000>; + <0x10e10000 0x10e10000 0x10000>, + <0x17010000 0x17010000 0x10000>; lcd@13100000 { compatible = "sirf,atlas7-lcdc"; @@ -1848,6 +1931,12 @@ clocks = <&car 54>; resets = <&car 29>; }; + g2d@17010000 { + compatible = "sirf, atlas7-g2d"; + reg = <0x17010000 0x10000>; + interrupts = <0 61 0>; + clocks = <&car 104>; + }; }; diff --git a/arch/arm/boot/dts/axp152.dtsi b/arch/arm/boot/dts/axp152.dtsi new file mode 100644 index 000000000000..f90ad6c64a07 --- /dev/null +++ b/arch/arm/boot/dts/axp152.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&axp152 { + compatible = "x-powers,axp152"; + interrupt-controller; + #interrupt-cells = <1>; +}; diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi index 60d8389fdb6c..32bcd45ef22b 100644 --- a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi @@ -36,56 +36,89 @@ clocks { ranges; osc: oscillator { + #clock-cells = <0>; compatible = "fixed-clock"; - #clock-cells = <1>; clock-frequency = <25000000>; }; - apb_clk: apb_clk { - compatible = "fixed-clock"; + /* Cygnus ARM PLL */ + armpll: armpll { #clock-cells = <0>; - clock-frequency = <1000000000>; + compatible = "brcm,cygnus-armpll"; + clocks = <&osc>; + reg = <0x19000000 0x1000>; }; - periph_clk: periph_clk { - compatible = "fixed-clock"; + /* peripheral clock for system timer */ + periph_clk: arm_periph_clk { #clock-cells = <0>; - clock-frequency = <500000000>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <2>; + clock-mult = <1>; }; - sdio_clk: lcpll_ch2 { - compatible = "fixed-clock"; + /* APB bus clock */ + apb_clk: apb_clk { #clock-cells = <0>; - clock-frequency = <200000000>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <4>; + clock-mult = <1>; }; - axi81_clk: axi81_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; + genpll: genpll { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; }; - keypad_clk: keypad_clk { - compatible = "fixed-clock"; + /* always 1/2 of the axi21 clock */ + axi41_clk: axi41_clk { #clock-cells = <0>; - clock-frequency = <31806>; + compatible = "fixed-factor-clock"; + clocks = <&genpll 1>; + clock-div = <2>; + clock-mult = <1>; }; - adc_clk: adc_clk { - compatible = "fixed-clock"; + /* always 1/4 of the axi21 clock */ + axi81_clk: axi81_clk { #clock-cells = <0>; - clock-frequency = <1562500>; + compatible = "fixed-factor-clock"; + clocks = <&genpll 1>; + clock-div = <4>; + clock-mult = <1>; }; - pwm_clk: pwm_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; + lcpll0: lcpll0 { + #clock-cells = <1>; + compatible = "brcm,cygnus-lcpll0"; + reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", + "usb_phy", "smart_card", "ch5"; }; - lcd_clk: mipipll_ch1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; + mipipll: mipipll { + #clock-cells = <1>; + compatible = "brcm,cygnus-mipipll"; + reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; + clocks = <&osc>; + clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", + "ch2_v3d", "ch3_unused", "ch4_unused", + "ch5_unused"; + }; + + asiu_clks: asiu_clks { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x0301d048 0xc>, <0x180aa024 0x4>; + + clocks = <&osc>; + clock-output-names = "keypad", "adc/touch", "pwm"; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 46780bb48bbf..ab5474e5d1c8 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -14,6 +14,13 @@ linux,default-trigger = "heartbeat"; }; }; + + soc { + firmware: firmware { + compatible = "raspberrypi,bcm2835-firmware"; + mboxes = <&mailbox>; + }; + }; }; &gpio { diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index 24f0ab59bf1b..42dcdfb769b2 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -135,3 +135,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index f03939311717..f18e80e0b61d 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -55,3 +55,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 326ce8f4e49c..64b8d10ccff8 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -24,16 +24,6 @@ reg = <0x00000000 0x08000000>; }; - chipcommonA { - uart0: serial@0300 { - status = "okay"; - }; - - uart1: serial@0400 { - status = "okay"; - }; - }; - leds { compatible = "gpio-leds"; @@ -92,3 +82,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index d6a033b97c70..64a5e8ab65e0 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -118,3 +118,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index bb0cb0bfafaf..38f0c00d1aca 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -122,3 +122,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 21fefd4cdc25..6f50f672efbd 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -78,10 +78,20 @@ compatible = "arm,pl310-cache"; reg = <0x2000 0x1000>; cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; cache-level = <2>; }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + clocks { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 58dcd666257c..3b6b17560687 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -109,6 +109,20 @@ brcm,int-fwd-mask = <0x70000>; }; + irq0_aon_intc: interrupt-controller@417280 { + compatible = "brcm,bcm7120-l2-intc"; + reg = <0x417280 0x8>; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <GIC_SPI 0x46 0x0>, + <GIC_SPI 0x44 0x0>, + <GIC_SPI 0x49 0x0>; + brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; + brcm,int-fwd-mask = <0x0>; + brcm,irq-can-wake; + }; + hif_intr2_intc: interrupt-controller@3e1000 { compatible = "brcm,l2-intc"; reg = <0x3e1000 0x30>; @@ -119,6 +133,16 @@ interrupt-names = "hif"; }; + aon_pm_l2_intc: interrupt-controller@410640 { + compatible = "brcm,l2-intc"; + reg = <0x410640 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 0x40 0x0>; + interrupt-parent = <&gic>; + brcm,irq-can-wake; + }; + nand: nand@3e2800 { status = "disabled"; #address-cells = <1>; @@ -167,6 +191,32 @@ #phy-cells = <0>; }; }; + + upg_gio: gpio@40a700 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x40a700 0x80>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupt-parent = <&irq0_intc>; + interrupts = <6>; + brcm,gpio-bank-widths = <32 32 32 24>; + }; + + upg_gio_aon: gpio@4172c0 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x4172c0 0x40>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts-extended = <&irq0_aon_intc 0x6>, + <&aon_pm_l2_intc 0x5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; + }; smpboot { diff --git a/arch/arm/boot/dts/cros-ec-sbs.dtsi b/arch/arm/boot/dts/cros-ec-sbs.dtsi new file mode 100644 index 000000000000..71f5c5ecce46 --- /dev/null +++ b/arch/arm/boot/dts/cros-ec-sbs.dtsi @@ -0,0 +1,52 @@ +/* + * Smart battery dts fragment for devices that use cros-ec-sbs + * + * Copyright (c) 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&i2c_tunnel { + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; +}; diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi index af333261d046..df4c6f1f93f9 100644 --- a/arch/arm/boot/dts/cx92755.dtsi +++ b/arch/arm/boot/dts/cx92755.dtsi @@ -88,6 +88,13 @@ interrupts = <25>; }; + watchdog@f0000fc0 { + compatible = "cnxt,cx92755-wdt"; + reg = <0xf0000fc0 0x8>; + clocks = <&main_clk>; + timeout-sec = <15>; + }; + uc_regs: syscon@f00003a0 { compatible = "cnxt,cx92755-uc", "syscon"; reg = <0xf00003a0 0x10>; diff --git a/arch/arm/boot/dts/cx92755_equinox.dts b/arch/arm/boot/dts/cx92755_equinox.dts index 90d52cc416dc..5da00806c41e 100644 --- a/arch/arm/boot/dts/cx92755_equinox.dts +++ b/arch/arm/boot/dts/cx92755_equinox.dts @@ -64,8 +64,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; }; diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts new file mode 100644 index 000000000000..92bacd3c8fab --- /dev/null +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -0,0 +1,28 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dm814x.dtsi" + +/ { + model = "DM8148 EVM"; + compatible = "ti,dm8148-evm", "ti,dm8148"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts new file mode 100644 index 000000000000..8c4bbc7573df --- /dev/null +++ b/arch/arm/boot/dts/dm8148-t410.dts @@ -0,0 +1,28 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dm814x.dtsi" + +/ { + model = "DM8148 EVM"; + compatible = "hp,t410", "ti,dm8148"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi new file mode 100644 index 000000000000..ef1e8e7a6cc6 --- /dev/null +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -0,0 +1,109 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&scm_clocks { + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + devosc_ck: devosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */ + auxosc_ck: auxosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000000>; + }; + + sysclk4_ck: sysclk4_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <222000000>; + }; + + sysclk6_ck: sysclk6_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + sysclk10_ck: sysclk10_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + sysclk18_ck: sysclk18_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + cpsw_125mhz_gclk: cpsw_125mhz_gclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <250000000>; + }; + +}; + +&pllss_clocks { + + aud_clkin0_ck: aud_clkin0_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + aud_clkin1_ck: aud_clkin1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + aud_clkin2_ck: aud_clkin2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + timer1_mux_ck: timer1_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <3>; + reg = <0x2e0>; + }; + + timer2_mux_ck: timer2_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck + &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; + ti,bit-shift = <6>; + reg = <0x2e0>; + }; +}; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi new file mode 100644 index 000000000000..972c9c9e885b --- /dev/null +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -0,0 +1,333 @@ +/* + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/omap.h> + +#include "skeleton.dtsi" + +/ { + compatible = "ti,dm814"; + interrupt-parent = <&intc>; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + /* + * See TRM "Table 1-317. L4LS Instance Summary", just deduct + * 0x1000 from the 1-317 addresses to get the device address + */ + l4ls: l4ls@48000000 { + compatible = "ti,dm814-l4ls", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x2000000>; + + i2c1: i2c@28000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + reg = <0x28000 0x1000>; + interrupts = <70>; + }; + + elm: elm@80000 { + compatible = "ti,814-elm"; + ti,hwmods = "elm"; + reg = <0x80000 0x2000>; + interrupts = <4>; + }; + + gpio1: gpio@32000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + reg = <0x32000 0x2000>; + interrupts = <96>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@4c000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + reg = <0x4c000 0x2000>; + interrupts = <98>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c2: i2c@2a000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + reg = <0x2a000 0x1000>; + interrupts = <71>; + }; + + mcspi1: spi@30000 { + compatible = "ti,omap4-mcspi"; + reg = <0x30000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <65>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi1"; + dmas = <&edma 16 &edma 17 + &edma 18 &edma 19>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + timer1: timer@2e000 { + compatible = "ti,dm814-timer"; + reg = <0x2e000 0x2000>; + interrupts = <67>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + uart1: uart@20000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + reg = <0x20000 0x2000>; + clock-frequency = <48000000>; + interrupts = <72>; + dmas = <&edma 26 &edma 27>; + dma-names = "tx", "rx"; + }; + + uart2: uart@22000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + reg = <0x22000 0x2000>; + clock-frequency = <48000000>; + interrupts = <73>; + dmas = <&edma 28 &edma 29>; + dma-names = "tx", "rx"; + }; + + uart3: uart@24000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + reg = <0x24000 0x2000>; + clock-frequency = <48000000>; + interrupts = <74>; + dmas = <&edma 30 &edma 31>; + dma-names = "tx", "rx"; + }; + + timer2: timer@40000 { + compatible = "ti,dm814-timer"; + reg = <0x40000 0x2000>; + interrupts = <68>; + ti,hwmods = "timer2"; + }; + + timer3: timer@42000 { + compatible = "ti,dm814-timer"; + reg = <0x42000 0x2000>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + control: control@160000 { + compatible = "ti,dm814-scm", "simple-bus"; + reg = <0x160000 0x16d000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x160000 0x16d000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scm_clockdomains: clockdomains { + }; + }; + + pincntl: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0xc38>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x300ff>; + }; + }; + + prcm: prcm@180000 { + compatible = "ti,dm814-prcm", "simple-bus"; + reg = <0x180000 0x4000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + pllss: pllss@1c5000 { + compatible = "ti,dm814-pllss", "simple-bus"; + reg = <0x1c5000 0x2000>; + + pllss_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pllss_clockdomains: clockdomains { + }; + }; + + wdt1: wdt@1c7000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer"; + reg = <0x1c7000 0x1000>; + interrupts = <91>; + }; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,dm814-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + edma: edma@49000000 { + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x40>; + interrupts = <12 13 14>; + #dma-cells = <1>; + }; + + /* See TRM "Table 1-318. L4HS Instance Summary" */ + l4hs: l4hs@4a000000 { + compatible = "ti,dm814-l4hs", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x1b4040>; + }; + + /* REVISIT: Move to live under l4hs once driver is fixed */ + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "cpgmac0"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x4a100000 0x800 + 0x4a100900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges; + syscon = <&scm_conf>; + + davinci_mdio: mdio@4a100800 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x4a100800 0x100>; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + phy_sel: cpsw-phy-sel@0x48160650 { + compatible = "ti,am3352-cpsw-phy-sel"; + reg= <0x48160650 0x4>; + reg-names = "gmii-sel"; + }; + }; + }; +}; + +#include "dm814x-clocks.dtsi" diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 289806adb343..3c99cfa1a876 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -58,7 +58,7 @@ * the whole bus hierarchy. */ ocp { - compatible = "ti,omap3-l3-smx", "simple-bus"; + compatible = "simple-bus"; reg = <0x44000000 0x10000>; interrupts = <9 10>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 38b1f7e6004e..179121630ad7 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -419,293 +419,325 @@ status = "disabled"; }; - thermal: thermal-diode@d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; - }; - - gate_clk: clock-gating-ctrl@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - pinctrl: pin-ctrl@d0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x14>, - <0xd0440 0x04>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_pcie1_clkreq: pmx-pcie1-clkreq { - marvell,pins = "mpp9"; - marvell,function = "pex1"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_pcie0_clkreq: pmx-pcie0-clkreq { - marvell,pins = "mpp11"; - marvell,function = "pex0"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_spi1_4_7: pmx-spi1-4-7 { - marvell,pins = "mpp4", "mpp5", - "mpp6", "mpp7"; - marvell,function = "spi1"; - }; - - pmx_spi1_20_23: pmx-spi1-20-23 { - marvell,pins = "mpp20", "mpp21", - "mpp22", "mpp23"; - marvell,function = "spi1"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - - pmx_i2c1: pmx-i2c1 { - marvell,pins = "mpp17", "mpp19"; - marvell,function = "twsi"; - }; - - pmx_i2c2: pmx-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "twsi"; - }; - - pmx_ssp_i2c2: pmx-ssp-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "ssp/twsi"; - }; - - pmx_i2cmux_0: pmx-i2cmux-0 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt1"; - }; - - pmx_i2cmux_1: pmx-i2cmux-1 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt2"; - }; - - pmx_i2cmux_2: pmx-i2cmux-2 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt3"; - }; - }; - - core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gpio0: gpio-ctrl@d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; + pmu: power-management@d0000 { + compatible = "marvell,dove-pmu", "simple-bus"; + reg = <0xd0000 0x8000>, <0xd8000 0x8000>; + ranges = <0x00000000 0x000d0000 0x8000 + 0x00008000 0x000d8000 0x8000>; + interrupts = <33>; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; - }; - - rtc: real-time-clock@d8500 { - compatible = "marvell,orion-rtc"; - reg = <0xd8500 0x20>; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + #reset-cells = <1>; + + domains { + vpu_domain: vpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000008>; + marvell,pmu_iso_mask = <0x00000001>; + resets = <&pmu 16>; + }; + + gpu_domain: gpu-domain { + #power-domain-cells = <0>; + marvell,pmu_pwr_mask = <0x00000004>; + marvell,pmu_iso_mask = <0x00000002>; + resets = <&pmu 18>; + }; + }; + + thermal: thermal-diode@001c { + compatible = "marvell,dove-thermal"; + reg = <0x001c 0x0c>, <0x005c 0x08>; + }; + + gate_clk: clock-gating-ctrl@0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0x0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + pinctrl: pin-ctrl@0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0x0200 0x14>, + <0x0440 0x04>; + clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_pcie1_clkreq: pmx-pcie1-clkreq { + marvell,pins = "mpp9"; + marvell,function = "pex1"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_pcie0_clkreq: pmx-pcie0-clkreq { + marvell,pins = "mpp11"; + marvell,function = "pex0"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_audio1_extclk: pmx-audio1-extclk { + marvell,pins = "mpp13"; + marvell,function = "audio1"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { + marvell,pins = "mpp_audio1"; + marvell,function = "i2s1/spdifo"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_spi1_4_7: pmx-spi1-4-7 { + marvell,pins = "mpp4", "mpp5", + "mpp6", "mpp7"; + marvell,function = "spi1"; + }; + + pmx_spi1_20_23: pmx-spi1-20-23 { + marvell,pins = "mpp20", "mpp21", + "mpp22", "mpp23"; + marvell,function = "spi1"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; + + pmx_i2c1: pmx-i2c1 { + marvell,pins = "mpp17", "mpp19"; + marvell,function = "twsi"; + }; + + pmx_i2c2: pmx-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "twsi"; + }; + + pmx_ssp_i2c2: pmx-ssp-i2c2 { + marvell,pins = "mpp_audio1"; + marvell,function = "ssp/twsi"; + }; + + pmx_i2cmux_0: pmx-i2cmux-0 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt1"; + }; + + pmx_i2cmux_1: pmx-i2cmux-1 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt2"; + }; + + pmx_i2cmux_2: pmx-i2cmux-2 { + marvell,pins = "twsi"; + marvell,function = "twsi-opt3"; + }; + }; + + core_clk: core-clocks@0214 { + compatible = "marvell,dove-core-clock"; + reg = <0x0214 0x4>; + #clock-cells = <1>; + }; + + gpio0: gpio-ctrl@0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio-ctrl@0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <61>; + }; + + rtc: real-time-clock@8500 { + compatible = "marvell,orion-rtc"; + reg = <0x8500 0x20>; + interrupts = <5>; + }; }; gconf: global-config@e802c { diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 096f68be99e2..a6c82e5b64fe 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -19,6 +19,15 @@ reg = <0x80000000 0x60000000>; /* 1536 MB */ }; + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + mmc2_3v3: fixedregulator-mmc2 { compatible = "regulator-fixed"; regulator-name = "mmc2_3v3"; @@ -349,6 +358,7 @@ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; regulator-boot-on; }; @@ -462,8 +472,14 @@ &mmc1 { status = "okay"; - vmmc-supply = <&ldo1_reg>; + vmmc-supply = <&evm_3v3_sd>; + vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is always hardwired. + */ + cd-gpios = <&gpio6 27 0>; }; &mmc2 { diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1e29ccf77ea2..5d65db9ebc2b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -141,7 +141,7 @@ dra7_pmx_core: pinmux@1400 { compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x1400 0x0464>; + reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; @@ -149,6 +149,11 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x3fffffff>; }; + + scm_conf1: scm_conf@1c04 { + compatible = "syscon"; + reg = <0x1c04 0x0020>; + }; }; cm_core_aon: cm_core_aon@5000 { @@ -211,7 +216,7 @@ #address-cells = <1>; ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>; - pcie@51000000 { + pcie1: pcie@51000000 { compatible = "ti,dra7-pcie"; reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; @@ -286,16 +291,6 @@ #thermal-sensor-cells = <1>; }; - dra7_ctrl_core: ctrl_core@4a002000 { - compatible = "syscon"; - reg = <0x4a002000 0x6d0>; - }; - - dra7_ctrl_general: tisyscon@4a002e00 { - compatible = "syscon"; - reg = <0x4a002e00 0x7c>; - }; - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -308,6 +303,15 @@ dma-requests = <127>; }; + sdma_xbar: dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; + gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; @@ -397,73 +401,73 @@ }; uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806a000 0x100>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 49>, <&sdma 50>; + dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; dma-names = "tx", "rx"; }; uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806c000 0x100>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 51>, <&sdma 52>; + dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; dma-names = "tx", "rx"; }; uart3: serial@48020000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48020000 0x100>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 53>, <&sdma 54>; + dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; dma-names = "tx", "rx"; }; uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806e000 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 55>, <&sdma 56>; + dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; dma-names = "tx", "rx"; }; uart5: serial@48066000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48066000 0x100>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 63>, <&sdma 64>; + dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; dma-names = "tx", "rx"; }; uart6: serial@48068000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48068000 0x100>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma 79>, <&sdma 80>; + dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; dma-names = "tx", "rx"; }; uart7: serial@48420000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48420000 0x100>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; @@ -472,7 +476,7 @@ }; uart8: serial@48422000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48422000 0x100>; interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; @@ -481,7 +485,7 @@ }; uart9: serial@48424000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48424000 0x100>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; @@ -490,7 +494,7 @@ }; uart10: serial@4ae2b000 { - compatible = "ti,omap4-uart"; + compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; @@ -867,7 +871,7 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; + dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; dma-names = "tx", "rx"; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; @@ -879,7 +883,7 @@ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -890,7 +894,7 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc3"; ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; + dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -901,7 +905,7 @@ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc4"; ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; + dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1046,14 +1050,14 @@ #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; + dmas = <&sdma_xbar 35>, + <&sdma_xbar 36>, + <&sdma_xbar 37>, + <&sdma_xbar 38>, + <&sdma_xbar 39>, + <&sdma_xbar 40>, + <&sdma_xbar 41>, + <&sdma_xbar 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; status = "disabled"; @@ -1067,10 +1071,10 @@ #size-cells = <0>; ti,hwmods = "mcspi2"; ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; + dmas = <&sdma_xbar 43>, + <&sdma_xbar 44>, + <&sdma_xbar 45>, + <&sdma_xbar 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -1083,7 +1087,7 @@ #size-cells = <0>; ti,hwmods = "mcspi3"; ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; + dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; dma-names = "tx0", "rx0"; status = "disabled"; }; @@ -1096,7 +1100,7 @@ #size-cells = <0>; ti,hwmods = "mcspi4"; ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; + dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; dma-names = "tx0", "rx0"; status = "disabled"; }; @@ -1296,7 +1300,12 @@ usb1: usb@48890000 { compatible = "snps,dwc3"; reg = <0x48890000 0x17000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; tx-fifo-resize; @@ -1319,7 +1328,12 @@ usb2: usb@488d0000 { compatible = "snps,dwc3"; reg = <0x488d0000 0x17000>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; phys = <&usb2_phy2>; phy-names = "usb2-phy"; tx-fifo-resize; @@ -1344,7 +1358,12 @@ usb3: usb@48910000 { compatible = "snps,dwc3"; reg = <0x48910000 0x17000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -1399,7 +1418,7 @@ }; mac: ethernet@4a100000 { - compatible = "ti,cpsw"; + compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; clock-names = "fck", "cpts"; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 803738414086..6f6bd98c98df 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -30,6 +30,15 @@ regulator-max-microvolt = <3300000>; }; + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; @@ -286,6 +295,7 @@ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; regulator-boot-on; }; @@ -343,6 +353,12 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + + cpsw_sel_s0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; }; }; @@ -491,14 +507,15 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; - - vmmc-supply = <&ldo1_reg>; + vmmc-supply = <&evm_3v3_sd>; + vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is a viable alternative */ cd-gpios = <&gpio6 27 0>; + max-frequency = <192000000>; }; &mmc2 { @@ -510,6 +527,7 @@ vmmc-supply = <&evm_3v3>; bus-width = <8>; ti,non-removable; + max-frequency = <192000000>; }; &dra7_pmx_core { @@ -571,9 +589,10 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; + slaves = <1>; }; -&cpsw_emac1 { +&cpsw_emac0 { phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; @@ -582,7 +601,6 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - active_slave = <1>; }; &dcan1 { diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index fa995d0ca1f2..feea98e0a4b5 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -65,7 +65,12 @@ usb4: usb@48950000 { compatible = "snps,dwc3"; reg = <0x48950000 0x17000>; - interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 1dee0aa4f40c..955c24ee4a8c 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -95,6 +95,14 @@ }; }; +&iic0 { + status = "okay"; +}; + +&iic1 { + status = "okay"; +}; + &pfc { uart1_pins: serial@e1030000 { renesas,groups = "uart1_ctrl", "uart1_data"; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index bb45694d91bc..edad0c4eea35 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -21,6 +21,8 @@ gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; + i2c0 = &iic0; + i2c1 = &iic1; }; cpus { @@ -66,6 +68,30 @@ clock-frequency = <32768>; #clock-cells = <0>; }; + iic0_sclkdiv: iic0_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic0_sclk: iic0_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x48c 1>; + clocks = <&iic0_sclkdiv>; + #clock-cells = <0>; + }; + iic1_sclkdiv: iic1_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic1_sclk: iic1_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x490 1>; + clocks = <&iic1_sclkdiv>; + #clock-cells = <0>; + }; pll3_fo: pll3_fo { compatible = "fixed-factor-clock"; clocks = <&c32ki>; @@ -234,4 +260,26 @@ interrupt-controller; #interrupt-cells = <2>; }; + + iic0: i2c@e0070000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe0070000 0x28>; + interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; + clocks = <&iic0_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; + + iic1: i2c@e10a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe10a0000 0x28>; + interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; + clocks = <&iic1_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index a5863acc5fff..540a0adf2be6 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -116,6 +116,21 @@ min-microvolt = <1100000>; max-microvolt = <2700000>; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Correspond to 500MHz at freq_table */ + cooling-device = <&cpu0 5 5>; + }; + map1 { + /* Correspond to 200MHz at freq_table */ + cooling-device = <&cpu0 8 8>; + }; + }; + }; + }; }; &adc { @@ -141,6 +156,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &exynos_usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 031853b75528..41a5fafb9aa9 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -107,6 +107,21 @@ min-microvolt = <1100000>; max-microvolt = <2700000>; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 500MHz */ + cooling-device = <&cpu0 5 5>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 8 8>; + }; + }; + }; + }; }; &adc { @@ -132,6 +147,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &exynos_usbphy { status = "okay"; }; @@ -182,7 +201,7 @@ display-timings { timing-0 { - clock-frequency = <0>; + clock-frequency = <4600000>; hactive = <320>; vactive = <320>; hfront-porch = <1>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 2db99433e17f..033def482fc3 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -53,6 +53,22 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; }; cpu1: cpu@1 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index b0d52b1a646a..98c0a368b777 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -702,6 +702,7 @@ clocks = <&clock CLK_JPEG>; clock-names = "jpeg"; power-domains = <&pd_cam>; + iommus = <&sysmmu_jpeg>; }; hdmi: hdmi@12D00000 { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 775892b2cc6a..eb379526e234 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -69,66 +69,6 @@ enable-active-high; }; - hsotg@12480000 { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; - }; - - sdhci_emmc: sdhci@12510000 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; - }; - - sdhci_sd: sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpx3 4 0>; - cd-inverted; - status = "okay"; - }; - - ehci@12580000 { - status = "okay"; - port@0 { - status = "okay"; - }; - }; - - ohci@12590000 { - status = "okay"; - port@0 { - status = "okay"; - }; - }; - - exynos-usbphy@125B0000 { - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; @@ -186,218 +126,6 @@ enable-active-high; }; - i2c@13890000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - tsp@4a { - /* TBD: Atmel maXtouch touchscreen */ - reg = <0x4a>; - }; - }; - - i2c@138B0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - regulator-name = "vdd_arm"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gpx0 5 0>, - <&gpx0 6 0>; - max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, - <1100000>, <1000000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gpe2 0 0>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD+VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "PS_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VHIC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_I_HOST_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "CAM_S_ANA_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VINT_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VG3D_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VMEM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-always-on; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; - }; - spi-lcd { compatible = "spi-gpio"; #address-cells = <1>; @@ -446,27 +174,6 @@ }; }; - fimd: fimd@11c00000 { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - samsung,invert-vden; - samsung,invert-vclk; - #address-cells = <1>; - #size-cells = <0>; - port@3 { - reg = <3>; - fimd_dpi_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; - }; - - pwm@139D0000 { - compatible = "samsung,s5p6440-pwm"; - status = "okay"; - }; - camera { status = "okay"; @@ -526,30 +233,287 @@ pinctrl-names = "default"; status = "okay"; }; +}; - mixer@12C10000 { +&cpu0 { + cpu0-supply = <&vdd_arm_reg>; +}; + +&ehci { + status = "okay"; + port@0 { status = "okay"; }; +}; - hdmi@12D00000 { - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - hdmi-en-supply = <&hdmi_en>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&hdmi_ddc>; - status = "okay"; +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + status = "okay"; + samsung,invert-vden; + samsung,invert-vclk; + #address-cells = <1>; + #size-cells = <0>; + port@3 { + reg = <3>; + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; }; +}; - i2c@138E0000 { - status = "okay"; +&hdmi { + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + hdmi-en-supply = <&hdmi_en>; + vdd-supply = <&ldo3_reg>; + vdd_osc-supply = <&ldo4_reg>; + vdd_pll-supply = <&ldo3_reg>; + ddc = <&hdmi_ddc>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo3_reg>; + vusb_a-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + tsp@4a { + /* TBD: Atmel maXtouch touchscreen */ + reg = <0x4a>; }; }; -&cpu0 { - cpu0-supply = <&vdd_arm_reg>; +&i2c_5 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + status = "okay"; + + vdd_arm_reg: pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + + max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; + max8952,default-mode = <0>; + max8952,dvs-mode-microvolt = <1250000>, <1200000>, + <1050000>, <950000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + + regulator-name = "vdd_arm"; + regulator-min-microvolt = <770000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + pmic@66 { + compatible = "national,lp3974"; + reg = <0x66>; + + max8998,pmic-buck1-default-dvs-idx = <0>; + max8998,pmic-buck1-dvs-gpios = <&gpx0 5 0>, + <&gpx0 6 0>; + max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, + <1100000>, <1000000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gpe2 0 0>; + max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB+MIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD+VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "PS_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VHIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "CAM_I_HOST_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "CAM_S_ANA_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VINT_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VG3D_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + }; + + safeout1_reg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-always-on; + }; + + safeout2_reg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; +}; + +&i2c_8 { + status = "okay"; +}; + +&mdma1 { + reg = <0x12840000 0x1000>; +}; + +&mixer { + status = "okay"; +}; + +&ohci { + status = "okay"; + port@0 { + status = "okay"; + }; }; &pinctrl_1 { @@ -568,6 +532,42 @@ }; }; -&mdma1 { - reg = <0x12840000 0x1000>; +&pwm { + compatible = "samsung,s5p6440-pwm"; + status = "okay"; +}; + +&sdhci_0 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo5_reg>; + cd-gpios = <&gpx3 4 0>; + cd-inverted; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index d9c8efeef208..538901123d37 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -30,6 +30,9 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; cooling-min-level = <13>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ @@ -39,6 +42,84 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp05 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp06 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + }; + opp07 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp08 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp09 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp10 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp11 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp12 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + opp13 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index ca7d168d1dd6..db52841297a5 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -107,6 +107,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + /* RSTN signal for eMMC */ &sd1_cd { samsung,pin-pud = <0>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 44684e57ead1..8632f35c6c26 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -13,6 +13,7 @@ /dts-v1/; #include "exynos4412-odroid-common.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Hardkernel ODROID-U3 board based on Exynos4412"; @@ -61,3 +62,10 @@ "Speakers", "SPKL", "Speakers", "SPKR"; }; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 84c76310b312..9d528af68c1a 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -78,6 +78,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &fimd { pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index afc199d78cb9..2a1ebb76ebe0 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -190,6 +190,9 @@ interrupt-parent = <&gpx2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; reg = <0x36>; + + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; }; }; @@ -285,6 +288,10 @@ status = "okay"; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &csis_0 { status = "okay"; vddcore-supply = <&ldo8_reg>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index b78ada70bd05..ca0e3c15977f 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -30,6 +30,9 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; cooling-min-level = <13>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ @@ -39,18 +42,98 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@A02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@A03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp05 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp06 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + }; + opp07 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp08 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp09 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp10 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp11 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp12 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + opp13 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 7e728a1b5559..db3f65f3eb45 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -117,6 +117,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &dp { status = "okay"; samsung,color-space = <0>; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 886cfca044ac..880917e508b2 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -12,807 +12,805 @@ * published by the Free Software Foundation. */ -/ { - pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpc4-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpc4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpc4-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpc4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@13400000 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0", "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_port_a: cam-port-a { - samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", - "gph1-0", "gph1-1", "gph1-2", "gph1-3", - "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@10d10000 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_rxd: c2c-rxd { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - c2c_txd: c2c-txd { - samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@03860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_hs_bus: i2c2-hs-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_hs_bus: i2c3-hs-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + ac97_bus: ac97-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpb2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpb2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_hs_bus: i2c0-hs-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_hs_bus: i2c1-hs-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc3-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpc4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpc4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpc4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + dp_hpd: dp_hpd { + samsung,pins = "gpx0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c2_bus: cam-i2c2-bus { + samsung,pins = "gpe0-6", "gpe1-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_bayrgb_bus: cam-bayrgb-bus { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0", "gpg2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_port_a: cam-port-a { + samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", + "gph1-0", "gph1-1", "gph1-2", "gph1-3", + "gph1-4", "gph1-5", "gph1-6", "gph1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + c2c_rxd: c2c-rxd { + samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", + "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", + "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + c2c_txd: c2c-txd { + samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", + "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", + "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_3 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 4fe186d01f8a..15aea760c1da 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -74,6 +74,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &dp { samsung,color-space = <0>; samsung,dynamic-range = <0>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index b7f4122df456..0720caab5511 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -235,6 +235,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &dp { status = "okay"; pinctrl-names = "default"; @@ -688,6 +692,7 @@ status = "okay"; samsung,spi-src-clk = <0>; num-cs = <1>; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; }; &usbdrd_dwc3 { diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index d03f9b8d376d..c1edd6d038a9 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -65,6 +65,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &dp { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index bf9bee67c416..b24610ea8c2a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -19,7 +19,6 @@ #include <dt-bindings/clock/exynos5250.h> #include "exynos5.dtsi" -#include "exynos5250-pinctrl.dtsi" #include "exynos4-cpu-thermal.dtsi" #include <dt-bindings/clock/exynos-audss-clk.h> @@ -63,6 +62,28 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; cooling-min-level = <15>; cooling-max-level = <9>; #cooling-cells = <2>; /* min followed by max */ @@ -1062,3 +1083,5 @@ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; + +#include "exynos5250-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index be3e02530b42..cebeaab3abec 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -62,13 +62,13 @@ }; &uart0 { - status = "okay"; + status = "okay"; }; &uart1 { - status = "okay"; + status = "okay"; }; &uart2 { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 8b153166ebdb..130563b2ca95 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -12,711 +12,710 @@ * published by the Free Software Foundation. */ -/ { - pinctrl@13400000 { - gpy7: gpy7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@13410000 { - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_rclk: sd0-rclk { - samsung,pins = "gpc0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <1>; - samsung,pin-drv = <3>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_int: sd1-int { - samsung,pins = "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - }; - - pinctrl@14000000 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@14010000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c4_hs_bus: i2c4-hs-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c5_hs_bus: i2c5-hs-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c6_hs_bus: i2c6-hs-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c7_hs_bus: i2c7-hs-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c8_hs_bus: i2c8-hs-bus { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c9_hs_bus: i2c9-hs-bus { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c10_hs_bus: i2c10-hs-bus { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@03860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; +&pinctrl_0 { + gpy7: gpy7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <23 0>, <24 0>, <25 0>, <25 1>, + <26 0>, <26 1>, <27 0>, <27 1>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&combiner>; + #interrupt-cells = <2>; + interrupts = <28 0>, <28 1>, <29 0>, <29 1>, + <30 0>, <30 1>, <31 0>, <31 1>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + dp_hpd: dp_hpd { + samsung,pins = "gpx0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_int: sd1-int { + samsung,pins = "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; +}; + +&pinctrl_2 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpj4: gpj4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c2_bus: cam-i2c2-bus { + samsung,pins = "gpf0-4", "gpf0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_bayrgb_bus: cam-bayrgb-bus { + samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", + "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", + "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", + "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", + "gpg2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_3 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_hs_bus: i2c4-hs-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_hs_bus: i2c5-hs-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", + "gpb1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_hs_bus: i2c6-hs-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpb2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpb2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_hs_bus: i2c7-hs-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_hs_bus: i2c8-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_hs_bus: i2c9-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_hs_bus: i2c10-hs-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_4 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 534f27ceb10b..df9aee92ecf4 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -15,7 +15,6 @@ #include <dt-bindings/clock/exynos5420.h> #include "exynos5.dtsi" -#include "exynos5420-pinctrl.dtsi" #include <dt-bindings/clock/exynos-audss-clk.h> @@ -1166,3 +1165,5 @@ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; + +#include "exynos5420-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi new file mode 100644 index 000000000000..2b289d7c0d13 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi @@ -0,0 +1,59 @@ +/* + * Device tree sources for Exynos5422 thermal zone + * + * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com> + * Anand Moon <linux.amoon@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <dt-bindings/thermal/thermal.h> + +/ { + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0 0>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + cpu_alert0: cpu-alert-0 { + temperature = <50000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert1: cpu-alert-1 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert2: cpu-alert-2 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 000000000000..b7f60c855459 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,81 @@ +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file to provide cpu ordering + * which could boot a cortex-a7 from cpu0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 8adf455744e9..79ffdfe712aa 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -15,6 +15,8 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/sound/samsung-i2s.h> #include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" +#include "exynos5422-cpu-thermal.dtsi" / { memory { @@ -107,6 +109,15 @@ clocks = <&i2s0 CLK_I2S_CDCLK>; }; }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 20972 0>; + cooling-min-state = <0>; + cooling-max-state = <3>; + #cooling-cells = <2>; + cooling-levels = <0 130 170 230>; + }; }; &clock_audss { @@ -461,6 +472,32 @@ */ pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; pinctrl-names = "default"; + samsung,pwm-outputs = <0>; + status = "okay"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&tmu_gpu { + vtmu-supply = <&ldo7_reg>; status = "okay"; }; @@ -477,3 +514,13 @@ &usbdrd_dwc3_1 { dr_mode = "otg"; }; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index b69be5c499cf..feb9d34b239c 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -144,6 +144,15 @@ clock-names = "ipg", "per"; }; + rtc: rtc@10007000 { + compatible = "fsl,imx21-rtc"; + reg = <0x10007000 0x1000>; + interrupts = <22>; + clocks = <&clks IMX27_CLK_CKIL>, + <&clks IMX27_CLK_RTC_IPG_GATE>; + clock-names = "ref", "ipg"; + }; + kpp: kpp@10008000 { compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; reg = <0x10008000 0x1000>; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index b0d5542ac829..53fd75c8ffcf 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -228,10 +228,11 @@ >; }; + /* open drain */ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec >; }; diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts index 82d623d05915..66e47de5e826 100644 --- a/arch/arm/boot/dts/imx53-qsrb.dts +++ b/arch/arm/boot/dts/imx53-qsrb.dts @@ -20,15 +20,7 @@ }; &iomuxc { - i2c1 { - /* open drain */ - pinctrl_i2c1_qsrb: i2c1grp-1 { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec - MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec - >; - }; - + imx53-qsrb { pinctrl_pmic: pmicgrp { fsl,pins = < MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */ @@ -38,10 +30,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_qsrb>; - status = "okay"; - pmic: mc34708@8 { compatible = "fsl,mc34708"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index f2867c4b34a8..7b31fdb79ced 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -248,7 +248,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 4493f6e99330..1b66328a8498 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -316,10 +316,13 @@ }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ status = "okay"; }; @@ -380,7 +383,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -469,7 +471,34 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a857d1294609..7c51839ff934 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -322,10 +322,13 @@ }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ status = "okay"; }; @@ -385,7 +388,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -476,7 +478,34 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 1afe3385e2d2..929e0b37bd9e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -415,10 +415,13 @@ }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ status = "okay"; }; @@ -478,7 +481,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -568,6 +570,34 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index d1866a0a2f13..741f3d529e3e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -250,7 +250,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 5c6587f6c420..d1e5048b00b5 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -202,7 +202,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index d7fe6672d00c..340bc8e42650 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -54,6 +54,17 @@ gpio = <&gpio3 22 0>; enable-active-high; }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; }; gpio-keys { @@ -149,6 +160,20 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -245,6 +270,20 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e329ca5c3322..c37bb9ff9fac 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -28,6 +28,71 @@ }; }; + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai>; + audio-asrc = <&asrc>; + audio-codec = <&codec>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + sound-spdif { compatible = "fsl,imx-audio-spdif", "fsl,imx-sabreauto-spdif"; @@ -45,6 +110,19 @@ }; }; +&clks { + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_PLL4_POST_DIV>, + <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, + <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -61,6 +139,16 @@ }; }; +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -76,6 +164,10 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -180,6 +272,18 @@ }; }; }; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&codec_osc>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + }; &i2c3 { @@ -257,6 +361,21 @@ >; }; + pinctrl_esai: esaigrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 @@ -318,6 +437,12 @@ >; }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -462,6 +587,18 @@ status = "okay"; }; +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 782379320517..ce4c7313f509 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -53,6 +53,17 @@ gpio = <&gpio3 22 0>; enable-active-high; }; + + reg_can_xcvr: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; }; gpio-keys { @@ -148,6 +159,20 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -239,6 +264,20 @@ >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 944eb81cb2b8..2c07d3a86b61 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -141,6 +141,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b57033e8c633..e716e6f301c6 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -300,8 +300,19 @@ }; esai: esai@02024000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, + <&clks IMX6QDL_CLK_ESAI_MEM>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>, + <&clks IMX6QDL_CLK_ESAI_IPG>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "core", "mem", "extal", "fsys", "dma"; + dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; + dma-names = "rx", "tx"; + status = "disabled"; }; ssi1: ssi@02028000 { @@ -353,8 +364,28 @@ }; asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, + <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "dma"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; }; spba@0203c000 { @@ -687,22 +718,23 @@ fsl,anatop = <&anatop>; }; - snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x020cc000 0x4000>; + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; - snvs_rtc: snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - reg = <0x34 0x58>; + regmap = <&snvs>; + offset = <0x34>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, <0 20 IRQ_TYPE_LEVEL_HIGH>; }; - snvs_poweroff: snvs-poweroff@38 { - compatible = "fsl,sec-v4.0-poweroff"; - reg = <0x38 0x4>; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; status = "disabled"; }; }; @@ -836,10 +868,31 @@ reg = <0x02100000 0x100000>; ranges; - caam@02100000 { - reg = <0x02100000 0x40000>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, - <0 106 IRQ_TYPE_LEVEL_HIGH>; + crypto: caam@2100000 { + compatible = "fsl,sec-v4.0"; + fsl,sec-era = <4>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2100000 0x10000>; + ranges = <0 0x2100000 0x10000>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, + <&clks IMX6QDL_CLK_CAAM_ACLK>, + <&clks IMX6QDL_CLK_CAAM_IPG>, + <&clks IMX6QDL_CLK_EIM_SLOW>; + clock-names = "mem", "aclk", "ipg", "emi_slow"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; }; aipstz@0217c000 { /* AIPSTZ2 */ diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 0da906bd8df2..10c69963100f 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -61,7 +61,9 @@ usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ + <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ }; @@ -73,16 +75,16 @@ status = "okay"; }; -&uart2 { +&uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; -&uart3 { +&uart5 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; status = "okay"; }; @@ -130,14 +132,6 @@ >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1 - MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1 - MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1 - MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1 - >; - }; pinctrl_uart3: uart3grp { fsl,pins = < @@ -146,6 +140,15 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 @@ -158,6 +161,7 @@ MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 >; }; @@ -173,6 +177,7 @@ MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 >; }; @@ -188,6 +193,7 @@ MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 >; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index a78e715e3982..320a27f8889e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -563,22 +563,23 @@ fsl,anatop = <&anatop>; }; - snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x020cc000 0x4000>; + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; - snvs_rtc: snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - reg = <0x34 0x58>; + regmap = <&snvs>; + offset = <0x34>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, <0 20 IRQ_TYPE_LEVEL_HIGH>; }; - snvs_poweroff: snvs-poweroff@38 { - compatible = "fsl,sec-v4.0-poweroff"; - reg = <0x38 0x4>; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 708175d59b9c..c94f2ea2316e 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/imx6sx-clock.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx6sx-pinfunc.h" #include "skeleton.dtsi" @@ -662,22 +663,31 @@ }; snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x020cc000 0x4000>; + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; - snvs_rtc: snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - reg = <0x34 0x58>; + regmap = <&snvs>; + offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; }; - snvs_poweroff: snvs-poweroff@38 { - compatible = "fsl,sec-v4.0-poweroff"; - reg = <0x38 0x4>; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; status = "disabled"; }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; }; epit1: epit@020d0000 { @@ -738,6 +748,33 @@ reg = <0x02100000 0x100000>; ranges; + crypto: caam@2100000 { + compatible = "fsl,sec-v4.0"; + fsl,sec-era = <4>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2100000 0x10000>; + ranges = <0 0x2100000 0x10000>; + interrupt-parent = <&intc>; + clocks = <&clks IMX6SX_CLK_CAAM_MEM>, + <&clks IMX6SX_CLK_CAAM_ACLK>, + <&clks IMX6SX_CLK_CAAM_IPG>, + <&clks IMX6SX_CLK_EIM_SLOW>; + clock-names = "mem", "aclk", "ipg", "emi_slow"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + usbotg1: usb@02184000 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts new file mode 100644 index 000000000000..25746b122ea6 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sim2: sim2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h new file mode 100644 index 000000000000..20c7da1affce --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pinfunc.h @@ -0,0 +1,938 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6UL_PINFUNC_H +#define __DTS_IMX6UL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 + +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 + +#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 +#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 +#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x0000 2 0 +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 +#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x0000 3 0 +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x0000 3 0 +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0000 8 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x0000 3 0 +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x0000 8 0 +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x0000 3 0 +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0000 8 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x0000 3 0 +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x0000 3 0 +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0000 8 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x0000 3 0 +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x0000 8 0 +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x0000 3 0 +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0000 8 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x0000 8 0 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0000 8 0 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x0000 8 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 +#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 +#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 +#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 +#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 +#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 +#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0000 8 0 +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 +#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 +#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 +#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 +#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 +#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 +#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 +#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 +#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 +#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 +#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x0000 8 0 +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 +#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 +#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 +#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 +#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 +#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 +#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 +#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 +#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 + +#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi new file mode 100644 index 000000000000..09edbedfd908 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -0,0 +1,707 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx6ul-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx6ul-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-latency = <61036>; /* two CLK32 periods */ + operating-points = < + /* kHz uV */ + 528000 1250000 + 396000 1150000 + 198000 1150000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1250000 + 396000 1150000 + 198000 1150000 + >; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", + "secondary_sel", "step", "pll1_sw", + "pll1_sys", "pll1_bypass", "pll1", + "pll1_bypass_src", "osc"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x1000>, + <0x00a04000 0x2000>, + <0x00a06000 0x2000>; + }; + + ckil: clock-cli { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@02018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02018000 0x4000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02020000 0x4000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart8: serial@02024000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02024000 0x4000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT1_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + fec2: ethernet@020b4000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x020b4000 0x4000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET2_REF_125M>, + <&clks IMX6UL_CLK_ENET2_REF_125M>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + }; + + src: src@020d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + gpt2: gpt@020e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + }; + + pwm5: pwm@020f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm6: pwm@020f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm7: pwm@020f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm8: pwm@020fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + fec1: ethernet@02188000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET_REF>, + <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + qspi: qspi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_QSPI>, + <&clks IMX6UL_CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@021fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021fc000 0x4000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index c42cf8db0451..b738ce0f9d9b 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -121,6 +121,209 @@ clock-output-names = "osc"; }; + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; + }; + + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -212,6 +415,37 @@ #interrupt-cells = <2>; }; + wdog1: wdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: wdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + gpt1: gpt@302d0000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302d0000 0x10000>; @@ -291,17 +525,31 @@ }; snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x30370000 0x10000>; + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; - snvs-rtc-lp@34 { + snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - reg = <0x34 0x58>; + regmap = <&snvs>; + offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; }; clks: ccm@30380000 { diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/kirkwood-d2net.dts index 6b7856025001..e1c25c35e9ce 100644 --- a/arch/arm/boot/dts/kirkwood-d2net.dts +++ b/arch/arm/boot/dts/kirkwood-d2net.dts @@ -10,6 +10,7 @@ /dts-v1/; +#include <dt-bindings/leds/leds-ns2.h> #include "kirkwood-netxbig.dtsi" / { @@ -28,6 +29,10 @@ label = "d2net_v2:blue:sata"; slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + modes-map = <NS_V2_LED_OFF 1 0 + NS_V2_LED_ON 0 1 + NS_V2_LED_ON 1 1 + NS_V2_LED_SATA 0 0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index da674bbd49a8..4121674abd1c 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/leds/leds-ns2.h> #include "kirkwood-ns2-common.dtsi" / { @@ -27,6 +28,10 @@ label = "ns2:blue:sata"; slow-gpio = <&gpio0 29 0>; cmd-gpio = <&gpio0 30 0>; + modes-map = <NS_V2_LED_OFF 1 0 + NS_V2_LED_ON 0 1 + NS_V2_LED_ON 1 1 + NS_V2_LED_SATA 0 0>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-lswvl.dts b/arch/arm/boot/dts/kirkwood-lswvl.dts new file mode 100644 index 000000000000..09eed3cea0af --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-lswvl.dts @@ -0,0 +1,301 @@ +/* + * Device Tree file for Buffalo Linkstation LS-WVL/VL + * + * Copyright (C) 2015, rogershimizu@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Buffalo Linkstation LS-WVL/VL"; + compatible = "buffalo,lswvl", "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd0: pmx-power-hdd0 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_power_hdd1: pmx-power-hdd1 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + pmx_led_hdderr0: pmx-led-hdderr0 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_hdderr1: pmx-led-hdderr1 { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function-red { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + spi@10600 { + status = "okay"; + + m25p40@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p40", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x60000>; + label = "uboot"; + read-only; + }; + + partition@60000 { + reg = <0x60000 0x10000>; + label = "dtb"; + read-only; + }; + + partition@70000 { + reg = <0x70000 0x10000>; + label = "uboot_env"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + + button@1 { + label = "Function Button"; + linux,code = <KEY_OPTION>; + gpios = <&gpio0 45 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Power-on Switch"; + linux,code = <KEY_RESERVED>; + linux,input-type = <5>; + gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + }; + + button@3 { + label = "Power-auto Switch"; + linux,code = <KEY_ESC>; + linux,input-type = <5>; + gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue + &pmx_led_hdderr0 + &pmx_led_hdderr1>; + pinctrl-names = "default"; + + led@1 { + label = "lswvl:red:alarm"; + gpios = <&gpio0 36 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "lswvl:red:func"; + gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; + }; + + led@3 { + label = "lswvl:amber:info"; + gpios = <&gpio0 38 GPIO_ACTIVE_LOW>; + }; + + led@4 { + label = "lswvl:blue:func"; + gpios = <&gpio0 39 GPIO_ACTIVE_LOW>; + }; + + led@5 { + label = "lswvl:blue:power"; + gpios = <&gpio0 40 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + led@6 { + label = "lswvl:red:hdderr0"; + gpios = <&gpio0 34 GPIO_ACTIVE_LOW>; + }; + + led@7 { + label = "lswvl:red:hdderr1"; + gpios = <&gpio0 35 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpios = <&gpio0 17 GPIO_ACTIVE_LOW + &gpio0 16 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + + alarm-gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + hdd_power0: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + hdd_power1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "HDD1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-lswxl.dts b/arch/arm/boot/dts/kirkwood-lswxl.dts new file mode 100644 index 000000000000..f5db16a08597 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-lswxl.dts @@ -0,0 +1,301 @@ +/* + * Device Tree file for Buffalo Linkstation LS-WXL/WSXL + * + * Copyright (C) 2015, rogershimizu@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Buffalo Linkstation LS-WXL/WSXL"; + compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pmx_power_hdd0: pmx-power-hdd0 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_power_hdd1: pmx-power-hdd1 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_usb_vbus: pmx-usb-vbus { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_hdderr0: pmx-led-hdderr0 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_led_hdderr1: pmx-led-hdderr1 { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_alarm: pmx-led-alarm { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_led_function_red: pmx-led-function-red { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + pmx_led_function_blue: pmx-led-function-blue { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + pmx_led_info: pmx-led-info { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + pmx_led_power: pmx-led-power { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + pmx_button_function: pmx-button-function { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_power_auto_switch: pmx-power-auto-switch { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + spi@10600 { + status = "okay"; + + m25p40@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p40", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + mode = <0>; + + partition@0 { + reg = <0x0 0x60000>; + label = "uboot"; + read-only; + }; + + partition@60000 { + reg = <0x60000 0x10000>; + label = "dtb"; + read-only; + }; + + partition@70000 { + reg = <0x70000 0x10000>; + label = "uboot_env"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + + button@1 { + label = "Function Button"; + linux,code = <KEY_OPTION>; + gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Power-on Switch"; + linux,code = <KEY_RESERVED>; + linux,input-type = <5>; + gpios = <&gpio1 42 GPIO_ACTIVE_LOW>; + }; + + button@3 { + label = "Power-auto Switch"; + linux,code = <KEY_ESC>; + linux,input-type = <5>; + gpios = <&gpio1 43 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue + &pmx_led_hdderr0 + &pmx_led_hdderr1>; + pinctrl-names = "default"; + + led@1 { + label = "lswxl:blue:func"; + gpios = <&gpio1 36 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "lswxl:red:alarm"; + gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; + }; + + led@3 { + label = "lswxl:amber:info"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led@4 { + label = "lswxl:blue:power"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led@5 { + label = "lswxl:red:func"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + led@6 { + label = "lswxl:red:hdderr0"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + led@7 { + label = "lswxl:red:hdderr1"; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpios = <&gpio0 47 GPIO_ACTIVE_LOW + &gpio0 48 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + + alarm-gpios = <&gpio1 49 GPIO_ACTIVE_HIGH>; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 37 GPIO_ACTIVE_HIGH>; + }; + hdd_power0: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + hdd_power1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "HDD1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index 53368d1022cc..190189d235e6 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/leds/leds-ns2.h> #include "kirkwood-ns2-common.dtsi" / { @@ -27,6 +28,10 @@ label = "ns2:blue:sata"; slow-gpio = <&gpio0 29 0>; cmd-gpio = <&gpio0 30 0>; + modes-map = <NS_V2_LED_OFF 1 0 + NS_V2_LED_ON 0 1 + NS_V2_LED_ON 1 1 + NS_V2_LED_SATA 0 0>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index 72c78d0b1116..55cc41d9c80c 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/leds/leds-ns2.h> #include "kirkwood-ns2-common.dtsi" / { @@ -46,6 +47,10 @@ label = "ns2:blue:sata"; slow-gpio = <&gpio0 29 0>; cmd-gpio = <&gpio0 30 0>; + modes-map = <NS_V2_LED_OFF 1 0 + NS_V2_LED_ON 0 1 + NS_V2_LED_ON 1 1 + NS_V2_LED_SATA 0 0>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index c441bf62c09f..9935f3ec29b4 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/leds/leds-ns2.h> #include "kirkwood-ns2-common.dtsi" / { @@ -47,6 +48,10 @@ label = "ns2:blue:sata"; slow-gpio = <&gpio0 29 0>; cmd-gpio = <&gpio0 30 0>; + modes-map = <NS_V2_LED_OFF 1 0 + NS_V2_LED_ON 0 1 + NS_V2_LED_ON 1 1 + NS_V2_LED_SATA 0 0>; }; }; }; diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 204da5b52ef9..2c569a6ddc9a 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -13,6 +13,12 @@ #include "armv7-m.dtsi" +#include "dt-bindings/clock/lpc18xx-cgu.h" +#include "dt-bindings/clock/lpc18xx-ccu.h" + +#define LPC_PIN(port, pin) (0x##port * 32 + pin) +#define LPC_GPIO(port, pin) (port * 32 + pin) + / { cpus { #address-cells = <1>; @@ -22,6 +28,7 @@ compatible = "arm,cortex-m3"; device_type = "cpu"; reg = <0x0>; + clocks = <&ccu1 CLK_CPU_CORE>; }; }; @@ -32,32 +39,173 @@ clock-frequency = <12000000>; }; - /* Temporary hardcode PLL1 until clk drivers are merged */ - pll1: pll1 { - compatible = "fixed-factor-clock"; - clocks = <&xtal>; + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; #clock-cells = <0>; - clock-div = <1>; - clock-mult = <12>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; }; }; soc { + mmcsd: mmcsd@40004000 { + compatible = "snps,dw-mshc"; + reg = <0x40004000 0x1000>; + interrupts = <6>; + num-slots = <1>; + clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; + clock-names = "ciu", "biu"; + status = "disabled"; + }; + + usb0: ehci@40006100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40006100 0x100>; + interrupts = <8>; + clocks = <&ccu1 CLK_CPU_USB0>; + phys = <&usb0_otg_phy>; + phy-names = "usb"; + has-transaction-translator; + status = "disabled"; + }; + + usb1: ehci@40007100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40007100 0x100>; + interrupts = <9>; + clocks = <&ccu1 CLK_CPU_USB1>; + status = "disabled"; + }; + + emc: memory-controller@40005000 { + compatible = "arm,pl172", "arm,primecell"; + reg = <0x40005000 0x1000>; + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x1c000000 0x1000000 + 1 0 0x1d000000 0x1000000 + 2 0 0x1e000000 0x1000000 + 3 0 0x1f000000 0x1000000>; + status = "disabled"; + }; + + lcdc: lcd-controller@40008000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x40008000 0x1000>; + interrupts = <7>; + interrupt-names = "combined"; + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + creg: syscon@40043000 { + compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; + reg = <0x40043000 0x1000>; + clocks = <&ccu1 CLK_CPU_CREG>; + + usb0_otg_phy: phy@004 { + compatible = "nxp,lpc1850-usb-otg-phy"; + clocks = <&ccu1 CLK_USB0>; + #phy-cells = <0>; + }; + }; + + cgu: clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + ccu1: clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + uart0: serial@40081000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart1: serial@40082000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + clock-names = "uartclk", "reg"; + status = "disabled"; + }; + + ssp0: spi@40083000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x40083000 0x1000>; + interrupts = <22>; + clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -65,7 +213,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; interrupts = <12>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER0>; clock-names = "timerclk"; }; @@ -73,25 +221,41 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40085000 0x1000>; interrupts = <13>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER1>; clock-names = "timerclk"; }; + pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + }; + + can1: can@400a4000 { + compatible = "bosch,c_can"; + reg = <0x400a4000 0x1000>; + interrupts = <43>; + clocks = <&ccu1 CLK_APB1_CAN1>; + status = "disabled"; + }; + uart2: serial@400c1000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart3: serial@400c2000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; + clock-names = "uartclk", "reg"; status = "disabled"; }; @@ -99,7 +263,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c3000 0x1000>; interrupts = <14>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER2>; clock-names = "timerclk"; }; @@ -107,8 +271,75 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c4000 0x1000>; interrupts = <15>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; + + ssp1: spi@400c5000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x400c5000 0x1000>; + interrupts = <23>; + clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@400e2000 { + compatible = "bosch,c_can"; + reg = <0x400e2000 0x1000>; + interrupts = <51>; + clocks = <&ccu1 CLK_APB3_CAN0>; + status = "disabled"; + }; + + gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, + <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, + <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, + <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, + <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, + <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, + <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, + <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, + <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, + <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, + <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, + <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, + <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, + <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, + <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, + <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, + <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, + <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, + <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, + <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, + <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, + <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, + <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, + <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, + <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, + <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, + <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, + <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, + <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, + <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, + <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, + <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, + <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, + <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, + <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, + <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, + <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, + <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; + }; }; }; diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/lpc4337-ciaa.dts new file mode 100644 index 000000000000..5f500c1ad89c --- /dev/null +++ b/arch/arm/boot/dts/lpc4337-ciaa.dts @@ -0,0 +1,187 @@ +/* + * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) + * + * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include "dt-bindings/gpio/gpio.h" + +/ { + model = "CIAA NXP LPC4337"; + compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; + + aliases { + serial0 = &uart2; + serial1 = &uart3; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x0800000>; /* 8 MB */ + }; +}; + +&pinctrl { + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "p7_7"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + ssp_pins: ssp-pins { + ssp1_cs { + pins = "p6_7"; + function = "gpio"; + bias-pull-up; + bias-disable; + }; + + ssp1_miso_mosi { + pins = "p1_3", "p1_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + input-enable; + input-schmitt-disable; + }; + + ssp1_sck { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-disable; + }; + }; + + uart2_pins: uart2-pins { + uart2_rx_cfg { + pins = "p7_2"; + function = "uart2"; + bias-disable; + input-enable; + }; + + uart2_tx_cfg { + pins = "p7_1"; + function = "uart2"; + bias-disable; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-disable; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp_pins>; + cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; + num-cs = <1>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index d04072f40817..32bc7ff4eb2a 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -36,10 +36,250 @@ }; }; -&pll1 { - clock-mult = <15>; +&pinctrl { + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_cs2_cfg { + pins = "p1_5", "pd_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + enet_mii_pins: enet-mii-pins { + enet_mii_rxd0_3_cfg { + pins = "p1_15", "p0_0", "p9_3", "p9_2"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_txd0_3_cfg { + pins = "p1_18", "p1_20", "p9_4", "p9_5"; + function = "enet"; + bias-disable; + }; + + enet_mii_crs_col_cfg { + pins = "p9_0", "p9_6"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_rx_clk_dv_er_cfg { + pins = "pc_0", "p1_16", "p9_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_tx_clk_en_cfg { + pins = "p1_19", "p0_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash@0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition@1 { + label = "kernel"; + reg = <0x040000 0x2C0000>; /* 2.75 MiB */ + }; + + partition@2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <30>; + mpmc,read-access-delay = <90>; + mpmc,page-mode-read-delay = <55>; + mpmc,write-access-delay = <55>; + mpmc,turn-round-delay = <55>; + + ext_sram: sram@2,0 { + compatible = "mmio-sram"; + reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <25000000>; +}; + +&mac { + status = "okay"; + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_mii_pins>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 08a6f757f924..5f7bdad80963 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -15,6 +15,9 @@ #include "lpc18xx.dtsi" #include "lpc4357.dtsi" +#include "dt-bindings/input/input.h" +#include "dt-bindings/gpio/gpio.h" + / { model = "Embedded Artists' LPC4357 Developer's Kit"; compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; @@ -34,8 +37,472 @@ device_type = "memory"; reg = <0x28000000 0x2000000>; /* 32 MB */ }; + + /* vmmc is controlled by sdmmc host internally */ + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + gpio_joystick { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_joystick_pins>; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + autorepeat; + + button@0 { + label = "joy_enter"; + linux,code = <KEY_ENTER>; + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; + + button@1 { + label = "joy_left"; + linux,code = <KEY_LEFT>; + gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "joy_up"; + linux,code = <KEY_UP>; + gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; + }; + + button@3 { + label = "joy_right"; + linux,code = <KEY_RIGHT>; + gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; + }; + + button@4 { + label = "joy_down"; + linux,code = <KEY_DOWN>; + gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; + }; + }; + + leds_mmio { + compatible = "gpio-leds"; + + led1 { + gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; + }; + + led4 { + gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; + }; + + led5 { + gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; + }; + + led6 { + gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; + }; + + led7 { + gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; + }; + + led8 { + gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; + }; + + led9 { + gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; + }; + + led10 { + gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; + }; + + led11 { + gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; + }; + + led12 { + gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; + }; + + led13 { + gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; + }; + + led14 { + gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; + }; + + led15 { + gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; + }; + + led16 { + gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_31_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3", + "pd_2", "pd_3", "pd_4", "pd_5", + "pd_6", "pd_7", "pd_8", "pd_9", + "pe_5", "pe_6", "pe_7", "pe_8", + "pe_9", "pe_10", "pe_11", "pe_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_3_cfg { + pins = "p1_5", "p6_3", "pd_12", "pd_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + gpio_joystick_pins: gpio-joystick-pins { + gpio_joystick_cfg { + pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + bias-pull-down; + input-enable; + }; + + sdmmc_pow_cfg { + pins = "pc_9"; + function = "sdmmc"; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p9_3"; + function = "uart3"; + bias-pull-down; + }; + }; + + usb0_pins: usb0-pins { + usb0_pwr_enable { + pins = "p2_3"; + function = "usb0"; + }; + + usb0_pwr_fault { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash@0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition@1 { + label = "kernel"; + reg = <0x040000 0x2c0000>; /* 2.75 MiB */ + }; + + partition@2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + + mmio_leds: gpio@2,0 { + compatible = "ti,7416374"; + reg = <2 0 0x2>; + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + +&mmcsd { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; }; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 9c5e16ba8c95..0521e6864cb7 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -58,6 +58,55 @@ enet0_sgmii_phy = &sgmii_phy1c; enet1_sgmii_phy = &sgmii_phy1d; }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; }; &dspi0 { @@ -75,10 +124,31 @@ }; }; +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1c>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1d>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy3>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + &i2c0 { status = "okay"; pca9547: mux@77 { + compatible = "nxp,pca9547"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; @@ -133,6 +203,21 @@ reg = <0x4c>; }; }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + codec: sgtl5000@2a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&sys_mclk 1>; + }; + }; }; }; @@ -231,6 +316,10 @@ }; }; +&sai2 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index a2c591e2d918..e008f9367510 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -56,6 +56,55 @@ enet0_sgmii_phy = &sgmii_phy2; enet1_sgmii_phy = &sgmii_phy0; }; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + }; + }; }; &dspi1 { @@ -73,12 +122,40 @@ }; }; +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy0>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; + codec: sgtl5000@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&sys_mclk 1>; + }; }; &ifc { @@ -118,6 +195,10 @@ }; }; +&sai1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index c70bb27ac65a..973a496207fc 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -53,6 +53,9 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; serial0 = &lpuart0; serial1 = &lpuart1; serial2 = &lpuart2; @@ -184,7 +187,7 @@ }; dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; @@ -197,7 +200,7 @@ }; dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; @@ -342,28 +345,30 @@ }; sai1: sai@2b50000 { + #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; - clock-names = "sai"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, <&edma0 1 46>; - big-endian; status = "disabled"; }; sai2: sai@2b60000 { + #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; - clock-names = "sai"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, <&edma0 1 44>; - big-endian; status = "disabled"; }; @@ -391,6 +396,91 @@ reg = <0x0 0x2d24000 0x0 0x4000>; }; + enet0: ethernet@2d10000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + fsl,magic-packet; + ranges; + + queue-group@2d10000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d10000 0x0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + }; + + queue-group@2d14000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d14000 0x0 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + enet1: ethernet@2d50000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + ranges; + + queue-group@2d50000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d50000 0x0 0x1000>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + }; + + queue-group@2d54000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d54000 0x0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + enet2: ethernet@2d90000 { + compatible = "fsl,etsec2"; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + ranges; + + queue-group@2d90000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d90000 0x0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + }; + + queue-group@2d94000 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x2d94000 0x0 0x1000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + usb@8600000 { compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; reg = <0x0 0x8600000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts new file mode 100644 index 000000000000..17daeae6bbe8 --- /dev/null +++ b/arch/arm/boot/dts/mt6580-evbp1.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt6580.dtsi" + +/ { + model = "MediaTek MT6580 evaluation board"; + compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi new file mode 100644 index 000000000000..06fdf6c2d5fd --- /dev/null +++ b/arch/arm/boot/dts/mt6580.dtsi @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt6580"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6580-timer", + "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6580-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11005000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11006000 { + compatible = "mediatek,mt6580-uart", + "mediatek,mt6577-uart"; + reg = <0x11006000 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts index 36677382bdd8..357a91fc2d1d 100644 --- a/arch/arm/boot/dts/mt8135-evbp1.dts +++ b/arch/arm/boot/dts/mt8135-evbp1.dts @@ -24,6 +24,199 @@ }; }; +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + + mt6397regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + regulator-always-on; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + }; +}; + &uart3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 0aba9eb28e2b..08371dbae543 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -12,8 +12,10 @@ * GNU General Public License for more details. */ +#include <dt-bindings/clock/mt8135-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset-controller/mt8135-resets.h> #include "skeleton64.dtsi" #include "mt8135-pinfunc.h" @@ -88,12 +90,11 @@ #clock-cells = <0>; }; - uart_clk: dummy26m { + clk26m: clk26m { compatible = "fixed-clock"; - clock-frequency = <26000000>; #clock-cells = <0>; + clock-frequency = <26000000>; }; - }; soc { @@ -102,6 +103,26 @@ compatible = "simple-bus"; ranges; + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8135-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + #reset-cells = <1>; + #clock-cells = <1>; + compatible = "mediatek,mt8135-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + }; + + pericfg: pericfg@10003000 { + #reset-cells = <1>; + #clock-cells = <1>; + compatible = "mediatek,mt8135-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + /* * Pinctrl access register at 0x10005000 and 0x1020c000 through * regmap. Register 0x1000b000 is used by EINT. @@ -134,6 +155,19 @@ clock-names = "system-clk", "rtc-clk"; }; + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + }; + sysirq: interrupt-controller@10200030 { compatible = "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq"; @@ -143,6 +177,12 @@ reg = <0 0x10200030 0 0x1c>; }; + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt8135-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + syscfg_pctl_b: syscfg_pctl_b@1020c000 { compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; reg = <0 0x1020c000 0 0x1000>; @@ -163,7 +203,8 @@ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; reg = <0 0x11006000 0 0x400>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -171,7 +212,8 @@ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; reg = <0 0x11007000 0 0x400>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -179,7 +221,8 @@ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; reg = <0 0x11008000 0 0x400>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -187,7 +230,8 @@ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; reg = <0 0x11009000 0 0x400>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi new file mode 100644 index 000000000000..9ca2865a83d6 --- /dev/null +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -0,0 +1,369 @@ +/* + * Author: Anil Kumar <anilk4.v@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/input/input.h> + +#include "omap34xx.dtsi" +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "devkit8000::led1"; + gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "devkit8000::led2"; + gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ + default-state = "on"; + linux,default-trigger = "none"; + }; + + usr { + label = "devkit8000::led3"; + gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ + default-state = "on"; + linux,default-trigger = "usr"; + }; + + pmu_stat { + label = "devkit8000::pmu_stat"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "devkit8000"; + + ti,mcbsp = <&mcbsp2>; + ti,audio-routing = + "Ext Spk", "PREDRIVEL", + "Ext Spk", "PREDRIVER", + "MAINMIC", "Main Mic", + "Main Mic", "Mic Bias 1"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_EXTRA>; + gpio-key,wakeup; + }; + }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector@1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + status = "disabled"; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&twl_gpio { + ti,use-leds; + /* + * pulldowns: + * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c6>; +}; + +&twl_keypad { + linux,keymap = <MATRIX_KEY(0, 0, KEY_1) + MATRIX_KEY(1, 0, KEY_2) + MATRIX_KEY(2, 0, KEY_3) + MATRIX_KEY(0, 1, KEY_4) + MATRIX_KEY(1, 1, KEY_5) + MATRIX_KEY(2, 1, KEY_6) + MATRIX_KEY(3, 1, KEY_F5) + MATRIX_KEY(0, 2, KEY_7) + MATRIX_KEY(1, 2, KEY_8) + MATRIX_KEY(2, 2, KEY_9) + MATRIX_KEY(3, 2, KEY_F6) + MATRIX_KEY(0, 3, KEY_F7) + MATRIX_KEY(1, 3, KEY_0) + MATRIX_KEY(2, 3, KEY_F8) + MATRIX_KEY(4, 5, KEY_RESERVED) + MATRIX_KEY(4, 4, KEY_VOLUMEUP) + MATRIX_KEY(5, 5, KEY_VOLUMEDOWN) + >; +}; + +&wdt2 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "sw"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; + +&gpmc { + ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ + + ethernet@0,0 { + compatible = "davicom,dm9000"; + reg = <6 0x000 2 + 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + bank-width = <2>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + davicom,no-eeprom; + + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <0>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <180>; + gpmc,cs-wr-off-ns = <180>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <144>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <90>; + gpmc,cycle2cycle-delay-ns = <90>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; +}; + +&omap3_pmx_core { + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&vpll1 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + vdds_dsi-supply = <&vpll1>; + vdda_dac-supply = <&vdac>; + + port { + dpi_dvi_out: endpoint@0 { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi new file mode 100644 index 000000000000..e84184de2a4a --- /dev/null +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi @@ -0,0 +1,73 @@ +/* + * Author: Anthoine Bourgeois <anthoine.bourgois@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-devkit8000-common.dtsi" +/ { + aliases { + display0 = &lcd0; + display1 = &dvi0; + display2 = &tv0; + }; + + lcd0: display@0 { + compatible = "panel-dpi"; + label = "lcd"; + + enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; +}; + +&dss { + port { + dpi_lcd_out: endpoint@1 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&vio { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcspi2 { + + /* touch controller */ + ads7846@0 { + compatible = "ti,ads7846"; + vcc-supply = <&vio>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <27 0>; /* gpio_27 */ + pendown-gpio = <&gpio1 27 0>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <5>; + ti,debounce-rep = /bits/ 16 <1>; + ti,keep-vref-on = <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + + linux,wakeup; + }; +}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts new file mode 100644 index 000000000000..d5705356d52c --- /dev/null +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts @@ -0,0 +1,37 @@ +/* + * Author: Anthoine Bourgeois <anthoine.bourgois@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/* + * 4.3'' LCD panel sold with devkit8000 board + */ + +#include "omap3-devkit8000-lcd-common.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; + compatible = "timll,omap3-devkit8000", "ti,omap3"; + + lcd0: display@0 { + panel-timing { + clock-frequency = <10164705>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts new file mode 100644 index 000000000000..4afad4b233ec --- /dev/null +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts @@ -0,0 +1,37 @@ +/* + * Author: Anthoine Bourgeois <anthoine.bourgois@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/* + * 7.0'' LCD panel sold with some devkit8000 board + */ + +#include "omap3-devkit8000-lcd-common.dtsi" +/ { + model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; + compatible = "timll,omap3-devkit8000", "ti,omap3"; + + lcd0: display@0 { + panel-timing { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <1>; + hback-porch = <1>; + hsync-len = <48>; + vback-porch = <25>; + vfront-porch = <12>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index be2297116a14..40ac89482f5d 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -1,5 +1,5 @@ /* - * Author: Anil Kumar <anilk4.v@gmail.com> + * Author: Anthoine Bourgeois <anthoine.bourgeois@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -7,194 +7,13 @@ */ /dts-v1/; -#include "omap34xx.dtsi" +#include "omap3-devkit8000-common.dtsi" / { model = "TimLL OMAP3 Devkit8000"; compatible = "timll,omap3-devkit8000", "ti,omap3"; - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "devkit8000::led1"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "devkit8000::led2"; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ - default-state = "on"; - linux,default-trigger = "none"; - }; - - usr { - label = "devkit8000::led3"; - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ - default-state = "on"; - linux,default-trigger = "usr"; - }; - - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "devkit8000"; - - ti,mcbsp = <&mcbsp2>; - ti,audio-routing = - "Ext Spk", "PREDRIVEL", - "Ext Spk", "PREDRIVER", - "MAINMIC", "Main Mic", - "Main Mic", "Mic Bias 1"; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&wdt2 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&gpmc { - ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ - - ethernet@0,0 { - compatible = "davicom,dm9000"; - reg = <6 0x000 2 - 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ - bank-width = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - davicom,no-eeprom; - - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <0>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; + aliases { + display1 = &dvi0; + display2 = &tv0; }; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index e63133304a34..d0dd0365bfda 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -319,12 +319,12 @@ pinctrl-names = "default"; pinctrl-0 = <&tsc2048_pins>; - ti,x-min = <300>; - ti,x-max = <3000>; - ti,y-min = <600>; - ti,y-max = <3600>; - ti,x-plate-ohms = <80>; - ti,pressure-max = <255>; + ti,x-min = /bits/ 16 <300>; + ti,x-max = /bits/ 16 <3000>; + ti,y-min = /bits/ 16 <600>; + ti,y-max = /bits/ 16 <3600>; + ti,x-plate-ohms = /bits/ 16 <80>; + ti,pressure-max = /bits/ 16 <255>; ti,swap-xy; linux,wakeup; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 18e1649681c1..28430f1596f2 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -218,3 +218,58 @@ pinctrl-0 = <&uart2_pins>; }; +&mcbsp2 { + status = "okay"; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>; + + nand@0,0 { + linux,mtd-name= "micron,mt29c4g96maz"; + reg = <0 0 0>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x80000>; /* 512KiB */ + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1C0000>; /* 1792KiB */ + }; + partition@1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; /* 256KiB */ + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x800000>; /* 8192KiB */ + }; + partition@780000 { + label = "Filesystem"; + reg = <0xA80000 0>; + /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index df8908adb0cb..80d236ac64a5 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -62,6 +62,7 @@ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ >; }; @@ -123,7 +124,7 @@ label = "lcd35"; reg = <1>; /* CS1 */ - spi-max-frequency = <10000000>; + spi-max-frequency = <500000>; spi-cpol; spi-cpha; diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi new file mode 100644 index 000000000000..680d7262399c --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" +#include "omap3-overo-common-lcd35.dtsi" + +#include <dt-bindings/input/input.h> + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ + linux,default-trigger = "heartbeat"; + }; + gpio22 { + label = "overo:blue:gpio22"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + #address-cells = <1>; + #size-cells = <0>; + button0@23 { + label = "button0"; + linux,code = <BTN_0>; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ + gpio-key,wakeup; + }; + button1@14 { + label = "button1"; + linux,code = <BTN_1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-palo35.dts b/arch/arm/boot/dts/omap3-overo-palo35.dts new file mode 100644 index 000000000000..e3e2bce6edbb --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-palo35.dts @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-palo35-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on Palo35"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts new file mode 100644 index 000000000000..4e725d2d0038 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Palo35 expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-palo35-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; + +&omap3_pmx_core2 { + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ + >; + }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts new file mode 100644 index 000000000000..da6afafcc6c1 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo-storm.dtsi" +#include "omap3-overo-tobiduo-common.dtsi" + +/ { + model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi new file mode 100644 index 000000000000..334109e14613 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +#include "omap3-overo-common-peripherals.dtsi" + +#include "omap-gpmc-smsc9221.dtsi" + +&gpmc { + ranges = <4 0 0x2b000000 0x1000000>, /* CS4 */ + <5 0 0x2c000000 0x1000000>; /* CS5 */ + + smsc1: ethernet@gpmc { + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ + }; + + smsc2: ethernet@4,0 { + compatible = "smsc,lan9221","smsc,lan9115"; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <42>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <42>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <36>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <54>; + gpmc,access-ns = <36>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wr-data-mux-bus-ns = <18>; + gpmc,wr-access-ns = <42>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + + reg = <4 0 0xff>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ + }; +}; + +&lis33de { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-tobiduo.dts new file mode 100644 index 000000000000..b9ce310f6e82 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo-tobiduo.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Ash Charles, Gumstix, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * TobiDuo expansion board is manufactured by Gumstix Inc. + */ + +/dts-v1/; + +#include "omap3-overo.dtsi" +#include "omap3-overo-tobiduo-common.dtsi" + +/ { + model = "OMAP35xx Gumstix Overo on TobiDuo"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index 69ca7c45bca2..932a02ff552a 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -32,7 +32,3 @@ >; }; }; - -&mcbsp2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts index 9619a28dfd7d..25498f756a29 100644 --- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts @@ -19,7 +19,7 @@ / { model = "Pandora Handheld Console 1GHz"; - compatible = "ti,omap36xx", "ti,omap3"; + compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts index fb803a70a2bb..8775897a4ce7 100644 --- a/arch/arm/boot/dts/omap3-pandora-600mhz.dts +++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts @@ -19,7 +19,7 @@ / { model = "Pandora Handheld Console"; - compatible = "ti,omap3"; + compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 782ab1ff1d08..f2084e6d01e7 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -199,6 +199,38 @@ gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ }; }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ + vcc-supply = <&vaux2>; + }; + + /* HS USB Host VBUS supply + * disabling this regulator causes current leakage, and LCD flicker + * on earlier (CC) board revisions, so keep it always on */ + usb_host_5v: fixed-regulator-usb_host_5v { + compatible = "regulator-fixed"; + regulator-name = "usb_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio6 4 0>; /* GPIO_164 */ + }; + + /* wg7210 (wifi+bt module) 32k clock buffer */ + wg7210_32k: fixed-regulator-wg7210_32k { + compatible = "regulator-fixed"; + regulator-name = "wg7210_32k"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + enable-active-high; + gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; + }; }; &omap3_pmx_core { @@ -459,13 +491,18 @@ power = <50>; }; +/* + * Many pandora boards have been produced with defective write-protect switches + * on either slot, so it was decided not to use this feature. If you know + * your board has good switches, feel free to uncomment wp-gpios below. + */ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */ + /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ }; &mmc2 { @@ -473,8 +510,13 @@ pinctrl-0 = <&mmc2_pins>; vmmc-supply = <&vmmc2>; bus-width = <4>; - cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */ + cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; + /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ +}; + +/* mmc3 is probed using pdata-quirks to pass wl1251 card data */ +&mmc3 { + status = "disabled"; }; /* bluetooth*/ @@ -496,6 +538,10 @@ port2-mode = "ehci-phy"; }; +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + &gpmc { ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ @@ -545,7 +591,7 @@ reg = <0x280000 0xa00000>; }; - filesystem@680000 { + filesystem@c80000 { label = "rootfs"; reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 275618f19a43..3cc8f357d5b8 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -510,6 +510,13 @@ }; }; }; + + palmas_power_button: palmas_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&palmas>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; }; twl6040: twl@4b { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b1a1263e6001..4205a8ac9ddb 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -873,7 +873,12 @@ dwc3@4a030000 { compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; phys = <&usb2_phy>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "peripheral"; diff --git a/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts b/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts new file mode 100644 index 000000000000..3daec912b4bf --- /dev/null +++ b/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts @@ -0,0 +1,273 @@ +/* + * Device Tree file for Buffalo Linkstation LS-WTGL + * + * Copyright (C) 2015, Roger Shimizu <rogershimizu@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Buffalo Linkstation LS-WTGL"; + compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 64 MB */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>; + + internal-regs { + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_usb_power &pmx_power_hdd + &pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + pmx_led_power: pmx-leds { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp12"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp13"; + marvell,function = "sata1"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp8", "mpp10"; + marvell,function = "gpio"; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_switch>; + pinctrl-names = "default"; + + button@1 { + label = "Power-on Switch"; + linux,code = <KEY_RESERVED>; + linux,input-type = <5>; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Power-auto Switch"; + linux,code = <KEY_ESC>; + linux,input-type = <5>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_alarm + &pmx_led_info>; + pinctrl-names = "default"; + + led@1 { + label = "lswtgl:blue:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "lswtgl:red:alarm"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led@3 { + label = "lswtgl:amber:info"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; + + gpios = <&gpio0 14 GPIO_ACTIVE_LOW + &gpio0 17 GPIO_ACTIVE_LOW>; + + gpio-fan,speed-map = <0 3 + 1500 2 + 3250 1 + 5000 0>; + + alarm-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd &pmx_usb_power>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + hdd_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "HDD Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c { + status = "okay"; + + rtc { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; +}; + +&wdt { + status = "disabled"; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts new file mode 100644 index 000000000000..6b47a52ceb9c --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lswsgl.dts @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2015 Benjamin Cama <benoar@dolka.fr> + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, + * Copyright (C) 2008 Alexey Kopytko <alexey@kopytko.ru> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Buffalo Linkstation Mini (LS-WSGL)"; + compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + func { + label = "Function Button"; + linux,code = <KEY_OPTION>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + power { + label = "Power-on Switch"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <KEY_RESERVED>; /* LSMINI_SW_POWER */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + + autopower { + label = "Power-auto Switch"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <KEY_ESC>; /* LSMINI_SW_AUTOPOWER */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func + &pmx_led_power>; + pinctrl-names = "default"; + + alarm { + label = "lswsgl:alarm:red"; + gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + info { + label = "lswsgl:info:amber"; + gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + func { + label = "lswsgl:func:blue:top"; + gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + power { + label = "lswsgl:power:blue:bottom"; + gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + restart_poweroff { + compatible = "restart-poweroff"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; + pinctrl-names = "default"; + + sata0_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; + }; + + usb_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x40000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full256Kb"; + reg = <0 0x40000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; +}; + +&pinctrl { + pmx_buttons: pmx-buttons { + marvell,pins = "mpp15", "mpp17", "mpp18"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_led_func: pmx-leds { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_led_power: pmx-leds { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_sata0_power: pmx-sata0-power { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_sata1_power: pmx-sata1-power { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 90b99714ad80..7f68a1ee7073 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -7,6 +7,15 @@ compatible = "marvell,pxa27x"; pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-channels = <32>; + #dma-cells = <2>; + status = "okay"; + }; + pxairq: interrupt-controller@40d00000 { marvell,intc-priority; marvell,intc-nr-irqs = <34>; @@ -17,6 +26,14 @@ clocks = <&clks CLK_NONE>; }; + pxa27x_ohci: usb@4c000000 { + compatible = "marvell,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + clocks = <&clks CLK_USBHOST>; + status = "disabled"; + }; + pwm0: pwm@40b00000 { compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; reg = <0x40b00000 0x10>; @@ -50,6 +67,8 @@ reg = <0x40f00180 0x24>; interrupts = <6>; clocks = <&clks CLK_PWRI2C>; + #address-cells = <0x1>; + #size-cells = <0>; status = "disabled"; }; @@ -68,6 +87,23 @@ clocks = <&clks CLK_KEYPAD>; status = "disabled"; }; + + pxa_camera: imaging@50000000 { + compatible = "marvell,pxa270-qci"; + reg = <0x50000000 0x1000>; + interrupts = <33>; + dmas = <&pdma 68 0 /* Y channel */ + &pdma 69 0 /* U channel */ + &pdma 70 0>; /* V channel */ + dma-names = "CI_Y", "CI_U", "CI_V"; + + clocks = <&clks CLK_CAMERA>; + clock-names = "ciclk"; + clock-frequency = <5000000>; + clock-output-names = "qci_mclk"; + + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 71a0cd7388d1..5e5af078b9b5 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -128,6 +128,10 @@ compatible = "marvell,pxa-mmc"; reg = <0x41100000 0x1000>; interrupts = <23>; + clocks = <&clks CLK_MMC>; + dmas = <&pdma 21 3 + &pdma 22 3>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 7ad0b1771098..cf6998a0804d 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -6,6 +6,15 @@ compatible = "marvell,pxa3xx"; pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-channels = <32>; + #dma-cells = <2>; + status = "okay"; + }; + pwri2c: i2c@40f500c0 { compatible = "mrvl,pwri2c"; reg = <0x40f500c0 0x30>; @@ -21,6 +30,8 @@ reg = <0x43100000 90>; interrupts = <45>; clocks = <&clks CLK_NAND>; + dmas = <&pdma 97>; + dma-names = "data"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; @@ -42,6 +53,47 @@ interrupt-controller; #interrupt-cells = <0x2>; }; + + mmc0: mmc@41100000 { + compatible = "marvell,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + clocks = <&clks CLK_MMC>; + dmas = <&pdma 21 3 + &pdma 22 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mmc1: mmc@42000000 { + compatible = "marvell,pxa-mmc"; + reg = <0x42000000 0x1000>; + interrupts = <41>; + clocks = <&clks CLK_MMC1>; + dmas = <&pdma 93 3 + &pdma 94 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mmc2: mmc@42500000 { + compatible = "marvell,pxa-mmc"; + reg = <0x42500000 0x1000>; + interrupts = <55>; + clocks = <&clks CLK_MMC2>; + dmas = <&pdma 46 3 + &pdma 47 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pxa3xx_ohci: usb@4c000000 { + compatible = "marvell,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + clocks = <&clks CLK_USBHOST>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 71512b3ca444..47c0282bdfca 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -4,6 +4,14 @@ model = "CompuLab CM-QS600"; compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; + aliases { + serial0 = &gsbi7_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { pinctrl@800000 { i2c1_pins: i2c1 { @@ -67,6 +75,12 @@ bias-pull-down; }; + pm8921_l5: l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + pm8921_l23: l23 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; @@ -140,19 +154,33 @@ status = "okay"; }; + /* on board fixed 3.3v supply */ + v3p3_fixed: v3p3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; }; /* External micro SD card */ sdcc3: sdcc@12180000 { status = "okay"; + vmmc-supply = <&v3p3_fixed>; }; /* WLAN */ sdcc4: sdcc@121c0000 { status = "okay"; + vmmc-supply = <&v3p3_fixed>; + vqmmc-supply = <&v3p3_fixed>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index a7c939ba8873..f3100da082b2 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -7,6 +7,11 @@ aliases { serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; soc { @@ -73,6 +78,12 @@ bias-pull-down; }; + pm8921_l5: l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + pm8921_l6: l6 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; @@ -84,9 +95,25 @@ regulator-max-microvolt = <1900000>; bias-pull-down; }; + + pm8921_lvs1: lvs1 { + bias-pull-down; + }; }; }; + ext_3p3v: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + gsbi3: gsbi@16200000 { status = "okay"; qcom,mode = <GSBI_PROT_I2C>; @@ -115,6 +142,18 @@ }; }; + gsbi@16500000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + + serial@16540000 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart_pins>; + }; + }; + gsbi@16600000 { status = "ok"; qcom,mode = <GSBI_PROT_I2C_UART>; @@ -175,11 +214,14 @@ /* eMMC */ sdcc1: sdcc@12400000 { status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; }; /* External micro SD card */ sdcc3: sdcc@12180000 { status = "okay"; + vmmc-supply = <&pm8921_l6>; pinctrl-names = "default"; pinctrl-0 = <&card_detect>; cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; @@ -187,6 +229,8 @@ /* WLAN */ sdcc4: sdcc@121c0000 { status = "okay"; + vmmc-supply = <&ext_3p3v>; + vqmmc-supply = <&pm8921_lvs1>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index df2061ec630d..d2e94d647c27 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -6,7 +6,6 @@ #include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/soc/qcom,gsbi.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - / { model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; @@ -127,6 +126,13 @@ function = "gsbi3"; }; }; + + uart_pins: uart_pins { + mux { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gsbi6"; + }; + }; }; intc: interrupt-controller@2000000 { @@ -243,13 +249,13 @@ gsbi3: gsbi@16200000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; reg = <0x16200000 0x100>; clocks = <&gcc GSBI3_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; - i2c3: i2c@16280000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16280000 0x1000>; @@ -260,6 +266,28 @@ }; }; + gsbi6: gsbi@16500000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <6>; + reg = <0x16500000 0x03>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi6_serial: serial@16540000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16540000 0x100>, + <0x16500000 0x03>; + interrupts = <0 156 0x0>; + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; @@ -287,6 +315,53 @@ compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8921"; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <74 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pm8921_gpio: gpio@150 { + + compatible = "qcom,pm8921-gpio"; + reg = <0x150>; + interrupts = <192 1>, <193 1>, <194 1>, + <195 1>, <196 1>, <197 1>, + <198 1>, <199 1>, <200 1>, + <201 1>, <202 1>, <203 1>, + <204 1>, <205 1>, <206 1>, + <207 1>, <208 1>, <209 1>, + <210 1>, <211 1>, <212 1>, + <213 1>, <214 1>, <215 1>, + <216 1>, <217 1>, <218 1>, + <219 1>, <220 1>, <221 1>, + <222 1>, <223 1>, <224 1>, + <225 1>, <226 1>, <227 1>, + <228 1>, <229 1>, <230 1>, + <231 1>, <232 1>, <233 1>, + <234 1>, <235 1>; + + gpio-controller; + #gpio-cells = <2>; + + }; + + pm8921_mpps: mpps@50 { + compatible = "qcom,pm8921-mpp"; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + interrupts = + <128 1>, <129 1>, <130 1>, <131 1>, + <132 1>, <133 1>, <134 1>, <135 1>, + <136 1>, <137 1>, <138 1>, <139 1>; + }; + + }; }; gcc: clock-controller@900000 { @@ -448,14 +523,6 @@ }; /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - sdcc1bam:dma@12402000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; @@ -505,7 +572,6 @@ non-removable; cap-sd-highspeed; cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; dma-names = "tx", "rx"; }; @@ -524,7 +590,6 @@ cap-mmc-highspeed; max-frequency = <192000000>; no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; @@ -542,8 +607,6 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <48000000>; - vmmc-supply = <&vsdcc_fixed>; - vqmmc-supply = <&vsdcc_fixed>; dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index d484d08163e9..835bdc71c5ba 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -6,6 +6,14 @@ model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { serial@f991e000 { status = "ok"; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts index f7725b96612c..c9c2b769554f 100644 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -5,6 +5,14 @@ model = "Qualcomm APQ8084/IFC6540"; compatible = "qcom,apq8084-ifc6540", "qcom,apq8084"; + aliases { + serial0 = &blsp2_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { serial@f995e000 { status = "okay"; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts index cb43acfc5d1d..3016c7048d44 100644 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -5,6 +5,14 @@ model = "Qualcomm APQ 8084-MTP"; compatible = "qcom,apq8084-mtp", "qcom,apq8084"; + aliases { + serial0 = &blsp2_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { serial@f995e000 { status = "okay"; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 7084010ee61b..0554fbd72c40 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -234,7 +234,7 @@ interrupts = <0 208 0>; }; - serial@f995e000 { + blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; interrupts = <0 114 0x0>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 55b2910efd87..d501382493e3 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -4,6 +4,14 @@ model = "Qualcomm IPQ8064/AP148"; compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 9f727d8eadf6..fa698635eea0 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -197,7 +197,7 @@ syscon-tcsr = <&tcsr>; - serial@16340000 { + gsbi4_serial: serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, <0x16300000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index e0883c376248..b17f379e8c2a 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -6,6 +6,14 @@ model = "Qualcomm MSM8660 SURF"; compatible = "qcom,msm8660-surf", "qcom,msm8660"; + aliases { + serial0 = &gsbi12_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { gsbi@19c00000 { status = "ok"; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index e0b2ce2910e0..e5f7f33aa467 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -67,15 +67,16 @@ cpu-offset = <0x40000>; }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x4000>; + tlmm: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + gpio-controller; #gpio-cells = <2>; - ngpio = <173>; interrupts = <0 16 0x4>; interrupt-controller; #interrupt-cells = <2>; + }; gcc: clock-controller@900000 { @@ -97,7 +98,7 @@ syscon-tcsr = <&tcsr>; - serial@19c40000 { + gsbi12_serial: serial@19c40000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; @@ -115,7 +116,7 @@ pmicintc: pmic@0 { compatible = "qcom,pm8058"; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <88 8>; #interrupt-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 7f70fae90959..b72a55462caf 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -6,6 +6,14 @@ model = "Qualcomm MSM8960 CDP"; compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + aliases { + serial0 = &gsbi5_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + soc { gsbi@16400000 { status = "ok"; @@ -26,6 +34,308 @@ status = "okay"; }; }; + + rpm@108000 { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; + }; + + gsbi@16000000 { + status = "ok"; + qcom,mode = <GSBI_PROT_SPI>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_default>; + spi@16080000 { + status = "ok"; + eth@0 { + compatible = "micrel,ks8851"; + reg = <0>; + interrupt-parent = <&msmgpio>; + interrupts = <90 8>; + spi-max-frequency = <5400000>; + vdd-supply = <&ext_l2>; + vdd-io-supply = <&pm8921_lvs6>; + reset-gpios = <&msmgpio 89 0>; + }; + }; + }; + + pinctrl@800000 { + spi1_default: spi1_default { + mux { + pins = "gpio6", "gpio7", "gpio9"; + function = "gsbi1"; + }; + + mosi { + pins = "gpio6"; + drive-strength = <12>; + bias-disable; + }; + + miso { + pins = "gpio7"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio8"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk { + pins = "gpio9"; + drive-strength = <12>; + bias-disable; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + ext_l2: gpio-regulator@91 { + compatible = "regulator-fixed"; + regulator-name = "ext_l2"; + gpio = <&msmgpio 91 0>; + startup-delay-us = <10000>; + enable-active-high; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index a02b984cc68d..134cd91d68ec 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/mfd/qcom-rpm.h> #include <dt-bindings/soc/qcom,gsbi.h> / { @@ -73,11 +74,10 @@ cpu-offset = <0x80000>; }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; gpio-controller; #gpio-cells = <2>; - ngpio = <150>; interrupts = <0 16 0x4>; interrupt-controller; #interrupt-cells = <2>; @@ -105,6 +105,24 @@ #reset-cells = <1>; }; + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x2011000 0x1000>; + }; + + rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + }; + }; + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; @@ -139,7 +157,7 @@ syscon-tcsr = <&tcsr>; - serial@16440000 { + gsbi5_serial: serial@16440000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; @@ -253,5 +271,30 @@ compatible = "qcom,tcsr-msm8960", "syscon"; reg = <0x1a400000 0x100>; }; + + gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <1>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16080000 0x1000>; + interrupts = <0 147 0>; + spi-max-frequency = <24000000>; + cs-gpios = <&msmgpio 8 0>; + + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index bd35b0674ff6..016f9ad9392a 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -6,6 +6,14 @@ model = "Sony Xperia Z1"; compatible = "sony,xperia-honami", "qcom,msm8974"; + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@0 { reg = <0 0x40000000>, <0x40000000 0x40000000>; device_type = "memory"; @@ -17,3 +25,13 @@ status = "ok"; }; }; + +&spmi_bus { + pm8941@0 { + coincell@2800 { + status = "ok"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 37b47b5538b8..ab8e57250468 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -9,6 +9,17 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -220,6 +231,11 @@ reg = <0xfc400000 0x4000>; }; + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + mmcc: clock-controller@fd8c0000 { compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; @@ -227,7 +243,23 @@ reg = <0xfd8c0000 0x6000>; }; - serial@f991e000 { + tcsr_mutex: tcsr-mutex { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; + + smem@fa00000 { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + reg = <0xfc428000 0x4000>; + + hwlocks = <&tcsr_mutex 3>; + }; + + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; interrupts = <0 108 0x0>; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index aa774e685018..968f1043d4f5 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -125,6 +125,12 @@ interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; qcom,external-resistor-micro-ohms = <10000>; }; + + coincell@2800 { + compatible = "qcom,pm8941-coincell"; + reg = <0x2800>; + status = "disabled"; + }; }; usid1: pm8941@1 { diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 277e73c110e5..060c32cbd669 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -86,6 +86,7 @@ reg = <0xfcfe0000 0x18>; clocks = <&extal_clk>, <&usb_x1_clk>; clock-output-names = "pll", "i", "g"; + #power-domain-cells = <0>; }; /* MSTP clocks */ @@ -157,6 +158,7 @@ <0 189 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -169,6 +171,7 @@ <0 193 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -181,6 +184,7 @@ <0 197 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -193,6 +197,7 @@ <0 201 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -205,6 +210,7 @@ <0 205 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -217,6 +223,7 @@ <0 209 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -229,6 +236,7 @@ <0 213 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -241,6 +249,7 @@ <0 217 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -252,6 +261,7 @@ <0 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -266,6 +276,7 @@ <0 243 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -280,6 +291,7 @@ <0 246 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -294,6 +306,7 @@ <0 249 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -308,6 +321,7 @@ <0 252 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -338,6 +352,7 @@ <0 164 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R7S72100_CLK_I2C0>; clock-frequency = <100000>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -356,6 +371,7 @@ <0 172 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R7S72100_CLK_I2C1>; clock-frequency = <100000>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -374,6 +390,7 @@ <0 180 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R7S72100_CLK_I2C2>; clock-frequency = <100000>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -392,6 +409,7 @@ <0 188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R7S72100_CLK_I2C3>; clock-frequency = <100000>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -402,6 +420,7 @@ interrupt-names = "tgi0a"; clocks = <&mstp3_clks R7S72100_CLK_MTU2>; clock-names = "fck"; + power-domains = <&cpg_clocks>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 7ee22a41c6c9..cb4f7b2798fe 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -207,6 +207,13 @@ reg = <0 0xe6050000 0 0x9000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 31>, <&pfc 32 32 9>, + <&pfc 64 64 22>, <&pfc 96 96 31>, + <&pfc 128 128 7>, <&pfc 160 160 19>, + <&pfc 192 192 31>, <&pfc 224 224 27>, + <&pfc 256 256 28>, <&pfc 288 288 21>, + <&pfc 320 320 10>; interrupts-extended = <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, @@ -434,7 +441,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 2e31d8c01cbf..105d9c95de4a 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -224,6 +224,9 @@ }; &pfc { + pinctrl-0 = <&lcd0_pins>; + pinctrl-names = "default"; + ether_pins: ether { renesas,groups = "gether_mii", "gether_int"; renesas,function = "gether"; @@ -259,6 +262,16 @@ "fsia_data_in_1", "fsia_data_out_0"; renesas,function = "fsia"; }; + + lcd0_pins: lcd0 { + renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; + renesas,function = "lcd0"; + + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; }; &tpu { diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index d84714468cce..e14cb1438216 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -291,6 +291,7 @@ <0xe605800c 0x20>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; interrupts-extended = <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 7ce9f5fd5865..4b1fa9f42ad5 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -53,6 +53,7 @@ reg = <0xfde00000 0x400>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7778_CLK_ETHER>; + power-domains = <&cpg_clocks>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -152,6 +153,7 @@ reg = <0xffc70000 0x1000>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -162,6 +164,7 @@ reg = <0xffc71000 0x1000>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -172,6 +175,7 @@ reg = <0xffc72000 0x1000>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -182,6 +186,7 @@ reg = <0xffc73000 0x1000>; interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -193,6 +198,7 @@ <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -207,6 +213,7 @@ <0 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -221,6 +228,7 @@ <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -288,6 +296,7 @@ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -297,6 +306,7 @@ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -306,6 +316,7 @@ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -315,6 +326,7 @@ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -324,6 +336,7 @@ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -333,6 +346,7 @@ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -341,6 +355,7 @@ reg = <0xffe4e000 0x100>; interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_MMC>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -349,6 +364,7 @@ reg = <0xffe4c000 0x100>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -357,6 +373,7 @@ reg = <0xffe4d000 0x100>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -365,6 +382,7 @@ reg = <0xffe4f000 0x100>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -373,6 +391,7 @@ reg = <0xfffc7000 0x18>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -383,6 +402,7 @@ reg = <0xfffc8000 0x18>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -393,6 +413,7 @@ reg = <0xfffc6000 0x18>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -419,6 +440,7 @@ clocks = <&extal_clk>; clock-output-names = "plla", "pllb", "b", "out", "p", "s", "s1"; + #power-domain-cells = <0>; }; /* Audio clocks; frequencies are set by boards if applicable. */ diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 5c8071e87ae9..6afa909865b5 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -148,7 +148,7 @@ interrupt-controller; }; - irqpin0: interrupt-controller@fe780010 { + irqpin0: interrupt-controller@fe78001c { compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; #interrupt-cells = <2>; status = "disabled"; @@ -157,7 +157,8 @@ <0xfe780010 4>, <0xfe780024 4>, <0xfe780044 4>, - <0xfe780064 4>; + <0xfe780064 4>, + <0xfe780000 4>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0 29 IRQ_TYPE_LEVEL_HIGH @@ -172,6 +173,7 @@ reg = <0xffc70000 0x1000>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -182,6 +184,7 @@ reg = <0xffc71000 0x1000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -192,6 +195,7 @@ reg = <0xffc72000 0x1000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -202,6 +206,7 @@ reg = <0xffc73000 0x1000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -211,6 +216,7 @@ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -220,6 +226,7 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -229,6 +236,7 @@ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -238,6 +246,7 @@ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -247,6 +256,7 @@ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -256,6 +266,7 @@ interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -277,6 +288,7 @@ <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -291,6 +303,7 @@ <0 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -305,6 +318,7 @@ <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #renesas,channels = <3>; @@ -316,6 +330,7 @@ reg = <0xfc600000 0x2000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; + power-domains = <&cpg_clocks>; }; sdhi0: sd@ffe4c000 { @@ -323,6 +338,7 @@ reg = <0xffe4c000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -331,6 +347,7 @@ reg = <0xffe4d000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -339,6 +356,7 @@ reg = <0xffe4e000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -347,6 +365,7 @@ reg = <0xffe4f000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -357,6 +376,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -367,6 +387,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -377,6 +398,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -385,6 +407,7 @@ reg = <0 0xfff80000 0 0x40000>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_DU>; + power-domains = <&cpg_clocks>; status = "disabled"; ports { @@ -426,6 +449,7 @@ #clock-cells = <1>; clock-output-names = "plla", "z", "zs", "s", "s1", "p", "b", "out"; + #power-domain-cells = <0>; }; /* Fixed factor clocks */ diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 2eb8a995ae9f..37dec5269491 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -174,7 +174,7 @@ 1800000 0>; }; - sound { + rsnd_ak4643: sound { compatible = "simple-audio-card"; simple-audio-card,format = "left_j"; @@ -548,7 +548,7 @@ compatible = "adi,adv7511w"; reg = <0x39>; interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; adi,input-depth = <8>; adi,input-colorspace = "rgb"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 51ab8865ea37..a0b2a79cbfbd 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -113,7 +113,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -134,6 +134,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; + power-domains = <&cpg_clocks>; }; gpio1: gpio@e6051000 { @@ -146,6 +147,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; + power-domains = <&cpg_clocks>; }; gpio2: gpio@e6052000 { @@ -158,6 +160,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; + power-domains = <&cpg_clocks>; }; gpio3: gpio@e6053000 { @@ -170,6 +173,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; + power-domains = <&cpg_clocks>; }; gpio4: gpio@e6054000 { @@ -182,6 +186,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; + power-domains = <&cpg_clocks>; }; gpio5: gpio@e6055000 { @@ -194,6 +199,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; + power-domains = <&cpg_clocks>; }; thermal@e61f0000 { @@ -201,6 +207,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; + power-domains = <&cpg_clocks>; }; timer { @@ -218,6 +225,7 @@ <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_CMT0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0x60>; @@ -237,6 +245,7 @@ <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_CMT1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0xff>; @@ -253,6 +262,7 @@ <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A7790_CLK_IRQC>; + power-domains = <&cpg_clocks>; }; dmac0: dma-controller@e6700000 { @@ -281,6 +291,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -311,6 +322,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -339,6 +351,7 @@ "ch12"; clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <13>; }; @@ -367,6 +380,7 @@ "ch12"; clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <13>; }; @@ -378,6 +392,7 @@ 0 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <2>; }; @@ -389,6 +404,7 @@ 0 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <2>; }; @@ -400,6 +416,7 @@ reg = <0 0xe6508000 0 0x40>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -410,6 +427,7 @@ reg = <0 0xe6518000 0 0x40>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -420,6 +438,7 @@ reg = <0 0xe6530000 0 0x40>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -430,6 +449,7 @@ reg = <0 0xe6540000 0 0x40>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_I2C3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -442,6 +462,7 @@ clocks = <&mstp3_clks R8A7790_CLK_IIC0>; dmas = <&dmac0 0x61>, <&dmac0 0x62>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -454,6 +475,7 @@ clocks = <&mstp3_clks R8A7790_CLK_IIC1>; dmas = <&dmac0 0x65>, <&dmac0 0x66>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -466,6 +488,7 @@ clocks = <&mstp3_clks R8A7790_CLK_IIC2>; dmas = <&dmac0 0x69>, <&dmac0 0x6a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -478,6 +501,7 @@ clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; dmas = <&dmac0 0x77>, <&dmac0 0x78>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -488,6 +512,7 @@ clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -500,6 +525,7 @@ clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -517,6 +543,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -527,6 +554,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; dmas = <&dmac1 0xc9>, <&dmac1 0xca>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -537,6 +565,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -547,6 +576,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -558,6 +588,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x21>, <&dmac0 0x22>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -569,6 +600,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x25>, <&dmac0 0x26>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -580,6 +612,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x27>, <&dmac0 0x28>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -591,6 +624,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -602,6 +636,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -613,6 +648,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -624,6 +660,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -635,6 +672,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -646,6 +684,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -657,6 +696,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -665,17 +705,30 @@ reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + power-domains = <&cpg_clocks>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata0: sata@ee300000 { compatible = "renesas,sata-r8a7790"; reg = <0 0xee300000 0 0x2000>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -684,6 +737,7 @@ reg = <0 0xee500000 0 0x2000>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -692,12 +746,13 @@ reg = <0 0xe6590000 0 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&cpg_clocks>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; status = "disabled"; }; @@ -708,6 +763,7 @@ #size-cells = <0>; clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; clock-names = "usbhs"; + power-domains = <&cpg_clocks>; status = "disabled"; usb0: usb-channel@0 { @@ -722,33 +778,37 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7790"; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7790"; - clocks = <&mstp8_clks R8A7790_CLK_VIN1>; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; vin2: video@e6ef2000 { compatible = "renesas,vin-r8a7790"; - clocks = <&mstp8_clks R8A7790_CLK_VIN2>; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; vin3: video@e6ef3000 { compatible = "renesas,vin-r8a7790"; - clocks = <&mstp8_clks R8A7790_CLK_VIN3>; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -757,6 +817,7 @@ reg = <0 0xfe920000 0 0x8000>; interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + power-domains = <&cpg_clocks>; renesas,has-sru; renesas,#rpf = <5>; @@ -769,6 +830,7 @@ reg = <0 0xfe928000 0 0x8000>; interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + power-domains = <&cpg_clocks>; renesas,has-lut; renesas,has-sru; @@ -782,6 +844,7 @@ reg = <0 0xfe930000 0 0x8000>; interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + power-domains = <&cpg_clocks>; renesas,has-lif; renesas,has-lut; @@ -795,6 +858,7 @@ reg = <0 0xfe938000 0 0x8000>; interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + power-domains = <&cpg_clocks>; renesas,has-lif; renesas,has-lut; @@ -849,6 +913,7 @@ clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -859,9 +924,18 @@ clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; status = "disabled"; }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7790"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_JPU>; + power-domains = <&cpg_clocks>; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -936,6 +1010,7 @@ clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", "adsp"; + #power-domain-cells = <0>; }; /* Variable factor clocks */ @@ -1249,16 +1324,18 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; + <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; clock-indices = < R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER + R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 + R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 >; clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; + "mlb", "vin3", "vin2", "vin1", "vin0", + "etheravb", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -1291,6 +1368,7 @@ <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; #clock-cells = <1>; @@ -1300,6 +1378,7 @@ R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 R8A7790_CLK_SCU_ALL R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 + R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 >; @@ -1309,6 +1388,7 @@ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; }; @@ -1321,6 +1401,7 @@ clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; dmas = <&dmac0 0x17>, <&dmac0 0x18>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1334,6 +1415,7 @@ clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1346,6 +1428,7 @@ clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; dmas = <&dmac0 0x55>, <&dmac0 0x56>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1358,6 +1441,7 @@ clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; dmas = <&dmac0 0x41>, <&dmac0 0x42>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1370,6 +1454,7 @@ clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; dmas = <&dmac0 0x45>, <&dmac0 0x46>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1380,6 +1465,7 @@ reg = <0 0xee000000 0 0xc00>; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + power-domains = <&cpg_clocks>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1388,10 +1474,11 @@ pci0: pci@ee090000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + power-domains = <&cpg_clocks>; status = "disabled"; bus-range = <0 0>; @@ -1422,10 +1509,11 @@ pci1: pci@ee0b0000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; reg = <0 0xee0b0000 0 0xc00>, <0 0xee0a0000 0 0x1100>; interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + power-domains = <&cpg_clocks>; status = "disabled"; bus-range = <1 1>; @@ -1443,6 +1531,7 @@ compatible = "renesas,pci-r8a7790"; device_type = "pci"; clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + power-domains = <&cpg_clocks>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; @@ -1495,6 +1584,7 @@ interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -1524,6 +1614,8 @@ <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, + <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", @@ -1531,6 +1623,8 @@ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; @@ -1547,6 +1641,22 @@ }; }; + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + rcar_sound,src { src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index cffe33ff4d16..dc158845afdc 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -242,7 +242,7 @@ 1800000 0>; }; - sound { + rsnd_ak4643: sound { compatible = "simple-audio-card"; simple-audio-card,format = "left_j"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index dc1cd3f16606..831525dd39a6 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -70,7 +70,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -91,6 +91,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; + power-domains = <&cpg_clocks>; }; gpio1: gpio@e6051000 { @@ -103,6 +104,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; + power-domains = <&cpg_clocks>; }; gpio2: gpio@e6052000 { @@ -115,6 +117,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; + power-domains = <&cpg_clocks>; }; gpio3: gpio@e6053000 { @@ -127,6 +130,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; + power-domains = <&cpg_clocks>; }; gpio4: gpio@e6054000 { @@ -139,6 +143,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; + power-domains = <&cpg_clocks>; }; gpio5: gpio@e6055000 { @@ -151,6 +156,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; + power-domains = <&cpg_clocks>; }; gpio6: gpio@e6055400 { @@ -163,6 +169,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; + power-domains = <&cpg_clocks>; }; gpio7: gpio@e6055800 { @@ -175,6 +182,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; + power-domains = <&cpg_clocks>; }; thermal@e61f0000 { @@ -182,6 +190,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; + power-domains = <&cpg_clocks>; }; timer { @@ -199,6 +208,7 @@ <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_CMT0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0x60>; @@ -218,6 +228,7 @@ <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_CMT1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0xff>; @@ -240,6 +251,7 @@ <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A7791_CLK_IRQC>; + power-domains = <&cpg_clocks>; }; dmac0: dma-controller@e6700000 { @@ -268,6 +280,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -298,6 +311,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -326,6 +340,7 @@ "ch12"; clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <13>; }; @@ -354,6 +369,7 @@ "ch12"; clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <13>; }; @@ -365,6 +381,7 @@ 0 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <2>; }; @@ -376,6 +393,7 @@ 0 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <2>; }; @@ -388,6 +406,7 @@ reg = <0 0xe6508000 0 0x40>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -398,6 +417,7 @@ reg = <0 0xe6518000 0 0x40>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -408,6 +428,7 @@ reg = <0 0xe6530000 0 0x40>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -418,6 +439,7 @@ reg = <0 0xe6540000 0 0x40>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C3>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -428,6 +450,7 @@ reg = <0 0xe6520000 0 0x40>; interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C4>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -439,6 +462,7 @@ reg = <0 0xe6528000 0 0x40>; interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C5>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -452,6 +476,7 @@ clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; dmas = <&dmac0 0x77>, <&dmac0 0x78>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -464,6 +489,7 @@ clocks = <&mstp3_clks R8A7791_CLK_IIC0>; dmas = <&dmac0 0x61>, <&dmac0 0x62>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -476,6 +502,7 @@ clocks = <&mstp3_clks R8A7791_CLK_IIC1>; dmas = <&dmac0 0x65>, <&dmac0 0x66>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -492,6 +519,7 @@ clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -504,6 +532,7 @@ clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -514,6 +543,7 @@ clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -524,6 +554,7 @@ clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -535,6 +566,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x21>, <&dmac0 0x22>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -546,6 +578,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x25>, <&dmac0 0x26>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -557,6 +590,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x27>, <&dmac0 0x28>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -568,6 +602,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -579,6 +614,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -590,6 +626,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x23>, <&dmac0 0x24>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -601,6 +638,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -612,6 +650,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -623,6 +662,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -634,6 +674,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -645,6 +686,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -656,6 +698,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -667,6 +710,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -678,6 +722,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -689,6 +734,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -700,6 +746,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -711,6 +758,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -722,6 +770,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -730,6 +779,7 @@ reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7791_CLK_ETHER>; + power-domains = <&cpg_clocks>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -741,6 +791,7 @@ reg = <0 0xee300000 0 0x2000>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -749,6 +800,7 @@ reg = <0 0xee500000 0 0x2000>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -757,12 +809,13 @@ reg = <0 0xe6590000 0 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&cpg_clocks>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; status = "disabled"; }; @@ -773,6 +826,7 @@ #size-cells = <0>; clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; clock-names = "usbhs"; + power-domains = <&cpg_clocks>; status = "disabled"; usb0: usb-channel@0 { @@ -787,25 +841,28 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7791"; - clocks = <&mstp8_clks R8A7791_CLK_VIN0>; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7791"; - clocks = <&mstp8_clks R8A7791_CLK_VIN1>; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; vin2: video@e6ef2000 { compatible = "renesas,vin-r8a7791"; - clocks = <&mstp8_clks R8A7791_CLK_VIN2>; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -814,6 +871,7 @@ reg = <0 0xfe928000 0 0x8000>; interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + power-domains = <&cpg_clocks>; renesas,has-lut; renesas,has-sru; @@ -827,6 +885,7 @@ reg = <0 0xfe930000 0 0x8000>; interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + power-domains = <&cpg_clocks>; renesas,has-lif; renesas,has-lut; @@ -840,6 +899,7 @@ reg = <0 0xfe938000 0 0x8000>; interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + power-domains = <&cpg_clocks>; renesas,has-lif; renesas,has-lut; @@ -885,6 +945,7 @@ clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -895,9 +956,18 @@ clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; status = "disabled"; }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7791"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_JPU>; + power-domains = <&cpg_clocks>; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -972,6 +1042,7 @@ clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z", "rcan", "adsp"; + #power-domain-cells = <0>; }; /* Variable factor clocks */ @@ -1311,6 +1382,7 @@ <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; #clock-cells = <1>; @@ -1320,6 +1392,7 @@ R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 R8A7791_CLK_SCU_ALL R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 + R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 >; @@ -1329,6 +1402,7 @@ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; }; @@ -1351,6 +1425,7 @@ clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; dmas = <&dmac0 0x17>, <&dmac0 0x18>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1364,6 +1439,7 @@ clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1376,6 +1452,7 @@ clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; dmas = <&dmac0 0x55>, <&dmac0 0x56>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1388,6 +1465,7 @@ clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; dmas = <&dmac0 0x41>, <&dmac0 0x42>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1398,6 +1476,7 @@ reg = <0 0xee000000 0 0xc00>; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + power-domains = <&cpg_clocks>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1406,10 +1485,11 @@ pci0: pci@ee090000 { compatible = "renesas,pci-r8a7791"; device_type = "pci"; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + power-domains = <&cpg_clocks>; status = "disabled"; bus-range = <0 0>; @@ -1440,10 +1520,11 @@ pci1: pci@ee0d0000 { compatible = "renesas,pci-r8a7791"; device_type = "pci"; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + power-domains = <&cpg_clocks>; status = "disabled"; bus-range = <1 1>; @@ -1493,6 +1574,7 @@ interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -1582,6 +1664,8 @@ <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, + <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", @@ -1589,6 +1673,8 @@ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; @@ -1605,6 +1691,22 @@ }; }; + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + rcar_sound,src { src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts new file mode 100644 index 000000000000..96443ec5f6ab --- /dev/null +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -0,0 +1,63 @@ +/* + * Device Tree Source for the Gose board + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7793.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Gose"; + compatible = "renesas,gose", "renesas,r8a7793"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&scif0 { + status = "okay"; +}; + +&scif1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi new file mode 100644 index 000000000000..c4654047e684 --- /dev/null +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -0,0 +1,374 @@ +/* + * Device Tree Source for the r8a7793 SoC + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7793-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "renesas,r8a7793"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + voltage-tolerance = <1>; /* 1% */ + clocks = <&cpg_clocks R8A7793_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7793", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7793_CLK_IRQC>; + power-domains = <&cpg_clocks>; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7793", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; + clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7793", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; + clock-names = "sci_ick"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7793-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan", "adsp"; + #power-domain-cells = <0>; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk@e615026c { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, + <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 + R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 + R8A7793_CLK_3DG R8A7793_CLK_2DDMAC + R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 + R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 + R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 + R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 + R8A7793_CLK_VSP1_S + >; + clock-output-names = + "vcp0", "vpc0", "ssp_dev", "tmu1", + "pvrsrvkm", "tddmac", "fdp1", "fdp0", + "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsps"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, + <&rclk_clk>, <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 + R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 + R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 + R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 + R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 + R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 + >; + clock-output-names = + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", + "i2c7", "pciec", "i2c8", "ssusb", "cmt1", + "usbdmac0", "usbdmac1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = <R8A7793_CLK_IRQC>; + clock-output-names = "irqc"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, + <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_EHCI R8A7793_CLK_HSUSB + R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 + R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 + R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 + R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 + R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 + R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 + >; + clock-output-names = + "ehci", "hsusb", "hscif2", "scif5", "scif4", + "hscif1", "hscif0", "scif3", "scif2", + "scif1", "scif0", "du1", "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&p_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 + R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 + R8A7793_CLK_ETHER R8A7793_CLK_SATA1 + R8A7793_CLK_SATA0 + >; + clock-output-names = + "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", + "sata1", "sata0"; + }; + }; + +}; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts new file mode 100644 index 000000000000..d4dd5a30ccdf --- /dev/null +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -0,0 +1,102 @@ +/* + * Device Tree Source for the SILK board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014-2015 Renesas Solutions Corp. + * Copyright (C) 2014-2015 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7794.dtsi" + +/ { + model = "SILK"; + compatible = "renesas,silk", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif2_pins: serial2 { + renesas,groups = "scif2_data"; + renesas,function = "scif2"; + }; + + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq8"; + renesas,function = "intc"; + }; + + mmcif0_pins: mmcif0 { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index b73819423311..97c8e9ace5eb 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -39,7 +39,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a7-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -57,6 +57,7 @@ <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7794_CLK_CMT0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0x60>; @@ -76,6 +77,7 @@ <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_CMT1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; renesas,channels-mask = <0xff>; @@ -106,6 +108,13 @@ <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A7794_CLK_IRQC>; + power-domains = <&cpg_clocks>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7794"; + reg = <0 0xe6060000 0 0x11c>; + #gpio-range-cells = <3>; }; dmac0: dma-controller@e6700000 { @@ -134,6 +143,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -164,6 +174,7 @@ "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; clock-names = "fck"; + power-domains = <&cpg_clocks>; #dma-cells = <1>; dma-channels = <15>; }; @@ -176,6 +187,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x21>, <&dmac0 0x22>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -187,6 +199,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x25>, <&dmac0 0x26>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -198,6 +211,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x27>, <&dmac0 0x28>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -209,6 +223,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -220,6 +235,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -231,6 +247,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x23>, <&dmac0 0x24>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -242,6 +259,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -253,6 +271,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -264,6 +283,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -275,6 +295,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -286,6 +307,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -297,6 +319,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -308,6 +331,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -319,6 +343,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -330,6 +355,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -341,6 +367,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -352,6 +379,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -363,6 +391,7 @@ clock-names = "sci_ick"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -371,17 +400,31 @@ reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + power-domains = <&cpg_clocks>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + reg-io-width = <4>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -390,6 +433,7 @@ reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -398,6 +442,7 @@ reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -424,6 +469,7 @@ #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z"; + #power-domain-cells = <0>; }; /* Variable factor clocks */ sd2_clk: sd2_clk@e6150078 { diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index b299b26926d4..c0273755431a 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -49,6 +49,7 @@ compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; memory { + device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 0a7304beb417..bae965c123c1 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -48,6 +48,7 @@ compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; memory { + device_type = "memory"; reg = <0x60000000 0x40000000>; }; @@ -201,6 +202,18 @@ status = "okay"; }; +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 3ac151102c2f..e36383c701dc 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -48,6 +48,7 @@ compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; memory { + device_type = "memory"; reg = <0x60000000 0x40000000>; }; @@ -459,6 +460,10 @@ status = "okay"; }; +&usbphy { + status = "okay"; +}; + &usb_otg { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index d32229b8a996..946f18705e96 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -169,6 +169,28 @@ clock-names = "timer", "pclk"; }; + usbphy: phy { + compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 42faa19edb7e..d2180e5d2b05 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -48,6 +48,7 @@ compatible = "radxa,rock", "rockchip,rk3188"; memory { + device_type = "memory"; reg = <0x60000000 0x80000000>; }; @@ -358,6 +359,10 @@ status = "okay"; }; +&usbphy { + status = "okay"; +}; + &usb_host { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 0f23aedf9349..316304272118 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -130,6 +130,28 @@ #reset-cells = <1>; }; + usbphy: phy { + compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 844a6fb64658..f6d2e7894b05 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -43,6 +43,7 @@ / { memory { + device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 0b42372e4379..20fa0ef0b96b 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -44,6 +44,7 @@ / { memory { + device_type = "memory"; reg = <0 0x80000000>; }; @@ -213,6 +214,8 @@ regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; vin-supply = <&vcc_sys>; }; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index d582811fbd7b..f82b956ebf17 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -49,6 +49,7 @@ compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; memory{ + device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts new file mode 100644 index 000000000000..14b9fc73c8a4 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include "rk3288.dtsi" + +/ { + compatible = "netxeon,r89", "rockchip,rk3288"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sdmmc: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "sys-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: pmic@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "VDD_CPU"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: pmic@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "VDD_GPU"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + }; + + act8846: pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_wl: REG7 { + regulator-name = "VCC_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_lan: REG9 { + regulator-name = "VCC_LAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + pmic_vsel: pmic-vsel { + rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pwr_hold: pwr-hold { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sdmmc>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi new file mode 100644 index 000000000000..136d650dd05f --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -0,0 +1,232 @@ +/* + * Google Veyron (and derivatives) board device tree source + * Chromebook specific parts + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/rockchip,rk808.h> +#include <dt-bindings/input/input.h> +#include "rk3288-veyron.dtsi" +#include "rk3288-veyron-sdmmc.dtsi" + +/ { + aliases { + /* Assign 20 so we don't get confused w/ builtin ones */ + i2c20 = &i2c_tunnel; + }; + + gpio-charger { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ac_present_ap>; + }; + + /* A non-regulated voltage from power supply or battery */ + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + + vcc33_sys: vcc33-sys { + vin-supply = <&vccsys>; + }; + + vcc_5v: vcc-5v { + vin-supply = <&vccsys>; + }; + + /* This turns on vbus for host1 (dwc2) */ + vcc5_host1: vcc5-host1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host1_pwr_en>; + regulator-name = "vcc5_host1"; + regulator-always-on; + regulator-boot-on; + }; + + /* This turns on vbus for otg for host mode (dwc2) */ + vcc5v_otg: vcc5v-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_pwren_h>; + regulator-name = "vcc5_host2"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; + lid { + label = "Lid"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + linux,code = <0>; /* SW_LID */ + linux,input-type = <5>; /* EV_SW */ + debounce-interval = <1>; + }; +}; + +&rk808 { + vcc11-supply = <&vcc_5v>; + + regulators { + vcc33_ccd: LDO_REG8 { + regulator-name = "vcc33_ccd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + google,cros-ec-spi-pre-delay = <30>; + interrupt-parent = <&gpio7>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_int>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c4 { + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio7>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; +}; + +&pinctrl { + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &global_pwroff + + /* Wake only */ + &suspend_l_wake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &global_pwroff + + /* Sleep only */ + &suspend_l_sleep + >; + + buttons { + ap_lid_int_l: ap-lid-int-l { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + charger { + ac_present_ap: ac-present-ap { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + cros-ec { + ec_int: ec-int { + rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + suspend { + suspend_l_wake: suspend-l-wake { + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; + }; + + suspend_l_sleep: suspend-l-sleep { + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + trackpad { + trackpad_int: trackpad-int { + rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-host { + host1_pwr_en: host1-pwr-en { + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbotg_pwren_h: usbotg-pwren-h { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts new file mode 100644 index 000000000000..60bd6e91e308 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -0,0 +1,197 @@ +/* + * Google Veyron Jerry Rev 3+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Jerry"; + compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", + "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", + "google,veyron-jerry-rev3", "google,veyron-jerry", + "google,veyron", "rockchip,rk3288"; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + + regulators { + mic_vcc: LDO_REG2 { + regulator-name = "mic_vcc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /* + * Trackpad pin control is shared between Elan and Synaptics devices + * so we have to pull it up to the bus level. + */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer &trackpad_int>; + + trackpad@15 { + /* + * Remove the inherited pinctrl settings to avoid clashing + * with bus-wide ones. + */ + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + }; + + trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&gpio7>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + vcc-supply = <&vcc33_io>; + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts new file mode 100644 index 000000000000..8fd8ef2c72da --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -0,0 +1,230 @@ +/* + * Google Veyron Minnie Rev 0+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Minnie"; + compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", + "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", + "google,veyron-minnie-rev0", "google,veyron-minnie", + "google,veyron", "rockchip,rk3288"; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <100>; + }; +}; + +&i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + regulators { + vcc33_touch: LDO_REG2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_touch: SWITCH_REG2 { + regulator-name = "vcc5v_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { + rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts new file mode 100644 index 000000000000..94b56e33d947 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -0,0 +1,128 @@ +/* + * Google Veyron Pinky Rev 2 board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Pinky"; + compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", + "google,veyron", "rockchip,rk3288"; + + /delete-node/emmc-pwrseq; +}; + +&emmc { + /* + * Use a pullup instead of a drive since the output is 3.3V and + * really should be 1.8V (oops). The external pulldown will help + * bring the voltage down if we only drive with a pullup here. + * Therefore disable the powerseq (and actual reset) for pinky. + */ + /delete-property/mmc-pwrseq; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; + + power { + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + }; +}; + +/* Touchpad connector */ +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +&pinctrl { + buttons { + pwr_key_h: pwr-key-h { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_wp_gpio: sdmmc-wp-gpio { + rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rk808 { + regulators { + vcc18_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_wp_gpio &sdmmc_bus4>; + wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; +}; + +&tsadc { + /* Some connection is flaky making the tsadc hang the system */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi new file mode 100644 index 000000000000..b5334ecff13c --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -0,0 +1,122 @@ +/* + * Google Veyron (and derivatives) fragment for sdmmc cards + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&io_domains { + sdcard-supply = <&vccio_sd>; +}; + +&pinctrl { + sdmmc { + /* + * We run sdmmc at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + /* + * Builtin CD line is hooked to ground to prevent JTAG at boot + * (and also to get the voltage rail correct). + * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't + * think there's a card inserted + */ + sdmmc_cd_disabled: sdmmc-cd-disabled { + rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD */ + sdmmc_cd_gpio: sdmmc-cd-gpio { + rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk808 { + vcc9-supply = <&vcc_5v>; + + regulators { + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_sd: LDO_REG5 { + regulator-name = "vcc33_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + status = "okay"; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + num-slots = <1>; + vmmc-supply = <&vcc33_sd>; + vqmmc-supply = <&vccio_sd>; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts new file mode 100644 index 000000000000..a7ea7d06cf7f --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,155 @@ +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Speedy"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi new file mode 100644 index 000000000000..2fa7a0dc83f7 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -0,0 +1,563 @@ +/* + * Google Veyron (and derivatives) board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/rockchip,rk808.h> +#include <dt-bindings/input/input.h> +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; + power { + label = "Power"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <100>; + gpio-key,wakeup; + }; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_warm_reset_h>; + priority = <200>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + rockchip,grf = <&grf>; + + bb-supply = <&vcc33_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc18_flashio>; + gpio1830-supply = <&vcc33_io>; + gpio30-supply = <&vcc33_io>; + lcdc-supply = <&vcc33_lcd>; + wifi-supply = <&vcc18_wl>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; + + vcc_5v: vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc33_sys: vcc33-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc33_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc50_hdmi: vcc50-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vcc50_hdmi"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_5v>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + status = "okay"; + + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ + i2c-scl-rising-time-ns = <100>; /* 45ns measured */ + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc33_sys>; + vcc2-supply = <&vcc33_sys>; + vcc3-supply = <&vcc33_sys>; + vcc4-supply = <&vcc33_sys>; + vcc6-supply = <&vcc_5v>; + vcc7-supply = <&vcc33_sys>; + vcc8-supply = <&vcc33_sys>; + vcc12-supply = <&vcc_18>; + vddio-supply = <&vcc33_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc135_ddr: DCDC_REG3 { + regulator-name = "vcc135_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* + * vcc_18 has several aliases. (vcc18_flashio and + * vcc18_wl). We'll add those aliases here just to + * make it easier to follow the schematic. The signals + * are actually hooked together and only separated for + * power measurement purposes). + */ + vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* + * Note that both vcc33_io and vcc33_pmuio are always + * powered together. To simplify the logic in the dts + * we just refer to vcc33_io every time something is + * powered from vcc33_pmuio. In fact, on later boards + * (such as danger) they're the same net. + */ + vcc33_io: LDO_REG1 { + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd10_lcd_pwren_h: LDO_REG7 { + regulator-name = "vdd10_lcd_pwren_h"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_lcd: SWITCH_REG1 { + regulator-name = "vcc33_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ + i2c-scl-rising-time-ns = <100>; /* 40ns measured */ + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&i2c2 { + status = "okay"; + + /* 100kHz since 4.7k resistors don't rise fast enough */ + clock-frequency = <100000>; + i2c-scl-falling-time-ns = <50>; /* 10ns measured */ + i2c-scl-rising-time-ns = <800>; /* 600ns measured */ +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; /* 11ns measured */ + i2c-scl-rising-time-ns = <300>; /* 225ns measured */ +}; + +&i2c5 { + status = "okay"; + + clock-frequency = <100000>; + i2c-scl-falling-time-ns = <300>; + i2c-scl-rising-time-ns = <1000>; +}; + +&pwm1 { + status = "okay"; +}; + +&sdio0 { + status = "okay"; + + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + vmmc-supply = <&vcc33_sys>; + vqmmc-supply = <&vcc18_wl>; +}; + +&spi2 { + status = "okay"; + + rx-sample-delay-ns = <12>; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + +&uart0 { + status = "okay"; + + /* We need to go faster than 24MHz, so adjust clock parents / rates */ + assigned-clocks = <&cru SCLK_UART0>; + assigned-clock-rates = <48000000>; + + /* Pins don't include flow control by default; add that in */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; + + needs-reset-on-resume; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + + assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; + assigned-clock-parents = <&cru SCLK_OTGPHY0>; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ + &global_pwroff + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &global_pwroff + >; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + buttons { + pwr_key_l: pwr-key-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, + <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + reboot { + ap_warm_reset_h: ap-warm-reset-h { + rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + recovery-switch { + rec_mode_l: rec-mode-l { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio0 { + wifi_enable_h: wifienable-h { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* NOTE: mislabelled on schematic; should be bt_enable_h */ + bt_enable_l: bt-enable-l { + rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* + * We run sdio0 at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, + <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + }; + + tpm { + tpm_int_h: tpm-int-h { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + /* + * On Marvell-based hardware this is a no-connect. Make sure we enable + * the pullup so that the line doesn't float. The pullup shouldn't + * hurt on Broadcom-based hardware since the other side is actively + * driving this signal. As proof: we've already got a pullup on RX. + */ + uart0 { + uart0_cts: uart0-cts { + rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + write-protect { + fw_wp_ap: fw-wp-ap { + rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 22316d00493e..906e938fb6bf 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -78,6 +78,7 @@ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; cpus { @@ -110,19 +111,19 @@ clock-latency = <40000>; clocks = <&cru ARMCLK>; }; - cpu@501 { + cpu1: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x501>; resets = <&cru SRST_CORE1>; }; - cpu@502 { + cpu2: cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; resets = <&cru SRST_CORE2>; }; - cpu@503 { + cpu3: cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; @@ -168,6 +169,26 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * The rk3288 cannot use the memory area above 0xfe000000 + * for dma operations for some reason. While there is + * probably a better solution available somewhere, we + * haven't found it yet and while devices with 2GB of ram + * are not affected, this issue prevents 4GB from booting. + * So to make these devices at least bootable, block + * this area for the time being until the real solution + * is found. + */ + dma-unusable@fe000000 { + reg = <0xfe000000 0x1000000>; + }; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -447,6 +468,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -626,7 +649,7 @@ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index a2ae9f32464d..4497d288a7cb 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -172,6 +172,13 @@ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + phys = <&usbphy0>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -181,6 +188,9 @@ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG1>; clock-names = "otg"; + dr_mode = "host"; + phys = <&usbphy1>; + phy-names = "usb2-phy"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi new file mode 100644 index 000000000000..034cd48ae28b --- /dev/null +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -0,0 +1,926 @@ +/* + * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC + * + * Copyright (C) 2015 Atmel, + * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel SAMA5D2 family SoC"; + compatible = "atmel,sama5d2"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &uart1; + serial1 = &uart3; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + ns_sram: sram@00200000 { + compatible = "mmio-sram"; + reg = <0x00200000 0x20000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: gadget@00300000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,sama5d3-udc"; + reg = <0x00300000 0x100000 + 0xfc02c000 0x400>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + }; + + usb1: ohci@00400000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + L2: cache-controller@00a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramc0: ramc@f000c000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf000c000 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0010000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0010000 0x1000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + pmc: pmc@f0014000 { + compatible = "atmel,sama5d2-pmc"; + reg = <0xf0014000 0x160>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <100000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc &main_osc>; + }; + + plla: pllack { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <12000000 12000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <124000000 166000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + h32ck: h32mxck { + #clock-cells = <0>; + compatible = "atmel,sama5d4-clk-h32mx"; + clocks = <&mck>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + iscck: iscck { + #clock-cells = <0>; + reg = <18>; + clocks = <&mck>; + }; + }; + + periph32ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&h32ck>; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <5>; + atmel,clk-output-range = <0 83000000>; + }; + + tdes_clk: tdes_clk { + #clock-cells = <0>; + reg = <11>; + atmel,clk-output-range = <0 83000000>; + }; + + matrix1_clk: matrix1_clk { + #clock-cells = <0>; + reg = <14>; + }; + + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <17>; + }; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <18>; + atmel,clk-output-range = <0 83000000>; + }; + + flx0_clk: flx0_clk { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 83000000>; + }; + + flx1_clk: flx1_clk { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 83000000>; + }; + + flx2_clk: flx2_clk { + #clock-cells = <0>; + reg = <21>; + atmel,clk-output-range = <0 83000000>; + }; + + flx3_clk: flx3_clk { + #clock-cells = <0>; + reg = <22>; + atmel,clk-output-range = <0 83000000>; + }; + + flx4_clk: flx4_clk { + #clock-cells = <0>; + reg = <23>; + atmel,clk-output-range = <0 83000000>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 83000000>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 83000000>; + }; + + uart2_clk: uart2_clk { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 83000000>; + }; + + uart3_clk: uart3_clk { + #clock-cells = <0>; + reg = <27>; + atmel,clk-output-range = <0 83000000>; + }; + + uart4_clk: uart4_clk { + #clock-cells = <0>; + reg = <28>; + atmel,clk-output-range = <0 83000000>; + }; + + twi0_clk: twi0_clk { + reg = <29>; + #clock-cells = <0>; + atmel,clk-output-range = <0 83000000>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <30>; + atmel,clk-output-range = <0 83000000>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <33>; + atmel,clk-output-range = <0 83000000>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <34>; + atmel,clk-output-range = <0 83000000>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <35>; + atmel,clk-output-range = <0 83000000>; + }; + + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <36>; + atmel,clk-output-range = <0 83000000>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 83000000>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 83000000>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 83000000>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <42>; + atmel,clk-output-range = <0 83000000>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <43>; + atmel,clk-output-range = <0 83000000>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <44>; + atmel,clk-output-range = <0 83000000>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <47>; + atmel,clk-output-range = <0 83000000>; + }; + + classd_clk: classd_clk { + #clock-cells = <0>; + reg = <59>; + atmel,clk-output-range = <0 83000000>; + }; + }; + + periph64ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <9>; + }; + + aesb_clk: aesb_clk { + #clock-cells = <0>; + reg = <10>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <12>; + }; + + mpddr_clk: mpddr_clk { + #clock-cells = <0>; + reg = <13>; + }; + + matrix0_clk: matrix0_clk { + #clock-cells = <0>; + reg = <15>; + }; + + sdmmc0_hclk: sdmmc0_hclk { + #clock-cells = <0>; + reg = <31>; + }; + + sdmmc1_hclk: sdmmc1_hclk { + #clock-cells = <0>; + reg = <32>; + }; + + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <45>; + }; + + isc_clk: isc_clk { + #clock-cells = <0>; + reg = <46>; + }; + + qspi0_clk: qspi0_clk { + #clock-cells = <0>; + reg = <52>; + }; + + qspi1_clk: qspi1_clk { + #clock-cells = <0>; + reg = <53>; + }; + }; + }; + + sha@f0028000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf0028000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + status = "disabled"; + }; + + aes@f002c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf002c000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(26))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + status = "disabled"; + }; + + spi0: spi@f8000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8000000 0x100>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + macb0: ethernet@f8008000 { + compatible = "atmel,sama5d2-gem"; + reg = <0xf8008000 0x1000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + tcb0: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f8010000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8010000 0x100>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + uart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&uart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8028000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + pit: timer@f8048030 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xf8048030 0x10>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&h32ck>; + }; + + sckc@f8048050 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xf8048050 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <250000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@f80480b0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xf80480b0 0x30>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + + spi1: spi@fc000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc000000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart3: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&uart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart4: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&uart4_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + aic: interrupt-controller@fc020000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d2-aic"; + interrupt-controller; + reg = <0xfc020000 0x200>; + atmel,external-irqs = <49>; + }; + + i2c1: i2c@fc028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xfc028000 0x100>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 9e2444b07bce..7fa276515f11 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -145,8 +145,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; i2c0: i2c@f0014000 { @@ -1259,13 +1259,15 @@ }; rstc@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; shutdown-controller@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -1279,6 +1281,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1315,6 +1318,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; }; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index f7fa58fe09f1..801f9745e82f 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -31,8 +31,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>; - clock-names = "t0_clk"; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 3ee22ee13c5a..8d1de29e8da1 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -957,8 +957,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf801c000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; macb0: ethernet@f8020000 { @@ -1185,29 +1185,20 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>; - clock-names = "t0_clk"; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; adc0: adc@fc034000 { compatible = "atmel,at91sam9x5-adc"; reg = <0xfc034000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger is conflict with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; clocks = <&adc_clk>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0x01f>; atmel,adc-startup-time = <40>; - atmel,adc-use-external; + atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; atmel,adc-res = <8 10>; atmel,adc-sample-hold-time = <11>; @@ -1277,13 +1268,15 @@ }; rstc@fc068600 { - compatible = "atmel,at91sam9g45-rstc"; + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; + clocks = <&clk32k>; }; shdwc@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; + clocks = <&clk32k>; }; pit: timer@fc068630 { @@ -1296,6 +1289,7 @@ watchdog@fc068640 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfc068640 0x10>; + clocks = <&clk32k>; status = "disabled"; }; @@ -1329,6 +1323,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfc0686b0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; dbgu: serial@fc069000 { diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 11e17c5f26e2..ff7c8f298f30 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -392,6 +392,9 @@ <0xe605801c 0x1c>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, + <&pfc 288 288 22>; interrupts-extended = <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 80f924deed37..314e589cfa00 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -164,7 +164,7 @@ dbg_base_clk: dbg_base_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; }; @@ -318,7 +318,7 @@ l3_sp_clk: l3_sp_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + clocks = <&l3_mp_clk>; div-reg = <0x64 2 2>; }; @@ -349,7 +349,7 @@ dbg_clk: dbg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; + clocks = <&dbg_at_clk>; div-reg = <0x68 2 2>; clk-gate = <0x60 5>; }; @@ -481,8 +481,37 @@ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + }; - }; + }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; @@ -565,7 +594,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; porta: gpio-controller@0 { @@ -585,7 +614,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portb: gpio-controller@0 { @@ -605,7 +634,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portc: gpio-controller@0 { @@ -639,6 +668,8 @@ cache-level = <2>; arm,tag-latency = <1 1 1>; arm,data-latency = <2 1 1>; + prefetch-data = <1>; + prefetch-instr = <1>; }; mmc: dwmmc0@ff704000 { @@ -752,6 +783,7 @@ #reset-cells = <1>; compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; + altr,modrst-offset = <0x10>; }; usbphy0: usbphy@0 { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4779b07310df..2340fcb2b535 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -16,11 +16,17 @@ #include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/altr,rst-mgr-a10.h> / { #address-cells = <1>; #size-cells = <1>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -409,6 +415,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -426,6 +434,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -588,6 +598,7 @@ #reset-cells = <1>; compatible = "altr,rst-mgr"; reg = <0xffd05000 0x100>; + altr,modrst-offset = <0x20>; }; scu: snoop-control-unit@ffffc000 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 94a0709b2fe6..99aa9a1c8af0 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -21,7 +21,8 @@ compatible = "altr,socfpga-arria10", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200 rootwait"; + bootargs = "earlyprintk"; + stdout-path = "serial1:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index ccaf41742fc3..a75a666032b2 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -22,7 +22,8 @@ compatible = "altr,socfpga-arria5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts new file mode 100644 index 000000000000..555e9caf21e1 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts @@ -0,0 +1,111 @@ +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE-0(Atlas)"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + speed-mode = <0>; + + adxl345: adxl345@0 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 258865da8f6a..d4d0a28fb331 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -22,7 +22,8 @@ compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 5e17fd147728..48bf651bd762 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -22,7 +22,8 @@ compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index b8f81fb418ce..50f5e9d09203 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -220,6 +220,13 @@ clocks { compatible = "stericsson,u8500-clks"; + /* + * Registers for the CLKRST block on peripheral + * groups 1, 2, 3, 5, 6, + */ + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; prcmu_clk: prcmu-clock { #clock-cells = <1>; @@ -287,7 +294,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; - + gpio-ranges = <&pinctrl 0 0 32>; clocks = <&prcc_pclk 1 9>; }; @@ -302,7 +309,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; - + gpio-ranges = <&pinctrl 0 32 5>; clocks = <&prcc_pclk 1 9>; }; @@ -317,7 +324,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; - + gpio-ranges = <&pinctrl 0 64 32>; clocks = <&prcc_pclk 3 8>; }; @@ -332,7 +339,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; - + gpio-ranges = <&pinctrl 0 96 2>; clocks = <&prcc_pclk 3 8>; }; @@ -347,7 +354,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <4>; - + gpio-ranges = <&pinctrl 0 128 32>; clocks = <&prcc_pclk 3 8>; }; @@ -362,7 +369,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <5>; - + gpio-ranges = <&pinctrl 0 160 12>; clocks = <&prcc_pclk 3 8>; }; @@ -377,7 +384,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <6>; - + gpio-ranges = <&pinctrl 0 192 32>; clocks = <&prcc_pclk 2 11>; }; @@ -392,7 +399,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <7>; - + gpio-ranges = <&pinctrl 0 224 7>; clocks = <&prcc_pclk 2 11>; }; @@ -407,12 +414,15 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <8>; - + gpio-ranges = <&pinctrl 0 256 12>; clocks = <&prcc_pclk 5 1>; }; - pinctrl { + pinctrl: pinctrl { compatible = "stericsson,db8500-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, + <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, + <&gpio8>; prcm = <&prcmu>; }; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 3d25dba143a5..4a21c6492dbb 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -17,12 +17,22 @@ }; aliases { + serial0 = &uart0; serial1 = &uart1; stmpe-i2c0 = &stmpe0; stmpe-i2c1 = &stmpe1; }; pinctrl { + uart0 { + uart0_nhk_mode: uart0_mux { + u0_default_mux { + function = "u0"; + groups = "u0txrx_a_1", "u0ctsrts_a_1"; + }; + }; + }; + stmpe2401_1 { stmpe2401_1_nhk_mode: stmpe2401_1_nhk { nhk_cfg1 { @@ -73,6 +83,11 @@ }; i2c0 { + lis3lv02dl@1d { + /* Accelerometer */ + compatible = "st,lis3lv02dl-accel"; + reg = <0x1d>; + }; stmpe0: stmpe2401@43 { compatible = "st,stmpe2401"; reg = <0x43>; @@ -131,22 +146,30 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + /* + * This will turn off SATA so that MMC/SD + * can thrive + */ + mmcsd-gpio { + gpio-hog; + gpios = <2 0x0>; + output-low; + line-name = "SATA EN"; + }; }; }; }; amba { + /* Activate RX/TX and CTS/RTS on UART 0 */ + uart0: uart@101fd000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_nhk_mode>; + status = "okay"; + }; mmcsd: sdi@101f6000 { cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; }; }; - - /* Custom board node with GPIO pins to active etc */ - usb-s8815 { - /* This will turn off SATA so that MMC/SD can thrive */ - mmcsd-gpio { - gpios = <&stmpe_gpio44 2 0x1>; - }; - }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 3c140d05f796..35282c0105c6 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -16,9 +16,20 @@ }; aliases { + serial0 = &uart0; serial1 = &uart1; }; + gpio3: gpio@101e7000 { + /* This hog will bias the MMC/SD card detect line */ + mmcsd-gpio { + gpio-hog; + gpios = <16 0x0>; + output-low; + line-name = "card detect bias"; + }; + }; + src@101e0000 { /* These chrystal drivers are not used on this board */ disable-sxtalo; @@ -30,6 +41,15 @@ pinctrl-names = "default"; pinctrl-0 = <&cd_default_mode>; + uart0 { + /* Only use RX/TX pins */ + uart0_s8815_mode: uart0_mux { + u0_default_mux { + function = "u0"; + groups = "u0txrx_a_1"; + }; + }; + }; mmcsd-cd { cd_default_mode: cd_default { cd_default_cfg1 { @@ -85,6 +105,14 @@ }; }; + i2c1 { + lis3lv02dl@1d { + /* Accelerometer */ + compatible = "st,lis3lv02dl-accel"; + reg = <0x1d>; + }; + }; + /* GPIO I2C connected to the USB portions of the STw4811 only */ gpio-i2c { compatible = "i2c-gpio"; @@ -102,21 +130,19 @@ }; - /* Configure card detect for the uSD slot */ amba { + /* Activate RXTX on UART 0 */ + uart0: uart@101fd000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_s8815_mode>; + status = "okay"; + }; + /* Configure card detect for the uSD slot */ mmcsd: sdi@101f6000 { cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; }; }; - /* Custom board node with GPIO pins to active etc */ - usb-s8815 { - /* This will bias the MMC/SD card detect line */ - mmcsd-gpio { - gpios = <&gpio3 16 0x1>; - }; - }; - /* The user LED on the board is set up to be used for heartbeat */ leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index ef794a33b4dc..314f59c12162 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -21,6 +21,13 @@ interrupts = <30>; cache-unified; cache-level = <2>; + cache-size = <131072>; + cache-sets = <512>; + cache-line-size = <32>; + /* At full speed latency must be >=2 */ + arm,tag-latency = <2>; + arm,data-latency = <2 2>; + arm,dirty-latency = <2>; }; mtu0: mtu@101e2000 { @@ -52,6 +59,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; clocks = <&pclk>; }; @@ -65,6 +73,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 32>; clocks = <&pclk>; }; @@ -78,12 +87,14 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; + gpio-ranges = <&pinctrl 0 64 32>; clocks = <&pclk>; }; gpio3: gpio@101e7000 { compatible = "st,nomadik-gpio"; reg = <0x101e7000 0x80>; + ngpio = <28>; interrupt-parent = <&vica>; interrupts = <9>; interrupt-controller; @@ -91,20 +102,14 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; + gpio-ranges = <&pinctrl 0 96 28>; clocks = <&pclk>; }; - pinctrl { + pinctrl: pinctrl { compatible = "stericsson,stn8815-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; /* Pin configurations */ - uart0 { - uart0_default_mux: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - }; - }; uart1 { uart1_default_mux: uart1_mux { u1_default_mux { @@ -721,11 +726,6 @@ compatible = "st,stw5095"; reg = <0x1a>; }; - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - reg = <0x1d>; - }; }; amba { @@ -755,8 +755,6 @@ interrupts = <12>; clocks = <&uart0clk>, <&pclkuart0>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_default_mux>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index e65744fc12ab..ad45f5e8fac7 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -134,7 +134,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; @@ -143,7 +143,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 838b812cbda1..ae0527754000 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -9,7 +9,7 @@ #include "stih407-pinctrl.dtsi" #include <dt-bindings/mfd/st-lpc.h> #include <dt-bindings/phy/phy.h> -#include <dt-bindings/reset-controller/stih407-resets.h> +#include <dt-bindings/reset/stih407-resets.h> #include <dt-bindings/interrupt-controller/irq-st.h> / { #address-cells = <1>; @@ -22,11 +22,15 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; }; }; @@ -65,6 +69,17 @@ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; + pwm_regulator: pwm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 3 8448>; + regulator-name = "CPU_1V0_AVS"; + regulator-min-microvolt = <784000>; + regulator-max-microvolt = <1299000>; + regulator-always-on; + max-duty-cycle = <255>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -539,6 +554,7 @@ status = "disabled"; }; + st_dwc3: dwc3@8f94000 { compatible = "st,stih407-dwc3"; reg = <0x08f94000 0x1000>, <0x110 0x4>; @@ -565,5 +581,34 @@ <&phy_port2 PHY_TYPE_USB3>; }; }; + + /* COMMS PWM Module */ + pwm0: pwm@9810000 { + compatible = "st,sti-pwm"; + status = "okay"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <1>; + }; + + /* SBC PWM Module */ + pwm1: pwm@9510000 { + compatible = "st,sti-pwm"; + status = "okay"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 0a754f275212..1683debd0854 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -439,6 +439,194 @@ }; }; }; + + tsin0 { + pinctrl_tsin0_parallel: tsin0_parallel { + st,pins { + DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin0_serial: tsin0_serial { + st,pins { + DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin1 { + pinctrl_tsin1_parallel: tsin1_parallel { + st,pins { + DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin1_serial: tsin1_serial { + st,pins { + DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin2 { + pinctrl_tsin2_parallel: tsin2_parallel { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; + DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin2_serial: tsin2_serial { + st,pins { + DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin3 { + pinctrl_tsin3_serial: tsin3_serial { + st,pins { + DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin4 { + pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { + st,pins { + DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; + ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; + PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsin5 { + pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { + st,pins { + DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { + st,pins { + DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsout0 { + pinctrl_tsout0_parallel: tsout0_parallel { + st,pins { + DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; + VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsout0_serial: tsout0_serial { + st,pins { + DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; + VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + tsout1 { + pinctrl_tsout1_serial: tsout1_serial { + st,pins { + DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; + VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + + mtsin0 { + pinctrl_mtsin0_parallel: mtsin0_parallel { + st,pins { + DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 { @@ -452,6 +640,18 @@ interrupts-names = "irqmux"; ranges = <0 0x09210000 0x10000>; + tsin4 { + pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { + st,pins { + DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + pio20: pio@09210000 { gpio-controller; #gpio-cells = <1>; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 2c560fc30503..3efa3b2ebe90 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -147,33 +147,5 @@ }; }; }; - - /* COMMS PWM Module */ - pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - }; - - /* SBC PWM Module */ - pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - }; }; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 6b5803a30096..d1f2acafc9b6 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 208b5e89036a..6f40bc99c22f 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -10,6 +10,10 @@ #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" / { + aliases { + bdisp0 = &bdisp0; + }; + soc { usb2_picophy1: phy2 { compatible = "st,stih407-usb2-phy"; @@ -218,5 +222,13 @@ }; }; }; + + bdisp0:bdisp@9f10000 { + compatible = "st,stih407-bdisp"; + reg = <0x9f10000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>; + clock-names = "bdisp"; + clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; + }; }; }; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 19b019b5f30e..12427e651e5e 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -10,7 +10,7 @@ #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset-controller/stih415-resets.h> +#include <dt-bindings/reset/stih415-resets.h> / { L2: cache-controller { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 9dca173e694a..9e3170ccd18c 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -12,7 +12,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset-controller/stih416-resets.h> +#include <dt-bindings/reset/stih416-resets.h> #include <dt-bindings/interrupt-controller/irq-st.h> / { L2: cache-controller { diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 0ab23daa2829..148e1772465f 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 354d90f521b6..8160a75539a4 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -17,11 +17,15 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ + cpu-release-addr = <0x94100A4>; }; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts new file mode 100644 index 000000000000..6964fc9e97cf --- /dev/null +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -0,0 +1,75 @@ +/* + * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f429.dtsi" + +/ { + model = "STMicroelectronics STM32429i-EVAL board"; + compatible = "st,stm32429i-eval", "st,stm32f429"; + + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xc0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 6b9aa59d978a..f0b731db6f53 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -53,8 +53,8 @@ compatible = "st,stm32f429i-disco", "st,stm32f429"; chosen { - bootargs = "console=ttyS0,115200 root=/dev/ram rdinit=/linuxrc"; - linux,stdout-path = &usart1; + bootargs = "root=/dev/ram rdinit=/linuxrc"; + stdout-path = "serial0:115200n8"; }; memory { @@ -66,6 +66,10 @@ }; }; +&clk_hse { + clock-frequency = <8000000>; +}; + &usart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index aa73b4f4172c..d78a4815da8f 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -49,48 +49,10 @@ / { clocks { - clk_sysclk: clk-sysclk { + clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <180000000>; - }; - - clk_hclk: clk-hclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <180000000>; - }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <45000000>; - }; - - clk_pclk2: clk-pclk2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <90000000>; - }; - - clk_pmtr1: clk-pmtr1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <90000000>; - }; - - clk_pmtr2: clk-pmtr2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <180000000>; - }; - - clk_systick: clk-systick { - compatible = "fixed-factor-clock"; - clocks = <&clk_hclk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; + clock-frequency = <0>; }; }; @@ -99,7 +61,7 @@ compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; interrupts = <28>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 128>; status = "disabled"; }; @@ -107,7 +69,7 @@ compatible = "st,stm32-timer"; reg = <0x40000400 0x400>; interrupts = <29>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 129>; status = "disabled"; }; @@ -115,7 +77,7 @@ compatible = "st,stm32-timer"; reg = <0x40000800 0x400>; interrupts = <30>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 130>; status = "disabled"; }; @@ -123,14 +85,14 @@ compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 131>; }; timer6: timer@40001000 { compatible = "st,stm32-timer"; reg = <0x40001000 0x400>; interrupts = <54>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 132>; status = "disabled"; }; @@ -138,7 +100,7 @@ compatible = "st,stm32-timer"; reg = <0x40001400 0x400>; interrupts = <55>; - clocks = <&clk_pmtr1>; + clocks = <&rcc 0 133>; status = "disabled"; }; @@ -146,7 +108,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 145>; status = "disabled"; }; @@ -154,7 +116,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 146>; status = "disabled"; }; @@ -162,7 +124,7 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 147>; status = "disabled"; }; @@ -170,7 +132,7 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 148>; status = "disabled"; }; @@ -178,7 +140,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; interrupts = <82>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 158>; status = "disabled"; }; @@ -186,7 +148,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007c00 0x400>; interrupts = <83>; - clocks = <&clk_pclk1>; + clocks = <&rcc 0 159>; status = "disabled"; }; @@ -194,7 +156,7 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 164>; status = "disabled"; }; @@ -202,13 +164,20 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; interrupts = <71>; - clocks = <&clk_pclk2>; + clocks = <&rcc 0 165>; status = "disabled"; }; + + rcc: rcc@40023810 { + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; }; }; &systick { - clocks = <&clk_systick>; + clocks = <&rcc 1 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 93d435670ef1..f3cb297fd1db 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -125,12 +125,21 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { usb2_vbus_pin_a: usb2_vbus_pin@0 { allwinner,pins = "PH12"; }; }; +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -146,7 +155,13 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index 5878a0b11f7b..143056872650 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -114,6 +114,30 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; +}; + +®_usb0_vbus { + status = "okay"; +}; + ®_usb2_vbus { status = "okay"; }; @@ -124,7 +148,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 9afb4e018593..046a84d9719d 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -155,6 +155,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { led_pins_cubieboard: led_pins@0 { allwinner,pins = "PH20", "PH21"; @@ -162,6 +166,13 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; }; ®_ahci_5v { @@ -216,7 +227,15 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts new file mode 100644 index 000000000000..985e15503378 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -0,0 +1,202 @@ +/* + * Copyright 2015 Josef Gajdusek <atx@atx.name> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Iteaduino Plus A10"; + compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index ebe2a04ef649..a7dd86d30fa2 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -114,6 +114,15 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -128,7 +137,13 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index b64aa4eb071e..28e32ad705cd 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -150,6 +150,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { allwinner,pins = "PC3"; @@ -164,6 +168,20 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { @@ -172,6 +190,10 @@ status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -186,7 +208,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 61c03d1fe530..1f3c51a08113 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -241,6 +241,7 @@ compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; + clock-indices = <0>; clock-output-names = "axi_dram"; }; @@ -257,17 +258,36 @@ compatible = "allwinner,sun4i-a10-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, <6>, + <7>, <8>, <9>, + <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, + <21>, <22>, <23>, + <24>, <25>, <26>, + <32>, <33>, <34>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <45>, + <46>, <47>, + <50>, <52>; clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", - "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", - "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", - "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", - "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", - "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + "ahb_ohci0", "ahb_ehci1", + "ahb_ohci1", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", + "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", + "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", + "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", + "ahb_de_fe0", "ahb_de_fe1", + "ahb_mp", "ahb_mali400"; }; apb0: apb0@01c20054 { @@ -283,9 +303,14 @@ compatible = "allwinner,sun4i-a10-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, + <5>, <6>, + <7>, <10>; clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; + "apb0_ac97", "apb0_iis", + "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; }; apb1: clk@01c20058 { @@ -301,12 +326,22 @@ compatible = "allwinner,sun4i-a10-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <4>, + <5>, <6>, + <7>, <16>, + <17>, <18>, + <19>, <20>, + <21>, <22>, + <23>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", "apb1_scr", - "apb1_ps20", "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", "apb1_uart3", - "apb1_uart4", "apb1_uart5", "apb1_uart6", - "apb1_uart7"; + "apb1_i2c2", "apb1_can", + "apb1_scr", "apb1_ps20", + "apb1_ps21", "apb1_uart0", + "apb1_uart1", "apb1_uart2", + "apb1_uart3", "apb1_uart4", + "apb1_uart5", "apb1_uart6", + "apb1_uart7"; }; nand_clk: clk@01c20080 { @@ -611,6 +646,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; @@ -643,6 +691,14 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <86>; + clocks = <&ahb_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; @@ -713,8 +769,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index a7e19e4847f7..5a422c1ff725 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -96,8 +96,15 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp152: pmic@30 { + reg = <0x30>; + interrupts = <0>; + }; }; +#include "axp152.dtsi" + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_a>; @@ -189,6 +196,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { allwinner,pins = "PG1"; @@ -217,6 +228,18 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG12"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + status = "okay"; }; ®_usb1_vbus { @@ -243,8 +266,20 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG11"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; - diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index f11efb722bbb..a513b416a807 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -85,6 +85,17 @@ compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <17>, <18>, + <20>, <21>, <22>, + <26>, <28>, <32>, + <34>, <36>, <40>, + <43>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", @@ -103,6 +114,9 @@ compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>, + <10>; clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", "apb0_ir", "apb0_keypad"; @@ -113,9 +127,14 @@ compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <16>, + <17>, <18>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3"; + "apb1_i2c2", "apb1_uart0", + "apb1_uart1", "apb1_uart2", + "apb1_uart3"; }; }; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 990f9d61ae4d..3724b988064e 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -45,6 +45,7 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/sun4i-a10.h> / { @@ -96,6 +97,25 @@ status = "okay"; }; +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; @@ -110,6 +130,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_h702: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -117,6 +141,20 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; #include "axp209.dtsi" @@ -152,13 +190,33 @@ regulator-name = "vcc-wifi"; }; +®_usb0_vbus { + pinctrl-0 = <&usb0_vbus_pin_a>; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 42324005eb7c..b3c234c65ea1 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -159,6 +159,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -174,6 +178,20 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { allwinner,pins = "PG11"; allwinner,function = "gpio_out"; @@ -182,6 +200,11 @@ }; }; +®_usb0_vbus { + status = "okay"; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; + ®_usb1_vbus { pinctrl-0 = <&usb1_vbus_pin_olinuxino>; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; @@ -194,7 +217,21 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 514f159a14d4..eb793d5a2bd6 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -93,7 +93,7 @@ compatible = "chipone,icn8318"; reg = <0x40>; interrupt-parent = <&pio>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ pinctrl-names = "default"; pinctrl-0 = <&ts_wake_pin_p66>; wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ @@ -153,6 +153,10 @@ }; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_p66: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -161,6 +165,20 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + i2c_lcd_pins: i2c_lcd_pin@0 { allwinner,pins = "PG10", "PG12"; allwinner,function = "gpio_out"; @@ -219,7 +237,16 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 976d4faa2179..f3631c9c6fa2 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -104,6 +104,16 @@ compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <20>, + <21>, <22>, + <28>, <32>, <36>, + <40>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", @@ -121,6 +131,8 @@ compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <5>, + <6>; clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; @@ -130,8 +142,12 @@ compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", "apb1_uart3"; + "apb1_i2c2", "apb1_uart1", + "apb1_uart3"; }; }; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 54b097830434..78b993abbaa3 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -178,6 +178,7 @@ compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; + clock-indices = <0>; clock-output-names = "axi_dram"; }; @@ -416,6 +417,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; @@ -475,8 +489,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; i2c0_pins_a: i2c0@0 { diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 4404f37d132e..4dd70cce2127 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -143,6 +143,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 008047a018cf..54bb83b58f42 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -252,6 +252,20 @@ compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb1>; + clock-indices = <1>, <5>, + <6>, <8>, <9>, + <10>, <11>, <12>, + <13>, <14>, + <17>, <18>, <19>, + <20>, <21>, <22>, + <23>, <24>, <26>, + <27>, <29>, + <30>, <31>, <32>, + <36>, <37>, <40>, + <43>, <44>, <45>, + <46>, <47>, <50>, + <52>, <55>, <56>, + <57>, <58>; clock-output-names = "ahb1_mipidsi", "ahb1_ss", "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", @@ -281,6 +295,9 @@ compatible = "allwinner,sun6i-a31-apb1-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb1>; + clock-indices = <0>, <4>, + <5>, <12>, + <13>; clock-output-names = "apb1_codec", "apb1_digital_mic", "apb1_pio", "apb1_daudio0", "apb1_daudio1"; @@ -299,6 +316,10 @@ compatible = "allwinner,sun6i-a31-apb2-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb2>; + clock-indices = <0>, <1>, + <2>, <3>, <16>, + <17>, <18>, <19>, + <20>, <21>; clock-output-names = "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", "apb2_i2c3", "apb2_uart0", "apb2_uart1", @@ -346,6 +367,14 @@ "mmc3_sample"; }; + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 0>; + clock-output-names = "ss"; + }; + spi0_clk: clk@01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -384,6 +413,9 @@ compatible = "allwinner,sun6i-a31-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&osc24M>; + clock-indices = <8>, <9>, <10>, + <16>, <17>, + <18>; clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", "usb_ohci0", "usb_ohci1", "usb_ohci2"; @@ -512,6 +544,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c19000 { + compatible = "allwinner,sun6i-a31-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun6i-a31-usb-phy"; reg = <0x01c19400 0x10>, @@ -599,8 +644,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { @@ -870,6 +914,16 @@ #size-cells = <0>; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 5>; + reset-names = "ahb"; + }; + timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts index 1e2411a2bcea..5e8f8c4f2b30 100644 --- a/arch/arm/boot/dts/sun6i-a31s-cs908.dts +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts @@ -93,6 +93,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 4611e2f5a99e..e6b019232a9e 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -88,15 +88,11 @@ }; }; - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_cubietruck>; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>; + reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; }; @@ -172,7 +168,8 @@ &mmc3 { pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -181,7 +178,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; @@ -199,23 +196,27 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { - vmmc3_pin_cubietruck: vmmc3_pin@0 { - allwinner,pins = "PH9"; + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { + allwinner,pins = "PH12"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - allwinner,pins = "PH12"; + led_pins_cubietruck: led_pins@0 { + allwinner,pins = "PH7", "PH11", "PH20", "PH21"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; + mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 { + allwinner,pins = "PH9"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; @@ -227,6 +228,20 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; &pwm { @@ -288,7 +303,16 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ + usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index f32f6f20d923..1e6bd360dac0 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -178,7 +178,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 769726dfb046..04237085dc39 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -135,6 +135,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { allwinner,pins = "PC3"; @@ -149,6 +153,20 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { @@ -157,6 +175,10 @@ status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -171,7 +193,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 00f8f25eccae..c5d70caade82 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -215,6 +215,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { allwinner,pins = "PH11"; @@ -229,12 +233,30 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -275,7 +297,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 6a63f30c9a69..2bebaa286f9a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -267,6 +267,19 @@ compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, <21>, + <22>, <23>, <25>, + <28>, <32>, <33>, <34>, + <35>, <36>, <37>, <40>, + <41>, <42>, <43>, + <44>, <45>, <46>, + <47>, <49>, <50>, + <52>; clock-output-names = "ahb_usb0", "ahb_ehci0", "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", @@ -295,6 +308,10 @@ compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, + <8>, <10>; clock-output-names = "apb0_codec", "apb0_spdif", "apb0_ac97", "apb0_iis0", "apb0_iis1", "apb0_pio", "apb0_ir0", "apb0_ir1", @@ -314,6 +331,12 @@ compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <5>, <6>, <7>, + <15>, <16>, <17>, + <18>, <19>, <20>, + <21>, <22>, <23>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_i2c3", "apb1_can", "apb1_scr", "apb1_ps20", "apb1_ps21", @@ -699,6 +722,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; @@ -731,6 +767,14 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; @@ -794,8 +838,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 7abd0ae3143d..27a925ec17d2 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -180,6 +180,15 @@ compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb1>; + clock-indices = <1>, <6>, + <8>, <9>, <10>, + <13>, <14>, + <19>, <20>, + <21>, <24>, <26>, + <29>, <32>, <36>, + <40>, <44>, <46>, + <52>, <54>, + <57>; clock-output-names = "ahb1_mipidsi", "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", "ahb1_sdram", @@ -196,6 +205,8 @@ compatible = "allwinner,sun8i-a23-apb1-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb1>; + clock-indices = <0>, <5>, + <12>, <13>; clock-output-names = "apb1_codec", "apb1_pio", "apb1_daudio0", "apb1_daudio1"; }; @@ -213,6 +224,10 @@ compatible = "allwinner,sun8i-a23-apb2-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb2>; + clock-indices = <0>, <1>, + <2>, <16>, + <17>, <18>, + <19>, <20>; clock-output-names = "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", "apb2_uart0", "apb2_uart1", "apb2_uart2", @@ -332,6 +347,28 @@ #size-cells = <0>; }; + ehci0: usb@01c1a000 { + compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl@01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; @@ -339,8 +376,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts index 95134c69cfc1..8d9da6886a4c 100644 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -125,3 +125,12 @@ pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 8698f7aa31c7..2cc27c7a59dc 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -58,6 +58,39 @@ clock-output-names = "mbus"; }; }; + + soc@01c00000 { + usb_otg: usb@01c19000 { + compatible = "allwinner,sun6i-a31-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&usb_clk 8>, + <&usb_clk 9>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + }; }; &pio { diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index 866703355b9c..1aefc6793e25 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -61,6 +61,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -109,6 +113,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &pio { mmc0_cd_pin_q8h: mmc0_cd_pin@0 { allwinner,pins = "PB4"; @@ -123,3 +131,12 @@ pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts new file mode 100644 index 000000000000..a43897515fb6 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts @@ -0,0 +1,133 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Ippo Q8H Quad Core Tablet (v1.2)"; + compatible = "ippo,a33-q8h-v1.2", "allwinner,sun8i-a33"; + + aliases { + serial0 = &r_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; + +/* + * FIXME for now we only support host mode and rely on u-boot to have + * turned on Vbus which is controlled by the axp223 pmic on the board. + * + * Once we have axp223 support we should switch to fully supporting otg. + */ +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 5788c29cb56a..1d5390d4e03a 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -63,6 +63,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &lradc { vref-supply = <®_vcc3v0>; status = "okay"; @@ -113,6 +117,10 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; +&ohci0 { + status = "okay"; +}; + &pio { mmc0_cd_pin_sina33: mmc0_cd_pin@0 { allwinner,pins = "PB4"; @@ -127,3 +135,8 @@ pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +}; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 85ee08098b7b..faa7d3c1fcea 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -80,6 +80,39 @@ clock-output-names = "mbus"; }; }; + + soc@01c00000 { + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&usb_clk 8>, + <&usb_clk 9>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + }; }; &pio { diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index a43ad779ee2f..5908e3dcf965 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -277,9 +277,12 @@ compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; reg = <0x06000580 0x4>; clocks = <&ahb0>; - clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>, - <14>, <15>, <16>, <18>, <20>, <21>, - <22>, <23>; + clock-indices = <0>, <1>, <3>, + <5>, <8>, <12>, + <13>, <14>, + <15>, <16>, <18>, + <20>, <21>, <22>, + <23>; clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", "ahb0_ss", "ahb0_sd", "ahb0_nand1", "ahb0_nand0", "ahb0_sdram", @@ -293,7 +296,10 @@ compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; reg = <0x06000584 0x4>; clocks = <&ahb1>; - clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>; + clock-indices = <0>, <1>, + <17>, <21>, + <22>, <23>, + <24>; clock-output-names = "ahb1_usbotg", "ahb1_usbhci", "ahb1_gmac", "ahb1_msgbox", "ahb1_spinlock", "ahb1_hstimer", @@ -305,8 +311,9 @@ compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; reg = <0x06000588 0x4>; clocks = <&ahb2>; - clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>, - <11>; + clock-indices = <0>, <1>, + <2>, <4>, <5>, + <7>, <8>, <11>; clock-output-names = "ahb2_lcd0", "ahb2_lcd1", "ahb2_edp", "ahb2_csi", "ahb2_hdmi", "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; @@ -317,8 +324,10 @@ compatible = "allwinner,sun9i-a80-apb0-gates-clk"; reg = <0x06000590 0x4>; clocks = <&apb0>; - clock-indices = <1>, <5>, <11>, <12>, <13>, <15>, - <17>, <18>, <19>; + clock-indices = <1>, <5>, + <11>, <12>, <13>, + <15>, <17>, <18>, + <19>; clock-output-names = "apb0_spdif", "apb0_pio", "apb0_ac97", "apb0_i2s0", "apb0_i2s1", "apb0_lradc", "apb0_gpadc", "apb0_twd", @@ -330,8 +339,11 @@ compatible = "allwinner,sun9i-a80-apb1-gates-clk"; reg = <0x06000594 0x4>; clocks = <&apb1>; - clock-indices = <0>, <1>, <2>, <3>, <4>, - <16>, <17>, <18>, <19>, <20>, <21>; + clock-indices = <0>, <1>, + <2>, <3>, <4>, + <16>, <17>, + <18>, <19>, + <20>, <21>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", "apb1_uart0", "apb1_uart1", diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 51cc8383f70f..f1953b0c5059 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -108,6 +108,7 @@ regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; enable-active-high; gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; status = "disabled"; @@ -120,6 +121,7 @@ regulator-name = "usb2-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; enable-active-high; gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index f58a3d9d5f13..9d4f86e9c50a 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -214,9 +214,9 @@ #dma-cells = <1>; }; - ahb: ahb@6000c004 { + ahb: ahb@6000c000 { compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; - reg = <0x6000c004 0x14c>; + reg = <0x6000c000 0x150>; }; gpio: gpio@6000d000 { @@ -234,6 +234,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + gpio-ranges = <&pinmux 0 0 246>; }; apbmisc@70000800 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index bd43ed6d6ec7..66b4451eb2ca 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -53,6 +53,14 @@ }; }; + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + pinmux: pinmux@0,70000868 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1462,7 +1470,7 @@ vin-ldo9-10-supply = <&vdd_5v0_sys>; vin-ldo11-supply = <&vdd_3v3_run>; - sd0 { + vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1514,7 +1522,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; @@ -1694,6 +1702,13 @@ non-removable; }; + /* CPU DFLL clock */ + clock@0,70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + ahub@0,70300000 { i2s@0,70301100 { status = "okay"; @@ -1732,6 +1747,12 @@ }; }; + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 79e724bb7df7..cfbdf429b45d 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -43,6 +43,14 @@ }; }; + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + pinmux: pinmux@0,70000868 { pinctrl-names = "boot"; pinctrl-0 = <&pinmux_boot>; @@ -735,7 +743,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 01a9f742b08f..1e204a6de12c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/tegra124-car.h> #include <dt-bindings/thermal/tegra124-soctherm.h> #include "skeleton.dtsi" @@ -188,6 +189,9 @@ clock-names = "gpu", "pwr"; resets = <&tegra_car 184>; reset-names = "gpu"; + + iommus = <&mc TEGRA_SWGROUP_GPU>; + status = "disabled"; }; @@ -254,6 +258,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + gpio-ranges = <&pinmux 0 0 251>; }; apbdma: dma@0,60020000 { @@ -702,6 +707,30 @@ #thermal-sensor-cells = <1>; }; + dfll: clock@0,70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, @@ -922,6 +951,15 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 { @@ -943,6 +981,18 @@ }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>, + <&{/cpus/cpu@2}>, + <&{/cpus/cpu@3}>; + }; + thermal-zones { cpu { polling-delay-passive = <1000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f444b67f55c6..e058709e6d98 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -225,9 +225,9 @@ #dma-cells = <1>; }; - ahb@6000c004 { + ahb@6000c000 { compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio@6000d000 { @@ -244,6 +244,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + gpio-ranges = <&pinmux 0 0 224>; }; apbmisc@70000800 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 782b11b2af6a..fe04fb5e155f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -329,9 +329,9 @@ #dma-cells = <1>; }; - ahb: ahb@6000c004 { + ahb: ahb@6000c000 { compatible = "nvidia,tegra30-ahb"; - reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ + reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ }; gpio: gpio@6000d000 { @@ -349,6 +349,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; + gpio-ranges = <&pinmux 0 0 248>; }; apbmisc@70000800 { diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts index 200b0c99ed34..bfd3bb8c8285 100644 --- a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts @@ -44,6 +44,7 @@ /dts-v1/; /include/ "uniphier-ph1-ld4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { @@ -57,11 +58,18 @@ chosen { bootargs = "console=ttyS0,115200"; - stdout-path = &serialsc; + stdout-path = &serial0; }; aliases { - serial0 = &serialsc; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; }; }; @@ -74,6 +82,30 @@ ranges = <0x00000000 1 0x03f00000 0x00100000>; }; -&serialsc { +ðsc { interrupts = <0 49 4>; }; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi index 6a34c56e4693..a6a185fae8f1 100644 --- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi @@ -64,6 +64,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -79,12 +91,141 @@ #size-cells = <1>; }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + system-bus-controller-misc@59800000 { compatible = "socionext,uniphier-system-bus-controller-misc", "syscon"; reg = <0x59800000 0x2000>; }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 80 4>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + interrupts = <0 81 4>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 82 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-ld4-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -108,3 +249,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts new file mode 100644 index 000000000000..33963acd7e8f --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts @@ -0,0 +1,105 @@ +/* + * Device Tree Source for UniPhier PH1-LD6b Reference Board + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-ld6b.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-LD6b Reference Board"; + compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&extbus { + ranges = <0 0x00000000 0x0f000000 0x01000000 + 1 0x00000000 0x00000000 0x08000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x03f00000 0x00100000>; +}; + +ðsc { + interrupts = <0 50 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi new file mode 100644 index 000000000000..c6499ee65bc6 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi @@ -0,0 +1,67 @@ +/* + * Device Tree Source for UniPhier PH1-LD6b SoC + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * PH1-LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the ProXstream2 die. + * Reuse the ProXstream2 device tree with some properties overridden. + */ +/include/ "uniphier-proxstream2.dtsi" + +/ { + compatible = "socionext,ph1-ld6b"; +}; + +/* UART3 unavilable: the pads are not wired to the package balls */ +&serial3 { + status = "disabled"; +}; + +/* + * PH1-LD6b and ProXstream2 have completely different packages, + * which makes the pinctrl driver unshareable. + */ +&pinctrl { + compatible = "socionext,ph1-ld6b-pinctrl", "syscon"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts index d891135a70c2..69a5b7d39629 100644 --- a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts @@ -44,6 +44,7 @@ /dts-v1/; /include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { @@ -57,11 +58,20 @@ chosen { bootargs = "console=ttyS0,115200"; - stdout-path = &serialsc; + stdout-path = &serial0; }; aliases { - serial0 = &serialsc; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; }; }; @@ -74,6 +84,30 @@ ranges = <0x00000000 1 0x03f00000 0x00100000>; }; -&serialsc { +ðsc { interrupts = <0 50 4>; }; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi index dc633603aed2..e8bbc454d788 100644 --- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi @@ -71,6 +71,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; }; soc { @@ -86,12 +98,156 @@ #size-cells = <1>; }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + system-bus-controller-misc@59800000 { compatible = "socionext,uniphier-system-bus-controller-misc", "syscon"; reg = <0x59800000 0x2000>; }; + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 80 4>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + interrupts = <0 81 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-pro4-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -115,3 +271,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi new file mode 100644 index 000000000000..59c2b127cffa --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi @@ -0,0 +1,252 @@ +/* + * Device Tree Source for UniPhier PH1-Pro5 SoC + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,ph1-pro5"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 177 4>; + clocks = <&uart_clk>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-pro5-pinctrl", "syscon"; + reg = <0x5f801000 0xe00>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts index 3ea64ae009e9..1a440f87fa92 100644 --- a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts @@ -44,6 +44,7 @@ /dts-v1/; /include/ "uniphier-ph1-sld3.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { @@ -58,11 +59,18 @@ chosen { bootargs = "console=ttyS0,115200"; - stdout-path = &serialsc; + stdout-path = &serial0; }; aliases { - serial0 = &serialsc; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; }; }; @@ -75,6 +83,38 @@ ranges = <0x00000000 1 0x03f00000 0x00100000>; }; -&serialsc { +ðsc { interrupts = <0 49 4>; }; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi index 248b1886834f..3cc90cd37a26 100644 --- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi @@ -71,6 +71,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -108,10 +120,120 @@ <0x20000100 0x100>; }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58600000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58600000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + system-bus-controller-misc@59800000 { compatible = "socionext,uniphier-system-bus-controller-misc", "syscon"; reg = <0x59800000 0x2000>; }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + }; + + usb3: usb@5a830100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a830100 0x100>; + interrupts = <0 83 4>; + }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts index dcdc4f74387d..955d417a5c42 100644 --- a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts @@ -44,6 +44,7 @@ /dts-v1/; /include/ "uniphier-ph1-sld8.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { @@ -57,11 +58,18 @@ chosen { bootargs = "console=ttyS0,115200"; - stdout-path = &serialsc; + stdout-path = &serial0; }; aliases { - serial0 = &serialsc; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; }; }; @@ -74,6 +82,34 @@ ranges = <0x00000000 1 0x03f00000 0x00100000>; }; -&serialsc { +ðsc { interrupts = <0 48 4>; }; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi index baa71e1febb8..58067dfc16e5 100644 --- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi @@ -64,6 +64,18 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; }; soc { @@ -79,12 +91,141 @@ #size-cells = <1>; }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 29 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + system-bus-controller-misc@59800000 { compatible = "socionext,uniphier-system-bus-controller-misc", "syscon"; reg = <0x59800000 0x2000>; }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 80 4>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + interrupts = <0 81 4>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + interrupts = <0 82 4>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-sld8-pinctrl", + "syscon"; + reg = <0x5f801000 0xe00>; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -108,3 +249,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi new file mode 100644 index 000000000000..f67445f4f10d --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -0,0 +1,105 @@ +/* + * Device Tree Source for UniPhier SoCs default pinctrl settings + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&pinctrl { + pinctrl_i2c0: i2c0_grp { + groups = "i2c0"; + function = "i2c0"; + }; + + pinctrl_i2c1: i2c1_grp { + groups = "i2c1"; + function = "i2c1"; + }; + + pinctrl_i2c2: i2c2_grp { + groups = "i2c2"; + function = "i2c2"; + }; + + pinctrl_i2c3: i2c3_grp { + groups = "i2c3"; + function = "i2c3"; + }; + + pinctrl_uart0: uart0_grp { + groups = "uart0"; + function = "uart0"; + }; + + pinctrl_uart1: uart1_grp { + groups = "uart1"; + function = "uart1"; + }; + + pinctrl_uart2: uart2_grp { + groups = "uart2"; + function = "uart2"; + }; + + pinctrl_uart3: uart3_grp { + groups = "uart3"; + function = "uart3"; + }; + + pinctrl_usb0: usb0_grp { + groups = "usb0"; + function = "usb0"; + }; + + pinctrl_usb1: usb1_grp { + groups = "usb1"; + function = "usb1"; + }; + + pinctrl_usb2: usb2_grp { + groups = "usb2"; + function = "usb2"; + }; + + pinctrl_usb3: usb3_grp { + groups = "usb3"; + function = "usb3"; + }; +}; diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi new file mode 100644 index 000000000000..4c7b24611012 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi @@ -0,0 +1,273 @@ +/* + * Device Tree Source for UniPhier ProXstream2 SoC + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,proxstream2"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <88900000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + interrupts = <0 177 4>; + clocks = <&uart_clk>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + interrupts = <0 42 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + interrupts = <0 44 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,proxstream2-pinctrl", "syscon"; + reg = <0x5f801000 0xe00>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0xf04>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0xf04>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi new file mode 100644 index 000000000000..3d29d2806cc0 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi @@ -0,0 +1,50 @@ +/* + * Device Tree Source for UniPhier Reference Daughter Board + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&i2c0 { + eeprom { + compatible = "microchip,24lc128"; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 2efb2058ba49..21b02874bea3 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -101,6 +101,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; /* PCI-E I2C bus */ diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index cb3090f919a7..e712c0af149b 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -100,6 +100,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; /* PCI-E I2C bus */ diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index 606753eb72c8..ed65e0f7dfc0 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -9,7 +9,7 @@ / { chosen { - bootargs = "console=ttyLP0,115200"; + stdout-path = "serial0:115200n8"; }; clk16m: clk16m { diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 4aa335166be7..6865137fd114 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -226,7 +226,10 @@ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ADC0>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; }; wdoga5: wdog@4003e000 { @@ -242,7 +245,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>; + reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_QSPI0_EN>, <&clks VF610_CLK_QSPI0>; @@ -347,6 +351,20 @@ status = "disabled"; }; + i2c1: i2c@40067000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40067000 0x1000>; + interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C1>; + clock-names = "ipg"; + dmas = <&edma0 0 52>, + <&edma0 0 53>; + dma-names = "rx","tx"; + status = "disabled"; + }; + clks: ccm@4006b000 { compatible = "fsl,vf610-ccm"; reg = <0x4006b000 0x1000>; @@ -404,14 +422,13 @@ }; snvs0: snvs@400a7000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400a7000 0x2000>; + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x400a7000 0x2000>; - snvsrtc: snvs-rtc-lp@34 { + snvsrtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - reg = <0x34 0x58>; + regmap = <&snvs0>; + offset = <0x34>; interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_SNVS>; clock-names = "snvs-rtc"; @@ -442,9 +459,23 @@ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_ADC1>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; + esdhc0: esdhc@400b1000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b1000 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC0>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + }; + esdhc1: esdhc@400b2000 { compatible = "fsl,imx53-esdhc"; reg = <0x400b2000 0x1000>; @@ -488,6 +519,19 @@ status = "disabled"; }; + qspi1: quadspi@400c4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI1_EN>, + <&clks VF610_CLK_QSPI1>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; @@ -520,6 +564,33 @@ status = "disabled"; }; + i2c2: i2c@400e6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e6000 0x1000>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C2>; + clock-names = "ipg"; + dmas = <&edma0 1 36>, + <&edma0 1 37>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + i2c3: i2c@400e7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e7000 0x1000>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_I2C3>; + clock-names = "ipg"; + dmas = <&edma0 1 38>, + <&edma0 1 39>; + dma-names = "rx","tx"; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 06915080b875..dc0457e40775 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -57,7 +57,7 @@ regulator-always-on; }; - amba { + amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -139,6 +139,7 @@ L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; @@ -258,6 +259,13 @@ reg = <0x100 0x100>; }; + rstc: rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <1>; + syscon = <&slcr>; + }; + pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index fb59d34e8ee6..5df8f81f4217 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -34,6 +34,27 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw14 { + label = "sw14"; + gpios = <&gpio0 12 0>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + sw13 { + label = "sw13"; + gpios = <&gpio0 14 0>; + linux,code = <103>; /* up */ + gpio-key,wakeup; + autorepeat; + }; + }; + leds { compatible = "gpio-leds"; @@ -50,6 +71,13 @@ }; }; +&amba { + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + }; +}; + &can0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 5114b68e99d5..96dabcb6c621 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -91,7 +91,7 @@ void it8152_init_irq(void) for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { irq_set_chip_and_handler(irq, &it8152_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } } diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index b55c3625d7ee..304adea4bc52 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -138,9 +138,9 @@ static struct locomo_dev_info locomo_devices[] = { }, }; -static void locomo_handler(unsigned int irq, struct irq_desc *desc) +static void locomo_handler(unsigned int __irq, struct irq_desc *desc) { - struct locomo *lchip = irq_get_chip_data(irq); + struct locomo *lchip = irq_desc_get_chip_data(desc); int req, i; /* Acknowledge the parent IRQ */ @@ -150,6 +150,8 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc) req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; if (req) { + unsigned int irq; + /* generate the next interrupt(s) */ irq = lchip->irq_base; for (i = 0; i <= 3; i++, irq++) { @@ -205,7 +207,7 @@ static void locomo_setup_irq(struct locomo *lchip) for ( ; irq <= lchip->irq_base + 3; irq++) { irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); irq_set_chip_data(irq, lchip); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } } @@ -475,8 +477,7 @@ static void __locomo_remove(struct locomo *lchip) device_for_each_child(lchip->dev, NULL, locomo_remove_child); if (lchip->irq != NO_IRQ) { - irq_set_chained_handler(lchip->irq, NULL); - irq_set_handler_data(lchip->irq, NULL); + irq_set_chained_handler_and_data(lchip->irq, NULL, NULL); } iounmap(lchip->base); diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c index 92e54d7c6f46..2b25b6038f66 100644 --- a/arch/arm/common/mcpm_platsmp.c +++ b/arch/arm/common/mcpm_platsmp.c @@ -65,14 +65,10 @@ static int mcpm_cpu_kill(unsigned int cpu) return !mcpm_wait_for_cpu_powerdown(pcpu, pcluster); } -static int mcpm_cpu_disable(unsigned int cpu) +static bool mcpm_cpu_can_disable(unsigned int cpu) { - /* - * We assume all CPUs may be shut down. - * This would be the hook to use for eventual Secure - * OS migration requests as described in the PSCI spec. - */ - return 0; + /* We assume all CPUs may be shut down. */ + return true; } static void mcpm_cpu_die(unsigned int cpu) @@ -92,7 +88,7 @@ static struct smp_operations __initdata mcpm_smp_ops = { .smp_secondary_init = mcpm_secondary_init, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = mcpm_cpu_kill, - .cpu_disable = mcpm_cpu_disable, + .cpu_can_disable = mcpm_cpu_can_disable, .cpu_die = mcpm_cpu_die, #endif }; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 93ee70dbbdd3..4f290250fa93 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -197,10 +197,11 @@ static struct sa1111_dev_info sa1111_devices[] = { * will call us again if there are more interrupts to process. */ static void -sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) +sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); unsigned int stat0, stat1, i; - struct sa1111 *sachip = irq_get_handler_data(irq); + struct sa1111 *sachip = irq_desc_get_handler_data(desc); void __iomem *mapbase = sachip->base + SA1111_INTC; stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); @@ -486,7 +487,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) irq_set_chip_and_handler(irq, &sa1111_low_chip, handle_edge_irq); irq_set_chip_data(irq, sachip); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { @@ -494,7 +495,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) irq_set_chip_and_handler(irq, &sa1111_high_chip, handle_edge_irq); irq_set_chip_data(irq, sachip); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } /* diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig deleted file mode 100644 index 5666e3700a82..000000000000 --- a/arch/arm/configs/armadillo800eva_defconfig +++ /dev/null @@ -1,162 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_PID_NS is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_R8A7740=y -CONFIG_MACH_ARMADILLO800EVA=y -# CONFIG_SH_TIMER_TMU is not set -CONFIG_ARM_THUMB=y -CONFIG_CACHE_L2X0=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_458693=y -CONFIG_ARM_ERRATA_460075=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_ARM_ERRATA_743622=y -CONFIG_ARM_ERRATA_751472=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_FORCE_MAX_ZONEORDER=13 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_KEXEC=y -CONFIG_VFP=y -CONFIG_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -CONFIG_SH_ETH=y -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST1232=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=9 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_SH_MOBILE=y -# CONFIG_HWMON is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_GPIO=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_MT9T112=y -CONFIG_VIDEO_SH_MOBILE_CEU=y -CONFIG_FB=y -CONFIG_FB_SH_MOBILE_LCDC=y -CONFIG_FB_SH_MOBILE_HDMI=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SOC_SH4_FSI=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_RENESAS_USBHS=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=y -CONFIG_USB_ETH=m -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_S35390A=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -CONFIG_UIO=y -CONFIG_UIO_PDRV_GENIRQ=y -CONFIG_PWM=y -CONFIG_PWM_RENESAS_TPU=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 94b5dcabdecc..090c5b25dbed 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -73,7 +73,6 @@ CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_ARM_AT91_ETHER=y CONFIG_MACB=y # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_DM9000=y @@ -131,8 +130,18 @@ CONFIG_POWER_RESET=y CONFIG_WATCHDOG=y CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_SSB=m +CONFIG_MFD_ATMEL_HLCDC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_ATMEL_ISI=y +CONFIG_SOC_CAMERA_OV2640=m +CONFIG_DRM=y +CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_LCD_SUPPORT=y @@ -140,6 +149,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_ATMEL_LCDC=y # CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y @@ -186,6 +196,7 @@ CONFIG_IIO=y CONFIG_AT91_ADC=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y +CONFIG_PWM_ATMEL_HLCDC_PWM=y CONFIG_PWM_ATMEL_TCB=y CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index dc01c049a520..3b32d5fd9326 100644 --- a/arch/arm/configs/cm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig @@ -157,7 +157,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_V3020=y -CONFIG_RTC_DRV_SA1100=y +CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_INOTIFY=y diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig index 4560c9ca6636..8e10df7ba1b4 100644 --- a/arch/arm/configs/em_x270_defconfig +++ b/arch/arm/configs/em_x270_defconfig @@ -157,7 +157,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_V3020=y -CONFIG_RTC_DRV_SA1100=y +CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_INOTIFY=y diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 72233b9c9d07..a7846d64b396 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -1,4 +1,6 @@ CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -15,19 +17,25 @@ CONFIG_CRUNCH=y CONFIG_MACH_ADSSPHERE=y CONFIG_MACH_EDB9301=y CONFIG_MACH_EDB9302=y +CONFIG_MACH_EDB9302A=y CONFIG_MACH_EDB9307=y +CONFIG_MACH_EDB9307A=y CONFIG_MACH_EDB9312=y CONFIG_MACH_EDB9315=y +CONFIG_MACH_EDB9315A=y CONFIG_MACH_GESBC9312=y CONFIG_MACH_MICRO9H=y +CONFIG_MACH_MICRO9M=y CONFIG_MACH_MICRO9L=y +CONFIG_MACH_MICRO9S=y +CONFIG_MACH_SIM_ONE=y +CONFIG_MACH_SNAPPER_CL15=y CONFIG_MACH_TS72XX=y +CONFIG_MACH_VISION_EP9307=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -74,11 +82,18 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y +CONFIG_SPI=y +CONFIG_SPI_EP93XX=y CONFIG_WATCHDOG=y CONFIG_EP93XX_WATCHDOG=y +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_EP93XX=y +CONFIG_LOGO=y CONFIG_USB=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_OHCI_HCD=y @@ -87,13 +102,23 @@ CONFIG_USB_STORAGE=y CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y CONFIG_USB_SERIAL_PL2303=y +CONFIG_MMC=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_M48T86=y CONFIG_RTC_DRV_EP93XX=y +CONFIG_DMADEVICES=y +CONFIG_EP93XX_DMA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 9504e7790288..1ff2bfa2e183 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -27,6 +27,8 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_VFP=y @@ -94,6 +96,7 @@ CONFIG_CHARGER_MAX14577=y CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_TPS65090=y CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_NTC_THERMISTOR=y CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_INA2XX=y CONFIG_THERMAL=y @@ -124,14 +127,14 @@ CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_DRM=y -CONFIG_DRM_PTN3460=y -CONFIG_DRM_PS8622=y +CONFIG_DRM_NXP_PTN3460=y +CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_EXYNOS=y CONFIG_DRM_EXYNOS_FIMD=y CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_PANEL_S6E8AA0=y +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y @@ -144,6 +147,8 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_SNOW=y +CONFIG_SND_SOC_ODROIDX2=y +CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_XHCI_HCD=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index b47863d49ac6..79194c60c78c 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -3,6 +3,8 @@ CONFIG_SYSVIPC=y CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_RELAY=y @@ -38,9 +40,10 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y CONFIG_SOC_IMX7D=y -CONFIG_SOC_VF610=y CONFIG_SOC_LS1021A=y +CONFIG_SOC_VF610=y CONFIG_PCI=y CONFIG_PCI_IMX6=y CONFIG_SMP=y @@ -50,13 +53,13 @@ CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_CMA=y CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_BINFMT_MISC=m -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_NET=y @@ -75,8 +78,8 @@ CONFIG_CAN=y CONFIG_CAN_FLEXCAN=y CONFIG_BT=y CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_3WIRE=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_RFKILL=y @@ -150,6 +153,7 @@ CONFIG_WLCORE_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y CONFIG_KEYBOARD_IMX=y CONFIG_MOUSE_PS2=m CONFIG_MOUSE_PS2_ELANTECH=y @@ -185,6 +189,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_IMX=y CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y @@ -219,10 +224,16 @@ CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_FB_HELPER=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_FB_MXS=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -CONFIG_FB_MXS=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -231,7 +242,7 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y -CONFIG_SND_SOC_FSL_SAI=y +CONFIG_SND_SOC_FSL_ASRC=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y @@ -239,6 +250,8 @@ CONFIG_SND_SOC_IMX_WM8962=y CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_MC13783=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y @@ -301,13 +314,6 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_FSL_EDMA=y CONFIG_STAGING=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_FB_HELPER=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_IPUV3=y -CONFIG_DRM_IMX_HDMI=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y CONFIG_PWM_IMX=y @@ -354,8 +360,7 @@ CONFIG_PROVE_LOCKING=y # CONFIG_FTRACE is not set # CONFIG_ARM_UNWIND is not set CONFIG_SECURITYFS=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRC_CCITT=m CONFIG_CRC_T10DIF=y CONFIG_CRC7=m diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig deleted file mode 100644 index 23e8d146dc16..000000000000 --- a/arch/arm/configs/kzm9g_defconfig +++ /dev/null @@ -1,154 +0,0 @@ -# CONFIG_ARM_PATCH_PHYS_VIRT is not set -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_NET_NS is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_SH73A0=y -CONFIG_MACH_KZM9G=y -CONFIG_MEMORY_START=0x41000000 -CONFIG_MEMORY_SIZE=0x1f000000 -CONFIG_ARM_ERRATA_743622=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_KEXEC=y -CONFIG_VFP=y -CONFIG_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=y -CONFIG_SH_IRDA=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_SMSC911X=y -# CONFIG_WLAN is not set -CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST1232=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_ADXL34X=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=9 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_GPIO_PCF857X=y -# CONFIG_HWMON is not set -CONFIG_MFD_AS3711=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_AS3711=y -CONFIG_FB=y -CONFIG_FB_SH_MOBILE_LCDC=y -CONFIG_BACKLIGHT_AS3711=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_FB_SH_MOBILE_MERAM=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_SOC_SH4_FSI=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_R8A66597_HCD=y -CONFIG_USB_RENESAS_USBHS=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=y -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RS5C372=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -CONFIG_ASYNC_TX_DMA=y -CONFIG_STAGING=y -CONFIG_IIO=y -CONFIG_AK8975=y -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_FTRACE is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_DES=y -CONFIG_CRC16=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index 557dd291288b..a5b4920cd6d4 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -150,7 +150,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DEBUG=y -CONFIG_RTC_DRV_SA1100=y +CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_INOTIFY=y CONFIG_MSDOS_FS=m diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig deleted file mode 100644 index 3c8b6d823189..000000000000 --- a/arch/arm/configs/marzen_defconfig +++ /dev/null @@ -1,124 +0,0 @@ -# CONFIG_ARM_PATCH_PHYS_VIRT is not set -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_NO_HZ=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_SYSCTL_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_R8A7779=y -CONFIG_MACH_MARZEN=y -CONFIG_MEMORY_START=0x60000000 -CONFIG_MEMORY_SIZE=0x10000000 -CONFIG_SHMOBILE_TIMER_HZ=1024 -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SWP_EMULATE is not set -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_458693=y -CONFIG_ARM_ERRATA_460075=y -CONFIG_ARM_ERRATA_743622=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_SMP=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_VFP=y -CONFIG_KEXEC=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_ATA=y -CONFIG_ATA_SFF=y -CONFIG_ATA_BMDMA=y -CONFIG_SATA_RCAR=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMSC911X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=6 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_RCAR=y -CONFIG_SPI=y -CONFIG_SPI_SH_HSPI=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_RCAR=y -# CONFIG_HWMON is not set -CONFIG_THERMAL=y -CONFIG_RCAR_THERMAL=y -CONFIG_SSB=y -CONFIG_REGULATOR=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_VIDEO_RCAR_VIN=y -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -CONFIG_VIDEO_ADV7180=y -CONFIG_DRM=y -CONFIG_DRM_RCAR_DU=y -CONFIG_USB=y -CONFIG_USB_RCAR_PHY=y -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_DMADEVICES=y -CONFIG_RCAR_HPB_DMAE=y -CONFIG_UIO=y -CONFIG_UIO_PDRV_GENIRQ=y -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_REDUCED=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_AVERAGE=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5fd8df6f50ea..03deb7fb35e8 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -49,6 +49,8 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_IMX7D=y CONFIG_SOC_VF610=y CONFIG_SOC_LS1021A=y CONFIG_ARCH_OMAP3=y @@ -80,6 +82,7 @@ CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y CONFIG_ARCH_R8A7791=y +CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y CONFIG_ARCH_SH73A0=y CONFIG_MACH_MARZEN=y @@ -98,6 +101,7 @@ CONFIG_MACH_SNOWBALL=y CONFIG_MACH_UX500_DT=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_VEXPRESS_CA9X4=y +CONFIG_ARCH_VEXPRESS_TC2_PM=y CONFIG_ARCH_WM8850=y CONFIG_ARCH_ZYNQ=y CONFIG_TRUSTED_FOUNDATIONS=y @@ -251,6 +255,7 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_UNIPHIER=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_ATMEL=y @@ -301,6 +306,7 @@ CONFIG_I2C_S3C2410=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_SIRF=y CONFIG_I2C_ST=y +CONFIG_I2C_SUN6I_P2WI=y CONFIG_I2C_TEGRA=y CONFIG_I2C_XILINX=y CONFIG_I2C_RCAR=y @@ -356,6 +362,7 @@ CONFIG_POWER_RESET_KEYSTONE=y CONFIG_POWER_RESET_RMOBILE=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM95245=y +CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_RCAR_THERMAL=y @@ -370,7 +377,9 @@ CONFIG_ARM_SP805_WATCHDOG=y CONFIG_ORION_WATCHDOG=y CONFIG_ST_LPC_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=y +CONFIG_TEGRA_WATCHDOG=m CONFIG_MESON_WATCHDOG=y +CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_MFD_AS3711=y CONFIG_MFD_AS3722=y CONFIG_MFD_BCM590XX=y @@ -402,7 +411,10 @@ CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77802=m CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_PBIAS=y +CONFIG_REGULATOR_PWM=m CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS51632=y @@ -429,15 +441,18 @@ CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ML86V7667=m CONFIG_DRM=y -CONFIG_DRM_PTN3460=m -CONFIG_DRM_PS8622=m +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_NOUVEAU=m CONFIG_DRM_EXYNOS=m CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_FIMD=y CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_TEGRA=y -CONFIG_DRM_PANEL_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB_ARMCLCD=y CONFIG_FB_WM8505=y @@ -454,12 +469,18 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_SOUND=m CONFIG_SND=m CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_HDA_TEGRA=m +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=m CONFIG_SND_ATMEL_SOC=m CONFIG_SND_ATMEL_SOC_WM8904=m CONFIG_SND_SOC_SH4_FSI=m CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_RSRC_CARD=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA_RT5640=m CONFIG_SND_SOC_TEGRA_WM8753=m @@ -491,8 +512,6 @@ CONFIG_USB_CHIPIDEA_HOST=y CONFIG_AB8500_USB=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_OMAP_USB3=y -CONFIG_SAMSUNG_USB2PHY=y -CONFIG_SAMSUNG_USB3PHY=y CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y CONFIG_USB_MXS_PHY=y @@ -587,6 +606,7 @@ CONFIG_IMX_DMA=y CONFIG_MXS_DMA=y CONFIG_DMA_OMAP=y CONFIG_XILINX_VDMA=y +CONFIG_DMA_SUN6I=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y @@ -612,9 +632,11 @@ CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_PM_DEVFREQ=y CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_MEMORY=y +CONFIG_EXTCON=y CONFIG_TI_AEMIF=y CONFIG_IIO=y CONFIG_AT91_ADC=m +CONFIG_EXYNOS_ADC=m CONFIG_XILINX_XADC=y CONFIG_AK8975=y CONFIG_PWM=y @@ -622,9 +644,11 @@ CONFIG_PWM_ATMEL=m CONFIG_PWM_ATMEL_TCB=m CONFIG_PWM_RENESAS_TPU=y CONFIG_PWM_SAMSUNG=m +CONFIG_PWM_SUN4I=y CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_PHY_HIX5HD2_SATA=y +CONFIG_PWM_STI=m CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y CONFIG_PHY_MIPHY28LP=y @@ -660,6 +684,7 @@ CONFIG_LOCKUP_DETECTOR=y CONFIG_CRYPTO_DEV_TEGRA_AES=y CONFIG_CPUFREQ_DT=y CONFIG_KEYSTONE_IRQ=y +CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index cacc9f4055a7..13fcd020e375 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -58,6 +58,7 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PXA3xx=y CONFIG_MTD_SPI_NOR=y +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_AHCI_MVEBU=y @@ -83,11 +84,14 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_WATCHDOG=y CONFIG_ORION_WATCHDOG=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index ac521e764d10..50c84e1876fc 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -136,6 +136,8 @@ CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_OMAP2=y CONFIG_MTD_UBI=y +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_M25P80=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 @@ -169,6 +171,7 @@ CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_TI_DAVINCI_EMAC=y CONFIG_TI_CPSW=y +CONFIG_TI_CPTS=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_AT803X_PHY=y @@ -208,6 +211,7 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_PIXCIR=m CONFIG_TOUCHSCREEN_TSC2005=m CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_INPUT_MISC=y CONFIG_INPUT_TPS65218_PWRBUTTON=m CONFIG_INPUT_TWL4030_PWRBUTTON=m @@ -269,6 +273,7 @@ CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS65910=y +CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_TWL6040_CORE=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PBIAS=y @@ -324,10 +329,13 @@ CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m CONFIG_SND_EDMA_SOC=m CONFIG_SND_AM33XX_SOC_EVM=m +CONFIG_SND_DAVINCI_SOC_MCASP=m CONFIG_SND_OMAP_SOC=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SOC_TLV320AIC3X=m CONFIG_HID_GENERIC=m CONFIG_USB_HIDDEV=y CONFIG_USB_KBD=m @@ -398,6 +406,8 @@ CONFIG_EXTCON=m CONFIG_EXTCON_USB_GPIO=m CONFIG_EXTCON_PALMAS=m CONFIG_TI_EMIF=m +CONFIG_IIO=m +CONFIG_TI_AM335X_ADC=m CONFIG_PWM=y CONFIG_PWM_TIECAP=m CONFIG_PWM_TIEHRPWM=m diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 855143fac6bd..8099417a9466 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -14,8 +14,10 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_ARCH_ORION5X=y +CONFIG_ARCH_ORION5X_DT=y CONFIG_MACH_DB88F5281=y CONFIG_MACH_RD88F5182=y +CONFIG_MACH_RD88F5182_DT=y CONFIG_MACH_KUROBOX_PRO=y CONFIG_MACH_DNS323=y CONFIG_MACH_TS209=y @@ -41,6 +43,7 @@ CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y CONFIG_NET=y diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig index 4baa83c1c577..83c135e19aba 100644 --- a/arch/arm/configs/palmz72_defconfig +++ b/arch/arm/configs/palmz72_defconfig @@ -67,7 +67,7 @@ CONFIG_MMC=y CONFIG_MMC_DEBUG=y CONFIG_MMC_PXA=y CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_SA1100=y +CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_DNOTIFY is not set diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig index 0a847d04ddc1..b5624e325817 100644 --- a/arch/arm/configs/pcm027_defconfig +++ b/arch/arm/configs/pcm027_defconfig @@ -82,7 +82,7 @@ CONFIG_MMC=y CONFIG_MMC_PXA=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_SA1100=m +CONFIG_RTC_DRV_PXA=m CONFIG_EXT2_FS=m CONFIG_EXT3_FS=m # CONFIG_DNOTIFY is not set diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index f610230b9c1f..7cc8e8e4d296 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_RELAY=y @@ -11,14 +10,12 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_SIRF=y -# CONFIG_SWP_EMULATE is not set CONFIG_SMP=y CONFIG_SCHED_MC=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y CONFIG_BINFMT_MISC=y -CONFIG_PM=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y @@ -29,6 +26,7 @@ CONFIG_CHR_DEV_SG=y CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y CONFIG_SERIAL_SIRFSOC=y CONFIG_SERIAL_SIRFSOC_CONSOLE=y CONFIG_HW_RANDOM=y @@ -45,10 +43,14 @@ CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_SIRF=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_SIRFSOC=y CONFIG_DMADEVICES=y CONFIG_DMADEVICES_DEBUG=y CONFIG_DMADEVICES_VDEBUG=y CONFIG_SIRF_DMA=y +CONFIG_HWSPINLOCK_SIRF=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_MSDOS_FS=y @@ -60,12 +62,12 @@ CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_INFO=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index e6a6f282e3de..ff7985ba226e 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -67,6 +67,7 @@ CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y +CONFIG_KS8851=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y CONFIG_SLIP=y @@ -104,8 +105,10 @@ CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y CONFIG_THERMAL=y +CONFIG_MFD_QCOM_RPM=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QCOM_RPM=y CONFIG_MEDIA_SUPPORT=y CONFIG_FB=y CONFIG_SOUND=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 9961fbd633f8..89bf31ccfbfa 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y CONFIG_ARCH_R8A7791=y +CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y CONFIG_ARCH_SH73A0=y CONFIG_MACH_MARZEN=y @@ -121,6 +122,7 @@ CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y CONFIG_MFD_AS3711=y CONFIG_MFD_DA9063=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_GPIO=y @@ -151,6 +153,7 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_SH4_FSI=y CONFIG_SND_SOC_RCAR=y +CONFIG_SND_SOC_RSRC_CARD=y CONFIG_SND_SOC_AK4642=y CONFIG_SND_SOC_WM8978=y CONFIG_USB=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 7ebc346bf9fa..51eea220baae 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -1,5 +1,7 @@ +CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y CONFIG_MODULES=y @@ -72,12 +74,12 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_SUN6I_P2WI=y CONFIG_SPI=y CONFIG_SPI_SUN4I=y CONFIG_SPI_SUN6I=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_SUPPLY=y -CONFIG_POWER_RESET=y CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_WATCHDOG=y @@ -109,7 +111,12 @@ CONFIG_RTC_CLASS=y # CONFIG_RTC_INTF_PROC is not set CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUNXI=y +CONFIG_DMADEVICES=y +CONFIG_DMA_SUN6I=y # CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON=y +CONFIG_PWM=y +CONFIG_PWM_SUN4I=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN9I_USB=y CONFIG_EXT4_FS=y @@ -123,3 +130,4 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index cdf9abb46015..9808581176cc 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -42,6 +42,7 @@ CONFIG_KEXEC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y @@ -146,7 +147,6 @@ CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y -CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_SBS=y CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y @@ -182,11 +182,10 @@ CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=y CONFIG_USB_GSPCA=y CONFIG_DRM=y +CONFIG_DRM_NOUVEAU=m CONFIG_DRM_TEGRA=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -196,14 +195,11 @@ CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_SUPPORT_OLD_API is not set # CONFIG_SND_DRIVERS is not set -CONFIG_SND_HDA=y CONFIG_SND_HDA_TEGRA=y CONFIG_SND_HDA_INPUT_BEEP=y -CONFIG_SND_HDA_INPUT_JACK=y CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_CODEC_REALTEK=y CONFIG_SND_HDA_CODEC_HDMI=y -CONFIG_SND_HDA_GENERIC=y # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set # CONFIG_SND_USB is not set @@ -300,5 +296,4 @@ CONFIG_DEBUG_SG=y CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index 932ee4e4a13a..4bc870028035 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig @@ -177,7 +177,7 @@ CONFIG_NEW_LEDS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_SA1100=y +CONFIG_RTC_DRV_PXA=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/crypto/.gitignore b/arch/arm/crypto/.gitignore index 6231d36b3635..31e1f538df7d 100644 --- a/arch/arm/crypto/.gitignore +++ b/arch/arm/crypto/.gitignore @@ -1 +1,3 @@ aesbs-core.S +sha256-core.S +sha512-core.S diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 30b3bc1666d2..be648eb47cd9 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -12,7 +12,6 @@ generic-y += irq_regs.h generic-y += kdebug.h generic-y += local.h generic-y += local64.h -generic-y += mcs_spinlock.h generic-y += mm-arch-hooks.h generic-y += msgbuf.h generic-y += param.h diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 4abe57279c66..7bbf325a4f31 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -108,33 +108,37 @@ .endm #endif - .macro asm_trace_hardirqs_off + .macro asm_trace_hardirqs_off, save=1 #if defined(CONFIG_TRACE_IRQFLAGS) + .if \save stmdb sp!, {r0-r3, ip, lr} + .endif bl trace_hardirqs_off + .if \save ldmia sp!, {r0-r3, ip, lr} + .endif #endif .endm - .macro asm_trace_hardirqs_on_cond, cond + .macro asm_trace_hardirqs_on, cond=al, save=1 #if defined(CONFIG_TRACE_IRQFLAGS) /* * actually the registers should be pushed and pop'd conditionally, but * after bl the flags are certainly clobbered */ + .if \save stmdb sp!, {r0-r3, ip, lr} + .endif bl\cond trace_hardirqs_on + .if \save ldmia sp!, {r0-r3, ip, lr} + .endif #endif .endm - .macro asm_trace_hardirqs_on - asm_trace_hardirqs_on_cond al - .endm - - .macro disable_irq + .macro disable_irq, save=1 disable_irq_notrace - asm_trace_hardirqs_off + asm_trace_hardirqs_off \save .endm .macro enable_irq @@ -173,7 +177,7 @@ .macro restore_irqs, oldcpsr tst \oldcpsr, #PSR_I_BIT - asm_trace_hardirqs_on_cond eq + asm_trace_hardirqs_on cond=eq restore_irqs_notrace \oldcpsr .endm @@ -445,6 +449,53 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #endif .endm + .macro uaccess_disable, tmp, isb=1 +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + /* + * Whenever we re-enter userspace, the domains should always be + * set appropriately. + */ + mov \tmp, #DACR_UACCESS_DISABLE + mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register + .if \isb + instr_sync + .endif +#endif + .endm + + .macro uaccess_enable, tmp, isb=1 +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + /* + * Whenever we re-enter userspace, the domains should always be + * set appropriately. + */ + mov \tmp, #DACR_UACCESS_ENABLE + mcr p15, 0, \tmp, c3, c0, 0 + .if \isb + instr_sync + .endif +#endif + .endm + + .macro uaccess_save, tmp +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + mrc p15, 0, \tmp, c3, c0, 0 + str \tmp, [sp, #S_FRAME_SIZE] +#endif + .endm + + .macro uaccess_restore +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + ldr r0, [sp, #S_FRAME_SIZE] + mcr p15, 0, r0, c3, c0, 0 +#endif + .endm + + .macro uaccess_save_and_disable, tmp + uaccess_save \tmp + uaccess_disable \tmp + .endm + .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo .macro ret\c, reg #if __LINUX_ARM_ARCH__ < 6 diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index e22c11970b7b..fe3ef397f5a4 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -57,12 +57,11 @@ static inline void atomic_##op(int i, atomic_t *v) \ } \ #define ATOMIC_OP_RETURN(op, c_op, asm_op) \ -static inline int atomic_##op##_return(int i, atomic_t *v) \ +static inline int atomic_##op##_return_relaxed(int i, atomic_t *v) \ { \ unsigned long tmp; \ int result; \ \ - smp_mb(); \ prefetchw(&v->counter); \ \ __asm__ __volatile__("@ atomic_" #op "_return\n" \ @@ -75,17 +74,17 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ : "r" (&v->counter), "Ir" (i) \ : "cc"); \ \ - smp_mb(); \ - \ return result; \ } -static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) +#define atomic_add_return_relaxed atomic_add_return_relaxed +#define atomic_sub_return_relaxed atomic_sub_return_relaxed + +static inline int atomic_cmpxchg_relaxed(atomic_t *ptr, int old, int new) { int oldval; unsigned long res; - smp_mb(); prefetchw(&ptr->counter); do { @@ -99,10 +98,9 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) : "cc"); } while (res); - smp_mb(); - return oldval; } +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed static inline int __atomic_add_unless(atomic_t *v, int a, int u) { @@ -194,6 +192,13 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) ATOMIC_OPS(add, +=, add) ATOMIC_OPS(sub, -=, sub) +#define atomic_andnot atomic_andnot + +ATOMIC_OP(and, &=, and) +ATOMIC_OP(andnot, &= ~, bic) +ATOMIC_OP(or, |=, orr) +ATOMIC_OP(xor, ^=, eor) + #undef ATOMIC_OPS #undef ATOMIC_OP_RETURN #undef ATOMIC_OP @@ -290,12 +295,12 @@ static inline void atomic64_##op(long long i, atomic64_t *v) \ } \ #define ATOMIC64_OP_RETURN(op, op1, op2) \ -static inline long long atomic64_##op##_return(long long i, atomic64_t *v) \ +static inline long long \ +atomic64_##op##_return_relaxed(long long i, atomic64_t *v) \ { \ long long result; \ unsigned long tmp; \ \ - smp_mb(); \ prefetchw(&v->counter); \ \ __asm__ __volatile__("@ atomic64_" #op "_return\n" \ @@ -309,8 +314,6 @@ static inline long long atomic64_##op##_return(long long i, atomic64_t *v) \ : "r" (&v->counter), "r" (i) \ : "cc"); \ \ - smp_mb(); \ - \ return result; \ } @@ -321,17 +324,26 @@ static inline long long atomic64_##op##_return(long long i, atomic64_t *v) \ ATOMIC64_OPS(add, adds, adc) ATOMIC64_OPS(sub, subs, sbc) +#define atomic64_add_return_relaxed atomic64_add_return_relaxed +#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed + +#define atomic64_andnot atomic64_andnot + +ATOMIC64_OP(and, and, and) +ATOMIC64_OP(andnot, bic, bic) +ATOMIC64_OP(or, orr, orr) +ATOMIC64_OP(xor, eor, eor) + #undef ATOMIC64_OPS #undef ATOMIC64_OP_RETURN #undef ATOMIC64_OP -static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old, - long long new) +static inline long long +atomic64_cmpxchg_relaxed(atomic64_t *ptr, long long old, long long new) { long long oldval; unsigned long res; - smp_mb(); prefetchw(&ptr->counter); do { @@ -346,17 +358,15 @@ static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old, : "cc"); } while (res); - smp_mb(); - return oldval; } +#define atomic64_cmpxchg_relaxed atomic64_cmpxchg_relaxed -static inline long long atomic64_xchg(atomic64_t *ptr, long long new) +static inline long long atomic64_xchg_relaxed(atomic64_t *ptr, long long new) { long long result; unsigned long tmp; - smp_mb(); prefetchw(&ptr->counter); __asm__ __volatile__("@ atomic64_xchg\n" @@ -368,10 +378,9 @@ static inline long long atomic64_xchg(atomic64_t *ptr, long long new) : "r" (&ptr->counter), "r" (new) : "cc"); - smp_mb(); - return result; } +#define atomic64_xchg_relaxed atomic64_xchg_relaxed static inline long long atomic64_dec_if_positive(atomic64_t *v) { diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 6c2327e1c732..3ff5642d9788 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -2,7 +2,6 @@ #define __ASM_BARRIER_H #ifndef __ASSEMBLY__ -#include <asm/outercache.h> #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); @@ -37,12 +36,20 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifdef CONFIG_ARM_HEAVY_MB +extern void (*soc_mb)(void); +extern void arm_heavy_mb(void); +#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0) +#else +#define __arm_heavy_mb(x...) dsb(x) +#endif + #ifdef CONFIG_ARCH_HAS_BARRIERS #include <mach/barriers.h> #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) -#define mb() do { dsb(); outer_sync(); } while (0) +#define mb() __arm_heavy_mb() #define rmb() dsb() -#define wmb() do { dsb(st); outer_sync(); } while (0) +#define wmb() __arm_heavy_mb(st) #define dma_rmb() dmb(osh) #define dma_wmb() dmb(oshst) #else @@ -67,12 +74,12 @@ do { \ compiletime_assert_atomic_type(*p); \ smp_mb(); \ - ACCESS_ONCE(*p) = (v); \ + WRITE_ONCE(*p, v); \ } while (0) #define smp_load_acquire(p) \ ({ \ - typeof(*p) ___p1 = ACCESS_ONCE(*p); \ + typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ smp_mb(); \ ___p1; \ diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 56380995f4c3..e943e6cee254 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -35,9 +35,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); *p |= mask; @@ -47,9 +47,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long * static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); *p &= ~mask; @@ -59,9 +59,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); *p ^= mask; @@ -73,9 +73,9 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; unsigned int res; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); res = *p; @@ -90,9 +90,9 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; unsigned int res; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); res = *p; @@ -107,9 +107,9 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) { unsigned long flags; unsigned int res; - unsigned long mask = 1UL << (bit & 31); + unsigned long mask = BIT_MASK(bit); - p += bit >> 5; + p += BIT_WORD(bit); raw_local_irq_save(flags); res = *p; diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 4812cda8fd17..d5525bfc7e3e 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -140,8 +140,6 @@ extern struct cpu_cache_fns cpu_cache; * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ -#define dmac_map_area cpu_cache.dma_map_area -#define dmac_unmap_area cpu_cache.dma_unmap_area #define dmac_flush_range cpu_cache.dma_flush_range #else @@ -161,8 +159,6 @@ extern void __cpuc_flush_dcache_area(void *, size_t); * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ -extern void dmac_map_area(const void *, size_t, int); -extern void dmac_unmap_area(const void *, size_t, int); extern void dmac_flush_range(const void *, const void *); #endif @@ -506,4 +502,21 @@ static inline void set_kernel_text_ro(void) { } void flush_uprobe_xol_access(struct page *page, unsigned long uaddr, void *kaddr, unsigned long len); +/** + * secure_flush_area - ensure coherency across the secure boundary + * @addr: virtual address + * @size: size of region + * + * Ensure that the specified area of memory is coherent across the secure + * boundary from the non-secure side. This is used when calling secure + * firmware where the secure firmware does not ensure coherency. + */ +static inline void secure_flush_area(const void *addr, size_t size) +{ + phys_addr_t phys = __pa(addr); + + __cpuc_flush_dcache_area((void *)addr, size); + outer_flush_range(phys, phys + size); +} + #endif diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05d3207..916a2744d5c6 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -35,7 +35,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size unsigned int tmp; #endif - smp_mb(); prefetchw((const void *)ptr); switch (size) { @@ -98,12 +97,11 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size __bad_xchg(ptr, size), ret = 0; break; } - smp_mb(); return ret; } -#define xchg(ptr, x) ({ \ +#define xchg_relaxed(ptr, x) ({ \ (__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \ sizeof(*(ptr))); \ }) @@ -117,6 +115,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size #error "SMP is not supported on this platform" #endif +#define xchg xchg_relaxed + /* * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make * them available. @@ -194,23 +194,11 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, return oldval; } -static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old, - unsigned long new, int size) -{ - unsigned long ret; - - smp_mb(); - ret = __cmpxchg(ptr, old, new, size); - smp_mb(); - - return ret; -} - -#define cmpxchg(ptr,o,n) ({ \ - (__typeof__(*(ptr)))__cmpxchg_mb((ptr), \ - (unsigned long)(o), \ - (unsigned long)(n), \ - sizeof(*(ptr))); \ +#define cmpxchg_relaxed(ptr,o,n) ({ \ + (__typeof__(*(ptr)))__cmpxchg((ptr), \ + (unsigned long)(o), \ + (unsigned long)(n), \ + sizeof(*(ptr))); \ }) static inline unsigned long __cmpxchg_local(volatile void *ptr, @@ -273,25 +261,6 @@ static inline unsigned long long __cmpxchg64(unsigned long long *ptr, #define cmpxchg64_local(ptr, o, n) cmpxchg64_relaxed((ptr), (o), (n)) -static inline unsigned long long __cmpxchg64_mb(unsigned long long *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long ret; - - smp_mb(); - ret = __cmpxchg64(ptr, old, new); - smp_mb(); - - return ret; -} - -#define cmpxchg64(ptr, o, n) ({ \ - (__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n)); \ -}) - #endif /* __LINUX_ARM_ARCH__ >= 6 */ #endif /* __ASM_ARM_CMPXCHG_H */ diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index b52101d37ec7..ccb3aa64640d 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -8,13 +8,12 @@ #include <linux/dma-attrs.h> #include <linux/dma-debug.h> -#include <asm-generic/dma-coherent.h> #include <asm/memory.h> #include <xen/xen.h> #include <asm/xen/hypervisor.h> -#define DMA_ERROR_CODE (~0) +#define DMA_ERROR_CODE (~(dma_addr_t)0x0) extern struct dma_map_ops arm_dma_ops; extern struct dma_map_ops arm_coherent_dma_ops; @@ -39,12 +38,15 @@ static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) dev->archdata.dma_ops = ops; } -#include <asm-generic/dma-mapping-common.h> +#define HAVE_ARCH_DMA_SUPPORTED 1 +extern int dma_supported(struct device *dev, u64 mask); -static inline int dma_set_mask(struct device *dev, u64 mask) -{ - return get_dma_ops(dev)->set_dma_mask(dev, mask); -} +/* + * Note that while the generic code provides dummy dma_{alloc,free}_noncoherent + * implementations, we don't provide a dma_cache_sync function so drivers using + * this API are highlighted with build warnings. + */ +#include <asm-generic/dma-mapping-common.h> #ifdef __arch_page_to_dma #error Please update to __arch_pfn_to_dma @@ -167,32 +169,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) static inline void dma_mark_clean(void *addr, size_t size) { } -/* - * DMA errors are defined by all-bits-set in the DMA address. - */ -static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) -{ - debug_dma_mapping_error(dev, dma_addr); - return dma_addr == DMA_ERROR_CODE; -} - -/* - * Dummy noncoherent implementation. We don't provide a dma_cache_sync - * function so drivers using this API are highlighted with build warnings. - */ -static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t *handle, gfp_t gfp) -{ - return NULL; -} - -static inline void dma_free_noncoherent(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t handle) -{ -} - -extern int dma_supported(struct device *dev, u64 mask); - extern int arm_dma_set_mask(struct device *dev, u64 dma_mask); /** @@ -209,21 +185,6 @@ extern int arm_dma_set_mask(struct device *dev, u64 dma_mask); extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); -#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL) - -static inline void *dma_alloc_attrs(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag, - struct dma_attrs *attrs) -{ - struct dma_map_ops *ops = get_dma_ops(dev); - void *cpu_addr; - BUG_ON(!ops); - - cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); - debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); - return cpu_addr; -} - /** * arm_dma_free - free memory allocated by arm_dma_alloc * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices @@ -241,19 +202,6 @@ static inline void *dma_alloc_attrs(struct device *dev, size_t size, extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle, struct dma_attrs *attrs); -#define dma_free_coherent(d, s, c, h) dma_free_attrs(d, s, c, h, NULL) - -static inline void dma_free_attrs(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t dma_handle, - struct dma_attrs *attrs) -{ - struct dma_map_ops *ops = get_dma_ops(dev); - BUG_ON(!ops); - - debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); - ops->free(dev, size, cpu_addr, dma_handle, attrs); -} - /** * arm_dma_mmap - map a coherent DMA allocation into user space * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h index 6ddbe446425e..e878129f2fee 100644 --- a/arch/arm/include/asm/domain.h +++ b/arch/arm/include/asm/domain.h @@ -34,15 +34,14 @@ */ #ifndef CONFIG_IO_36 #define DOMAIN_KERNEL 0 -#define DOMAIN_TABLE 0 #define DOMAIN_USER 1 #define DOMAIN_IO 2 #else #define DOMAIN_KERNEL 2 -#define DOMAIN_TABLE 2 #define DOMAIN_USER 1 #define DOMAIN_IO 0 #endif +#define DOMAIN_VECTORS 3 /* * Domain types @@ -55,11 +54,46 @@ #define DOMAIN_MANAGER 1 #endif -#define domain_val(dom,type) ((type) << (2*(dom))) +#define domain_mask(dom) ((3) << (2 * (dom))) +#define domain_val(dom,type) ((type) << (2 * (dom))) + +#ifdef CONFIG_CPU_SW_DOMAIN_PAN +#define DACR_INIT \ + (domain_val(DOMAIN_USER, DOMAIN_NOACCESS) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)) +#else +#define DACR_INIT \ + (domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)) +#endif + +#define __DACR_DEFAULT \ + domain_val(DOMAIN_KERNEL, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT) + +#define DACR_UACCESS_DISABLE \ + (__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_NOACCESS)) +#define DACR_UACCESS_ENABLE \ + (__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_CLIENT)) #ifndef __ASSEMBLY__ -#ifdef CONFIG_CPU_USE_DOMAINS +static inline unsigned int get_domain(void) +{ + unsigned int domain; + + asm( + "mrc p15, 0, %0, c3, c0 @ get domain" + : "=r" (domain)); + + return domain; +} + static inline void set_domain(unsigned val) { asm volatile( @@ -68,17 +102,16 @@ static inline void set_domain(unsigned val) isb(); } +#ifdef CONFIG_CPU_USE_DOMAINS #define modify_domain(dom,type) \ do { \ - struct thread_info *thread = current_thread_info(); \ - unsigned int domain = thread->cpu_domain; \ - domain &= ~domain_val(dom, DOMAIN_MANAGER); \ - thread->cpu_domain = domain | domain_val(dom, type); \ - set_domain(thread->cpu_domain); \ + unsigned int domain = get_domain(); \ + domain &= ~domain_mask(dom); \ + domain = domain | domain_val(dom, type); \ + set_domain(domain); \ } while (0) #else -static inline void set_domain(unsigned val) { } static inline void modify_domain(unsigned dom, unsigned type) { } #endif diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index 0415eae1df27..58cfe9f1a687 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -6,9 +6,13 @@ #define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE) #include <asm/kmap_types.h> +#include <asm/pgtable.h> enum fixed_addresses { - FIX_KMAP_BEGIN, + FIX_EARLYCON_MEM_BASE, + __end_of_permanent_fixed_addresses, + + FIX_KMAP_BEGIN = __end_of_permanent_fixed_addresses, FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1, /* Support writing RO kernel text via kprobes, jump labels, etc. */ @@ -18,7 +22,16 @@ enum fixed_addresses { __end_of_fixed_addresses }; +#define FIXMAP_PAGE_COMMON (L_PTE_YOUNG | L_PTE_PRESENT | L_PTE_XN | L_PTE_DIRTY) + +#define FIXMAP_PAGE_NORMAL (FIXMAP_PAGE_COMMON | L_PTE_MT_WRITEBACK) + +/* Used by set_fixmap_(io|nocache), both meant for mapping a device */ +#define FIXMAP_PAGE_IO (FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED) +#define FIXMAP_PAGE_NOCACHE FIXMAP_PAGE_IO + void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot); +void __init early_fixmap_init(void); #include <asm-generic/fixmap.h> diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index 5eed82809d82..6795368ad023 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h @@ -22,8 +22,11 @@ #ifdef CONFIG_SMP #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ +({ \ + unsigned int __ua_flags; \ smp_mb(); \ prefetchw(uaddr); \ + __ua_flags = uaccess_save_and_enable(); \ __asm__ __volatile__( \ "1: ldrex %1, [%3]\n" \ " " insn "\n" \ @@ -34,12 +37,15 @@ __futex_atomic_ex_table("%5") \ : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ - : "cc", "memory") + : "cc", "memory"); \ + uaccess_restore(__ua_flags); \ +}) static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { + unsigned int __ua_flags; int ret; u32 val; @@ -49,6 +55,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, smp_mb(); /* Prefetching cannot fault */ prefetchw(uaddr); + __ua_flags = uaccess_save_and_enable(); __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" "1: ldrex %1, [%4]\n" " teq %1, %2\n" @@ -61,6 +68,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, : "=&r" (ret), "=&r" (val) : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) : "cc", "memory"); + uaccess_restore(__ua_flags); smp_mb(); *uval = val; @@ -73,6 +81,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, #include <asm/domain.h> #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ +({ \ + unsigned int __ua_flags = uaccess_save_and_enable(); \ __asm__ __volatile__( \ "1: " TUSER(ldr) " %1, [%3]\n" \ " " insn "\n" \ @@ -81,12 +91,15 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, __futex_atomic_ex_table("%5") \ : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ - : "cc", "memory") + : "cc", "memory"); \ + uaccess_restore(__ua_flags); \ +}) static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { + unsigned int __ua_flags; int ret = 0; u32 val; @@ -94,6 +107,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, return -EFAULT; preempt_disable(); + __ua_flags = uaccess_save_and_enable(); __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" "1: " TUSER(ldr) " %1, [%4]\n" " teq %1, %2\n" @@ -103,6 +117,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, : "+r" (ret), "=&r" (val) : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) : "cc", "memory"); + uaccess_restore(__ua_flags); *uval = val; preempt_enable(); diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index a3c24cd5b7c8..cab07f69382d 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -158,8 +158,6 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) -#define dmac_map_area __glue(_CACHE,_dma_map_area) -#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) #endif diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 53c15dec7af6..be1d07d59ee9 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -35,6 +35,11 @@ extern void (*handle_arch_irq)(struct pt_regs *); extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); #endif +#ifdef CONFIG_SMP +extern void arch_trigger_all_cpu_backtrace(bool); +#define arch_trigger_all_cpu_backtrace(x) arch_trigger_all_cpu_backtrace(x) +#endif + #endif #endif diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h index 5f337dc5c108..34f7b6980d21 100644 --- a/arch/arm/include/asm/jump_label.h +++ b/arch/arm/include/asm/jump_label.h @@ -4,23 +4,32 @@ #ifndef __ASSEMBLY__ #include <linux/types.h> +#include <asm/unified.h> #define JUMP_LABEL_NOP_SIZE 4 -#ifdef CONFIG_THUMB2_KERNEL -#define JUMP_LABEL_NOP "nop.w" -#else -#define JUMP_LABEL_NOP "nop" -#endif +static __always_inline bool arch_static_branch(struct static_key *key, bool branch) +{ + asm_volatile_goto("1:\n\t" + WASM(nop) "\n\t" + ".pushsection __jump_table, \"aw\"\n\t" + ".word 1b, %l[l_yes], %c0\n\t" + ".popsection\n\t" + : : "i" (&((char *)key)[branch]) : : l_yes); + + return false; +l_yes: + return true; +} -static __always_inline bool arch_static_branch(struct static_key *key) +static __always_inline bool arch_static_branch_jump(struct static_key *key, bool branch) { asm_volatile_goto("1:\n\t" - JUMP_LABEL_NOP "\n\t" + WASM(b) " %l[l_yes]\n\t" ".pushsection __jump_table, \"aw\"\n\t" ".word 1b, %l[l_yes], %c0\n\t" ".popsection\n\t" - : : "i" (key) : : l_yes); + : : "i" (&((char *)key)[branch]) : : l_yes); return false; l_yes: diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index e896d2c196e6..dcba0fa5176e 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -231,4 +231,9 @@ static inline void kvm_arch_sync_events(struct kvm *kvm) {} static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} +static inline void kvm_arm_init_debug(void) {} +static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {} +static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {} +static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {} + #endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 28b9bb35949e..8857d2869a5f 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -19,9 +19,7 @@ struct pci_bus; struct device; struct hw_pci { -#ifdef CONFIG_PCI_MSI struct msi_controller *msi_ctrl; -#endif struct pci_ops *ops; int nr_controllers; void **private_data; @@ -42,9 +40,6 @@ struct hw_pci { * Per-controller structure */ struct pci_sys_data { -#ifdef CONFIG_PCI_MSI - struct msi_controller *msi_ctrl; -#endif struct list_head node; int busnr; /* primary bus number */ u64 mem_offset; /* bus->cpu memory mapping offset */ diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index b7f6fb462ea0..98d58bb04ac5 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -119,12 +119,6 @@ #endif /* - * Convert a physical address to a Page Frame Number and back - */ -#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT)) -#define __pfn_to_phys(pfn) ((phys_addr_t)(pfn) << PAGE_SHIFT) - -/* * Convert a page to/from a physical address */ #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 563b92fc2f41..c2bf24f40177 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -129,21 +129,4 @@ static inline void outer_resume(void) { } #endif -#ifdef CONFIG_OUTER_CACHE_SYNC -/** - * outer_sync - perform a sync point for outer cache - * - * Ensure that all outer cache operations are complete and any store - * buffers are drained. - */ -static inline void outer_sync(void) -{ - if (outer_cache.sync) - outer_cache.sync(); -} -#else -static inline void outer_sync(void) -{ } -#endif - #endif /* __ASM_OUTERCACHE_H */ diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h index 5e68278e953e..d0131ee6f6af 100644 --- a/arch/arm/include/asm/pgtable-2level-hwdef.h +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h @@ -23,6 +23,7 @@ #define PMD_PXNTABLE (_AT(pmdval_t, 1) << 2) /* v7 */ #define PMD_BIT4 (_AT(pmdval_t, 1) << 4) #define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5) +#define PMD_DOMAIN_MASK PMD_DOMAIN(0x0f) #define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */ /* * - section diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h deleted file mode 100644 index 3fc87dfd77e6..000000000000 --- a/arch/arm/include/asm/pmu.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * linux/arch/arm/include/asm/pmu.h - * - * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __ARM_PMU_H__ -#define __ARM_PMU_H__ - -#include <linux/interrupt.h> -#include <linux/perf_event.h> - -#include <asm/cputype.h> - -/* - * struct arm_pmu_platdata - ARM PMU platform data - * - * @handle_irq: an optional handler which will be called from the - * interrupt and passed the address of the low level handler, - * and can be used to implement any platform specific handling - * before or after calling it. - */ -struct arm_pmu_platdata { - irqreturn_t (*handle_irq)(int irq, void *dev, - irq_handler_t pmu_handler); -}; - -#ifdef CONFIG_HW_PERF_EVENTS - -/* - * The ARMv7 CPU PMU supports up to 32 event counters. - */ -#define ARMPMU_MAX_HWEVENTS 32 - -#define HW_OP_UNSUPPORTED 0xFFFF -#define C(_x) PERF_COUNT_HW_CACHE_##_x -#define CACHE_OP_UNSUPPORTED 0xFFFF - -#define PERF_MAP_ALL_UNSUPPORTED \ - [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED - -#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ -[0 ... C(MAX) - 1] = { \ - [0 ... C(OP_MAX) - 1] = { \ - [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ - }, \ -} - -/* The events for a given PMU register set. */ -struct pmu_hw_events { - /* - * The events that are active on the PMU for the given index. - */ - struct perf_event *events[ARMPMU_MAX_HWEVENTS]; - - /* - * A 1 bit for an index indicates that the counter is being used for - * an event. A 0 means that the counter can be used. - */ - DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); - - /* - * Hardware lock to serialize accesses to PMU registers. Needed for the - * read/modify/write sequences. - */ - raw_spinlock_t pmu_lock; - - /* - * When using percpu IRQs, we need a percpu dev_id. Place it here as we - * already have to allocate this struct per cpu. - */ - struct arm_pmu *percpu_pmu; -}; - -struct arm_pmu { - struct pmu pmu; - cpumask_t active_irqs; - cpumask_t supported_cpus; - int *irq_affinity; - char *name; - irqreturn_t (*handle_irq)(int irq_num, void *dev); - void (*enable)(struct perf_event *event); - void (*disable)(struct perf_event *event); - int (*get_event_idx)(struct pmu_hw_events *hw_events, - struct perf_event *event); - void (*clear_event_idx)(struct pmu_hw_events *hw_events, - struct perf_event *event); - int (*set_event_filter)(struct hw_perf_event *evt, - struct perf_event_attr *attr); - u32 (*read_counter)(struct perf_event *event); - void (*write_counter)(struct perf_event *event, u32 val); - void (*start)(struct arm_pmu *); - void (*stop)(struct arm_pmu *); - void (*reset)(void *); - int (*request_irq)(struct arm_pmu *, irq_handler_t handler); - void (*free_irq)(struct arm_pmu *); - int (*map_event)(struct perf_event *event); - int num_events; - atomic_t active_events; - struct mutex reserve_mutex; - u64 max_period; - struct platform_device *plat_device; - struct pmu_hw_events __percpu *hw_events; - struct notifier_block hotplug_nb; -}; - -#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) - -int armpmu_register(struct arm_pmu *armpmu, int type); - -u64 armpmu_event_update(struct perf_event *event); - -int armpmu_event_set_period(struct perf_event *event); - -int armpmu_map_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask); - -struct pmu_probe_info { - unsigned int cpuid; - unsigned int mask; - int (*init)(struct arm_pmu *); -}; - -#define PMU_PROBE(_cpuid, _mask, _fn) \ -{ \ - .cpuid = (_cpuid), \ - .mask = (_mask), \ - .init = (_fn), \ -} - -#define ARM_PMU_PROBE(_cpuid, _fn) \ - PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn) - -#define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK) - -#define XSCALE_PMU_PROBE(_version, _fn) \ - PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn) - -int arm_pmu_device_probe(struct platform_device *pdev, - const struct of_device_id *of_table, - const struct pmu_probe_info *probe_table); - -#endif /* CONFIG_HW_PERF_EVENTS */ - -#endif /* __ARM_PMU_H__ */ diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index c25ef3ec6d1f..68ee3ce17b82 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -14,34 +14,11 @@ #ifndef __ASM_ARM_PSCI_H #define __ASM_ARM_PSCI_H -#define PSCI_POWER_STATE_TYPE_STANDBY 0 -#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1 - -struct psci_power_state { - u16 id; - u8 type; - u8 affinity_level; -}; - -struct psci_operations { - int (*cpu_suspend)(struct psci_power_state state, - unsigned long entry_point); - int (*cpu_off)(struct psci_power_state state); - int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); - int (*migrate)(unsigned long cpuid); - int (*affinity_info)(unsigned long target_affinity, - unsigned long lowest_affinity_level); - int (*migrate_info_type)(void); -}; - -extern struct psci_operations psci_ops; extern struct smp_operations psci_smp_ops; #ifdef CONFIG_ARM_PSCI -int psci_init(void); bool psci_smp_available(void); #else -static inline int psci_init(void) { return 0; } static inline bool psci_smp_available(void) { return false; } #endif diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 2f3ac1ba6fb4..ef356659b4f4 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -74,7 +74,6 @@ extern void secondary_startup_arm(void); extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); -extern void cpu_die(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); @@ -105,6 +104,7 @@ struct smp_operations { #ifdef CONFIG_HOTPLUG_CPU int (*cpu_kill)(unsigned int cpu); void (*cpu_die)(unsigned int cpu); + bool (*cpu_can_disable)(unsigned int cpu); int (*cpu_disable)(unsigned int cpu); #endif #endif diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index 993e5224d8f7..f9080717fc88 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -107,4 +107,13 @@ static inline u32 mpidr_hash_size(void) extern int platform_can_secondary_boot(void); extern int platform_can_cpu_hotplug(void); +#ifdef CONFIG_HOTPLUG_CPU +extern int platform_can_hotplug_cpu(unsigned int cpu); +#else +static inline int platform_can_hotplug_cpu(unsigned int cpu) +{ + return 0; +} +#endif + #endif diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index c99e259469f7..12ebfcc1d539 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -10,7 +10,9 @@ * CPU. */ #if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) -#define finish_arch_switch(prev) dsb(ish) +#define __complete_pending_tlbi() dsb(ish) +#else +#define __complete_pending_tlbi() #endif /* @@ -22,6 +24,7 @@ extern struct task_struct *__switch_to(struct task_struct *, struct thread_info #define switch_to(prev,next,last) \ do { \ + __complete_pending_tlbi(); \ last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ } while (0) diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index bd32eded3e50..d0a1119dcaf3 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -74,9 +74,6 @@ struct thread_info { .flags = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ .addr_limit = KERNEL_DS, \ - .cpu_domain = domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_IO, DOMAIN_CLIENT), \ } #define init_thread_info (init_thread_union.thread_info) @@ -136,22 +133,18 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *, /* * thread information flags: - * TIF_SYSCALL_TRACE - syscall trace active - * TIF_SYSCAL_AUDIT - syscall auditing active - * TIF_SIGPENDING - signal pending - * TIF_NEED_RESCHED - rescheduling necessary - * TIF_NOTIFY_RESUME - callback before returning to user * TIF_USEDFPU - FPU was used by this task this quantum (SMP) * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_SIGPENDING 0 -#define TIF_NEED_RESCHED 1 +#define TIF_SIGPENDING 0 /* signal pending */ +#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ -#define TIF_UPROBE 7 -#define TIF_SYSCALL_TRACE 8 -#define TIF_SYSCALL_AUDIT 9 -#define TIF_SYSCALL_TRACEPOINT 10 -#define TIF_SECCOMP 11 /* seccomp syscall filtering active */ +#define TIF_UPROBE 3 /* breakpointed or singlestepping */ +#define TIF_SYSCALL_TRACE 4 /* syscall trace active */ +#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ +#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ +#define TIF_SECCOMP 7 /* seccomp syscall filtering active */ + #define TIF_NOHZ 12 /* in adaptive nohz mode */ #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 74b17d09ef7a..8cc85a4ebec2 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -50,6 +50,35 @@ struct exception_table_entry extern int fixup_exception(struct pt_regs *regs); /* + * These two functions allow hooking accesses to userspace to increase + * system integrity by ensuring that the kernel can not inadvertantly + * perform such accesses (eg, via list poison values) which could then + * be exploited for priviledge escalation. + */ +static inline unsigned int uaccess_save_and_enable(void) +{ +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + unsigned int old_domain = get_domain(); + + /* Set the current domain access to permit user accesses */ + set_domain((old_domain & ~domain_mask(DOMAIN_USER)) | + domain_val(DOMAIN_USER, DOMAIN_CLIENT)); + + return old_domain; +#else + return 0; +#endif +} + +static inline void uaccess_restore(unsigned int flags) +{ +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + /* Restore the user access mask */ + set_domain(flags); +#endif +} + +/* * These two are intentionally not defined anywhere - if the kernel * code generates any references to them, that's a bug. */ @@ -165,6 +194,7 @@ extern int __get_user_64t_4(void *); register typeof(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ + unsigned int __ua_flags = uaccess_save_and_enable(); \ switch (sizeof(*(__p))) { \ case 1: \ if (sizeof((x)) >= 8) \ @@ -192,6 +222,7 @@ extern int __get_user_64t_4(void *); break; \ default: __e = __get_user_bad(); break; \ } \ + uaccess_restore(__ua_flags); \ x = (typeof(*(p))) __r2; \ __e; \ }) @@ -224,6 +255,7 @@ extern int __put_user_8(void *, unsigned long long); register const typeof(*(p)) __user *__p asm("r0") = __tmp_p; \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ + unsigned int __ua_flags = uaccess_save_and_enable(); \ switch (sizeof(*(__p))) { \ case 1: \ __put_user_x(__r2, __p, __e, __l, 1); \ @@ -239,6 +271,7 @@ extern int __put_user_8(void *, unsigned long long); break; \ default: __e = __put_user_bad(); break; \ } \ + uaccess_restore(__ua_flags); \ __e; \ }) @@ -300,20 +333,23 @@ static inline void set_fs(mm_segment_t fs) do { \ unsigned long __gu_addr = (unsigned long)(ptr); \ unsigned long __gu_val; \ + unsigned int __ua_flags; \ __chk_user_ptr(ptr); \ might_fault(); \ + __ua_flags = uaccess_save_and_enable(); \ switch (sizeof(*(ptr))) { \ case 1: __get_user_asm_byte(__gu_val, __gu_addr, err); break; \ case 2: __get_user_asm_half(__gu_val, __gu_addr, err); break; \ case 4: __get_user_asm_word(__gu_val, __gu_addr, err); break; \ default: (__gu_val) = __get_user_bad(); \ } \ + uaccess_restore(__ua_flags); \ (x) = (__typeof__(*(ptr)))__gu_val; \ } while (0) -#define __get_user_asm_byte(x, addr, err) \ +#define __get_user_asm(x, addr, err, instr) \ __asm__ __volatile__( \ - "1: " TUSER(ldrb) " %1,[%2],#0\n" \ + "1: " TUSER(instr) " %1, [%2], #0\n" \ "2:\n" \ " .pushsection .text.fixup,\"ax\"\n" \ " .align 2\n" \ @@ -329,6 +365,9 @@ do { \ : "r" (addr), "i" (-EFAULT) \ : "cc") +#define __get_user_asm_byte(x, addr, err) \ + __get_user_asm(x, addr, err, ldrb) + #ifndef __ARMEB__ #define __get_user_asm_half(x, __gu_addr, err) \ ({ \ @@ -348,22 +387,7 @@ do { \ #endif #define __get_user_asm_word(x, addr, err) \ - __asm__ __volatile__( \ - "1: " TUSER(ldr) " %1,[%2],#0\n" \ - "2:\n" \ - " .pushsection .text.fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: mov %0, %3\n" \ - " mov %1, #0\n" \ - " b 2b\n" \ - " .popsection\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .popsection" \ - : "+r" (err), "=&r" (x) \ - : "r" (addr), "i" (-EFAULT) \ - : "cc") + __get_user_asm(x, addr, err, ldr) #define __put_user(x, ptr) \ ({ \ @@ -381,9 +405,11 @@ do { \ #define __put_user_err(x, ptr, err) \ do { \ unsigned long __pu_addr = (unsigned long)(ptr); \ + unsigned int __ua_flags; \ __typeof__(*(ptr)) __pu_val = (x); \ __chk_user_ptr(ptr); \ might_fault(); \ + __ua_flags = uaccess_save_and_enable(); \ switch (sizeof(*(ptr))) { \ case 1: __put_user_asm_byte(__pu_val, __pu_addr, err); break; \ case 2: __put_user_asm_half(__pu_val, __pu_addr, err); break; \ @@ -391,11 +417,12 @@ do { \ case 8: __put_user_asm_dword(__pu_val, __pu_addr, err); break; \ default: __put_user_bad(); \ } \ + uaccess_restore(__ua_flags); \ } while (0) -#define __put_user_asm_byte(x, __pu_addr, err) \ +#define __put_user_asm(x, __pu_addr, err, instr) \ __asm__ __volatile__( \ - "1: " TUSER(strb) " %1,[%2],#0\n" \ + "1: " TUSER(instr) " %1, [%2], #0\n" \ "2:\n" \ " .pushsection .text.fixup,\"ax\"\n" \ " .align 2\n" \ @@ -410,6 +437,9 @@ do { \ : "r" (x), "r" (__pu_addr), "i" (-EFAULT) \ : "cc") +#define __put_user_asm_byte(x, __pu_addr, err) \ + __put_user_asm(x, __pu_addr, err, strb) + #ifndef __ARMEB__ #define __put_user_asm_half(x, __pu_addr, err) \ ({ \ @@ -427,21 +457,7 @@ do { \ #endif #define __put_user_asm_word(x, __pu_addr, err) \ - __asm__ __volatile__( \ - "1: " TUSER(str) " %1,[%2],#0\n" \ - "2:\n" \ - " .pushsection .text.fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: mov %0, %3\n" \ - " b 2b\n" \ - " .popsection\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .popsection" \ - : "+r" (err) \ - : "r" (x), "r" (__pu_addr), "i" (-EFAULT) \ - : "cc") + __put_user_asm(x, __pu_addr, err, str) #ifndef __ARMEB__ #define __reg_oper0 "%R2" @@ -474,11 +490,46 @@ do { \ #ifdef CONFIG_MMU -extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n); -extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); -extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned long n); +extern unsigned long __must_check +arm_copy_from_user(void *to, const void __user *from, unsigned long n); + +static inline unsigned long __must_check +__copy_from_user(void *to, const void __user *from, unsigned long n) +{ + unsigned int __ua_flags = uaccess_save_and_enable(); + n = arm_copy_from_user(to, from, n); + uaccess_restore(__ua_flags); + return n; +} + +extern unsigned long __must_check +arm_copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check +__copy_to_user_std(void __user *to, const void *from, unsigned long n); + +static inline unsigned long __must_check +__copy_to_user(void __user *to, const void *from, unsigned long n) +{ + unsigned int __ua_flags = uaccess_save_and_enable(); + n = arm_copy_to_user(to, from, n); + uaccess_restore(__ua_flags); + return n; +} + +extern unsigned long __must_check +arm_clear_user(void __user *addr, unsigned long n); +extern unsigned long __must_check +__clear_user_std(void __user *addr, unsigned long n); + +static inline unsigned long __must_check +__clear_user(void __user *addr, unsigned long n) +{ + unsigned int __ua_flags = uaccess_save_and_enable(); + n = arm_clear_user(addr, n); + uaccess_restore(__ua_flags); + return n; +} + #else #define __copy_from_user(to, from, n) (memcpy(to, (void __force *)from, n), 0) #define __copy_to_user(to, from, n) (memcpy((void __force *)to, from, n), 0) @@ -511,6 +562,7 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo return n; } +/* These are from lib/ code, and use __get_user() and friends */ extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strlen_user(const char __user *str); diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h index 8b1f37bfeeec..71e473d05fcc 100644 --- a/arch/arm/include/asm/xen/events.h +++ b/arch/arm/include/asm/xen/events.h @@ -20,4 +20,10 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) atomic64_t, \ counter), (val)) +/* Rebind event channel is supported by default */ +static inline bool xen_support_evtchn_rebind(void) +{ + return true; +} + #endif /* _ASM_ARM_XEN_EVENTS_H */ diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h index 1bee8ca12494..127956353b00 100644 --- a/arch/arm/include/asm/xen/page.h +++ b/arch/arm/include/asm/xen/page.h @@ -34,7 +34,19 @@ typedef struct xpaddr { unsigned long __pfn_to_mfn(unsigned long pfn); extern struct rb_root phys_to_mach; -static inline unsigned long pfn_to_mfn(unsigned long pfn) +/* Pseudo-physical <-> Guest conversion */ +static inline unsigned long pfn_to_gfn(unsigned long pfn) +{ + return pfn; +} + +static inline unsigned long gfn_to_pfn(unsigned long gfn) +{ + return gfn; +} + +/* Pseudo-physical <-> BUS conversion */ +static inline unsigned long pfn_to_bfn(unsigned long pfn) { unsigned long mfn; @@ -47,33 +59,21 @@ static inline unsigned long pfn_to_mfn(unsigned long pfn) return pfn; } -static inline unsigned long mfn_to_pfn(unsigned long mfn) +static inline unsigned long bfn_to_pfn(unsigned long bfn) { - return mfn; + return bfn; } -#define mfn_to_local_pfn(mfn) mfn_to_pfn(mfn) +#define bfn_to_local_pfn(bfn) bfn_to_pfn(bfn) -static inline xmaddr_t phys_to_machine(xpaddr_t phys) -{ - unsigned offset = phys.paddr & ~PAGE_MASK; - return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset); -} - -static inline xpaddr_t machine_to_phys(xmaddr_t machine) -{ - unsigned offset = machine.maddr & ~PAGE_MASK; - return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset); -} -/* VIRT <-> MACHINE conversion */ -#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) -#define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v))) -#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) +/* VIRT <-> GUEST conversion */ +#define virt_to_gfn(v) (pfn_to_gfn(virt_to_pfn(v))) +#define gfn_to_virt(m) (__va(gfn_to_pfn(m) << PAGE_SHIFT)) +/* Only used in PV code. But ARM guests are always HVM. */ static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr) { - /* TODO: assuming it is mapped in the kernel 1:1 */ - return virt_to_machine(vaddr); + BUG(); } /* TODO: this shouldn't be here but it is because the frontend drivers @@ -108,7 +108,7 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn) bool xen_arch_need_swiotlb(struct device *dev, unsigned long pfn, - unsigned long mfn); + unsigned long bfn); unsigned long xen_get_swiotlb_free_pages(unsigned int order); #endif /* _ASM_ARM_XEN_PAGE_H */ diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S index c3c45e628e33..2556a8801c8c 100644 --- a/arch/arm/include/debug/at91.S +++ b/arch/arm/include/debug/at91.S @@ -13,9 +13,12 @@ #define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */ #elif defined(CONFIG_AT91_DEBUG_LL_DBGU1) #define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */ -#else +#elif defined(CONFIG_AT91_DEBUG_LL_DBGU2) /* On sama5d4, use USART3 as low level serial console */ #define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ +#else +/* On sama5d2, use UART1 as low level serial console */ +#define AT91_DBGU 0xf8020000 #endif #ifdef CONFIG_MMU diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index 66f736f74684..bce58e975ad1 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -90,6 +90,17 @@ #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) +#define IMX6UL_UART1_BASE_ADDR 0x02020000 +#define IMX6UL_UART2_BASE_ADDR 0x021e8000 +#define IMX6UL_UART3_BASE_ADDR 0x021ec000 +#define IMX6UL_UART4_BASE_ADDR 0x021f0000 +#define IMX6UL_UART5_BASE_ADDR 0x021f4000 +#define IMX6UL_UART6_BASE_ADDR 0x021fc000 +#define IMX6UL_UART7_BASE_ADDR 0x02018000 +#define IMX6UL_UART8_BASE_ADDR 0x02024000 +#define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR +#define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n) + #define IMX7D_UART1_BASE_ADDR 0x30860000 #define IMX7D_UART2_BASE_ADDR 0x30890000 #define IMX7D_UART3_BASE_ADDR 0x30880000 @@ -124,6 +135,8 @@ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) #elif defined(CONFIG_DEBUG_IMX6SX_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) +#elif defined(CONFIG_DEBUG_IMX6UL_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL) #elif defined(CONFIG_DEBUG_IMX7D_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S index bd13dedbdeff..de86b9247564 100644 --- a/arch/arm/include/debug/zynq.S +++ b/arch/arm/include/debug/zynq.S @@ -38,7 +38,7 @@ .endm .macro senduart,rd,rx - str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA .endm .macro waituart,rd,rx diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index e69f7a19735d..af9e59bf3831 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -71,8 +71,7 @@ obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o \ - perf_event_xscale.o perf_event_v6.o \ +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_xscale.o perf_event_v6.o \ perf_event_v7.o CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt @@ -89,7 +88,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o ifeq ($(CONFIG_ARM_PSCI),y) -obj-y += psci.o psci-call.o +obj-y += psci-call.o obj-$(CONFIG_SMP) += psci_smp.o endif diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 5e5a51a99e68..f89811fb9a55 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -97,9 +97,9 @@ EXPORT_SYMBOL(mmiocpy); #ifdef CONFIG_MMU EXPORT_SYMBOL(copy_page); -EXPORT_SYMBOL(__copy_from_user); -EXPORT_SYMBOL(__copy_to_user); -EXPORT_SYMBOL(__clear_user); +EXPORT_SYMBOL(arm_copy_from_user); +EXPORT_SYMBOL(arm_copy_to_user); +EXPORT_SYMBOL(arm_clear_user); EXPORT_SYMBOL(__get_user_1); EXPORT_SYMBOL(__get_user_2); diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index fcbbbb1b9e95..874e1823f803 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -18,15 +18,6 @@ static int debug_pci; -#ifdef CONFIG_PCI_MSI -struct msi_controller *pcibios_msi_controller(struct pci_dev *dev) -{ - struct pci_sys_data *sysdata = dev->bus->sysdata; - - return sysdata->msi_ctrl; -} -#endif - /* * We can't use pci_get_device() here since we are * called from interrupt context. @@ -459,12 +450,9 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); - if (!sys) - panic("PCI: unable to allocate sys data!"); + if (WARN(!sys, "PCI: unable to allocate sys data!")) + break; -#ifdef CONFIG_PCI_MSI - sys->msi_ctrl = hw->msi_ctrl; -#endif sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; @@ -486,11 +474,14 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, if (hw->scan) sys->bus = hw->scan(nr, sys); else - sys->bus = pci_scan_root_bus(parent, sys->busnr, - hw->ops, sys, &sys->resources); + sys->bus = pci_scan_root_bus_msi(parent, + sys->busnr, hw->ops, sys, + &sys->resources, hw->msi_ctrl); - if (!sys->bus) - panic("PCI: unable to scan bus!"); + if (WARN(!sys->bus, "PCI: unable to scan bus!")) { + kfree(sys); + break; + } busnr = sys->bus->busn_res.end + 1; @@ -521,6 +512,8 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) struct pci_bus *bus = sys->bus; if (!pci_has_flag(PCI_PROBE_ONLY)) { + struct pci_bus *child; + /* * Size the bridge windows. */ @@ -530,25 +523,15 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) * Assign resources. */ pci_bus_assign_resources(bus); - } + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + } /* * Tell drivers about devices found. */ pci_bus_add_devices(bus); } - - list_for_each_entry(sys, &head, node) { - struct pci_bus *bus = sys->bus; - - /* Configure PCI Express settings */ - if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { - struct pci_bus *child; - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - } - } } #ifndef CONFIG_PCI_HOST_ITE8152 diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index cb4fb1e69778..3e1c26eb32b4 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -149,10 +149,10 @@ ENDPROC(__und_invalid) #define SPFIX(code...) #endif - .macro svc_entry, stack_hole=0, trace=1 + .macro svc_entry, stack_hole=0, trace=1, uaccess=1 UNWIND(.fnstart ) UNWIND(.save {r0 - pc} ) - sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) + sub sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4) #ifdef CONFIG_THUMB2_KERNEL SPFIX( str r0, [sp] ) @ temporarily saved SPFIX( mov r0, sp ) @@ -167,7 +167,7 @@ ENDPROC(__und_invalid) ldmia r0, {r3 - r5} add r7, sp, #S_SP - 4 @ here for interlock avoidance mov r6, #-1 @ "" "" "" "" - add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) + add r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4) SPFIX( addeq r2, r2, #4 ) str r3, [sp, #-4]! @ save the "real" r0 copied @ from the exception stack @@ -185,6 +185,11 @@ ENDPROC(__und_invalid) @ stmia r7, {r2 - r6} + uaccess_save r0 + .if \uaccess + uaccess_disable r0 + .endif + .if \trace #ifdef CONFIG_TRACE_IRQFLAGS bl trace_hardirqs_off @@ -194,7 +199,7 @@ ENDPROC(__und_invalid) .align 5 __dabt_svc: - svc_entry + svc_entry uaccess=0 mov r2, sp dabt_helper THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR @@ -368,7 +373,7 @@ ENDPROC(__fiq_abt) #error "sizeof(struct pt_regs) must be a multiple of 8" #endif - .macro usr_entry, trace=1 + .macro usr_entry, trace=1, uaccess=1 UNWIND(.fnstart ) UNWIND(.cantunwind ) @ don't unwind the user space sub sp, sp, #S_FRAME_SIZE @@ -400,6 +405,10 @@ ENDPROC(__fiq_abt) ARM( stmdb r0, {sp, lr}^ ) THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) + .if \uaccess + uaccess_disable ip + .endif + @ Enable the alignment trap while in kernel mode ATRAP( teq r8, r7) ATRAP( mcrne p15, 0, r8, c1, c0, 0) @@ -435,7 +444,7 @@ ENDPROC(__fiq_abt) .align 5 __dabt_usr: - usr_entry + usr_entry uaccess=0 kuser_cmpxchg_check mov r2, sp dabt_helper @@ -458,7 +467,7 @@ ENDPROC(__irq_usr) .align 5 __und_usr: - usr_entry + usr_entry uaccess=0 mov r2, r4 mov r3, r5 @@ -484,6 +493,8 @@ __und_usr: 1: ldrt r0, [r4] ARM_BE8(rev r0, r0) @ little endian instruction + uaccess_disable ip + @ r0 = 32-bit ARM instruction which caused the exception @ r2 = PC value for the following instruction (:= regs->ARM_pc) @ r4 = PC value for the faulting instruction @@ -518,9 +529,10 @@ __und_usr_thumb: 2: ldrht r5, [r4] ARM_BE8(rev16 r5, r5) @ little endian instruction cmp r5, #0xe800 @ 32bit instruction if xx != 0 - blo __und_usr_fault_16 @ 16bit undefined instruction + blo __und_usr_fault_16_pan @ 16bit undefined instruction 3: ldrht r0, [r2] ARM_BE8(rev16 r0, r0) @ little endian instruction + uaccess_disable ip add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update orr r0, r0, r5, lsl #16 @@ -715,6 +727,8 @@ ENDPROC(no_fp) __und_usr_fault_32: mov r1, #4 b 1f +__und_usr_fault_16_pan: + uaccess_disable ip __und_usr_fault_16: mov r1, #2 1: mov r0, sp @@ -770,6 +784,8 @@ ENTRY(__switch_to) ldr r4, [r2, #TI_TP_VALUE] ldr r5, [r2, #TI_TP_VALUE + 4] #ifdef CONFIG_CPU_USE_DOMAINS + mrc p15, 0, r6, c3, c0, 0 @ Get domain register + str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register ldr r6, [r2, #TI_CPU_DOMAIN] #endif switch_tls r1, r4, r5, r3, r7 diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index b48dd4f37f80..30a7228eaceb 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -24,35 +24,55 @@ .align 5 +#if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING)) /* - * This is the fast syscall return path. We do as little as - * possible here, and this includes saving r0 back into the SVC - * stack. + * This is the fast syscall return path. We do as little as possible here, + * such as avoiding writing r0 to the stack. We only use this path if we + * have tracing and context tracking disabled - the overheads from those + * features make this path too inefficient. */ ret_fast_syscall: UNWIND(.fnstart ) UNWIND(.cantunwind ) - disable_irq @ disable interrupts + disable_irq_notrace @ disable interrupts ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing - tst r1, #_TIF_SYSCALL_WORK - bne __sys_trace_return - tst r1, #_TIF_WORK_MASK + tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK bne fast_work_pending - asm_trace_hardirqs_on /* perform architecture specific actions before user return */ arch_ret_to_user r1, lr - ct_user_enter restore_user_regs fast = 1, offset = S_OFF UNWIND(.fnend ) +ENDPROC(ret_fast_syscall) -/* - * Ok, we need to do extra processing, enter the slow path. - */ + /* Ok, we need to do extra processing, enter the slow path. */ fast_work_pending: str r0, [sp, #S_R0+S_OFF]! @ returned r0 -work_pending: + /* fall through to work_pending */ +#else +/* + * The "replacement" ret_fast_syscall for when tracing or context tracking + * is enabled. As we will need to call out to some C functions, we save + * r0 first to avoid needing to save registers around each C function call. + */ +ret_fast_syscall: + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + str r0, [sp, #S_R0 + S_OFF]! @ save returned r0 + disable_irq_notrace @ disable interrupts + ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing + tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK + beq no_work_pending + UNWIND(.fnend ) +ENDPROC(ret_fast_syscall) + + /* Slower path - fall through to work_pending */ +#endif + + tst r1, #_TIF_SYSCALL_WORK + bne __sys_trace_return_nosave +slow_work_pending: mov r0, sp @ 'regs' mov r2, why @ 'syscall' bl do_work_pending @@ -65,16 +85,19 @@ ENDPROC(ret_fast_syscall) /* * "slow" syscall return path. "why" tells us if this was a real syscall. + * IRQs may be enabled here, so always disable them. Note that we use the + * "notrace" version to avoid calling into the tracing code unnecessarily. + * do_work_pending() will update this state if necessary. */ ENTRY(ret_to_user) ret_slow_syscall: - disable_irq @ disable interrupts + disable_irq_notrace @ disable interrupts ENTRY(ret_to_user_from_irq) ldr r1, [tsk, #TI_FLAGS] tst r1, #_TIF_WORK_MASK - bne work_pending + bne slow_work_pending no_work_pending: - asm_trace_hardirqs_on + asm_trace_hardirqs_on save = 0 /* perform architecture specific actions before user return */ arch_ret_to_user r1, lr @@ -174,6 +197,8 @@ ENTRY(vector_swi) USER( ldr scno, [lr, #-4] ) @ get SWI instruction #endif + uaccess_disable tbl + adr tbl, sys_call_table @ load syscall table pointer #if defined(CONFIG_OABI_COMPAT) @@ -252,6 +277,12 @@ __sys_trace_return: bl syscall_trace_exit b ret_slow_syscall +__sys_trace_return_nosave: + enable_irq_notrace + mov r0, sp + bl syscall_trace_exit + b ret_slow_syscall + .align 5 #ifdef CONFIG_ALIGNMENT_TRAP .type __cr_alignment, #object diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 1a0045abead7..0d22ad206d52 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -196,7 +196,7 @@ msr cpsr_c, \rtemp @ switch back to the SVC mode .endm -#ifndef CONFIG_THUMB2_KERNEL + .macro svc_exit, rpsr, irq = 0 .if \irq != 0 @ IRQs already off @@ -215,6 +215,10 @@ blne trace_hardirqs_off #endif .endif + uaccess_restore + +#ifndef CONFIG_THUMB2_KERNEL + @ ARM mode SVC restore msr spsr_cxsf, \rpsr #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K) @ We must avoid clrex due to Cortex-A15 erratum #830321 @@ -222,6 +226,20 @@ strex r1, r2, [r0] @ clear the exclusive monitor #endif ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr +#else + @ Thumb mode SVC restore + ldr lr, [sp, #S_SP] @ top of the stack + ldrd r0, r1, [sp, #S_LR] @ calling lr and pc + + @ We must avoid clrex due to Cortex-A15 erratum #830321 + strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor + + stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context + ldmia sp, {r0 - r12} + mov sp, lr + ldr lr, [sp], #4 + rfeia sp! +#endif .endm @ @@ -241,6 +259,9 @@ @ on the stack remains correct). @ .macro svc_exit_via_fiq + uaccess_restore +#ifndef CONFIG_THUMB2_KERNEL + @ ARM mode restore mov r0, sp ldmib r0, {r1 - r14} @ abort is deadly from here onward (it will @ clobber state restored below) @@ -250,9 +271,27 @@ msr spsr_cxsf, r9 ldr r0, [r0, #S_R0] ldmia r8, {pc}^ +#else + @ Thumb mode restore + add r0, sp, #S_R2 + ldr lr, [sp, #S_LR] + ldr sp, [sp, #S_SP] @ abort is deadly from here onward (it will + @ clobber state restored below) + ldmia r0, {r2 - r12} + mov r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT + msr cpsr_c, r1 + sub r0, #S_R2 + add r8, r0, #S_PC + ldmia r0, {r0 - r1} + rfeia r8 +#endif .endm + .macro restore_user_regs, fast = 0, offset = 0 + uaccess_enable r1, isb=0 +#ifndef CONFIG_THUMB2_KERNEL + @ ARM mode restore mov r2, sp ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr ldr lr, [r2, #\offset + S_PC]! @ get pc @@ -270,72 +309,16 @@ @ after ldm {}^ add sp, sp, #\offset + S_FRAME_SIZE movs pc, lr @ return & move spsr_svc into cpsr - .endm - -#else /* CONFIG_THUMB2_KERNEL */ - .macro svc_exit, rpsr, irq = 0 - .if \irq != 0 - @ IRQs already off -#ifdef CONFIG_TRACE_IRQFLAGS - @ The parent context IRQs must have been enabled to get here in - @ the first place, so there's no point checking the PSR I bit. - bl trace_hardirqs_on -#endif - .else - @ IRQs off again before pulling preserved data off the stack - disable_irq_notrace -#ifdef CONFIG_TRACE_IRQFLAGS - tst \rpsr, #PSR_I_BIT - bleq trace_hardirqs_on - tst \rpsr, #PSR_I_BIT - blne trace_hardirqs_off -#endif - .endif - ldr lr, [sp, #S_SP] @ top of the stack - ldrd r0, r1, [sp, #S_LR] @ calling lr and pc - - @ We must avoid clrex due to Cortex-A15 erratum #830321 - strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor - - stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context - ldmia sp, {r0 - r12} - mov sp, lr - ldr lr, [sp], #4 - rfeia sp! - .endm - - @ - @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit - @ - @ For full details see non-Thumb implementation above. - @ - .macro svc_exit_via_fiq - add r0, sp, #S_R2 - ldr lr, [sp, #S_LR] - ldr sp, [sp, #S_SP] @ abort is deadly from here onward (it will - @ clobber state restored below) - ldmia r0, {r2 - r12} - mov r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT - msr cpsr_c, r1 - sub r0, #S_R2 - add r8, r0, #S_PC - ldmia r0, {r0 - r1} - rfeia r8 - .endm - -#ifdef CONFIG_CPU_V7M - /* - * Note we don't need to do clrex here as clearing the local monitor is - * part of each exception entry and exit sequence. - */ - .macro restore_user_regs, fast = 0, offset = 0 +#elif defined(CONFIG_CPU_V7M) + @ V7M restore. + @ Note that we don't need to do clrex here as clearing the local + @ monitor is part of the exception entry and exit sequence. .if \offset add sp, #\offset .endif v7m_exception_slow_exit ret_r0 = \fast - .endm -#else /* ifdef CONFIG_CPU_V7M */ - .macro restore_user_regs, fast = 0, offset = 0 +#else + @ Thumb mode restore mov r2, sp load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr @@ -353,9 +336,8 @@ .endif add sp, sp, #S_FRAME_SIZE - S_SP movs pc, lr @ return & move spsr_svc into cpsr - .endm -#endif /* ifdef CONFIG_CPU_V7M / else */ #endif /* !CONFIG_THUMB2_KERNEL */ + .endm /* * Context tracking subsystem. Used to instrument transitions diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 29e2991465cb..04286fd9e09c 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -464,10 +464,7 @@ __enable_mmu: #ifdef CONFIG_ARM_LPAE mcrr p15, 0, r4, r5, c2 @ load TTBR0 #else - mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_IO, DOMAIN_CLIENT)) + mov r5, #DACR_INIT mcr p15, 0, r5, c3, c0, 0 @ load domain access register mcr p15, 0, r4, c2, c0, 0 @ load page table pointer #endif diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 350f188c92d2..5ff4826cb154 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -39,6 +39,7 @@ #include <linux/export.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/outercache.h> #include <asm/exception.h> #include <asm/mach/arch.h> #include <asm/mach/irq.h> @@ -140,7 +141,7 @@ int __init arch_probe_nr_irqs(void) static bool migrate_one_irq(struct irq_desc *desc) { struct irq_data *d = irq_desc_get_irq_data(desc); - const struct cpumask *affinity = d->affinity; + const struct cpumask *affinity = irq_data_get_affinity_mask(d); struct irq_chip *c; bool ret = false; @@ -160,7 +161,7 @@ static bool migrate_one_irq(struct irq_desc *desc) if (!c->irq_set_affinity) pr_debug("IRQ%u: unable to set affinity\n", d->irq); else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret) - cpumask_copy(d->affinity, affinity); + cpumask_copy(irq_data_get_affinity_mask(d), affinity); return ret; } diff --git a/arch/arm/kernel/jump_label.c b/arch/arm/kernel/jump_label.c index e39cbf488cfe..845a5dd9c42b 100644 --- a/arch/arm/kernel/jump_label.c +++ b/arch/arm/kernel/jump_label.c @@ -12,7 +12,7 @@ static void __arch_jump_label_transform(struct jump_entry *entry, void *addr = (void *)entry->code; unsigned int insn; - if (type == JUMP_LABEL_ENABLE) + if (type == JUMP_LABEL_JMP) insn = arm_gen_branch(entry->code, entry->target); else insn = arm_gen_nop(); diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c deleted file mode 100644 index 54272e0be713..000000000000 --- a/arch/arm/kernel/perf_event.c +++ /dev/null @@ -1,896 +0,0 @@ -#undef DEBUG - -/* - * ARM performance counter support. - * - * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles - * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> - * - * This code is based on the sparc64 perf event code, which is in turn based - * on the x86 code. - */ -#define pr_fmt(fmt) "hw perfevents: " fmt - -#include <linux/bitmap.h> -#include <linux/cpumask.h> -#include <linux/export.h> -#include <linux/kernel.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> - -#include <asm/cputype.h> -#include <asm/irq_regs.h> -#include <asm/pmu.h> - -static int -armpmu_map_cache_event(const unsigned (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u64 config) -{ - unsigned int cache_type, cache_op, cache_result, ret; - - cache_type = (config >> 0) & 0xff; - if (cache_type >= PERF_COUNT_HW_CACHE_MAX) - return -EINVAL; - - cache_op = (config >> 8) & 0xff; - if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) - return -EINVAL; - - cache_result = (config >> 16) & 0xff; - if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) - return -EINVAL; - - ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; - - if (ret == CACHE_OP_UNSUPPORTED) - return -ENOENT; - - return ret; -} - -static int -armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) -{ - int mapping; - - if (config >= PERF_COUNT_HW_MAX) - return -EINVAL; - - mapping = (*event_map)[config]; - return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; -} - -static int -armpmu_map_raw_event(u32 raw_event_mask, u64 config) -{ - return (int)(config & raw_event_mask); -} - -int -armpmu_map_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask) -{ - u64 config = event->attr.config; - int type = event->attr.type; - - if (type == event->pmu->type) - return armpmu_map_raw_event(raw_event_mask, config); - - switch (type) { - case PERF_TYPE_HARDWARE: - return armpmu_map_hw_event(event_map, config); - case PERF_TYPE_HW_CACHE: - return armpmu_map_cache_event(cache_map, config); - case PERF_TYPE_RAW: - return armpmu_map_raw_event(raw_event_mask, config); - } - - return -ENOENT; -} - -int armpmu_event_set_period(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - s64 left = local64_read(&hwc->period_left); - s64 period = hwc->sample_period; - int ret = 0; - - if (unlikely(left <= -period)) { - left = period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - if (unlikely(left <= 0)) { - left += period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - /* - * Limit the maximum period to prevent the counter value - * from overtaking the one we are about to program. In - * effect we are reducing max_period to account for - * interrupt latency (and we are being very conservative). - */ - if (left > (armpmu->max_period >> 1)) - left = armpmu->max_period >> 1; - - local64_set(&hwc->prev_count, (u64)-left); - - armpmu->write_counter(event, (u64)(-left) & 0xffffffff); - - perf_event_update_userpage(event); - - return ret; -} - -u64 armpmu_event_update(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - u64 delta, prev_raw_count, new_raw_count; - -again: - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = armpmu->read_counter(event); - - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count) - goto again; - - delta = (new_raw_count - prev_raw_count) & armpmu->max_period; - - local64_add(delta, &event->count); - local64_sub(delta, &hwc->period_left); - - return new_raw_count; -} - -static void -armpmu_read(struct perf_event *event) -{ - armpmu_event_update(event); -} - -static void -armpmu_stop(struct perf_event *event, int flags) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - - /* - * ARM pmu always has to update the counter, so ignore - * PERF_EF_UPDATE, see comments in armpmu_start(). - */ - if (!(hwc->state & PERF_HES_STOPPED)) { - armpmu->disable(event); - armpmu_event_update(event); - hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; - } -} - -static void armpmu_start(struct perf_event *event, int flags) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - - /* - * ARM pmu always has to reprogram the period, so ignore - * PERF_EF_RELOAD, see the comment below. - */ - if (flags & PERF_EF_RELOAD) - WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); - - hwc->state = 0; - /* - * Set the period again. Some counters can't be stopped, so when we - * were stopped we simply disabled the IRQ source and the counter - * may have been left counting. If we don't do this step then we may - * get an interrupt too soon or *way* too late if the overflow has - * happened since disabling. - */ - armpmu_event_set_period(event); - armpmu->enable(event); -} - -static void -armpmu_del(struct perf_event *event, int flags) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - armpmu_stop(event, PERF_EF_UPDATE); - hw_events->events[idx] = NULL; - clear_bit(idx, hw_events->used_mask); - if (armpmu->clear_event_idx) - armpmu->clear_event_idx(hw_events, event); - - perf_event_update_userpage(event); -} - -static int -armpmu_add(struct perf_event *event, int flags) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx; - int err = 0; - - /* An event following a process won't be stopped earlier */ - if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) - return -ENOENT; - - perf_pmu_disable(event->pmu); - - /* If we don't have a space for the counter then finish early. */ - idx = armpmu->get_event_idx(hw_events, event); - if (idx < 0) { - err = idx; - goto out; - } - - /* - * If there is an event in the counter we are going to use then make - * sure it is disabled. - */ - event->hw.idx = idx; - armpmu->disable(event); - hw_events->events[idx] = event; - - hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; - if (flags & PERF_EF_START) - armpmu_start(event, PERF_EF_RELOAD); - - /* Propagate our changes to the userspace mapping. */ - perf_event_update_userpage(event); - -out: - perf_pmu_enable(event->pmu); - return err; -} - -static int -validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, - struct perf_event *event) -{ - struct arm_pmu *armpmu; - - if (is_software_event(event)) - return 1; - - /* - * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The - * core perf code won't check that the pmu->ctx == leader->ctx - * until after pmu->event_init(event). - */ - if (event->pmu != pmu) - return 0; - - if (event->state < PERF_EVENT_STATE_OFF) - return 1; - - if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) - return 1; - - armpmu = to_arm_pmu(event->pmu); - return armpmu->get_event_idx(hw_events, event) >= 0; -} - -static int -validate_group(struct perf_event *event) -{ - struct perf_event *sibling, *leader = event->group_leader; - struct pmu_hw_events fake_pmu; - - /* - * Initialise the fake PMU. We only need to populate the - * used_mask for the purposes of validation. - */ - memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); - - if (!validate_event(event->pmu, &fake_pmu, leader)) - return -EINVAL; - - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { - if (!validate_event(event->pmu, &fake_pmu, sibling)) - return -EINVAL; - } - - if (!validate_event(event->pmu, &fake_pmu, event)) - return -EINVAL; - - return 0; -} - -static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) -{ - struct arm_pmu *armpmu; - struct platform_device *plat_device; - struct arm_pmu_platdata *plat; - int ret; - u64 start_clock, finish_clock; - - /* - * we request the IRQ with a (possibly percpu) struct arm_pmu**, but - * the handlers expect a struct arm_pmu*. The percpu_irq framework will - * do any necessary shifting, we just need to perform the first - * dereference. - */ - armpmu = *(void **)dev; - plat_device = armpmu->plat_device; - plat = dev_get_platdata(&plat_device->dev); - - start_clock = sched_clock(); - if (plat && plat->handle_irq) - ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq); - else - ret = armpmu->handle_irq(irq, armpmu); - finish_clock = sched_clock(); - - perf_sample_event_took(finish_clock - start_clock); - return ret; -} - -static void -armpmu_release_hardware(struct arm_pmu *armpmu) -{ - armpmu->free_irq(armpmu); -} - -static int -armpmu_reserve_hardware(struct arm_pmu *armpmu) -{ - int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); - if (err) { - armpmu_release_hardware(armpmu); - return err; - } - - return 0; -} - -static void -hw_perf_event_destroy(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - atomic_t *active_events = &armpmu->active_events; - struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; - - if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { - armpmu_release_hardware(armpmu); - mutex_unlock(pmu_reserve_mutex); - } -} - -static int -event_requires_mode_exclusion(struct perf_event_attr *attr) -{ - return attr->exclude_idle || attr->exclude_user || - attr->exclude_kernel || attr->exclude_hv; -} - -static int -__hw_perf_event_init(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int mapping; - - mapping = armpmu->map_event(event); - - if (mapping < 0) { - pr_debug("event %x:%llx not supported\n", event->attr.type, - event->attr.config); - return mapping; - } - - /* - * We don't assign an index until we actually place the event onto - * hardware. Use -1 to signify that we haven't decided where to put it - * yet. For SMP systems, each core has it's own PMU so we can't do any - * clever allocation or constraints checking at this point. - */ - hwc->idx = -1; - hwc->config_base = 0; - hwc->config = 0; - hwc->event_base = 0; - - /* - * Check whether we need to exclude the counter from certain modes. - */ - if ((!armpmu->set_event_filter || - armpmu->set_event_filter(hwc, &event->attr)) && - event_requires_mode_exclusion(&event->attr)) { - pr_debug("ARM performance counters do not support " - "mode exclusion\n"); - return -EOPNOTSUPP; - } - - /* - * Store the event encoding into the config_base field. - */ - hwc->config_base |= (unsigned long)mapping; - - if (!is_sampling_event(event)) { - /* - * For non-sampling runs, limit the sample_period to half - * of the counter width. That way, the new counter value - * is far less likely to overtake the previous one unless - * you have some serious IRQ latency issues. - */ - hwc->sample_period = armpmu->max_period >> 1; - hwc->last_period = hwc->sample_period; - local64_set(&hwc->period_left, hwc->sample_period); - } - - if (event->group_leader != event) { - if (validate_group(event) != 0) - return -EINVAL; - } - - return 0; -} - -static int armpmu_event_init(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - int err = 0; - atomic_t *active_events = &armpmu->active_events; - - /* - * Reject CPU-affine events for CPUs that are of a different class to - * that which this PMU handles. Process-following events (where - * event->cpu == -1) can be migrated between CPUs, and thus we have to - * reject them later (in armpmu_add) if they're scheduled on a - * different class of CPU. - */ - if (event->cpu != -1 && - !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus)) - return -ENOENT; - - /* does not support taken branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - - if (armpmu->map_event(event) == -ENOENT) - return -ENOENT; - - event->destroy = hw_perf_event_destroy; - - if (!atomic_inc_not_zero(active_events)) { - mutex_lock(&armpmu->reserve_mutex); - if (atomic_read(active_events) == 0) - err = armpmu_reserve_hardware(armpmu); - - if (!err) - atomic_inc(active_events); - mutex_unlock(&armpmu->reserve_mutex); - } - - if (err) - return err; - - err = __hw_perf_event_init(event); - if (err) - hw_perf_event_destroy(event); - - return err; -} - -static void armpmu_enable(struct pmu *pmu) -{ - struct arm_pmu *armpmu = to_arm_pmu(pmu); - struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); - int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); - - /* For task-bound events we may be called on other CPUs */ - if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) - return; - - if (enabled) - armpmu->start(armpmu); -} - -static void armpmu_disable(struct pmu *pmu) -{ - struct arm_pmu *armpmu = to_arm_pmu(pmu); - - /* For task-bound events we may be called on other CPUs */ - if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) - return; - - armpmu->stop(armpmu); -} - -/* - * In heterogeneous systems, events are specific to a particular - * microarchitecture, and aren't suitable for another. Thus, only match CPUs of - * the same microarchitecture. - */ -static int armpmu_filter_match(struct perf_event *event) -{ - struct arm_pmu *armpmu = to_arm_pmu(event->pmu); - unsigned int cpu = smp_processor_id(); - return cpumask_test_cpu(cpu, &armpmu->supported_cpus); -} - -static void armpmu_init(struct arm_pmu *armpmu) -{ - atomic_set(&armpmu->active_events, 0); - mutex_init(&armpmu->reserve_mutex); - - armpmu->pmu = (struct pmu) { - .pmu_enable = armpmu_enable, - .pmu_disable = armpmu_disable, - .event_init = armpmu_event_init, - .add = armpmu_add, - .del = armpmu_del, - .start = armpmu_start, - .stop = armpmu_stop, - .read = armpmu_read, - .filter_match = armpmu_filter_match, - }; -} - -int armpmu_register(struct arm_pmu *armpmu, int type) -{ - armpmu_init(armpmu); - pr_info("enabled with %s PMU driver, %d counters available\n", - armpmu->name, armpmu->num_events); - return perf_pmu_register(&armpmu->pmu, armpmu->name, type); -} - -/* Set at runtime when we know what CPU type we are. */ -static struct arm_pmu *__oprofile_cpu_pmu; - -/* - * Despite the names, these two functions are CPU-specific and are used - * by the OProfile/perf code. - */ -const char *perf_pmu_name(void) -{ - if (!__oprofile_cpu_pmu) - return NULL; - - return __oprofile_cpu_pmu->name; -} -EXPORT_SYMBOL_GPL(perf_pmu_name); - -int perf_num_counters(void) -{ - int max_events = 0; - - if (__oprofile_cpu_pmu != NULL) - max_events = __oprofile_cpu_pmu->num_events; - - return max_events; -} -EXPORT_SYMBOL_GPL(perf_num_counters); - -static void cpu_pmu_enable_percpu_irq(void *data) -{ - int irq = *(int *)data; - - enable_percpu_irq(irq, IRQ_TYPE_NONE); -} - -static void cpu_pmu_disable_percpu_irq(void *data) -{ - int irq = *(int *)data; - - disable_percpu_irq(irq); -} - -static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) -{ - int i, irq, irqs; - struct platform_device *pmu_device = cpu_pmu->plat_device; - struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - - irq = platform_get_irq(pmu_device, 0); - if (irq >= 0 && irq_is_percpu(irq)) { - on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1); - free_percpu_irq(irq, &hw_events->percpu_pmu); - } else { - for (i = 0; i < irqs; ++i) { - int cpu = i; - - if (cpu_pmu->irq_affinity) - cpu = cpu_pmu->irq_affinity[i]; - - if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs)) - continue; - irq = platform_get_irq(pmu_device, i); - if (irq >= 0) - free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu)); - } - } -} - -static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) -{ - int i, err, irq, irqs; - struct platform_device *pmu_device = cpu_pmu->plat_device; - struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; - - if (!pmu_device) - return -ENODEV; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - if (irqs < 1) { - pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n"); - return 0; - } - - irq = platform_get_irq(pmu_device, 0); - if (irq >= 0 && irq_is_percpu(irq)) { - err = request_percpu_irq(irq, handler, "arm-pmu", - &hw_events->percpu_pmu); - if (err) { - pr_err("unable to request IRQ%d for ARM PMU counters\n", - irq); - return err; - } - on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1); - } else { - for (i = 0; i < irqs; ++i) { - int cpu = i; - - err = 0; - irq = platform_get_irq(pmu_device, i); - if (irq < 0) - continue; - - if (cpu_pmu->irq_affinity) - cpu = cpu_pmu->irq_affinity[i]; - - /* - * If we have a single PMU interrupt that we can't shift, - * assume that we're running on a uniprocessor machine and - * continue. Otherwise, continue without this interrupt. - */ - if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) { - pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n", - irq, cpu); - continue; - } - - err = request_irq(irq, handler, - IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", - per_cpu_ptr(&hw_events->percpu_pmu, cpu)); - if (err) { - pr_err("unable to request IRQ%d for ARM PMU counters\n", - irq); - return err; - } - - cpumask_set_cpu(cpu, &cpu_pmu->active_irqs); - } - } - - return 0; -} - -/* - * PMU hardware loses all context when a CPU goes offline. - * When a CPU is hotplugged back in, since some hardware registers are - * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading - * junk values out of them. - */ -static int cpu_pmu_notify(struct notifier_block *b, unsigned long action, - void *hcpu) -{ - int cpu = (unsigned long)hcpu; - struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb); - - if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) - return NOTIFY_DONE; - - if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) - return NOTIFY_DONE; - - if (pmu->reset) - pmu->reset(pmu); - else - return NOTIFY_DONE; - - return NOTIFY_OK; -} - -static int cpu_pmu_init(struct arm_pmu *cpu_pmu) -{ - int err; - int cpu; - struct pmu_hw_events __percpu *cpu_hw_events; - - cpu_hw_events = alloc_percpu(struct pmu_hw_events); - if (!cpu_hw_events) - return -ENOMEM; - - cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify; - err = register_cpu_notifier(&cpu_pmu->hotplug_nb); - if (err) - goto out_hw_events; - - for_each_possible_cpu(cpu) { - struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu); - raw_spin_lock_init(&events->pmu_lock); - events->percpu_pmu = cpu_pmu; - } - - cpu_pmu->hw_events = cpu_hw_events; - cpu_pmu->request_irq = cpu_pmu_request_irq; - cpu_pmu->free_irq = cpu_pmu_free_irq; - - /* Ensure the PMU has sane values out of reset. */ - if (cpu_pmu->reset) - on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset, - cpu_pmu, 1); - - /* If no interrupts available, set the corresponding capability flag */ - if (!platform_get_irq(cpu_pmu->plat_device, 0)) - cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; - - return 0; - -out_hw_events: - free_percpu(cpu_hw_events); - return err; -} - -static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) -{ - unregister_cpu_notifier(&cpu_pmu->hotplug_nb); - free_percpu(cpu_pmu->hw_events); -} - -/* - * CPU PMU identification and probing. - */ -static int probe_current_pmu(struct arm_pmu *pmu, - const struct pmu_probe_info *info) -{ - int cpu = get_cpu(); - unsigned int cpuid = read_cpuid_id(); - int ret = -ENODEV; - - pr_info("probing PMU on CPU %d\n", cpu); - - for (; info->init != NULL; info++) { - if ((cpuid & info->mask) != info->cpuid) - continue; - ret = info->init(pmu); - break; - } - - put_cpu(); - return ret; -} - -static int of_pmu_irq_cfg(struct arm_pmu *pmu) -{ - int i, irq, *irqs; - struct platform_device *pdev = pmu->plat_device; - - /* Don't bother with PPIs; they're already affine */ - irq = platform_get_irq(pdev, 0); - if (irq >= 0 && irq_is_percpu(irq)) - return 0; - - irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); - if (!irqs) - return -ENOMEM; - - for (i = 0; i < pdev->num_resources; ++i) { - struct device_node *dn; - int cpu; - - dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", - i); - if (!dn) { - pr_warn("Failed to parse %s/interrupt-affinity[%d]\n", - of_node_full_name(pdev->dev.of_node), i); - break; - } - - for_each_possible_cpu(cpu) - if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL)) - break; - - if (cpu >= nr_cpu_ids) { - pr_warn("Failed to find logical CPU for %s\n", - dn->name); - of_node_put(dn); - break; - } - of_node_put(dn); - - irqs[i] = cpu; - cpumask_set_cpu(cpu, &pmu->supported_cpus); - } - - if (i == pdev->num_resources) { - pmu->irq_affinity = irqs; - } else { - kfree(irqs); - cpumask_setall(&pmu->supported_cpus); - } - - return 0; -} - -int arm_pmu_device_probe(struct platform_device *pdev, - const struct of_device_id *of_table, - const struct pmu_probe_info *probe_table) -{ - const struct of_device_id *of_id; - const int (*init_fn)(struct arm_pmu *); - struct device_node *node = pdev->dev.of_node; - struct arm_pmu *pmu; - int ret = -ENODEV; - - pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL); - if (!pmu) { - pr_info("failed to allocate PMU device!\n"); - return -ENOMEM; - } - - if (!__oprofile_cpu_pmu) - __oprofile_cpu_pmu = pmu; - - pmu->plat_device = pdev; - - if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) { - init_fn = of_id->data; - - ret = of_pmu_irq_cfg(pmu); - if (!ret) - ret = init_fn(pmu); - } else { - ret = probe_current_pmu(pmu, probe_table); - cpumask_setall(&pmu->supported_cpus); - } - - if (ret) { - pr_info("failed to probe PMU!\n"); - goto out_free; - } - - ret = cpu_pmu_init(pmu); - if (ret) - goto out_free; - - ret = armpmu_register(pmu, -1); - if (ret) - goto out_destroy; - - return 0; - -out_destroy: - cpu_pmu_destroy(pmu); -out_free: - pr_info("failed to register PMU devices!\n"); - kfree(pmu); - return ret; -} diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 09f83e414a72..09413e7b49aa 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -34,9 +34,9 @@ #include <asm/cputype.h> #include <asm/irq_regs.h> -#include <asm/pmu.h> #include <linux/of.h> +#include <linux/perf/arm_pmu.h> #include <linux/platform_device.h> enum armv6_perf_types { diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index f9b37f876e20..126dc679b230 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -21,11 +21,11 @@ #include <asm/cp15.h> #include <asm/cputype.h> #include <asm/irq_regs.h> -#include <asm/pmu.h> #include <asm/vfp.h> #include "../vfp/vfpinstr.h" #include <linux/of.h> +#include <linux/perf/arm_pmu.h> #include <linux/platform_device.h> /* diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 304d056d5b25..aa0499e2eef7 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -16,9 +16,9 @@ #include <asm/cputype.h> #include <asm/irq_regs.h> -#include <asm/pmu.h> #include <linux/of.h> +#include <linux/perf/arm_pmu.h> #include <linux/platform_device.h> enum xscale_perf_types { diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index f192a2a41719..a3089bacb8d8 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -91,13 +91,6 @@ void arch_cpu_idle_exit(void) ledtrig_cpu(CPU_LED_IDLE_END); } -#ifdef CONFIG_HOTPLUG_CPU -void arch_cpu_idle_dead(void) -{ - cpu_die(); -} -#endif - void __show_regs(struct pt_regs *regs) { unsigned long flags; @@ -129,12 +122,36 @@ void __show_regs(struct pt_regs *regs) buf[4] = '\0'; #ifndef CONFIG_CPU_V7M - printk("Flags: %s IRQs o%s FIQs o%s Mode %s ISA %s Segment %s\n", - buf, interrupts_enabled(regs) ? "n" : "ff", - fast_interrupts_enabled(regs) ? "n" : "ff", - processor_modes[processor_mode(regs)], - isa_modes[isa_mode(regs)], - get_fs() == get_ds() ? "kernel" : "user"); + { + unsigned int domain = get_domain(); + const char *segment; + +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + /* + * Get the domain register for the parent context. In user + * mode, we don't save the DACR, so lets use what it should + * be. For other modes, we place it after the pt_regs struct. + */ + if (user_mode(regs)) + domain = DACR_UACCESS_ENABLE; + else + domain = *(unsigned int *)(regs + 1); +#endif + + if ((domain & domain_mask(DOMAIN_USER)) == + domain_val(DOMAIN_USER, DOMAIN_NOACCESS)) + segment = "none"; + else if (get_fs() == get_ds()) + segment = "kernel"; + else + segment = "user"; + + printk("Flags: %s IRQs o%s FIQs o%s Mode %s ISA %s Segment %s\n", + buf, interrupts_enabled(regs) ? "n" : "ff", + fast_interrupts_enabled(regs) ? "n" : "ff", + processor_modes[processor_mode(regs)], + isa_modes[isa_mode(regs)], segment); + } #else printk("xPSR: %08lx\n", regs->ARM_cpsr); #endif @@ -146,10 +163,9 @@ void __show_regs(struct pt_regs *regs) buf[0] = '\0'; #ifdef CONFIG_CPU_CP15_MMU { - unsigned int transbase, dac; + unsigned int transbase, dac = get_domain(); asm("mrc p15, 0, %0, c2, c0\n\t" - "mrc p15, 0, %1, c3, c0\n" - : "=r" (transbase), "=r" (dac)); + : "=r" (transbase)); snprintf(buf, sizeof(buf), " Table: %08x DAC: %08x", transbase, dac); } @@ -210,6 +226,14 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save)); + /* + * Copy the initial value of the domain access control register + * from the current thread: thread->addr_limit will have been + * copied from the current thread via setup_thread_stack() in + * kernel/fork.c + */ + thread->cpu_domain = get_domain(); + if (likely(!(p->flags & PF_KTHREAD))) { *childregs = *current_pt_regs(); childregs->ARM_r0 = 0; diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c deleted file mode 100644 index f90fdf4ce7c7..000000000000 --- a/arch/arm/kernel/psci.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2012 ARM Limited - * - * Author: Will Deacon <will.deacon@arm.com> - */ - -#define pr_fmt(fmt) "psci: " fmt - -#include <linux/init.h> -#include <linux/of.h> -#include <linux/reboot.h> -#include <linux/pm.h> -#include <uapi/linux/psci.h> - -#include <asm/compiler.h> -#include <asm/errno.h> -#include <asm/psci.h> -#include <asm/system_misc.h> - -struct psci_operations psci_ops; - -static int (*invoke_psci_fn)(u32, u32, u32, u32); -typedef int (*psci_initcall_t)(const struct device_node *); - -asmlinkage int __invoke_psci_fn_hvc(u32, u32, u32, u32); -asmlinkage int __invoke_psci_fn_smc(u32, u32, u32, u32); - -enum psci_function { - PSCI_FN_CPU_SUSPEND, - PSCI_FN_CPU_ON, - PSCI_FN_CPU_OFF, - PSCI_FN_MIGRATE, - PSCI_FN_AFFINITY_INFO, - PSCI_FN_MIGRATE_INFO_TYPE, - PSCI_FN_MAX, -}; - -static u32 psci_function_id[PSCI_FN_MAX]; - -static int psci_to_linux_errno(int errno) -{ - switch (errno) { - case PSCI_RET_SUCCESS: - return 0; - case PSCI_RET_NOT_SUPPORTED: - return -EOPNOTSUPP; - case PSCI_RET_INVALID_PARAMS: - return -EINVAL; - case PSCI_RET_DENIED: - return -EPERM; - }; - - return -EINVAL; -} - -static u32 psci_power_state_pack(struct psci_power_state state) -{ - return ((state.id << PSCI_0_2_POWER_STATE_ID_SHIFT) - & PSCI_0_2_POWER_STATE_ID_MASK) | - ((state.type << PSCI_0_2_POWER_STATE_TYPE_SHIFT) - & PSCI_0_2_POWER_STATE_TYPE_MASK) | - ((state.affinity_level << PSCI_0_2_POWER_STATE_AFFL_SHIFT) - & PSCI_0_2_POWER_STATE_AFFL_MASK); -} - -static int psci_get_version(void) -{ - int err; - - err = invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); - return err; -} - -static int psci_cpu_suspend(struct psci_power_state state, - unsigned long entry_point) -{ - int err; - u32 fn, power_state; - - fn = psci_function_id[PSCI_FN_CPU_SUSPEND]; - power_state = psci_power_state_pack(state); - err = invoke_psci_fn(fn, power_state, entry_point, 0); - return psci_to_linux_errno(err); -} - -static int psci_cpu_off(struct psci_power_state state) -{ - int err; - u32 fn, power_state; - - fn = psci_function_id[PSCI_FN_CPU_OFF]; - power_state = psci_power_state_pack(state); - err = invoke_psci_fn(fn, power_state, 0, 0); - return psci_to_linux_errno(err); -} - -static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point) -{ - int err; - u32 fn; - - fn = psci_function_id[PSCI_FN_CPU_ON]; - err = invoke_psci_fn(fn, cpuid, entry_point, 0); - return psci_to_linux_errno(err); -} - -static int psci_migrate(unsigned long cpuid) -{ - int err; - u32 fn; - - fn = psci_function_id[PSCI_FN_MIGRATE]; - err = invoke_psci_fn(fn, cpuid, 0, 0); - return psci_to_linux_errno(err); -} - -static int psci_affinity_info(unsigned long target_affinity, - unsigned long lowest_affinity_level) -{ - int err; - u32 fn; - - fn = psci_function_id[PSCI_FN_AFFINITY_INFO]; - err = invoke_psci_fn(fn, target_affinity, lowest_affinity_level, 0); - return err; -} - -static int psci_migrate_info_type(void) -{ - int err; - u32 fn; - - fn = psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE]; - err = invoke_psci_fn(fn, 0, 0, 0); - return err; -} - -static int get_set_conduit_method(struct device_node *np) -{ - const char *method; - - pr_info("probing for conduit method from DT.\n"); - - if (of_property_read_string(np, "method", &method)) { - pr_warn("missing \"method\" property\n"); - return -ENXIO; - } - - if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; - } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; - } else { - pr_warn("invalid \"method\" property: %s\n", method); - return -EINVAL; - } - return 0; -} - -static void psci_sys_reset(enum reboot_mode reboot_mode, const char *cmd) -{ - invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); -} - -static void psci_sys_poweroff(void) -{ - invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0); -} - -/* - * PSCI Function IDs for v0.2+ are well defined so use - * standard values. - */ -static int psci_0_2_init(struct device_node *np) -{ - int err, ver; - - err = get_set_conduit_method(np); - - if (err) - goto out_put_node; - - ver = psci_get_version(); - - if (ver == PSCI_RET_NOT_SUPPORTED) { - /* PSCI v0.2 mandates implementation of PSCI_ID_VERSION. */ - pr_err("PSCI firmware does not comply with the v0.2 spec.\n"); - err = -EOPNOTSUPP; - goto out_put_node; - } else { - pr_info("PSCIv%d.%d detected in firmware.\n", - PSCI_VERSION_MAJOR(ver), - PSCI_VERSION_MINOR(ver)); - - if (PSCI_VERSION_MAJOR(ver) == 0 && - PSCI_VERSION_MINOR(ver) < 2) { - err = -EINVAL; - pr_err("Conflicting PSCI version detected.\n"); - goto out_put_node; - } - } - - pr_info("Using standard PSCI v0.2 function IDs\n"); - psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN_CPU_SUSPEND; - psci_ops.cpu_suspend = psci_cpu_suspend; - - psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF; - psci_ops.cpu_off = psci_cpu_off; - - psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN_CPU_ON; - psci_ops.cpu_on = psci_cpu_on; - - psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN_MIGRATE; - psci_ops.migrate = psci_migrate; - - psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN_AFFINITY_INFO; - psci_ops.affinity_info = psci_affinity_info; - - psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] = - PSCI_0_2_FN_MIGRATE_INFO_TYPE; - psci_ops.migrate_info_type = psci_migrate_info_type; - - arm_pm_restart = psci_sys_reset; - - pm_power_off = psci_sys_poweroff; - -out_put_node: - of_node_put(np); - return err; -} - -/* - * PSCI < v0.2 get PSCI Function IDs via DT. - */ -static int psci_0_1_init(struct device_node *np) -{ - u32 id; - int err; - - err = get_set_conduit_method(np); - - if (err) - goto out_put_node; - - pr_info("Using PSCI v0.1 Function IDs from DT\n"); - - if (!of_property_read_u32(np, "cpu_suspend", &id)) { - psci_function_id[PSCI_FN_CPU_SUSPEND] = id; - psci_ops.cpu_suspend = psci_cpu_suspend; - } - - if (!of_property_read_u32(np, "cpu_off", &id)) { - psci_function_id[PSCI_FN_CPU_OFF] = id; - psci_ops.cpu_off = psci_cpu_off; - } - - if (!of_property_read_u32(np, "cpu_on", &id)) { - psci_function_id[PSCI_FN_CPU_ON] = id; - psci_ops.cpu_on = psci_cpu_on; - } - - if (!of_property_read_u32(np, "migrate", &id)) { - psci_function_id[PSCI_FN_MIGRATE] = id; - psci_ops.migrate = psci_migrate; - } - -out_put_node: - of_node_put(np); - return err; -} - -static const struct of_device_id psci_of_match[] __initconst = { - { .compatible = "arm,psci", .data = psci_0_1_init}, - { .compatible = "arm,psci-0.2", .data = psci_0_2_init}, - {}, -}; - -int __init psci_init(void) -{ - struct device_node *np; - const struct of_device_id *matched_np; - psci_initcall_t init_fn; - - np = of_find_matching_node_and_match(NULL, psci_of_match, &matched_np); - if (!np) - return -ENODEV; - - init_fn = (psci_initcall_t)matched_np->data; - return init_fn(np); -} diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c index 28a1db4da704..61c04b02faeb 100644 --- a/arch/arm/kernel/psci_smp.c +++ b/arch/arm/kernel/psci_smp.c @@ -17,6 +17,8 @@ #include <linux/smp.h> #include <linux/of.h> #include <linux/delay.h> +#include <linux/psci.h> + #include <uapi/linux/psci.h> #include <asm/psci.h> @@ -51,22 +53,34 @@ static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle) { if (psci_ops.cpu_on) return psci_ops.cpu_on(cpu_logical_map(cpu), - __pa(secondary_startup)); + virt_to_idmap(&secondary_startup)); return -ENODEV; } #ifdef CONFIG_HOTPLUG_CPU +int psci_cpu_disable(unsigned int cpu) +{ + /* Fail early if we don't have CPU_OFF support */ + if (!psci_ops.cpu_off) + return -EOPNOTSUPP; + + /* Trusted OS will deny CPU_OFF */ + if (psci_tos_resident_on(cpu)) + return -EPERM; + + return 0; +} + void __ref psci_cpu_die(unsigned int cpu) { - const struct psci_power_state ps = { - .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, - }; + u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN << + PSCI_0_2_POWER_STATE_TYPE_SHIFT; - if (psci_ops.cpu_off) - psci_ops.cpu_off(ps); + if (psci_ops.cpu_off) + psci_ops.cpu_off(state); - /* We should never return */ - panic("psci: cpu %d failed to shutdown\n", cpu); + /* We should never return */ + panic("psci: cpu %d failed to shutdown\n", cpu); } int __ref psci_cpu_kill(unsigned int cpu) @@ -109,6 +123,7 @@ bool __init psci_smp_available(void) struct smp_operations __initdata psci_smp_ops = { .smp_boot_secondary = psci_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU + .cpu_disable = psci_cpu_disable, .cpu_die = psci_cpu_die, .cpu_kill = psci_cpu_kill, #endif diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 36c18b73c1f4..20edd349d379 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -31,12 +31,14 @@ #include <linux/bug.h> #include <linux/compiler.h> #include <linux/sort.h> +#include <linux/psci.h> #include <asm/unified.h> #include <asm/cp15.h> #include <asm/cpu.h> #include <asm/cputype.h> #include <asm/elf.h> +#include <asm/fixmap.h> #include <asm/procinfo.h> #include <asm/psci.h> #include <asm/sections.h> @@ -954,6 +956,9 @@ void __init setup_arch(char **cmdline_p) strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); *cmdline_p = cmd_line; + if (IS_ENABLED(CONFIG_FIX_EARLYCON_MEM)) + early_fixmap_init(); + parse_early_param(); #ifdef CONFIG_MMU @@ -972,7 +977,7 @@ void __init setup_arch(char **cmdline_p) unflatten_device_tree(); arm_dt_init_cpu_maps(); - psci_init(); + psci_dt_init(); xen_early_init(); #ifdef CONFIG_SMP if (is_smp()) { @@ -1015,7 +1020,7 @@ static int __init topology_init(void) for_each_possible_cpu(cpu) { struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu); - cpuinfo->cpu.hotpluggable = 1; + cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu); register_cpu(&cpuinfo->cpu, cpu); } diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 423663e23791..b6cda06b455f 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -562,6 +562,12 @@ static int do_signal(struct pt_regs *regs, int syscall) asmlinkage int do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) { + /* + * The assembly code enters us with IRQs off, but it hasn't + * informed the tracing code of that for efficiency reasons. + * Update the trace code with the current status. + */ + trace_hardirqs_off(); do { if (likely(thread_flags & _TIF_NEED_RESCHED)) { schedule(); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 3d6b7821cff8..48185a773852 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -21,6 +21,7 @@ #include <linux/cpu.h> #include <linux/seq_file.h> #include <linux/irq.h> +#include <linux/nmi.h> #include <linux/percpu.h> #include <linux/clockchips.h> #include <linux/completion.h> @@ -72,6 +73,7 @@ enum ipi_msg_type { IPI_CPU_STOP, IPI_IRQ_WORK, IPI_COMPLETION, + IPI_CPU_BACKTRACE = 15, }; static DECLARE_COMPLETION(cpu_running); @@ -175,13 +177,26 @@ static int platform_cpu_disable(unsigned int cpu) if (smp_ops.cpu_disable) return smp_ops.cpu_disable(cpu); + return 0; +} + +int platform_can_hotplug_cpu(unsigned int cpu) +{ + /* cpu_die must be specified to support hotplug */ + if (!smp_ops.cpu_die) + return 0; + + if (smp_ops.cpu_can_disable) + return smp_ops.cpu_can_disable(cpu); + /* * By default, allow disabling all CPUs except the first one, * since this is special on a lot of platforms, e.g. because * of clock tick interrupts. */ - return cpu == 0 ? -EPERM : 0; + return cpu != 0; } + /* * __cpu_disable runs on the processor to be shutdown. */ @@ -253,7 +268,7 @@ void __cpu_die(unsigned int cpu) * of the other hotplug-cpu capable cores, so presumably coming * out of idle fixes this. */ -void __ref cpu_die(void) +void arch_cpu_idle_dead(void) { unsigned int cpu = smp_processor_id(); @@ -630,6 +645,12 @@ void handle_IPI(int ipinr, struct pt_regs *regs) irq_exit(); break; + case IPI_CPU_BACKTRACE: + irq_enter(); + nmi_cpu_backtrace(regs); + irq_exit(); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); @@ -724,3 +745,13 @@ static int __init register_cpufreq_notifier(void) core_initcall(register_cpufreq_notifier); #endif + +static void raise_nmi(cpumask_t *mask) +{ + smp_cross_call(mask, IPI_CPU_BACKTRACE); +} + +void arch_trigger_all_cpu_backtrace(bool include_self) +{ + nmi_trigger_all_cpu_backtrace(include_self, raise_nmi); +} diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 172c6a05d27f..e9035cda1485 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -36,29 +36,30 @@ static DEFINE_PER_CPU(bool, percpu_setup_called); static struct clock_event_device __percpu *twd_evt; static int twd_ppi; -static void twd_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) +static int twd_shutdown(struct clock_event_device *clk) { - unsigned long ctrl; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE - | TWD_TIMER_CONTROL_PERIODIC; - writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), - twd_base + TWD_TIMER_LOAD); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } + writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); + return 0; +} +static int twd_set_oneshot(struct clock_event_device *clk) +{ + /* period set, and timer enabled in 'next_event' hook */ + writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT, + twd_base + TWD_TIMER_CONTROL); + return 0; +} + +static int twd_set_periodic(struct clock_event_device *clk) +{ + unsigned long ctrl = TWD_TIMER_CONTROL_ENABLE | + TWD_TIMER_CONTROL_IT_ENABLE | + TWD_TIMER_CONTROL_PERIODIC; + + writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), + twd_base + TWD_TIMER_LOAD); writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); + return 0; } static int twd_set_next_event(unsigned long evt, @@ -94,7 +95,7 @@ static void twd_timer_stop(void) { struct clock_event_device *clk = raw_cpu_ptr(twd_evt); - twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk); + twd_shutdown(clk); disable_percpu_irq(clk->irq); } @@ -296,7 +297,10 @@ static void twd_timer_setup(void) clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; clk->rating = 350; - clk->set_mode = twd_set_mode; + clk->set_state_shutdown = twd_shutdown; + clk->set_state_periodic = twd_set_periodic; + clk->set_state_oneshot = twd_set_oneshot; + clk->tick_resume = twd_shutdown; clk->set_next_event = twd_set_next_event; clk->irq = twd_ppi; clk->cpumask = cpumask_of(cpu); diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index 1361756782c7..5b26e7efa9ea 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -141,11 +141,14 @@ static int emulate_swpX(unsigned int address, unsigned int *data, while (1) { unsigned long temp; + unsigned int __ua_flags; + __ua_flags = uaccess_save_and_enable(); if (type == TYPE_SWPB) __user_swpb_asm(*data, address, res, temp); else __user_swp_asm(*data, address, res, temp); + uaccess_restore(__ua_flags); if (likely(res != -EAGAIN) || signal_pending(current)) break; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index d358226236f2..969f9d9e665f 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -870,7 +870,6 @@ void __init early_trap_init(void *vectors_base) kuser_init(vectors_base); flush_icache_range(vectors, vectors + PAGE_SIZE * 2); - modify_domain(DOMAIN_USER, DOMAIN_CLIENT); #else /* ifndef CONFIG_CPU_V7M */ /* * on V7-M there is no need to copy the vector table to a dedicated diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index bc738d2b8392..ce404a5c3062 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -125,6 +125,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) if (ret) goto out_free_stage2_pgd; + kvm_vgic_early_init(kvm); kvm_timer_init(kvm); /* Mark the initial VMID generation invalid */ @@ -249,6 +250,7 @@ out: void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) { + kvm_vgic_vcpu_early_init(vcpu); } void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) @@ -278,6 +280,8 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) /* Set up the timer */ kvm_timer_vcpu_init(vcpu); + kvm_arm_reset_debug_ptr(vcpu); + return 0; } @@ -301,13 +305,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_arm_set_running_vcpu(NULL); } -int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, - struct kvm_guest_debug *dbg) -{ - return -EINVAL; -} - - int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, struct kvm_mp_state *mp_state) { @@ -528,10 +525,20 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) if (vcpu->arch.pause) vcpu_pause(vcpu); - kvm_vgic_flush_hwstate(vcpu); + /* + * Disarming the background timer must be done in a + * preemptible context, as this call may sleep. + */ kvm_timer_flush_hwstate(vcpu); + /* + * Preparing the interrupts to be injected also + * involves poking the GIC, which must be done in a + * non-preemptible context. + */ preempt_disable(); + kvm_vgic_flush_hwstate(vcpu); + local_irq_disable(); /* @@ -544,12 +551,14 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) { local_irq_enable(); + kvm_vgic_sync_hwstate(vcpu); preempt_enable(); kvm_timer_sync_hwstate(vcpu); - kvm_vgic_sync_hwstate(vcpu); continue; } + kvm_arm_setup_debug(vcpu); + /************************************************************** * Enter the guest */ @@ -564,6 +573,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) * Back from guest *************************************************************/ + kvm_arm_clear_debug(vcpu); + /* * We may have taken a host interrupt in HYP mode (ie * while executing the guest). This interrupt is still @@ -586,11 +597,12 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) */ kvm_guest_exit(); trace_kvm_exit(kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu)); - preempt_enable(); + kvm_vgic_sync_hwstate(vcpu); + + preempt_enable(); kvm_timer_sync_hwstate(vcpu); - kvm_vgic_sync_hwstate(vcpu); ret = handle_exit(vcpu, run, ret); } @@ -921,6 +933,8 @@ static void cpu_init_hyp_mode(void *dummy) vector_ptr = (unsigned long)__kvm_hyp_vector; __cpu_init_hyp_mode(boot_pgd_ptr, pgd_ptr, hyp_stack_ptr, vector_ptr); + + kvm_arm_init_debug(); } static int hyp_init_cpu_notify(struct notifier_block *self, diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index d503fbb787d3..96e935bbc38c 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -290,3 +290,9 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, { return -EINVAL; } + +int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, + struct kvm_guest_debug *dbg) +{ + return -EINVAL; +} diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index 568494dbbbb5..900ef6dd8f72 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -361,10 +361,6 @@ hyp_hvc: @ Check syndrome register mrc p15, 4, r1, c5, c2, 0 @ HSR lsr r0, r1, #HSR_EC_SHIFT -#ifdef CONFIG_VFPv3 - cmp r0, #HSR_EC_CP_0_13 - beq switch_to_guest_vfp -#endif cmp r0, #HSR_EC_HVC bne guest_trap @ Not HVC instr. @@ -378,7 +374,10 @@ hyp_hvc: cmp r2, #0 bne guest_trap @ Guest called HVC -host_switch_to_hyp: + /* + * Getting here means host called HVC, we shift parameters and branch + * to Hyp function. + */ pop {r0, r1, r2} /* Check for __hyp_get_vectors */ @@ -409,6 +408,10 @@ guest_trap: @ Check if we need the fault information lsr r1, r1, #HSR_EC_SHIFT +#ifdef CONFIG_VFPv3 + cmp r1, #HSR_EC_CP_0_13 + beq switch_to_guest_vfp +#endif cmp r1, #HSR_EC_IABT mrceq p15, 4, r2, c6, c0, 2 @ HIFAR beq 2f @@ -477,7 +480,6 @@ guest_trap: */ #ifdef CONFIG_VFPv3 switch_to_guest_vfp: - load_vcpu @ Load VCPU pointer to r0 push {r3-r7} @ NEON/VFP used. Turn on VFP access. diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c index f558c073c023..eeb85858d6bb 100644 --- a/arch/arm/kvm/reset.c +++ b/arch/arm/kvm/reset.c @@ -77,7 +77,5 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) kvm_reset_coprocs(vcpu); /* Reset arch_timer context */ - kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq); - - return 0; + return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq); } diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S index 1710fd7db2d5..970d6c043774 100644 --- a/arch/arm/lib/clear_user.S +++ b/arch/arm/lib/clear_user.S @@ -12,14 +12,14 @@ .text -/* Prototype: int __clear_user(void *addr, size_t sz) +/* Prototype: unsigned long arm_clear_user(void *addr, size_t sz) * Purpose : clear some user memory * Params : addr - user memory address to clear * : sz - number of bytes to clear * Returns : number of bytes NOT cleared */ ENTRY(__clear_user_std) -WEAK(__clear_user) +WEAK(arm_clear_user) stmfd sp!, {r1, lr} mov r2, #0 cmp r1, #4 @@ -44,7 +44,7 @@ WEAK(__clear_user) USER( strnebt r2, [r0]) mov r0, #0 ldmfd sp!, {r1, pc} -ENDPROC(__clear_user) +ENDPROC(arm_clear_user) ENDPROC(__clear_user_std) .pushsection .text.fixup,"ax" diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index 7a235b9952be..1512bebfbf1b 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -17,7 +17,7 @@ /* * Prototype: * - * size_t __copy_from_user(void *to, const void *from, size_t n) + * size_t arm_copy_from_user(void *to, const void *from, size_t n) * * Purpose: * @@ -89,11 +89,11 @@ .text -ENTRY(__copy_from_user) +ENTRY(arm_copy_from_user) #include "copy_template.S" -ENDPROC(__copy_from_user) +ENDPROC(arm_copy_from_user) .pushsection .fixup,"ax" .align 0 diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S index 9648b0675a3e..caf5019d8161 100644 --- a/arch/arm/lib/copy_to_user.S +++ b/arch/arm/lib/copy_to_user.S @@ -17,7 +17,7 @@ /* * Prototype: * - * size_t __copy_to_user(void *to, const void *from, size_t n) + * size_t arm_copy_to_user(void *to, const void *from, size_t n) * * Purpose: * @@ -93,11 +93,11 @@ .text ENTRY(__copy_to_user_std) -WEAK(__copy_to_user) +WEAK(arm_copy_to_user) #include "copy_template.S" -ENDPROC(__copy_to_user) +ENDPROC(arm_copy_to_user) ENDPROC(__copy_to_user_std) .pushsection .text.fixup,"ax" diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index 1d0957e61f89..1712f132b80d 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -17,6 +17,19 @@ .text +#ifdef CONFIG_CPU_SW_DOMAIN_PAN + .macro save_regs + mrc p15, 0, ip, c3, c0, 0 + stmfd sp!, {r1, r2, r4 - r8, ip, lr} + uaccess_enable ip + .endm + + .macro load_regs + ldmfd sp!, {r1, r2, r4 - r8, ip, lr} + mcr p15, 0, ip, c3, c0, 0 + ret lr + .endm +#else .macro save_regs stmfd sp!, {r1, r2, r4 - r8, lr} .endm @@ -24,6 +37,7 @@ .macro load_regs ldmfd sp!, {r1, r2, r4 - r8, pc} .endm +#endif .macro load1b, reg1 ldrusr \reg1, r0, 1 diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 4b39af2dfda9..d72b90905132 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -136,7 +136,7 @@ out: } unsigned long -__copy_to_user(void __user *to, const void *from, unsigned long n) +arm_copy_to_user(void __user *to, const void *from, unsigned long n) { /* * This test is stubbed out of the main function above to keep @@ -190,7 +190,7 @@ out: return n; } -unsigned long __clear_user(void __user *addr, unsigned long n) +unsigned long arm_clear_user(void __user *addr, unsigned long n) { /* See rational for this in __copy_to_user() above. */ if (n < 64) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index fd95f34945f4..89a755b90db2 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -8,6 +8,18 @@ menuconfig ARCH_AT91 select SOC_BUS if ARCH_AT91 +config SOC_SAMA5D2 + bool "SAMA5D2 family" if ARCH_MULTI_V7 + select SOC_SAMA5 + select CACHE_L2X0 + select HAVE_FB_ATMEL + select HAVE_AT91_UTMI + select HAVE_AT91_USB_CLK + select HAVE_AT91_H32MX + select HAVE_AT91_GENERATED_CLK + help + Select this if ou are using one of Atmel's SAMA5D2 family SoC. + config SOC_SAMA5D3 bool "SAMA5D3 family" if ARCH_MULTI_V7 select SOC_SAMA5 diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index eaf58f88ef5d..c1a7c6cc00e1 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -8,7 +8,6 @@ * Licensed under GPLv2 or later. */ -#include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_platform.h> @@ -38,7 +37,7 @@ static void __init at91rm9200_dt_device_init(void) at91rm9200_pm_init(); } -static const char *at91rm9200_dt_board_compat[] __initconst = { +static const char *const at91rm9200_dt_board_compat[] __initconst = { "atmel,at91rm9200", NULL }; diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c index e47a2093a0e7..7eb64f763034 100644 --- a/arch/arm/mach-at91/at91sam9.c +++ b/arch/arm/mach-at91/at91sam9.c @@ -72,7 +72,7 @@ static void __init at91sam9_dt_device_init(void) at91sam9260_pm_init(); } -static const char *at91_dt_board_compat[] __initconst = { +static const char *const at91_dt_board_compat[] __initconst = { "atmel,at91sam9", NULL }; @@ -89,7 +89,7 @@ static void __init at91sam9g45_dt_device_init(void) at91sam9g45_pm_init(); } -static const char *at91sam9g45_board_compat[] __initconst = { +static const char *const at91sam9g45_board_compat[] __initconst = { "atmel,at91sam9g45", NULL }; @@ -106,7 +106,7 @@ static void __init at91sam9x5_dt_device_init(void) at91sam9x5_pm_init(); } -static const char *at91sam9x5_board_compat[] __initconst = { +static const char *const at91sam9x5_board_compat[] __initconst = { "atmel,at91sam9x5", "atmel,at91sam9n12", NULL diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index e24df77abd79..80e277cfcc8b 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -311,7 +311,7 @@ static void at91sam9_sdram_standby(void) at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); } -static const struct of_device_id ramc_ids[] __initconst = { +static const struct of_device_id const ramc_ids[] __initconst = { { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, @@ -369,7 +369,7 @@ static void __init at91_pm_sram_init(void) return; } - sram_pool = gen_pool_get(&pdev->dev); + sram_pool = gen_pool_get(&pdev->dev, NULL); if (!sram_pool) { pr_warn("%s: sram pool unavailable!\n", __func__); return; diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index 41d829d8e7d5..d9cf6799aec0 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -18,6 +18,8 @@ #include "soc.h" static const struct at91_soc sama5_socs[] = { + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27_EXID_MATCH, + "sama5d27", "sama5d2"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, "sama5d31", "sama5d3"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, @@ -52,7 +54,7 @@ static void __init sama5_dt_device_init(void) at91sam9x5_pm_init(); } -static const char *sama5_dt_board_compat[] __initconst = { +static const char *const sama5_dt_board_compat[] __initconst = { "atmel,sama5", NULL }; @@ -63,7 +65,8 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5") .dt_compat = sama5_dt_board_compat, MACHINE_END -static const char *sama5_alt_dt_board_compat[] __initconst = { +static const char *const sama5_alt_dt_board_compat[] __initconst = { + "atmel,sama5d2", "atmel,sama5d4", NULL }; diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index be23c400596b..8ede0ef86172 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -62,6 +62,9 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 +#define SAMA5D2_CIDR_MATCH 0x0a5c08c0 +#define SAMA5D27_EXID_MATCH 0x00000021 + #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 #define SAMA5D31_EXID_MATCH 0x00444300 #define SAMA5D33_EXID_MATCH 0x00414300 diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 0ac9e4b3b265..1319c3c14327 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -140,10 +140,12 @@ config ARCH_BCM_63XX config ARCH_BRCMSTB bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7 select ARM_GIC + select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select BRCMSTB_GISB_ARB select BRCMSTB_L2_IRQ select BCM7120_L2_IRQ + select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE select ARCH_WANT_OPTIONAL_GPIOLIB help Say Y if you intend to run the kernel on a Broadcom ARM-based STB diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 4fb0da458e91..1780a3ff42f9 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -39,10 +39,8 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o # BCM63XXx ifeq ($(CONFIG_ARCH_BCM_63XX),y) -CFLAGS_bcm63xx_headsmp.o += -march=armv7-a obj-y += bcm63xx.o -obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_headsmp.o \ - bcm63xx_pmb.o +obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o endif ifeq ($(CONFIG_ARCH_BRCMSTB),y) diff --git a/arch/arm/mach-bcm/bcm63xx_headsmp.S b/arch/arm/mach-bcm/bcm63xx_headsmp.S deleted file mode 100644 index c7af397c7f14..000000000000 --- a/arch/arm/mach-bcm/bcm63xx_headsmp.S +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2015, Broadcom Corporation - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/assembler.h> - -ENTRY(bcm63138_secondary_startup) - ARM_BE8(setend be) - /* - * L1 cache does have unpredictable contents at power-up clean its - * contents without flushing - */ - bl v7_invalidate_l1 - nop - - b secondary_startup -ENDPROC(bcm63138_secondary_startup) diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c index 3f014f18cea5..19be90421f4d 100644 --- a/arch/arm/mach-bcm/bcm63xx_smp.c +++ b/arch/arm/mach-bcm/bcm63xx_smp.c @@ -127,7 +127,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu, } /* Locate the secondary CPU node */ - dn = of_get_cpu_node(cpu_logical_map(cpu), NULL); + dn = of_get_cpu_node(cpu, NULL); if (!dn) { pr_err("SMP: failed to locate secondary CPU%d node\n", cpu); ret = -ENODEV; @@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu, } /* Write the secondary init routine to the BootLUT reset vector */ - val = virt_to_phys(bcm63138_secondary_startup); + val = virt_to_phys(secondary_startup); writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT); /* Power up the core, will jump straight to its reset vector when we diff --git a/arch/arm/mach-bcm/bcm63xx_smp.h b/arch/arm/mach-bcm/bcm63xx_smp.h index 50b76044536e..9c6d50e2b111 100644 --- a/arch/arm/mach-bcm/bcm63xx_smp.h +++ b/arch/arm/mach-bcm/bcm63xx_smp.h @@ -3,7 +3,6 @@ struct device_node; -extern void bcm63138_secondary_startup(void); extern int bcm63xx_pmb_power_on_cpu(struct device_node *dn); #endif /* __BCM63XX_SMP_H */ diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c index 7aef92720eb4..5478fe6bcce6 100644 --- a/arch/arm/mach-bcm/bcm_5301x.c +++ b/arch/arm/mach-bcm/bcm_5301x.c @@ -44,7 +44,7 @@ static void __init bcm5301x_init_early(void) "imprecise external abort"); } -static const char __initconst *bcm5301x_dt_compat[] = { +static const char *const bcm5301x_dt_compat[] __initconst = { "brcm,bcm4708", NULL, }; diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index a55a7ecf146a..cf3f8658f0e5 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -33,7 +33,7 @@ struct bcm_kona_smc_data { unsigned result; }; -static const struct of_device_id bcm_kona_smc_ids[] __initconst = { +static const struct of_device_id const bcm_kona_smc_ids[] __initconst = { {.compatible = "brcm,kona-smc"}, {.compatible = "bcm,kona-smc"}, /* deprecated name */ {}, diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index 45abf6bd5f68..c3d964221767 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -160,7 +160,7 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = { }, }; -static const struct gpio autcpu12_gpios[] __initconst = { +static const struct gpio const autcpu12_gpios[] __initconst = { { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" }, { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" }, { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" }, diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index 1ec378c334e5..972abdb10028 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c @@ -95,7 +95,7 @@ static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = { static struct resource cdb89712_bootrom_resources[] __initdata = { DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM | - IORESOURCE_CACHEABLE | IORESOURCE_READONLY), + IORESOURCE_READONLY), }; static struct platform_device cdb89712_bootrom_pdev __initdata = { diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 4e9837ded96d..9b1dc223d8d3 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -113,30 +113,33 @@ void cns3xxx_power_off(void) */ static void __iomem *cns3xxx_tmr1; -static void cns3xxx_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) +static int cns3xxx_shutdown(struct clock_event_device *clk) +{ + writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + return 0; +} + +static int cns3xxx_set_oneshot(struct clock_event_device *clk) +{ + unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + + /* period set, and timer enabled in 'next_event' hook */ + ctrl |= (1 << 2) | (1 << 9); + writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + return 0; +} + +static int cns3xxx_set_periodic(struct clock_event_device *clk) { unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); int pclk = cns3xxx_cpu_clock() / 8; int reload; - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - reload = pclk * 20 / (3 * HZ) * 0x25000; - writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - ctrl |= (1 << 0) | (1 << 2) | (1 << 9); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl |= (1 << 2) | (1 << 9); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - + reload = pclk * 20 / (3 * HZ) * 0x25000; + writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 0) | (1 << 2) | (1 << 9); writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + return 0; } static int cns3xxx_timer_set_next_event(unsigned long evt, @@ -151,12 +154,16 @@ static int cns3xxx_timer_set_next_event(unsigned long evt, } static struct clock_event_device cns3xxx_tmr1_clockevent = { - .name = "cns3xxx timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = cns3xxx_timer_set_mode, - .set_next_event = cns3xxx_timer_set_next_event, - .rating = 350, - .cpumask = cpu_all_mask, + .name = "cns3xxx timer1", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = cns3xxx_shutdown, + .set_state_periodic = cns3xxx_set_periodic, + .set_state_oneshot = cns3xxx_set_oneshot, + .tick_resume = cns3xxx_shutdown, + .set_next_event = cns3xxx_timer_set_next_event, + .rating = 350, + .cpumask = cpu_all_mask, }; static void __init cns3xxx_clockevents_init(unsigned int timer_irq) @@ -339,7 +346,7 @@ static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { .power_off = csn3xxx_usb_power_off, }; -static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { +static const struct of_dev_auxdata const cns3xxx_auxdata[] __initconst = { { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, @@ -392,7 +399,7 @@ static void __init cns3xxx_init(void) cns3xxx_auxdata, NULL); } -static const char *cns3xxx_dt_compat[] __initdata = { +static const char *const cns3xxx_dt_compat[] __initconst = { "cavium,cns3410", "cavium,cns3420", NULL, diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 006dae8dfe44..507aad4b8dd9 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -85,23 +85,13 @@ static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) return 0; } -/* - * Faking this allows us to to work with suspend functions of - * generic drivers which call {enable|disable}_irq_wake for - * wake up interrupt sources (eg RTC on DA850). - */ -static int cp_intc_set_wake(struct irq_data *d, unsigned int on) -{ - return 0; -} - static struct irq_chip cp_intc_irq_chip = { .name = "cp_intc", .irq_ack = cp_intc_ack_irq, .irq_mask = cp_intc_mask_irq, .irq_unmask = cp_intc_unmask_irq, .irq_set_type = cp_intc_set_irq_type, - .irq_set_wake = cp_intc_set_wake, + .flags = IRQCHIP_SKIP_SET_WAKE, }; static struct irq_domain *cp_intc_domain; @@ -112,7 +102,7 @@ static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); irq_set_chip(virq, &cp_intc_irq_chip); - set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + irq_set_probe(virq); irq_set_handler(virq, handle_edge_irq); return 0; } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 3b8740c083c4..676997895e13 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -715,7 +715,7 @@ const short da850_lcdcntl_pins[] __initconst = { -1 }; -const short da850_vpif_capture_pins[] __initdata = { +const short da850_vpif_capture_pins[] __initconst = { DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, @@ -725,7 +725,7 @@ const short da850_vpif_capture_pins[] __initdata = { -1 }; -const short da850_vpif_display_pins[] __initdata = { +const short da850_vpif_display_pins[] __initconst = { DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 438f68547f4c..06b6451225c1 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -20,7 +20,7 @@ #define DA8XX_NUM_UARTS 3 -static const struct of_device_id da8xx_irq_match[] __initconst = { +static const struct of_device_id const da8xx_irq_match[] __initconst = { { .compatible = "ti,cp-intc", .data = cp_intc_of_init, }, { } }; @@ -59,7 +59,7 @@ static void __init da850_init_machine(void) } -static const char *da850_boards_compat[] __initdata = { +static const char *const da850_boards_compat[] __initconst = { "enbw,cmc", "ti,da850-evm", "ti,da850", diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index ddfdd820e6f2..29e08aac8294 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -1010,11 +1010,13 @@ static struct davinci_spi_platform_data da8xx_spi_pdata[] = { .version = SPI_VERSION_2, .intr_line = 1, .dma_event_q = EVENTQ_0, + .prescaler_limit = 2, }, [1] = { .version = SPI_VERSION_2, .intr_line = 1, .dma_event_q = EVENTQ_0, + .prescaler_limit = 2, }, }; diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 9cbeda798584..567dc56fe8cd 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -411,6 +411,7 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = { .num_chipselect = 2, .cshold_bug = true, .dma_event_q = EVENTQ_1, + .prescaler_limit = 1, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index e3a3c54b6832..6a890a8486d0 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -646,6 +646,7 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, .dma_event_q = EVENTQ_3, + .prescaler_limit = 1, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 160c9602f490..6c18445a4639 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -303,36 +303,42 @@ static int davinci_set_next_event(unsigned long cycles, return 0; } -static void davinci_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int davinci_shutdown(struct clock_event_device *evt) { struct timer_s *t = &timers[TID_CLOCKEVENT]; - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - t->period = davinci_clock_tick_rate / (HZ); - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_PERIODIC; - timer32_config(t); - break; - case CLOCK_EVT_MODE_ONESHOT: - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_ONESHOT; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_DISABLED; - break; - case CLOCK_EVT_MODE_RESUME: - break; - } + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_DISABLED; + return 0; +} + +static int davinci_set_oneshot(struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_ONESHOT; + return 0; +} + +static int davinci_set_periodic(struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + t->period = davinci_clock_tick_rate / (HZ); + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_PERIODIC; + timer32_config(t); + return 0; } static struct clock_event_device clockevent_davinci = { - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = davinci_set_next_event, - .set_mode = davinci_set_mode, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = davinci_set_next_event, + .set_state_shutdown = davinci_shutdown, + .set_state_periodic = davinci_set_periodic, + .set_state_oneshot = davinci_set_oneshot, }; diff --git a/arch/arm/mach-digicolor/digicolor.c b/arch/arm/mach-digicolor/digicolor.c index cfc88d1caa47..4d62f1bde4ed 100644 --- a/arch/arm/mach-digicolor/digicolor.c +++ b/arch/arm/mach-digicolor/digicolor.c @@ -8,7 +8,7 @@ #include <asm/mach/arch.h> -static const char *digicolor_dt_compat[] __initconst = { +static const char *const digicolor_dt_compat[] __initconst = { "cnxt,cx92755", NULL, }; diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index df0223f76fa9..305d7c6242bb 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -69,8 +69,9 @@ static struct irq_chip pmu_irq_chip = { .irq_ack = pmu_irq_ack, }; -static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) +static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); unsigned long cause = readl(PMU_INTERRUPT_CAUSE); cause &= readl(PMU_INTERRUPT_MASK); @@ -172,7 +173,7 @@ void __init dove_init_irq(void) for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); } diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 8254e716b095..688e5fed49a7 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -65,7 +65,7 @@ static void __init ebsa110_init_irq(void) for (irq = 0; irq < NR_IRQS; irq++) { irq_set_chip_and_handler(irq, &ebsa110_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } } diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index bec570ae6494..61a75ca3684e 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -15,45 +15,8 @@ config CRUNCH comment "EP93xx Platforms" -choice - prompt "EP93xx first SDRAM bank selection" - default EP93XX_SDCE3_SYNC_PHYS_OFFSET - -config EP93XX_SDCE3_SYNC_PHYS_OFFSET - bool "0x00000000 - SDCE3/SyncBoot" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0x00000000. - -config EP93XX_SDCE0_PHYS_OFFSET - bool "0xc0000000 - SDCEO" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0xc0000000. - -config EP93XX_SDCE1_PHYS_OFFSET - bool "0xd0000000 - SDCE1" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0xd0000000. - -config EP93XX_SDCE2_PHYS_OFFSET - bool "0xe0000000 - SDCE2" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0xe0000000. - -config EP93XX_SDCE3_ASYNC_PHYS_OFFSET - bool "0xf0000000 - SDCE3/AsyncBoot" - help - Select this option if you want support for EP93xx boards with the - first SDRAM bank at 0xf0000000. - -endchoice - config MACH_ADSSPHERE bool "Support ADS Sphere" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the ADS Sphere board. @@ -63,7 +26,6 @@ config MACH_EDB93XX config MACH_EDB9301 bool "Support Cirrus Logic EDB9301" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -71,7 +33,6 @@ config MACH_EDB9301 config MACH_EDB9302 bool "Support Cirrus Logic EDB9302" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -79,7 +40,6 @@ config MACH_EDB9302 config MACH_EDB9302A bool "Support Cirrus Logic EDB9302A" - depends on EP93XX_SDCE0_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -87,7 +47,6 @@ config MACH_EDB9302A config MACH_EDB9307 bool "Support Cirrus Logic EDB9307" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -95,7 +54,6 @@ config MACH_EDB9307 config MACH_EDB9307A bool "Support Cirrus Logic EDB9307A" - depends on EP93XX_SDCE0_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -103,7 +61,6 @@ config MACH_EDB9307A config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -111,7 +68,6 @@ config MACH_EDB9312 config MACH_EDB9315 bool "Support Cirrus Logic EDB9315" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus @@ -119,14 +75,12 @@ config MACH_EDB9315 config MACH_EDB9315A bool "Support Cirrus Logic EDB9315A" - depends on EP93XX_SDCE0_PHYS_OFFSET select MACH_EDB93XX help Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315A Evaluation Board. config MACH_GESBC9312 - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET bool "Support Glomation GESBC-9312-sx" help Say 'Y' here if you want your kernel to support the Glomation @@ -137,7 +91,6 @@ config MACH_MICRO9 config MACH_MICRO9H bool "Support Contec Micro9-High" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_MICRO9 help Say 'Y' here if you want your kernel to support the @@ -145,7 +98,6 @@ config MACH_MICRO9H config MACH_MICRO9M bool "Support Contec Micro9-Mid" - depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET select MACH_MICRO9 help Say 'Y' here if you want your kernel to support the @@ -153,7 +105,6 @@ config MACH_MICRO9M config MACH_MICRO9L bool "Support Contec Micro9-Lite" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET select MACH_MICRO9 help Say 'Y' here if you want your kernel to support the @@ -161,7 +112,6 @@ config MACH_MICRO9L config MACH_MICRO9S bool "Support Contec Micro9-Slim" - depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET select MACH_MICRO9 help Say 'Y' here if you want your kernel to support the @@ -169,28 +119,24 @@ config MACH_MICRO9S config MACH_SIM_ONE bool "Support Simplemachines Sim.One board" - depends on EP93XX_SDCE0_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the Simplemachines Sim.One board. config MACH_SNAPPER_CL15 bool "Support Bluewater Systems Snapper CL15 Module" - depends on EP93XX_SDCE0_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the Bluewater Systems Snapper CL15 Module. config MACH_TS72XX bool "Support Technologic Systems TS-72xx SBC" - depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the Technologic Systems TS-72xx board. config MACH_VISION_EP9307 bool "Support Vision Engraving Systems EP9307 SoM" - depends on EP93XX_SDCE0_PHYS_OFFSET help Say 'Y' here if you want your kernel to support the Vision Engraving Systems EP9307 SoM. diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 78d427b34b1f..b7ae4345ac08 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -1,7 +1,7 @@ # # Makefile for the linux kernel. # -obj-y := core.o clock.o +obj-y := core.o clock.o timer-ep93xx.o obj-$(CONFIG_EP93XX_DMA) += dma.o diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot index d3113a71cb40..ed82ed7c949f 100644 --- a/arch/arm/mach-ep93xx/Makefile.boot +++ b/arch/arm/mach-ep93xx/Makefile.boot @@ -1,14 +1 @@ - zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) += 0x00008000 -params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00000100 - - zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) += 0xc0008000 -params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0000100 - - zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) += 0xd0008000 -params_phys-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) := 0xd0000100 - - zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) += 0xe0008000 -params_phys-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) := 0xe0000100 - - zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) += 0xf0008000 -params_phys-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) := 0xf0000100 +# Empty file waiting for deletion once Makefile.boot isn't needed any more. diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 0e571f1749d6..c393b1b0310d 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -22,7 +22,6 @@ #include <linux/interrupt.h> #include <linux/dma-mapping.h> #include <linux/sys_soc.h> -#include <linux/timex.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/gpio.h> @@ -38,6 +37,7 @@ #include <linux/irqchip/arm-vic.h> #include <linux/reboot.h> #include <linux/usb/ohci_pdriver.h> +#include <linux/random.h> #include <mach/hardware.h> #include <linux/platform_data/video-ep93xx.h> @@ -47,7 +47,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/time.h> #include "soc.h" @@ -73,113 +72,6 @@ void __init ep93xx_map_io(void) iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); } - -/************************************************************************* - * Timer handling for EP93xx - ************************************************************************* - * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and - * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate - * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, - * is free-running, and can't generate interrupts. - * - * The 508 kHz timers are ideal for use for the timer interrupt, as the - * most common values of HZ divide 508 kHz nicely. We pick one of the 16 - * bit timers (timer 1) since we don't need more than 16 bits of reload - * value as long as HZ >= 8. - * - * The higher clock rate of timer 4 makes it a better choice than the - * other timers for use in gettimeoffset(), while the fact that it can't - * generate interrupts means we don't have to worry about not being able - * to use this timer for something else. We also use timer 4 for keeping - * track of lost jiffies. - */ -#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) -#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) -#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) -#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) -#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) -#define EP93XX_TIMER123_CONTROL_MODE (1 << 6) -#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) -#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) -#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) -#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) -#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) -#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) -#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) -#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) -#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) -#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) -#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) -#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) -#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) - -#define EP93XX_TIMER123_CLOCK 508469 -#define EP93XX_TIMER4_CLOCK 983040 - -#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) -#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ) - -static unsigned int last_jiffy_time; - -static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) -{ - /* Writing any value clears the timer interrupt */ - __raw_writel(1, EP93XX_TIMER1_CLEAR); - - /* Recover lost jiffies */ - while ((signed long) - (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) - >= TIMER4_TICKS_PER_JIFFY) { - last_jiffy_time += TIMER4_TICKS_PER_JIFFY; - timer_tick(); - } - - return IRQ_HANDLED; -} - -static struct irqaction ep93xx_timer_irq = { - .name = "ep93xx timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = ep93xx_timer_interrupt, -}; - -static u32 ep93xx_gettimeoffset(void) -{ - int offset; - - offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; - - /* - * Timer 4 is based on a 983.04 kHz reference clock, - * so dividing by 983040 gives the fraction of a second, - * so dividing by 0.983040 converts to uS. - * Refactor the calculation to avoid overflow. - * Finally, multiply by 1000 to give nS. - */ - return (offset + (53 * offset / 3072)) * 1000; -} - -void __init ep93xx_timer_init(void) -{ - u32 tmode = EP93XX_TIMER123_CONTROL_MODE | - EP93XX_TIMER123_CONTROL_CLKSEL; - - arch_gettimeoffset = ep93xx_gettimeoffset; - - /* Enable periodic HZ timer. */ - __raw_writel(tmode, EP93XX_TIMER1_CONTROL); - __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); - __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER1_CONTROL); - - /* Enable lost jiffy timer. */ - __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); - - setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); -} - - /************************************************************************* * EP93xx IRQ handling *************************************************************************/ @@ -971,6 +863,12 @@ static const char __init *ep93xx_get_soc_id(void) if (id != id2) return "invalid"; + /* Toss the unique ID into the entropy pool */ + add_device_randomness(&id2, 4); + add_device_randomness(&id3, 4); + add_device_randomness(&id4, 4); + add_device_randomness(&id5, 4); + snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id), "%08x%08x%08x%08x", id2, id3, id4, id5); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 27b14ae92c7e..ad92d9f7e4df 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -205,8 +205,6 @@ static void __init edb93xx_register_pwm(void) * EDB93xx framebuffer *************************************************************************/ static struct ep93xxfb_mach_info __initdata edb93xxfb_info = { - .num_modes = EP93XXFB_USE_MODEDB, - .bpp = 16, .flags = 0, }; diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 3c950f5864f3..7bb540c421ee 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -40,8 +40,6 @@ static struct ep93xx_eth_data __initdata simone_eth_data = { }; static struct ep93xxfb_mach_info __initdata simone_fb_info = { - .num_modes = EP93XXFB_USE_MODEDB, - .bpp = 16, .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, }; @@ -169,6 +167,7 @@ static struct spi_board_info simone_spi_devices[] __initdata = { static struct ep93xx_spi_info simone_spi_info __initdata = { .num_chipselect = ARRAY_SIZE(simone_spi_devices), + .use_dma = 1, }; static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = { diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index aa86f86638dd..c4904264256a 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -144,8 +144,6 @@ static struct i2c_board_info __initdata snappercl15_i2c_data[] = { }; static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = { - .num_modes = EP93XXFB_USE_MODEDB, - .bpp = 16, }; static struct platform_device snappercl15_audio_device = { diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c new file mode 100644 index 000000000000..e5f791145bd0 --- /dev/null +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -0,0 +1,143 @@ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/sched_clock.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <asm/mach/time.h> +#include "soc.h" + +/************************************************************************* + * Timer handling for EP93xx + ************************************************************************* + * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and + * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate + * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, + * is free-running, and can't generate interrupts. + * + * The 508 kHz timers are ideal for use for the timer interrupt, as the + * most common values of HZ divide 508 kHz nicely. We pick the 32 bit + * timer (timer 3) to get as long sleep intervals as possible when using + * CONFIG_NO_HZ. + * + * The higher clock rate of timer 4 makes it a better choice than the + * other timers for use as clock source and for sched_clock(), providing + * a stable 40 bit time base. + ************************************************************************* + */ +#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) +#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) +#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) +#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) +#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) +#define EP93XX_TIMER123_CONTROL_MODE (1 << 6) +#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) +#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) +#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) +#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) +#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) +#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) +#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) +#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) +#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) +#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) +#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) +#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) +#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) + +#define EP93XX_TIMER123_RATE 508469 +#define EP93XX_TIMER4_RATE 983040 + +static u64 notrace ep93xx_read_sched_clock(void) +{ + u64 ret; + + ret = readl(EP93XX_TIMER4_VALUE_LOW); + ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); + return ret; +} + +cycle_t ep93xx_clocksource_read(struct clocksource *c) +{ + u64 ret; + + ret = readl(EP93XX_TIMER4_VALUE_LOW); + ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); + return (cycle_t) ret; +} + +static int ep93xx_clkevt_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + /* Default mode: periodic, off, 508 kHz */ + u32 tmode = EP93XX_TIMER123_CONTROL_MODE | + EP93XX_TIMER123_CONTROL_CLKSEL; + + /* Clear timer */ + writel(tmode, EP93XX_TIMER3_CONTROL); + + /* Set next event */ + writel(next, EP93XX_TIMER3_LOAD); + writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, + EP93XX_TIMER3_CONTROL); + return 0; +} + + +static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) +{ + /* Disable timer */ + writel(0, EP93XX_TIMER3_CONTROL); + + return 0; +} + +static struct clock_event_device ep93xx_clockevent = { + .name = "timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = ep93xx_clkevt_shutdown, + .set_state_oneshot = ep93xx_clkevt_shutdown, + .tick_resume = ep93xx_clkevt_shutdown, + .set_next_event = ep93xx_clkevt_set_next_event, + .rating = 300, +}; + +static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* Writing any value clears the timer interrupt */ + writel(1, EP93XX_TIMER3_CLEAR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction ep93xx_timer_irq = { + .name = "ep93xx timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = ep93xx_timer_interrupt, + .dev_id = &ep93xx_clockevent, +}; + +void __init ep93xx_timer_init(void) +{ + /* Enable and register clocksource and sched_clock on timer 4 */ + writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, + EP93XX_TIMER4_VALUE_HIGH); + clocksource_mmio_init(NULL, "timer4", + EP93XX_TIMER4_RATE, 200, 40, + ep93xx_clocksource_read); + sched_clock_register(ep93xx_read_sched_clock, 40, + EP93XX_TIMER4_RATE); + + /* Set up clockevent on timer 3 */ + setup_irq(IRQ_EP93XX_TIMER3, &ep93xx_timer_irq); + clockevents_config_and_register(&ep93xx_clockevent, + EP93XX_TIMER123_RATE, + 1, + 0xffffffffU); +} diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index 6bc1c181581d..5cced5988498 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -29,6 +29,8 @@ #include <linux/spi/mmc_spi.h> #include <linux/mmc/host.h> +#include <sound/cs4271.h> + #include <mach/hardware.h> #include <linux/platform_data/video-ep93xx.h> #include <linux/platform_data/spi-ep93xx.h> @@ -104,8 +106,6 @@ static void vision_lcd_blank(int blank_mode, struct fb_info *info) } static struct ep93xxfb_mach_info ep93xxfb_info __initdata = { - .num_modes = EP93XXFB_USE_MODEDB, - .bpp = 16, .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, .setup = vision_lcd_setup, .teardown = vision_lcd_teardown, @@ -169,6 +169,35 @@ static struct i2c_board_info vision_i2c_info[] __initdata = { }; /************************************************************************* + * SPI CS4271 Audio Codec + *************************************************************************/ +static struct cs4271_platform_data vision_cs4271_data = { + .gpio_nreset = EP93XX_GPIO_LINE_H(2), +}; + +static int vision_cs4271_hw_setup(struct spi_device *spi) +{ + return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6, + GPIOF_OUT_INIT_HIGH, spi->modalias); +} + +static void vision_cs4271_hw_cleanup(struct spi_device *spi) +{ + gpio_free(EP93XX_GPIO_LINE_EGPIO6); +} + +static void vision_cs4271_hw_cs_control(struct spi_device *spi, int value) +{ + gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value); +} + +static struct ep93xx_spi_chip_ops vision_cs4271_hw = { + .setup = vision_cs4271_hw_setup, + .cleanup = vision_cs4271_hw_cleanup, + .cs_control = vision_cs4271_hw_cs_control, +}; + +/************************************************************************* * SPI Flash *************************************************************************/ #define VISION_SPI_FLASH_CS EP93XX_GPIO_LINE_EGPIO7 @@ -262,12 +291,20 @@ static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = { *************************************************************************/ static struct spi_board_info vision_spi_board_info[] __initdata = { { + .modalias = "cs4271", + .platform_data = &vision_cs4271_data, + .controller_data = &vision_cs4271_hw, + .max_speed_hz = 6000000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_3, + }, { .modalias = "sst25l", .platform_data = &vision_spi_flash_data, .controller_data = &vision_spi_flash_hw, .max_speed_hz = 20000000, .bus_num = 0, - .chip_select = 0, + .chip_select = 1, .mode = SPI_MODE_3, }, { .modalias = "mmc_spi", @@ -275,16 +312,31 @@ static struct spi_board_info vision_spi_board_info[] __initdata = { .controller_data = &vision_spi_mmc_hw, .max_speed_hz = 20000000, .bus_num = 0, - .chip_select = 1, + .chip_select = 2, .mode = SPI_MODE_3, }, }; static struct ep93xx_spi_info vision_spi_master __initdata = { - .num_chipselect = ARRAY_SIZE(vision_spi_board_info), + .num_chipselect = ARRAY_SIZE(vision_spi_board_info), + .use_dma = 1, }; /************************************************************************* + * I2S Audio + *************************************************************************/ +static struct platform_device vision_audio_device = { + .name = "edb93xx-audio", + .id = -1, +}; + +static void __init vision_register_i2s(void) +{ + ep93xx_register_i2s(); + platform_device_register(&vision_audio_device); +} + +/************************************************************************* * Machine Initialization *************************************************************************/ static void __init vision_init_machine(void) @@ -309,6 +361,7 @@ static void __init vision_init_machine(void) ARRAY_SIZE(vision_i2c_info)); ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, ARRAY_SIZE(vision_spi_board_info)); + vision_register_i2s(); } MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 81064cd61a0a..3a10f1a8317a 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -15,6 +15,7 @@ menuconfig ARCH_EXYNOS select ARM_AMBA select ARM_GIC select COMMON_CLK_SAMSUNG + select EXYNOS_THERMAL select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -24,12 +25,18 @@ menuconfig ARCH_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC select SRAM + select THERMAL select MFD_SYSCON help Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) if ARCH_EXYNOS +config S5P_DEV_MFC + bool + help + Compile in setup memory (init) code for MFC + config ARCH_EXYNOS3 bool "SAMSUNG EXYNOS3" select ARM_CPU_SUSPEND if PM diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index bcefb5473ee4..2f306767cdfe 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -23,3 +23,5 @@ AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec) obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o CFLAGS_mcpm-exynos.o += -march=armv7-a + +obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e3a9256ed55f..153492513c40 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -128,6 +128,12 @@ void exynos_firmware_init(void); /* CPU BOOT mode flag for Exynos3250 SoC bootloader */ #define C2_STATE (1 << 3) +/* + * Magic values for bootloader indicating chosen low power mode. + * See also Documentation/arm/Samsung/Bootloader-interface.txt + */ +#define EXYNOS_SLEEP_MAGIC 0x00000bad +#define EXYNOS_AFTR_MAGIC 0xfcba0d10 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode); void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode); diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 5f8ddcdeeacf..1c47aee31e9c 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -225,7 +225,11 @@ static void __init exynos_init_irq(void) } static const struct of_device_id exynos_cpufreq_matches[] = { + { .compatible = "samsung,exynos3250", .data = "cpufreq-dt" }, { .compatible = "samsung,exynos4210", .data = "cpufreq-dt" }, + { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" }, + { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" }, + { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" }, { /* sentinel */ } }; diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 245f6dec1ded..111cfbf66fdb 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -25,8 +25,6 @@ #include "common.h" #include "smc.h" -#define EXYNOS_SLEEP_MAGIC 0x00000bad -#define EXYNOS_AFTR_MAGIC 0xfcba0d10 #define EXYNOS_BOOT_ADDR 0x8 #define EXYNOS_BOOT_FLAG 0xc diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 58e05a2eae57..98a2c0cbb833 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -182,7 +182,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) boot_reg = cpu_boot_reg_base(); if (!boot_reg) - return ERR_PTR(-ENODEV); + return IOMEM_ERR_PTR(-ENODEV); if (soc_is_exynos4412()) boot_reg += 4*cpu; else if (soc_is_exynos5420() || soc_is_exynos5800()) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index e812c1c85624..de68938ee6aa 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -698,7 +698,7 @@ static void exynos_power_off(void) ; } -void exynos5420_powerdown_conf(enum sys_powerdown mode) +static void exynos5420_powerdown_conf(enum sys_powerdown mode) { u32 this_cluster; @@ -991,7 +991,6 @@ static int exynos_pmu_probe(struct platform_device *pdev) static struct platform_driver exynos_pmu_driver = { .driver = { .name = "exynos-pmu", - .owner = THIS_MODULE, .of_match_table = exynos_pmu_of_device_ids, }, .probe = exynos_pmu_probe, diff --git a/arch/arm/plat-samsung/include/plat/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h index 9b6729c81cda..5c4d4427db7b 100644 --- a/arch/arm/plat-samsung/include/plat/regs-srom.h +++ b/arch/arm/mach-exynos/regs-srom.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h - * +/* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com * diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/mach-exynos/s5p-dev-mfc.c index 0b04b6b0fa30..0b04b6b0fa30 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/mach-exynos/s5p-dev-mfc.c diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index f572219c7a40..e00eb39453a4 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -32,13 +32,11 @@ #include <asm/suspend.h> #include <plat/pm-common.h> -#include <plat/regs-srom.h> #include "common.h" -#include "regs-pmu.h" #include "exynos-pmu.h" - -#define S5P_CHECK_SLEEP 0x00000BAD +#include "regs-pmu.h" +#include "regs-srom.h" #define REG_TABLE_END (-1U) @@ -331,7 +329,7 @@ static void exynos_pm_enter_sleep_mode(void) { /* Set value of power down register for sleep mode */ exynos_sys_powerdown_conf(SYS_SLEEP); - pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); + pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1); } static void exynos_pm_prepare(void) diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 9e8220e38398..0f0c9e040fcc 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -106,7 +106,7 @@ static void __init __fb_init_irq(void) for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } } diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index bf7aa7d298e7..810edc78c817 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -57,34 +57,32 @@ static int ckevt_dc21285_set_next_event(unsigned long delta, return 0; } -static void ckevt_dc21285_set_mode(enum clock_event_mode mode, - struct clock_event_device *c) +static int ckevt_dc21285_shutdown(struct clock_event_device *c) { - switch (mode) { - case CLOCK_EVT_MODE_RESUME: - case CLOCK_EVT_MODE_PERIODIC: - *CSR_TIMER1_CLR = 0; - *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); - *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | - TIMER_CNTL_DIV16; - break; - - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - *CSR_TIMER1_CNTL = 0; - break; - } + *CSR_TIMER1_CNTL = 0; + return 0; +} + +static int ckevt_dc21285_set_periodic(struct clock_event_device *c) +{ + *CSR_TIMER1_CLR = 0; + *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); + *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | + TIMER_CNTL_DIV16; + return 0; } static struct clock_event_device ckevt_dc21285 = { - .name = "dc21285_timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .irq = IRQ_TIMER1, - .set_next_event = ckevt_dc21285_set_next_event, - .set_mode = ckevt_dc21285_set_mode, + .name = "dc21285_timer1", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .irq = IRQ_TIMER1, + .set_next_event = ckevt_dc21285_set_next_event, + .set_state_shutdown = ckevt_dc21285_shutdown, + .set_state_periodic = ckevt_dc21285_set_periodic, + .set_state_oneshot = ckevt_dc21285_shutdown, + .tick_resume = ckevt_dc21285_set_periodic, }; static irqreturn_t timer1_interrupt(int irq, void *dev_id) @@ -94,7 +92,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id) *CSR_TIMER1_CLR = 0; /* Stop the timer if in one-shot mode */ - if (ce->mode == CLOCK_EVT_MODE_ONESHOT) + if (clockevent_state_oneshot(ce)) *CSR_TIMER1_CNTL = 0; ce->event_handler(ce); diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index c3a0abbc9049..fcd79bc3a3e1 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -153,13 +153,13 @@ void __init isa_init_irq(unsigned int host_irq) for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { irq_set_chip_and_handler(irq, &isa_lo_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { irq_set_chip_and_handler(irq, &isa_hi_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } request_resource(&ioport_resource, &pic1_resource); @@ -175,8 +175,8 @@ void __init isa_init_irq(unsigned int host_irq) * resistor on this line. */ if (machine_is_netwinder()) - set_irq_flags(_ISA_IRQ(11), IRQF_VALID | - IRQF_PROBE | IRQF_NOAUTOEN); + irq_modify_status(_ISA_IRQ(11), + IRQ_NOREQUEST | IRQ_NOPROBE, IRQ_NOAUTOEN); } } diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index 3292f2e6ed6f..220333ed741d 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -220,7 +220,7 @@ void __init gemini_gpio_init(void) j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { irq_set_chip_and_handler(j, &gpio_irq_chip, handle_edge_irq); - set_irq_flags(j, IRQF_VALID); + irq_clear_status_flags(j, IRQ_NOREQUEST); } irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler, diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h index 98e7b0f286bf..f0390f184742 100644 --- a/arch/arm/mach-gemini/include/mach/hardware.h +++ b/arch/arm/mach-gemini/include/mach/hardware.h @@ -57,9 +57,6 @@ #define GEMINI_USB1_BASE 0x69000000 #define GEMINI_BIG_ENDIAN_BASE 0x80000000 -#define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE -#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10) -#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20) /* * UART Clock when System clk is 150MHz diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 44f50dcb616d..d929b3ff18fd 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -92,7 +92,7 @@ void __init gemini_init_irq(void) } else { irq_set_handler(i, handle_level_irq); } - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); } /* Disable all interrupts */ diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index 0a63c4d25b64..f5f18df5aacd 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -15,93 +15,147 @@ #include <asm/mach/time.h> #include <linux/clockchips.h> #include <linux/clocksource.h> +#include <linux/sched_clock.h> /* * Register definitions for the timers */ -#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00) -#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04) -#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08) -#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C) -#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30) - -#define TIMER_1_CR_ENABLE (1 << 0) -#define TIMER_1_CR_CLOCK (1 << 1) -#define TIMER_1_CR_INT (1 << 2) -#define TIMER_2_CR_ENABLE (1 << 3) -#define TIMER_2_CR_CLOCK (1 << 4) -#define TIMER_2_CR_INT (1 << 5) -#define TIMER_3_CR_ENABLE (1 << 6) -#define TIMER_3_CR_CLOCK (1 << 7) -#define TIMER_3_CR_INT (1 << 8) + +#define TIMER1_BASE GEMINI_TIMER_BASE +#define TIMER2_BASE (GEMINI_TIMER_BASE + 0x10) +#define TIMER3_BASE (GEMINI_TIMER_BASE + 0x20) + +#define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00) +#define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04) +#define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08) +#define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C) +#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30) +#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34) +#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38) + +#define TIMER_1_CR_ENABLE (1 << 0) +#define TIMER_1_CR_CLOCK (1 << 1) +#define TIMER_1_CR_INT (1 << 2) +#define TIMER_2_CR_ENABLE (1 << 3) +#define TIMER_2_CR_CLOCK (1 << 4) +#define TIMER_2_CR_INT (1 << 5) +#define TIMER_3_CR_ENABLE (1 << 6) +#define TIMER_3_CR_CLOCK (1 << 7) +#define TIMER_3_CR_INT (1 << 8) +#define TIMER_1_CR_UPDOWN (1 << 9) +#define TIMER_2_CR_UPDOWN (1 << 10) +#define TIMER_3_CR_UPDOWN (1 << 11) +#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \ + TIMER_3_CR_ENABLE | \ + TIMER_3_CR_UPDOWN) + +#define TIMER_1_INT_MATCH1 (1 << 0) +#define TIMER_1_INT_MATCH2 (1 << 1) +#define TIMER_1_INT_OVERFLOW (1 << 2) +#define TIMER_2_INT_MATCH1 (1 << 3) +#define TIMER_2_INT_MATCH2 (1 << 4) +#define TIMER_2_INT_OVERFLOW (1 << 5) +#define TIMER_3_INT_MATCH1 (1 << 6) +#define TIMER_3_INT_MATCH2 (1 << 7) +#define TIMER_3_INT_OVERFLOW (1 << 8) +#define TIMER_INT_ALL_MASK 0x1ff + static unsigned int tick_rate; +static u64 notrace gemini_read_sched_clock(void) +{ + return readl(TIMER_COUNT(TIMER3_BASE)); +} + static int gemini_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { u32 cr; - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + /* Setup the match register */ + cr = readl(TIMER_COUNT(TIMER1_BASE)); + writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE)); + if (readl(TIMER_COUNT(TIMER1_BASE)) - cr > cycles) + return -ETIME; - /* This may be overdoing it, feel free to test without this */ - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + return 0; +} - /* Set next event */ - writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +static int gemini_timer_shutdown(struct clock_event_device *evt) +{ + u32 cr; + + /* + * Disable also for oneshot: the set_next() call will arm the timer + * instead. + */ + /* Stop timer and interrupt. */ + cr = readl(TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, TIMER_CR); + + /* Setup counter start from 0 */ + writel(0, TIMER_COUNT(TIMER1_BASE)); + writel(0, TIMER_LOAD(TIMER1_BASE)); + + /* enable interrupt */ + cr = readl(TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_MATCH1; + writel(cr, TIMER_INTR_MASK); + + /* start the timer */ + cr = readl(TIMER_CR); + cr |= TIMER_1_CR_ENABLE; + writel(cr, TIMER_CR); return 0; } -static void gemini_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int gemini_timer_set_periodic(struct clock_event_device *evt) { u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); u32 cr; - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - /* Start the timer */ - writel(period, - TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - writel(period, - TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - /* - * Disable also for oneshot: the set_next() call will - * arm the timer instead. - */ - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - break; - default: - break; - } + /* Stop timer and interrupt */ + cr = readl(TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, TIMER_CR); + + /* Setup timer to fire at 1/HT intervals. */ + cr = 0xffffffff - (period - 1); + writel(cr, TIMER_COUNT(TIMER1_BASE)); + writel(cr, TIMER_LOAD(TIMER1_BASE)); + + /* enable interrupt on overflow */ + cr = readl(TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_OVERFLOW; + writel(cr, TIMER_INTR_MASK); + + /* Start the timer */ + cr = readl(TIMER_CR); + cr |= TIMER_1_CR_ENABLE; + cr |= TIMER_1_CR_INT; + writel(cr, TIMER_CR); + + return 0; } -/* Use TIMER2 as clock event */ +/* Use TIMER1 as clock event */ static struct clock_event_device gemini_clockevent = { - .name = "TIMER2", - .rating = 300, /* Reasonably fast and accurate clock event */ - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = gemini_timer_set_next_event, - .set_mode = gemini_timer_set_mode, + .name = "TIMER1", + /* Reasonably fast and accurate clock event */ + .rating = 300, + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = gemini_timer_set_next_event, + .set_state_shutdown = gemini_timer_shutdown, + .set_state_periodic = gemini_timer_set_periodic, + .set_state_oneshot = gemini_timer_shutdown, + .tick_resume = gemini_timer_shutdown, }; /* @@ -151,20 +205,35 @@ void __init gemini_timer_init(void) } /* - * Make irqs happen for the system timer + * Reset the interrupt mask and status */ - setup_irq(IRQ_TIMER2, &gemini_timer_irq); - - /* Enable and use TIMER1 as clock source */ - writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), - "TIMER1", tick_rate, 300, 32, - clocksource_mmio_readl_up)) - pr_err("timer: failed to initialize gemini clock source\n"); - - /* Configure and register the clockevent */ + writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK); + writel(0, TIMER_INTR_STATE); + writel(TIMER_DEFAULT_FLAGS, TIMER_CR); + + /* + * Setup free-running clocksource timer (interrupts + * disabled.) + */ + writel(0, TIMER_COUNT(TIMER3_BASE)); + writel(0, TIMER_LOAD(TIMER3_BASE)); + writel(0, TIMER_MATCH1(TIMER3_BASE)); + writel(0, TIMER_MATCH2(TIMER3_BASE)); + clocksource_mmio_init(TIMER_COUNT(TIMER3_BASE), + "gemini_clocksource", tick_rate, + 300, 32, clocksource_mmio_readl_up); + sched_clock_register(gemini_read_sched_clock, 32, tick_rate); + + /* + * Setup clockevent timer (interrupt-driven.) + */ + writel(0, TIMER_COUNT(TIMER1_BASE)); + writel(0, TIMER_LOAD(TIMER1_BASE)); + writel(0, TIMER_MATCH1(TIMER1_BASE)); + writel(0, TIMER_MATCH2(TIMER1_BASE)); + setup_irq(IRQ_TIMER1, &gemini_timer_irq); + gemini_clockevent.cpumask = cpumask_of(0); clockevents_config_and_register(&gemini_clockevent, tick_rate, 1, 0xffffffff); + } diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 231fba0d03e5..6050a14faee6 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -28,8 +28,8 @@ #include <linux/reboot.h> #include <linux/amba/bus.h> #include <linux/platform_device.h> +#include <linux/psci.h> -#include <asm/psci.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 7f2bd85eb935..400311695548 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c @@ -16,19 +16,21 @@ #include <linux/cpu_pm.h> #include <linux/init.h> +#include <linux/psci.h> #include <linux/suspend.h> #include <asm/suspend.h> -#include <asm/psci.h> + +#include <uapi/linux/psci.h> + +#define HIGHBANK_SUSPEND_PARAM \ + ((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \ + (1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \ + (PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT)) static int highbank_suspend_finish(unsigned long val) { - const struct psci_power_state ps = { - .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, - .affinity_level = 1, - }; - - return psci_ops.cpu_suspend(ps, __pa(cpu_resume)); + return psci_ops.cpu_suspend(HIGHBANK_SUSPEND_PARAM, __pa(cpu_resume)); } static int highbank_pm_enter(suspend_state_t state) diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c index c6bd7c7bd4aa..8cc62150116a 100644 --- a/arch/arm/mach-hisi/hisilicon.c +++ b/arch/arm/mach-hisi/hisilicon.c @@ -11,7 +11,6 @@ * published by the Free Software Foundation. */ -#include <linux/clk-provider.h> #include <linux/clocksource.h> #include <linux/irqchip.h> diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c index 134377352966..45903be6e7b3 100644 --- a/arch/arm/mach-imx/3ds_debugboard.c +++ b/arch/arm/mach-imx/3ds_debugboard.c @@ -195,7 +195,7 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio) for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); irq_set_chained_handler(p_irq, mxc_expio_irq_handler); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 573536f1bb73..8ceda2844c4f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -548,6 +548,14 @@ config SOC_IMX6SX help This enables support for Freescale i.MX6 SoloX processor. +config SOC_IMX6UL + bool "i.MX6 UltraLite support" + select PINCTRL_IMX6UL + select SOC_IMX6 + + help + This enables support for Freescale i.MX6 UltraLite processor. + config SOC_IMX7D bool "i.MX7 Dual support" select PINCTRL_IMX7D diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 37c502ac9595..fb689d813b09 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -83,6 +83,7 @@ endif obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o ifeq ($(CONFIG_SUSPEND),y) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index a7fa92a7b1d7..5b0f752d5507 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -130,6 +130,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX6Q: soc_id = "i.MX6Q"; break; + case MXC_CPU_IMX6UL: + soc_id = "i.MX6UL"; + break; case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index 074b1a81ba76..08ce20771bb3 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c @@ -57,7 +57,6 @@ #include "hardware.h" static struct clock_event_device clockevent_epit; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; static void __iomem *timer_base; @@ -106,8 +105,8 @@ static int epit_set_next_event(unsigned long evt, return 0; } -static void epit_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +/* Left event sources disabled, no more interrupts appear */ +static int epit_shutdown(struct clock_event_device *evt) { unsigned long flags; @@ -120,39 +119,41 @@ static void epit_set_mode(enum clock_event_mode mode, /* Disable interrupt in GPT module */ epit_irq_disable(); - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - - /* Clear pending interrupt */ - epit_irq_acknowledge(); - } + /* Clear pending interrupt */ + epit_irq_acknowledge(); - /* Remember timer mode */ - clockevent_mode = mode; local_irq_restore(flags); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR "epit_set_mode: Periodic mode is not " - "supported for i.MX EPIT\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: + return 0; +} + +static int epit_set_oneshot(struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call epit_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + epit_irq_disable(); + + /* Clear pending interrupt, only while switching mode */ + if (!clockevent_state_oneshot(evt)) + epit_irq_acknowledge(); + /* * Do not put overhead of interrupt enable/disable into * epit_set_next_event(), the core has about 4 minutes * to call epit_set_next_event() or shutdown clock after * mode switching */ - local_irq_save(flags); - epit_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } + epit_irq_enable(); + local_irq_restore(flags); + + return 0; } /* @@ -176,11 +177,13 @@ static struct irqaction epit_timer_irq = { }; static struct clock_event_device clockevent_epit = { - .name = "epit", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = epit_set_mode, - .set_next_event = epit_set_next_event, - .rating = 200, + .name = "epit", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = epit_shutdown, + .tick_resume = epit_shutdown, + .set_state_oneshot = epit_set_oneshot, + .set_next_event = epit_set_next_event, + .rating = 200, }; static int __init epit_clockevent_init(struct clk *timer_clk) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c new file mode 100644 index 000000000000..1b97fe133cef --- /dev/null +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/irqchip.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/micrel_phy.h> +#include <linux/of_platform.h> +#include <linux/phy.h> +#include <linux/regmap.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +static void __init imx6ul_enet_clk_init(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR, + IMX6UL_GPR1_ENET_CLK_OUTPUT); + else + pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n"); + +} + +static int ksz8081_phy_fixup(struct phy_device *dev) +{ + if (dev && dev->interface == PHY_INTERFACE_MODE_MII) { + phy_write(dev, 0x1f, 0x8110); + phy_write(dev, 0x16, 0x201); + } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) { + phy_write(dev, 0x1f, 0x8190); + phy_write(dev, 0x16, 0x202); + } + + return 0; +} + +static void __init imx6ul_enet_phy_init(void) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, + ksz8081_phy_fixup); +} + +static inline void imx6ul_enet_init(void) +{ + imx6ul_enet_clk_init(); + imx6ul_enet_phy_init(); +} + +static void __init imx6ul_init_machine(void) +{ + struct device *parent; + + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + imx6ul_enet_init(); + imx_anatop_init(); +} + +static void __init imx6ul_init_irq(void) +{ + imx_init_revision_from_anatop(); + imx_src_init(); + irqchip_init(); +} + +static const char *imx6ul_dt_compat[] __initconst = { + "fsl,imx6ul", + NULL, +}; + +DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") + .init_irq = imx6ul_init_irq, + .init_machine = imx6ul_init_machine, + .dt_compat = imx6ul_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 4d4a19099a43..62f3437257f1 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -31,7 +31,7 @@ static void __init imx7d_init_irq(void) irqchip_init(); } -static const char *imx7d_dt_compat[] __initconst = { +static const char *const imx7d_dt_compat[] __initconst = { "fsl,imx7d", NULL, }; diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index d08c37c696f6..2c0853560bd2 100644 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c @@ -238,7 +238,7 @@ static void __init mx31ads_init_expio(void) for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4)); irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index c4436d4fd6fd..a5b1af6d7441 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -38,6 +38,7 @@ #define MXC_CPU_IMX6DL 0x61 #define MXC_CPU_IMX6SX 0x62 #define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX6UL 0x64 #define MXC_CPU_IMX7D 0x72 #define IMX_DDR_TYPE_LPDDR2 1 @@ -165,6 +166,11 @@ static inline bool cpu_is_imx6sx(void) return __mxc_cpu_type == MXC_CPU_IMX6SX; } +static inline bool cpu_is_imx6ul(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6UL; +} + static inline bool cpu_is_imx6q(void) { return __mxc_cpu_type == MXC_CPU_IMX6Q; diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 1885676c23c0..532d4b08276d 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -297,7 +297,7 @@ static int __init imx_suspend_alloc_ocram( goto put_node; } - ocram_pool = gen_pool_get(&pdev->dev); + ocram_pool = gen_pool_get(&pdev->dev, NULL); if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 93ecf559d06d..8ff8fc0b261c 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -451,7 +451,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) goto put_node; } - ocram_pool = gen_pool_get(&pdev->dev); + ocram_pool = gen_pool_get(&pdev->dev, NULL); if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index bc739701c301..623d85a4af2d 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -233,7 +233,7 @@ void __init iop13xx_init_irq(void) irq_set_chip(i, &iop13xx_irqchip4); irq_set_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); } iop13xx_msi_init(); diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d7ee2789d890..2d1f69a68cbc 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -69,6 +69,6 @@ void __init iop32x_init_irq(void) for (i = 0; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); } } diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index f7f5d3e451c7..c99ec8d0d285 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -113,6 +113,6 @@ void __init iop33x_init_irq(void) irq_set_chip_and_handler(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); } } diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 8537d4c41e34..1cb6f2f02880 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -296,7 +296,7 @@ void __init ixp4xx_init_irq(void) for(i = 0; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &ixp4xx_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } } @@ -521,43 +521,55 @@ static int ixp4xx_set_next_event(unsigned long evt, return 0; } -static void ixp4xx_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int ixp4xx_shutdown(struct clock_event_device *evt) { unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK; - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK; - opts = IXP4XX_OST_ENABLE; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set by 'set next_event' */ - osrt = 0; - opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT; - break; - case CLOCK_EVT_MODE_SHUTDOWN: - opts &= ~IXP4XX_OST_ENABLE; - break; - case CLOCK_EVT_MODE_RESUME: - opts |= IXP4XX_OST_ENABLE; - break; - case CLOCK_EVT_MODE_UNUSED: - default: - osrt = opts = 0; - break; - } + opts &= ~IXP4XX_OST_ENABLE; + *IXP4XX_OSRT1 = osrt | opts; + return 0; +} +static int ixp4xx_set_oneshot(struct clock_event_device *evt) +{ + unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT; + unsigned long osrt = 0; + + /* period set by 'set next_event' */ *IXP4XX_OSRT1 = osrt | opts; + return 0; +} + +static int ixp4xx_set_periodic(struct clock_event_device *evt) +{ + unsigned long opts = IXP4XX_OST_ENABLE; + unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK; + + *IXP4XX_OSRT1 = osrt | opts; + return 0; +} + +static int ixp4xx_resume(struct clock_event_device *evt) +{ + unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; + unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK; + + opts |= IXP4XX_OST_ENABLE; + *IXP4XX_OSRT1 = osrt | opts; + return 0; } static struct clock_event_device clockevent_ixp4xx = { - .name = "ixp4xx timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_mode = ixp4xx_set_mode, - .set_next_event = ixp4xx_set_next_event, + .name = "ixp4xx timer1", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_state_shutdown = ixp4xx_shutdown, + .set_state_periodic = ixp4xx_set_periodic, + .set_state_oneshot = ixp4xx_set_oneshot, + .tick_resume = ixp4xx_resume, + .set_next_event = ixp4xx_set_next_event, }; static void __init ixp4xx_clockevent_init(void) diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c index edea697e8253..e283939a216f 100644 --- a/arch/arm/mach-keystone/pm_domain.c +++ b/arch/arm/mach-keystone/pm_domain.c @@ -16,7 +16,6 @@ #include <linux/pm_runtime.h> #include <linux/pm_clock.h> #include <linux/platform_device.h> -#include <linux/clk-provider.h> #include <linux/of.h> static struct dev_pm_domain keystone_pm_domain = { diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 76802aac0f45..31439f2ee21e 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -172,6 +172,6 @@ void __init ks8695_init_irq(void) handle_edge_irq); } - set_irq_flags(irq, IRQF_VALID); + irq_clear_status_flags(irq, IRQ_NOREQUEST); } } diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c index a197874bf382..18eb0fbd8d82 100644 --- a/arch/arm/mach-ks8695/time.c +++ b/arch/arm/mach-ks8695/time.c @@ -54,28 +54,25 @@ /* Timer0 Timeout Counter Register */ #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ -static void ks8695_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int ks8695_set_periodic(struct clock_event_device *evt) { + u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); + u32 half = DIV_ROUND_CLOSEST(rate, 2); u32 tmcon; - if (mode == CLOCK_EVT_FEAT_PERIODIC) { - u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); - u32 half = DIV_ROUND_CLOSEST(rate, 2); - - /* Disable timer 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + /* Disable timer 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - /* Both registers need to count down */ - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); + /* Both registers need to count down */ + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); - /* Re-enable timer1 */ - tmcon |= TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - } + /* Re-enable timer1 */ + tmcon |= TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + return 0; } static int ks8695_set_next_event(unsigned long cycles, @@ -102,11 +99,13 @@ static int ks8695_set_next_event(unsigned long cycles, } static struct clock_event_device clockevent_ks8695 = { - .name = "ks8695_t1tc", - .rating = 300, /* Reasonably fast and accurate clock event */ - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_next_event = ks8695_set_next_event, - .set_mode = ks8695_set_mode, + .name = "ks8695_t1tc", + /* Reasonably fast and accurate clock event */ + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = ks8695_set_next_event, + .set_state_periodic = ks8695_set_periodic, }; /* diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index d4f7dc87042b..cce4cef12b6e 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -283,25 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: /* Rising edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 1); - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: /* Falling edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 1); - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: /* Low level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 0); - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 0); - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); break; /* Other modes are not supported */ @@ -434,7 +434,7 @@ void __init lpc32xx_init_irq(void) for (i = 0; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &lpc32xx_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } /* Set default mappings */ diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 7858d5b6f6ce..77d6b1bab278 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -212,7 +212,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { .dma_filter = pl08x_filter_id, }; -static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { +static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL), OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), @@ -248,7 +248,7 @@ static void __init lpc3250_machine_init(void) lpc32xx_auxdata_lookup, NULL); } -static char const *lpc32xx_dt_compat[] __initdata = { +static const char *const lpc32xx_dt_compat[] __initconst = { "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240", diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 4e5837299c04..ff3499d1fb1a 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -43,36 +43,24 @@ static int lpc32xx_clkevt_next_event(unsigned long delta, return 0; } -static void lpc32xx_clkevt_mode(enum clock_event_mode mode, - struct clock_event_device *dev) +static int lpc32xx_shutdown(struct clock_event_device *evt) { - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - WARN_ON(1); - break; - - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_SHUTDOWN: - /* - * Disable the timer. When using oneshot, we must also - * disable the timer to wait for the first call to - * set_next_event(). - */ - __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - break; - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - break; - } + /* + * Disable the timer. When using oneshot, we must also + * disable the timer to wait for the first call to + * set_next_event(). + */ + __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + return 0; } static struct clock_event_device lpc32xx_clkevt = { - .name = "lpc32xx_clkevt", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = lpc32xx_clkevt_next_event, - .set_mode = lpc32xx_clkevt_mode, + .name = "lpc32xx_clkevt", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_next_event = lpc32xx_clkevt_next_event, + .set_state_shutdown = lpc32xx_shutdown, + .set_state_oneshot = lpc32xx_shutdown, }; static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 9f59e58da3a4..aeece17e5cea 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -3,6 +3,7 @@ menuconfig ARCH_MEDIATEK select ARM_GIC select PINCTRL select MTK_TIMER + select MFD_SYSCON help Support for Mediatek MT65xx & MT81xx SoCs diff --git a/arch/arm/mach-mmp/include/mach/regs-rtc.h b/arch/arm/mach-mmp/include/mach/regs-rtc.h deleted file mode 100644 index 5bff886a3941..000000000000 --- a/arch/arm/mach-mmp/include/mach/regs-rtc.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_MACH_REGS_RTC_H -#define __ASM_MACH_REGS_RTC_H - -#include <mach/addr-map.h> - -#define RTC_VIRT_BASE (APB_VIRT_BASE + 0x10000) -#define RTC_REG(x) (*((volatile u32 __iomem *)(RTC_VIRT_BASE + (x)))) - -/* - * Real Time Clock - */ - -#define RCNR RTC_REG(0x00) /* RTC Count Register */ -#define RTAR RTC_REG(0x04) /* RTC Alarm Register */ -#define RTSR RTC_REG(0x08) /* RTC Status Register */ -#define RTTR RTC_REG(0x0C) /* RTC Timer Trim Register */ - -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ - -#endif /* __ASM_MACH_REGS_RTC_H */ diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index b2296c9309b8..6e155f03b83c 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -20,12 +20,12 @@ extern void __init mmp_dt_init_timer(void); -static const char *pxa168_dt_board_compat[] __initdata = { +static const char *const pxa168_dt_board_compat[] __initconst = { "mrvl,pxa168-aspenite", NULL, }; -static const char *pxa910_dt_board_compat[] __initdata = { +static const char *const pxa910_dt_board_compat[] __initconst = { "mrvl,pxa910-dkb", NULL, }; diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c index 998c0f533abc..0341359b24a4 100644 --- a/arch/arm/mach-mmp/mmp2-dt.c +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -30,7 +30,7 @@ static void __init mmp_init_time(void) of_clk_init(NULL); } -static const char *mmp2_dt_board_compat[] __initdata = { +static const char *const mmp2_dt_board_compat[] __initconst = { "mrvl,mmp2-brownstone", NULL, }; diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c index 04c9daf9f8d7..7db5870d127f 100644 --- a/arch/arm/mach-mmp/pm-pxa910.c +++ b/arch/arm/mach-mmp/pm-pxa910.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/irq.h> #include <asm/mach-types.h> +#include <asm/outercache.h> #include <mach/hardware.h> #include <mach/cputype.h> #include <mach/addr-map.h> diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 10bfa03e58d4..dbc697b2fda1 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -124,32 +124,25 @@ static int timer_set_next_event(unsigned long delta, return 0; } -static void timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *dev) +static int timer_set_shutdown(struct clock_event_device *evt) { unsigned long flags; local_irq_save(flags); - switch (mode) { - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - /* disable the matching interrupt */ - __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); - break; - case CLOCK_EVT_MODE_RESUME: - case CLOCK_EVT_MODE_PERIODIC: - break; - } + /* disable the matching interrupt */ + __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); local_irq_restore(flags); + + return 0; } static struct clock_event_device ckevt = { - .name = "clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = timer_set_next_event, - .set_mode = timer_set_mode, + .name = "clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = timer_set_next_event, + .set_state_shutdown = timer_set_shutdown, + .set_state_oneshot = timer_set_shutdown, }; static cycle_t clksrc_read(struct clocksource *cs) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 97473168d6b6..c86a5a0aefac 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -96,6 +96,7 @@ config MACH_DOVE select MACH_MVEBU_ANY select ORION_IRQCHIP select ORION_TIMER + select PM_GENERIC_DOMAINS if PM select PINCTRL_DOVE help Say 'Y' here if you want your kernel to support the diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index afee9083ad92..9f739f3cad4c 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -14,7 +14,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/of_fdt.h> #include <linux/of_platform.h> diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index e46e9ea1e187..44eedf331ae7 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = { int ll_enable_coherency(void); void ll_add_cpu_to_smp_group(void); -int set_cpu_coherent(void) -{ - if (!coherency_base) { - pr_warn("Can't make current CPU cache coherent.\n"); - pr_warn("Coherency fabric is not initialized\n"); - return 1; - } - - ll_add_cpu_to_smp_group(); - return ll_enable_coherency(); -} - static int mvebu_hwcc_notifier(struct notifier_block *nb, unsigned long event, void *__dev) { @@ -206,6 +194,23 @@ static int coherency_type(void) return type; } +int set_cpu_coherent(void) +{ + int type = coherency_type(); + + if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) { + if (!coherency_base) { + pr_warn("Can't make current CPU cache coherent.\n"); + pr_warn("Coherency fabric is not initialized\n"); + return 1; + } + ll_add_cpu_to_smp_group(); + return ll_enable_coherency(); + } + + return 0; +} + int coherency_available(void) { return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 3e0aca1f288a..6b775492cfad 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -25,6 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev); void __iomem *mvebu_get_scu_base(void); -int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)); - +int mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg, + u32 srcmd)); #endif diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index 5a1741500a30..1aebb82e3d7b 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -12,6 +12,7 @@ #include <linux/mbus.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/soc/dove/pmu.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> #include "common.h" @@ -24,6 +25,7 @@ static void __init dove_init(void) tauros2_init(0); #endif BUG_ON(mvebu_mbus_dt_init(false)); + dove_init_pmu(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c index 301ab38d38ba..db17121d7d63 100644 --- a/arch/arm/mach-mvebu/pm-board.c +++ b/arch/arm/mach-mvebu/pm-board.c @@ -1,7 +1,7 @@ /* * Board-level suspend/resume support. * - * Copyright (C) 2014 Marvell + * Copyright (C) 2014-2015 Marvell * * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * @@ -20,27 +20,27 @@ #include <linux/slab.h> #include "common.h" -#define ARMADA_XP_GP_PIC_NR_GPIOS 3 +#define ARMADA_PIC_NR_GPIOS 3 static void __iomem *gpio_ctrl; -static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; -static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; +static int pic_gpios[ARMADA_PIC_NR_GPIOS]; +static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS]; -static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd) +static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd) { u32 reg, ackcmd; int i; /* Put 001 as value on the GPIOs */ reg = readl(gpio_ctrl); - for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) + for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) reg &= ~BIT(pic_raw_gpios[i]); reg |= BIT(pic_raw_gpios[0]); writel(reg, gpio_ctrl); /* Prepare writing 111 to the GPIOs */ ackcmd = readl(gpio_ctrl); - for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) + for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) ackcmd |= BIT(pic_raw_gpios[i]); srcmd = cpu_to_le32(srcmd); @@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd) [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1"); } -static int mvebu_armada_xp_gp_pm_init(void) +static int __init mvebu_armada_pm_init(void) { struct device_node *np; struct device_node *gpio_ctrl_np; @@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void) if (!np) return -ENODEV; - for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) { + for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) { char *name; struct of_phandle_args args; @@ -134,11 +134,19 @@ static int mvebu_armada_xp_gp_pm_init(void) if (!gpio_ctrl) return -ENOMEM; - mvebu_pm_init(mvebu_armada_xp_gp_pm_enter); + mvebu_pm_suspend_init(mvebu_armada_pm_enter); out: of_node_put(np); return ret; } -late_initcall(mvebu_armada_xp_gp_pm_init); +/* + * Registering the mvebu_board_pm_enter callback must be done before + * the platform_suspend_ops will be registered. In the same time we + * also need to have the gpio devices registered. That's why we use a + * device_initcall_sync which is called after all the device_initcall + * (used by the gpio device) but before the late_initcall (used to + * register the platform_suspend_ops) + */ +device_initcall_sync(mvebu_armada_pm_init); diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c index 6573a8f11f70..8d32bf762b86 100644 --- a/arch/arm/mach-mvebu/pm.c +++ b/arch/arm/mach-mvebu/pm.c @@ -105,12 +105,10 @@ static phys_addr_t mvebu_internal_reg_base(void) return of_translate_address(np, in_addr); } -static void mvebu_pm_store_bootinfo(void) +static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr) { - u32 *store_addr; phys_addr_t resume_pc; - store_addr = phys_to_virt(BOOT_INFO_ADDR); resume_pc = virt_to_phys(armada_370_xp_cpu_resume); /* @@ -151,14 +149,30 @@ static void mvebu_pm_store_bootinfo(void) writel(BOOT_MAGIC_LIST_END, store_addr); } -static int mvebu_pm_enter(suspend_state_t state) +static int mvebu_pm_store_bootinfo(void) { - if (state != PM_SUSPEND_MEM) - return -EINVAL; + u32 *store_addr; + + store_addr = phys_to_virt(BOOT_INFO_ADDR); + + if (of_machine_is_compatible("marvell,armadaxp")) + mvebu_pm_store_armadaxp_bootinfo(store_addr); + else + return -ENODEV; + + return 0; +} + +static int mvebu_enter_suspend(void) +{ + int ret; + + ret = mvebu_pm_store_bootinfo(); + if (ret) + return ret; cpu_pm_enter(); - mvebu_pm_store_bootinfo(); cpu_suspend(0, mvebu_pm_powerdown); outer_resume(); @@ -168,23 +182,62 @@ static int mvebu_pm_enter(suspend_state_t state) set_cpu_coherent(); cpu_pm_exit(); + return 0; +} + +static int mvebu_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + cpu_do_idle(); + break; + case PM_SUSPEND_MEM: + pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n"); + return mvebu_enter_suspend(); + default: + return -EINVAL; + } + return 0; +} + +static int mvebu_pm_valid(suspend_state_t state) +{ + if (state == PM_SUSPEND_STANDBY) + return 1; + + if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL) + return 1; return 0; } static const struct platform_suspend_ops mvebu_pm_ops = { .enter = mvebu_pm_enter, - .valid = suspend_valid_only_mem, + .valid = mvebu_pm_valid, }; -int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)) +static int __init mvebu_pm_init(void) +{ + if (!of_machine_is_compatible("marvell,armadaxp") && + !of_machine_is_compatible("marvell,armada370") && + !of_machine_is_compatible("marvell,armada380") && + !of_machine_is_compatible("marvell,armada390")) + return -ENODEV; + + suspend_set_ops(&mvebu_pm_ops); + + return 0; +} + + +late_initcall(mvebu_pm_init); + +int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg, + u32 srcmd)) { struct device_node *np; struct resource res; - if (!of_machine_is_compatible("marvell,armadaxp")) - return -ENODEV; - np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-sdram-controller"); if (!np) @@ -212,7 +265,5 @@ int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)) mvebu_board_pm_enter = board_pm_enter; - suspend_set_ops(&mvebu_pm_ops); - return 0; } diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 4f4e22206ae5..e8fdb9ceedf0 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -415,7 +415,7 @@ static __init int armada_38x_cpuidle_init(void) void __iomem *mpsoc_base; u32 reg; - pr_warn("CPU idle is currently broken on Armada 38x: disabling"); + pr_warn("CPU idle is currently broken on Armada 38x: disabling\n"); return 0; np = of_find_compatible_node(NULL, NULL, @@ -486,7 +486,7 @@ static int __init mvebu_v7_cpu_pm_init(void) */ if (of_machine_is_compatible("marvell,armada380")) { cpu_hotplug_disable(); - pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling"); + pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n"); } if (of_machine_is_compatible("marvell,armadaxp")) diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 2e7cec86e50e..f1ea4700efcf 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -282,7 +282,7 @@ static void __init apx4devkit_init(void) #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) #define TX28_FEC_nINT MXS_GPIO_NR(4, 5) -static const struct gpio tx28_gpios[] __initconst = { +static const struct gpio const tx28_gpios[] __initconst = { { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, @@ -528,7 +528,7 @@ static void mxs_restart(enum reboot_mode mode, const char *cmd) soft_restart(0); } -static const char *mxs_dt_compat[] __initdata = { +static const char *const mxs_dt_compat[] __initconst = { "fsl,imx28", "fsl,imx23", NULL, diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index db25b0cef3a7..6373e2bff203 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -174,7 +174,7 @@ void __init netx_init_irq(void) for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { irq_set_chip_and_handler(irq, &netx_hif_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); + irq_clear_status_flags(irq, IRQ_NOREQUEST); } writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index 5fb2a590ec17..054a8a61e379 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -34,40 +34,40 @@ #define TIMER_CLOCKEVENT 0 #define TIMER_CLOCKSOURCE 1 -static void netx_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) +static inline void timer_shutdown(struct clock_event_device *evt) { - u32 tmode; - /* disable timer */ writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); +} + +static int netx_shutdown(struct clock_event_device *evt) +{ + timer_shutdown(evt); + + return 0; +} + +static int netx_set_oneshot(struct clock_event_device *evt) +{ + u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN; + + timer_shutdown(evt); + writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); + writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); - tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | - NETX_GPIO_COUNTER_CTRL_IRQ_EN | - NETX_GPIO_COUNTER_CTRL_RUN; - break; - - case CLOCK_EVT_MODE_ONESHOT: - writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); - tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | - NETX_GPIO_COUNTER_CTRL_RUN; - break; - - default: - WARN(1, "%s: unhandled mode %d\n", __func__, mode); - /* fall through */ - - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - tmode = 0; - break; - } + return 0; +} +static int netx_set_periodic(struct clock_event_device *evt) +{ + u32 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | + NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN; + + timer_shutdown(evt); + writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); + + return 0; } static int netx_set_next_event(unsigned long evt, @@ -81,7 +81,10 @@ static struct clock_event_device netx_clockevent = { .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = netx_set_next_event, - .set_mode = netx_set_mode, + .set_state_shutdown = netx_shutdown, + .set_state_periodic = netx_set_periodic, + .set_state_oneshot = netx_set_oneshot, + .tick_resume = netx_shutdown, }; /* diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 9bda46f1fab7..0c612d95bd5c 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -26,10 +26,8 @@ #include <linux/irq.h> #include <linux/dma-mapping.h> #include <linux/of_irq.h> -#include <linux/of_gpio.h> #include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -109,40 +107,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd) writel(1, srcbase + 0x18); } -/* - * This GPIO pin turns on a line that is used to detect card insertion - * on this board. - */ -static int __init cpu8815_mmcsd_init(void) -{ - struct device_node *cdbias; - int gpio, err; - - cdbias = of_find_node_by_path("/usb-s8815/mmcsd-gpio"); - if (!cdbias) { - pr_info("could not find MMC/SD card detect bias node\n"); - return 0; - } - gpio = of_get_gpio(cdbias, 0); - if (gpio < 0) { - pr_info("could not obtain MMC/SD card detect bias GPIO\n"); - return 0; - } - err = gpio_request(gpio, "card detect bias"); - if (err) { - pr_info("failed to request card detect bias GPIO %d\n", gpio); - return -ENODEV; - } - err = gpio_direction_output(gpio, 0); - if (err){ - pr_info("failed to set GPIO %d as output, low\n", gpio); - return err; - } - pr_info("enabled USB-S8815 CD bias GPIO %d, low\n", gpio); - return 0; -} -device_initcall(cpu8815_mmcsd_init); - static const char * cpu8815_board_compat[] = { "st,nomadik-nhk-15", "calaosystems,usb-s8815", @@ -150,9 +114,8 @@ static const char * cpu8815_board_compat[] = { }; DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") - /* At full speed latency must be >=2, so 0x249 in low bits */ - .l2c_aux_val = 0x00700249, - .l2c_aux_mask = 0xfe0fefff, + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .map_io = cpu8815_map_io, .restart = cpu8815_restart, .dt_compat = cpu8815_board_compat, diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 3c0e42219200..dfec671b1639 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -169,7 +169,7 @@ void omap1510_fpga_init_irq(void) } irq_set_handler(i, handle_edge_irq); - set_irq_flags(i, IRQF_VALID); + irq_clear_status_flags(i, IRQ_NOREQUEST); } /* diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index f4d346fda9da..b11edc8a46f0 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -262,7 +262,7 @@ void __init omap1_init_irq(void) irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); - set_irq_flags(j, IRQF_VALID); + irq_clear_status_flags(j, IRQ_NOREQUEST); } omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); } diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index a7588cfd0286..524977a31a49 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -124,29 +124,26 @@ static int omap_mpu_set_next_event(unsigned long cycles, return 0; } -static void omap_mpu_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int omap_mpu_set_oneshot(struct clock_event_device *evt) { - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - omap_mpu_set_autoreset(0); - break; - case CLOCK_EVT_MODE_ONESHOT: - omap_mpu_timer_stop(0); - omap_mpu_remove_autoreset(0); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - break; - } + omap_mpu_timer_stop(0); + omap_mpu_remove_autoreset(0); + return 0; +} + +static int omap_mpu_set_periodic(struct clock_event_device *evt) +{ + omap_mpu_set_autoreset(0); + return 0; } static struct clock_event_device clockevent_mpu_timer1 = { - .name = "mpu_timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = omap_mpu_set_next_event, - .set_mode = omap_mpu_set_mode, + .name = "mpu_timer1", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = omap_mpu_set_next_event, + .set_state_periodic = omap_mpu_set_periodic, + .set_state_oneshot = omap_mpu_set_oneshot, }; static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 36bf174b3fac..0ae6c52a7d70 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -114,29 +114,28 @@ static int omap_32k_timer_set_next_event(unsigned long delta, return 0; } -static void omap_32k_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int omap_32k_timer_shutdown(struct clock_event_device *evt) { omap_32k_timer_stop(); + return 0; +} - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - break; - case CLOCK_EVT_MODE_RESUME: - break; - } +static int omap_32k_timer_set_periodic(struct clock_event_device *evt) +{ + omap_32k_timer_stop(); + omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); + return 0; } static struct clock_event_device clockevent_32k_timer = { - .name = "32k-timer", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = omap_32k_timer_set_next_event, - .set_mode = omap_32k_timer_set_mode, + .name = "32k-timer", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = omap_32k_timer_set_next_event, + .set_state_shutdown = omap_32k_timer_shutdown, + .set_state_periodic = omap_32k_timer_set_periodic, + .set_state_oneshot = omap_32k_timer_shutdown, + .tick_resume = omap_32k_timer_shutdown, }; static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4a023e8d1bdb..07d2e100caab 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -29,6 +29,7 @@ config ARCH_OMAP4 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select OMAP_INTERCONNECT + select OMAP_INTERCONNECT_BARRIER select PL310_ERRATA_588369 if CACHE_L2X0 select PL310_ERRATA_727915 if CACHE_L2X0 select PM_OPP if PM @@ -46,6 +47,7 @@ config SOC_OMAP5 select HAVE_ARM_TWD if SMP select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 if SMP + select OMAP_INTERCONNECT_BARRIER config SOC_AM33XX bool "TI AM33XX" @@ -71,6 +73,7 @@ config SOC_DRA7XX select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR select ARM_ERRATA_798181 if SMP + select OMAP_INTERCONNECT_BARRIER config ARCH_OMAP2PLUS bool @@ -92,6 +95,10 @@ config ARCH_OMAP2PLUS help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 +config OMAP_INTERCONNECT_BARRIER + bool + select ARM_HEAVY_MB + if ARCH_OMAP2PLUS @@ -178,26 +185,6 @@ config MACH_OMAP_LDP default y select OMAP_PACKAGE_CBB -config MACH_OMAP3530_LV_SOM - bool "OMAP3 Logic 3530 LV SOM board" - depends on ARCH_OMAP3 - default y - select OMAP_PACKAGE_CBB - help - Support for the LogicPD OMAP3530 SOM Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit - -config MACH_OMAP3_TORPEDO - bool "OMAP3 Logic 35x Torpedo board" - depends on ARCH_OMAP3 - default y - select OMAP_PACKAGE_CBB - help - Support for the LogicPD OMAP35x Torpedo Development kit - for full description please see the products webpage at - http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit - config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 903c85be2897..935869698cbc 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -12,8 +12,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o +clock-common = clock.o secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) @@ -182,24 +181,17 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o -obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) +obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) -obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += $(clock-common) -obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) -obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM43XX) += $(clock-common) # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o @@ -234,8 +226,7 @@ obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o # EMU peripherals obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o -iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o -obj-y += $(iommu-m) $(iommu-y) +obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o # OMAP2420 MSDI controller integration support ("MMC") obj-$(CONFIG_SOC_OMAP2420) += msdi.o @@ -243,9 +234,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 34ff14b7beab..24c9afc9e8a7 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -169,7 +169,7 @@ static const char *const ti814x_boards_compat[] __initconst = { NULL, }; -DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)") +DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)") .reserve = omap_reserve, .map_io = ti81xx_map_io, .init_early = ti814x_init_early, @@ -297,7 +297,7 @@ static const char *const dra74x_boards_compat[] __initconst = { DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") .reserve = omap_reserve, .smp = smp_ops(omap4_smp_ops), - .map_io = omap5_map_io, + .map_io = dra7xx_map_io, .init_early = dra7xx_init_early, .init_late = dra7xx_init_late, .init_irq = omap_gic_of_init, @@ -316,7 +316,7 @@ static const char *const dra72x_boards_compat[] __initconst = { DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)") .reserve = omap_reserve, - .map_io = omap5_map_io, + .map_io = dra7xx_map_io, .init_early = dra7xx_init_early, .init_late = dra7xx_init_late, .init_irq = omap_gic_of_init, diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c deleted file mode 100644 index 6049f60a8813..000000000000 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-omap3logic.c - * - * Copyright (C) 2010 Li-Pro.Net - * Stephan Linz <linz@li-pro.net> - * - * Copyright (C) 2010-2012 Logic Product Development, Inc. - * Peter Barada <peter.barada@logicpd.com> - * Ashwin BIhari <ashwin.bihari@logicpd.com> - * - * Modified from Beagle, EVM, and RX51 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> - -#include <linux/i2c/twl.h> -#include <linux/mmc/host.h> -#include <linux/usb/phy.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "mux.h" -#include "hsmmc.h" -#include "control.h" -#include "common-board-devices.h" -#include "gpmc.h" -#include "gpmc-smsc911x.h" - -#define OMAP3LOGIC_SMSC911X_CS 1 - -#define OMAP3530_LV_SOM_MMC_GPIO_CD 110 -#define OMAP3530_LV_SOM_MMC_GPIO_WP 126 -#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152 - -#define OMAP3_TORPEDO_MMC_GPIO_CD 127 -#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 - -static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data omap3logic_vmmc1 = { - .constraints = { - .name = "VMMC1", - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply), - .consumer_supplies = omap3logic_vmmc1_supply, -}; - -static struct twl4030_gpio_platform_data omap3logic_gpio_data = { - .use_leds = true, - .pullups = BIT(1), - .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) - | BIT(13) | BIT(15) | BIT(16) | BIT(17), -}; - -static struct twl4030_usb_data omap3logic_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, -}; - - -static struct twl4030_platform_data omap3logic_twldata = { - /* platform_data for children goes here */ - .gpio = &omap3logic_gpio_data, - .vmmc1 = &omap3logic_vmmc1, - .usb = &omap3logic_usb_data, -}; - -static int __init omap3logic_i2c_init(void) -{ - omap3_pmic_init("twl4030", &omap3logic_twldata); - return 0; -} - -static struct omap2_hsmmc_info __initdata board_mmc_info[] = { - { - .name = "external", - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - {} /* Terminator */ -}; - -static void __init board_mmc_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD; - board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP; - omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD; - omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - omap_hsmmc_init(board_mmc_info); -} - -static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { - .cs = OMAP3LOGIC_SMSC911X_CS, - .gpio_irq = -EINVAL, - .gpio_reset = -EINVAL, -}; - -/* TODO/FIXME (comment by Peter Barada, LogicPD): - * Fix the PBIAS voltage for Torpedo MMC1 pins that - * are used for other needs (IRQs, etc). */ -static void omap3torpedo_fix_pbias_voltage(void) -{ - u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - u32 reg; - - if (machine_is_omap3_torpedo()) - { - /* Set the bias for the pin */ - reg = omap_ctrl_readl(control_pbias_offset); - - reg &= ~OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg, control_pbias_offset); - - /* 100ms delay required for PBIAS configuration */ - msleep(100); - - reg |= OMAP343X_PBIASLITEVMODE1; - reg |= OMAP343X_PBIASLITEPWRDNZ1; - omap_ctrl_writel(reg | 0x300, control_pbias_offset); - } -} - -static inline void __init board_smsc911x_init(void) -{ - if (machine_is_omap3530_lv_som()) { - /* OMAP3530 LV SOM board */ - board_smsc911x_data.gpio_irq = - OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT); - } else if (machine_is_omap3_torpedo()) { - /* OMAP3 Torpedo board */ - board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ; - omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT); - } else { - /* unsupported board */ - printk(KERN_ERR "%s(): unknown machine type\n", __func__); - return; - } - - gpmc_smsc911x_init(&board_smsc911x_data); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* mUSB */ - OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x.0"), - REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), -}; - -static void __init omap3logic_init(void) -{ - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3torpedo_fix_pbias_voltage(); - omap3logic_i2c_init(); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - board_mmc_init(); - board_smsc911x_init(); - - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); - usb_musb_init(NULL); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -} - -MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap3_map_io, - .init_early = omap35xx_init_early, - .init_irq = omap3_init_irq, - .init_machine = omap3logic_init, - .init_late = omap35xx_init_late, - .init_time = omap3_sync32k_timer_init, - .restart = omap3xxx_restart, -MACHINE_END - -MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap3_map_io, - .init_early = omap35xx_init_early, - .init_irq = omap3_init_irq, - .init_machine = omap3logic_init, - .init_late = omap35xx_init_late, - .init_time = omap3_sync32k_timer_init, - .restart = omap3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c deleted file mode 100644 index 969e1003dd92..000000000000 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * board-omap3pandora.c (Pandora Handheld Console) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <linux/spi/spi.h> -#include <linux/regulator/machine.h> -#include <linux/i2c/twl.h> -#include <linux/omap-gpmc.h> -#include <linux/wl12xx.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/nand.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/input/matrix_keypad.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/mmc/host.h> -#include <linux/mmc/card.h> -#include <linux/regulator/fixed.h> -#include <linux/usb/phy.h> -#include <linux/platform_data/spi-omap2-mcspi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include <video/omapdss.h> -#include <video/omap-panel-data.h> -#include <linux/platform_data/mtd-nand-omap2.h> - -#include "mux.h" -#include "sdram-micron-mt46h32m32lf-6.h" -#include "hsmmc.h" -#include "common-board-devices.h" - -#define PANDORA_WIFI_IRQ_GPIO 21 -#define PANDORA_WIFI_NRESET_GPIO 23 -#define OMAP3_PANDORA_TS_GPIO 94 - -static struct mtd_partition omap3pandora_nand_partitions[] = { - { - .name = "xloader", - .offset = 0, - .size = 4 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE - }, { - .name = "uboot", - .offset = MTDPART_OFS_APPEND, - .size = 15 * NAND_BLOCK_SIZE, - }, { - .name = "uboot-env", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - }, { - .name = "boot", - .offset = MTDPART_OFS_APPEND, - .size = 80 * NAND_BLOCK_SIZE, - }, { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_nand_platform_data pandora_nand_data = { - .cs = 0, - .devsize = NAND_BUSWIDTH_16, - .xfer_type = NAND_OMAP_PREFETCH_DMA, - .parts = omap3pandora_nand_partitions, - .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), -}; - -static struct gpio_led pandora_gpio_leds[] = { - { - .name = "pandora::sd1", - .default_trigger = "mmc0", - .gpio = 128, - }, { - .name = "pandora::sd2", - .default_trigger = "mmc1", - .gpio = 129, - }, { - .name = "pandora::bluetooth", - .gpio = 158, - }, { - .name = "pandora::wifi", - .gpio = 159, - }, -}; - -static struct gpio_led_platform_data pandora_gpio_led_data = { - .leds = pandora_gpio_leds, - .num_leds = ARRAY_SIZE(pandora_gpio_leds), -}; - -static struct platform_device pandora_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &pandora_gpio_led_data, - }, -}; - -static struct platform_device pandora_backlight = { - .name = "pandora-backlight", - .id = -1, -}; - -#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \ -{ \ - .gpio = gpio_num, \ - .type = ev_type, \ - .code = ev_code, \ - .active_low = act_low, \ - .debounce_interval = 4, \ - .desc = "btn " descr, \ -} - -#define GPIO_BUTTON_LOW(gpio_num, event_code, description) \ - GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description) - -static struct gpio_keys_button pandora_gpio_keys[] = { - GPIO_BUTTON_LOW(110, KEY_UP, "up"), - GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), - GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), - GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(109, KEY_PAGEUP, "game 1"), - GPIO_BUTTON_LOW(111, KEY_END, "game 2"), - GPIO_BUTTON_LOW(106, KEY_PAGEDOWN, "game 3"), - GPIO_BUTTON_LOW(101, KEY_HOME, "game 4"), - GPIO_BUTTON_LOW(102, KEY_RIGHTSHIFT, "l"), - GPIO_BUTTON_LOW(97, KEY_KPPLUS, "l2"), - GPIO_BUTTON_LOW(105, KEY_RIGHTCTRL, "r"), - GPIO_BUTTON_LOW(107, KEY_KPMINUS, "r2"), - GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), - GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), - GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), - GPIO_BUTTON(100, EV_KEY, KEY_LEFTALT, 0, "alt"), - GPIO_BUTTON(108, EV_SW, SW_LID, 1, "lid"), -}; - -static struct gpio_keys_platform_data pandora_gpio_key_info = { - .buttons = pandora_gpio_keys, - .nbuttons = ARRAY_SIZE(pandora_gpio_keys), -}; - -static struct platform_device pandora_keys_gpio = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &pandora_gpio_key_info, - }, -}; - -static const uint32_t board_keymap[] = { - /* row, col, code */ - KEY(0, 0, KEY_9), - KEY(0, 1, KEY_8), - KEY(0, 2, KEY_I), - KEY(0, 3, KEY_J), - KEY(0, 4, KEY_N), - KEY(0, 5, KEY_M), - KEY(1, 0, KEY_0), - KEY(1, 1, KEY_7), - KEY(1, 2, KEY_U), - KEY(1, 3, KEY_H), - KEY(1, 4, KEY_B), - KEY(1, 5, KEY_SPACE), - KEY(2, 0, KEY_BACKSPACE), - KEY(2, 1, KEY_6), - KEY(2, 2, KEY_Y), - KEY(2, 3, KEY_G), - KEY(2, 4, KEY_V), - KEY(2, 5, KEY_FN), - KEY(3, 0, KEY_O), - KEY(3, 1, KEY_5), - KEY(3, 2, KEY_T), - KEY(3, 3, KEY_F), - KEY(3, 4, KEY_C), - KEY(4, 0, KEY_P), - KEY(4, 1, KEY_4), - KEY(4, 2, KEY_R), - KEY(4, 3, KEY_D), - KEY(4, 4, KEY_X), - KEY(5, 0, KEY_K), - KEY(5, 1, KEY_3), - KEY(5, 2, KEY_E), - KEY(5, 3, KEY_S), - KEY(5, 4, KEY_Z), - KEY(6, 0, KEY_L), - KEY(6, 1, KEY_2), - KEY(6, 2, KEY_W), - KEY(6, 3, KEY_A), - KEY(6, 4, KEY_DOT), - KEY(7, 0, KEY_ENTER), - KEY(7, 1, KEY_1), - KEY(7, 2, KEY_Q), - KEY(7, 3, KEY_LEFTSHIFT), - KEY(7, 4, KEY_COMMA), -}; - -static struct matrix_keymap_data board_map_data = { - .keymap = board_keymap, - .keymap_size = ARRAY_SIZE(board_keymap), -}; - -static struct twl4030_keypad_data pandora_kp_data = { - .keymap_data = &board_map_data, - .rows = 8, - .cols = 6, - .rep = 1, -}; - -static struct connector_atv_platform_data pandora_tv_pdata = { - .name = "tv", - .source = "venc.0", - .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, - .invert_polarity = false, -}; - -static struct platform_device pandora_tv_connector_device = { - .name = "connector-analog-tv", - .id = 0, - .dev.platform_data = &pandora_tv_pdata, -}; - -static struct omap_dss_board_info pandora_dss_data = { - .default_display_name = "lcd", -}; - -static void pandora_wl1251_init_card(struct mmc_card *card) -{ - /* - * We have TI wl1251 attached to MMC3. Pass this information to - * SDIO core because it can't be probed by normal methods. - */ - if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) { - card->quirks |= MMC_QUIRK_NONSTD_SDIO; - card->cccr.wide_bus = 1; - card->cis.vendor = 0x104c; - card->cis.device = 0x9066; - card->cis.blksize = 512; - card->cis.max_dtr = 20000000; - } -} - -static struct omap2_hsmmc_info omap3pandora_mmc[] = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = 126, - .ext_clock = 0, - .deferred = true, - }, - { - .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = 127, - .ext_clock = 1, - .transceiver = true, - .deferred = true, - }, - { - .mmc = 3, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .init_card = pandora_wl1251_init_card, - }, - {} /* Terminator */ -}; - -static int omap3pandora_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) -{ - int ret, gpio_32khz; - - /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ - omap3pandora_mmc[0].gpio_cd = gpio + 0; - omap3pandora_mmc[1].gpio_cd = gpio + 1; - omap_hsmmc_late_init(omap3pandora_mmc); - - /* gpio + 13 drives 32kHz buffer for wifi module */ - gpio_32khz = gpio + 13; - ret = gpio_request_one(gpio_32khz, GPIOF_OUT_INIT_HIGH, "wifi 32kHz"); - if (ret < 0) { - pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret); - return -ENODEV; - } - - return 0; -} - -static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { - .setup = omap3pandora_twl_gpio_setup, -}; - -static struct regulator_consumer_supply pandora_vmmc1_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -}; - -static struct regulator_consumer_supply pandora_vmmc2_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1") -}; - -static struct regulator_consumer_supply pandora_vmmc3_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"), -}; - -static struct regulator_consumer_supply pandora_vdds_supplies[] = { - REGULATOR_SUPPLY("vdds_sdi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), -}; - -static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { - REGULATOR_SUPPLY("vcc", "spi1.1"), -}; - -static struct regulator_consumer_supply pandora_usb_phy_supply[] = { - REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ -}; - -/* ads7846 on SPI and 2 nub controllers on I2C */ -static struct regulator_consumer_supply pandora_vaux4_supplies[] = { - REGULATOR_SUPPLY("vcc", "spi1.0"), - REGULATOR_SUPPLY("vcc", "3-0066"), - REGULATOR_SUPPLY("vcc", "3-0067"), -}; - -static struct regulator_consumer_supply pandora_adac_supply[] = { - REGULATOR_SUPPLY("vcc", "soc-audio"), -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data pandora_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply), - .consumer_supplies = pandora_vmmc1_supply, -}; - -/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */ -static struct regulator_init_data pandora_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply), - .consumer_supplies = pandora_vmmc2_supply, -}; - -/* VAUX1 for LCD */ -static struct regulator_init_data pandora_vaux1 = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply), - .consumer_supplies = pandora_vcc_lcd_supply, -}; - -/* VAUX2 for USB host PHY */ -static struct regulator_init_data pandora_vaux2 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply), - .consumer_supplies = pandora_usb_phy_supply, -}; - -/* VAUX4 for ads7846 and nubs */ -static struct regulator_init_data pandora_vaux4 = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_vaux4_supplies), - .consumer_supplies = pandora_vaux4_supplies, -}; - -/* VSIM for audio DAC */ -static struct regulator_init_data pandora_vsim = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply), - .consumer_supplies = pandora_adac_supply, -}; - -/* Fixed regulator internal to Wifi module */ -static struct regulator_init_data pandora_vmmc3 = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply), - .consumer_supplies = pandora_vmmc3_supply, -}; - -static struct fixed_voltage_config pandora_vwlan = { - .supply_name = "vwlan", - .microvolts = 1800000, /* 1.8V */ - .gpio = PANDORA_WIFI_NRESET_GPIO, - .startup_delay = 50000, /* 50ms */ - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &pandora_vmmc3, -}; - -static struct platform_device pandora_vwlan_device = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &pandora_vwlan, - }, -}; - -static struct twl4030_bci_platform_data pandora_bci_data; - -static struct twl4030_power_data pandora_power_data = { - .use_poweroff = true, -}; - -static struct twl4030_platform_data omap3pandora_twldata = { - .gpio = &omap3pandora_gpio_data, - .vmmc1 = &pandora_vmmc1, - .vmmc2 = &pandora_vmmc2, - .vaux1 = &pandora_vaux1, - .vaux2 = &pandora_vaux2, - .vaux4 = &pandora_vaux4, - .vsim = &pandora_vsim, - .keypad = &pandora_kp_data, - .bci = &pandora_bci_data, - .power = &pandora_power_data, -}; - -static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = { - { - I2C_BOARD_INFO("bq27500", 0x55), - .flags = I2C_CLIENT_WAKE, - }, -}; - -static int __init omap3pandora_i2c_init(void) -{ - omap3_pmic_get_config(&omap3pandora_twldata, - TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO, - TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); - - omap3pandora_twldata.vdac->constraints.apply_uV = true; - - omap3pandora_twldata.vpll2->constraints.apply_uV = true; - omap3pandora_twldata.vpll2->num_consumer_supplies = - ARRAY_SIZE(pandora_vdds_supplies); - omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies; - - omap3_pmic_init("tps65950", &omap3pandora_twldata); - /* i2c2 pins are not connected */ - omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo, - ARRAY_SIZE(omap3pandora_i2c3_boardinfo)); - return 0; -} - -static struct panel_tpo_td043mtea1_platform_data pandora_lcd_pdata = { - .name = "lcd", - .source = "dpi.0", - - .data_lines = 24, - .nreset_gpio = 157, -}; - -static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { - { - .modalias = "panel-tpo-td043mtea1", - .bus_num = 1, - .chip_select = 1, - .max_speed_hz = 375000, - .platform_data = &pandora_lcd_pdata, - } -}; - -static void __init pandora_wl1251_init(void) -{ - struct wl1251_platform_data pandora_wl1251_pdata; - int ret; - - memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata)); - - pandora_wl1251_pdata.power_gpio = -1; - - ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq"); - if (ret < 0) - goto fail; - - pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); - if (pandora_wl1251_pdata.irq < 0) - goto fail_irq; - - pandora_wl1251_pdata.use_eeprom = true; - ret = wl1251_set_platform_data(&pandora_wl1251_pdata); - if (ret < 0) - goto fail_irq; - - return; - -fail_irq: - gpio_free(PANDORA_WIFI_IRQ_GPIO); -fail: - printk(KERN_ERR "wl1251 board initialisation failed\n"); -} - -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 16, - .vcc_gpio = -EINVAL, - }, -}; - -static struct platform_device *omap3pandora_devices[] __initdata = { - &pandora_leds_gpio, - &pandora_keys_gpio, - &pandora_vwlan_device, - &pandora_backlight, - &pandora_tv_connector_device, -}; - -static struct usbhs_omap_platform_data usbhs_bdata __initdata = { - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#endif - -static void __init omap3pandora_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_hsmmc_init(omap3pandora_mmc); - omap3pandora_i2c_init(); - pandora_wl1251_init(); - platform_add_devices(omap3pandora_devices, - ARRAY_SIZE(omap3pandora_devices)); - omap_display_init(&pandora_dss_data); - omap_serial_init(); - omap_sdrc_init(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - spi_register_board_info(omap3pandora_spi_board_info, - ARRAY_SIZE(omap3pandora_spi_board_info)); - omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); - usbhs_init(&usbhs_bdata); - - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); - usb_musb_init(NULL); - gpmc_nand_init(&pandora_nand_data, NULL); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -} - -MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap3_map_io, - .init_early = omap35xx_init_early, - .init_irq = omap3_init_irq, - .init_machine = omap3pandora_init, - .init_late = omap35xx_init_late, - .init_time = omap3_sync32k_timer_init, - .restart = omap3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf21014..3f6521313c93 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -23,12 +23,13 @@ #include "clock.h" #include "clock3xxx.h" -#include "clock34xx.h" #include "sdrc.h" #include "sram.h" #define CYCLES_PER_MHZ 1000000 +struct clk *sdrc_ick_p, *arm_fck_p; + /* * CORE DPLL (DPLL3) M2 divider rate programming functions * @@ -60,12 +61,14 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, if (!clk || !rate) return -EINVAL; - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + new_div = DIV_ROUND_UP(parent_rate, rate); + validrate = parent_rate / new_div; + if (validrate != rate) return -EINVAL; - sdrcrate = __clk_get_rate(sdrc_ick_p); - clkrate = __clk_get_rate(hw->clk); + sdrcrate = clk_get_rate(sdrc_ick_p); + clkrate = clk_hw_get_rate(hw); if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -83,7 +86,7 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, /* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; + _mpurate = clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS; diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c deleted file mode 100644 index 7ee26108ac0d..000000000000 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ /dev/null @@ -1,466 +0,0 @@ -/* - * clkt_clksel.c - OMAP2/3/4 clksel clock functions - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - * clksel clocks are clocks that do not have a fixed parent, or that - * can divide their parent's rate, or possibly both at the same time, based - * on the contents of a hardware register bitfield. - * - * All of the various mux and divider settings can be encoded into - * struct clksel* data structures, and then these can be autogenerated - * from some hardware database for each new chip generation. This - * should avoid the need to write, review, and validate a lot of new - * clock code for each new chip, since it can be exported from the SoC - * design flow. This is now done on OMAP4. - * - * The fusion of mux and divider clocks is a software creation. In - * hardware reality, the multiplexer (parent selection) and the - * divider exist separately. XXX At some point these clksel clocks - * should be split into "divider" clocks and "mux" clocks to better - * match the hardware. - * - * (The name "clksel" comes from the name of the corresponding - * register field in the OMAP2/3 family of SoCs.) - * - * XXX Currently these clocks are only used in the OMAP2/3/4 code, but - * many of the OMAP1 clocks should be convertible to use this - * mechanism. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/bug.h> - -#include "clock.h" - -/* Private functions */ - -/** - * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for - * - * Scan the struct clksel array associated with the clock to find - * the element associated with the supplied parent clock address. - * Returns a pointer to the struct clksel on success or NULL on error. - */ -static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) -{ - const struct clksel *clks; - - if (!src_clk) - return NULL; - - for (clks = clk->clksel; clks->parent; clks++) - if (clks->parent == src_clk) - break; /* Found the requested parent */ - - if (!clks->parent) { - /* This indicates a data problem */ - WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", - __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); - return NULL; - } - - return clks; -} - -/** - * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program - * @v: clksel bitfield value to program (with LSB at bit 0) - * - * Shift the clksel register bitfield value @v to its appropriate - * location in the clksel register and write it in. This function - * will ensure that the write to the clksel_reg reaches its - * destination before returning -- important since PRM and CM register - * accesses can be quite slow compared to ARM cycles -- but does not - * take into account any time the hardware might take to switch the - * clock source. - */ -static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) -{ - u32 v; - - v = omap2_clk_readl(clk, clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - omap2_clk_writel(v, clk, clk->clksel_reg); - - v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ -} - -/** - * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use - * @field_val: register field value to find - * - * Given a struct clk of a rate-selectable clksel clock, and a register field - * value to search for, find the corresponding clock divisor. The register - * field value should be pre-masked and shifted down so the LSB is at bit 0 - * before calling. Returns 0 on error or returns the actual integer divisor - * upon success. - */ -static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - struct clk *parent; - - parent = __clk_get_parent(clk->hw.clk); - - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == field_val) - break; - } - - if (!clkr->div) { - /* This indicates a data error */ - WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", - __clk_get_name(clk->hw.clk), field_val, - __clk_get_name(parent)); - return 0; - } - - return clkr->div; -} - -/** - * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use - * @div: integer divisor to search for - * - * Given a struct clk of a rate-selectable clksel clock, and a clock - * divisor, find the corresponding register field value. Returns the - * register field value _before_ left-shifting (i.e., LSB is at bit - * 0); or returns 0xFFFFFFFF (~0) upon error. - */ -static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - struct clk *parent; - - /* should never happen */ - WARN_ON(div == 0); - - parent = __clk_get_parent(clk->hw.clk); - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->div == div) - break; - } - - if (!clkr->div) { - pr_err("clock: %s: could not find divisor %d for parent %s\n", - __clk_get_name(clk->hw.clk), div, - __clk_get_name(parent)); - return ~0; - } - - return clkr->val; -} - -/** - * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. - * - * Read the current divisor register value for @clk that is programmed - * into the hardware, convert it into the actual divisor value, and - * return it; or return 0 on error. - */ -static u32 _read_divisor(struct clk_hw_omap *clk) -{ - u32 v; - - if (!clk->clksel || !clk->clksel_mask) - return 0; - - v = omap2_clk_readl(clk, clk->clksel_reg); - v &= clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); - - return _clksel_to_divisor(clk, v); -} - -/* Public functions */ - -/** - * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * @new_div: ptr to where we should store the divisor - * - * Finds 'best' divider value in an array based on the source and target - * rates. The divider array must be sorted with smallest divider first. - * This function is also used by the DPLL3 M2 divider code. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, - unsigned long target_rate, - u32 *new_div) -{ - unsigned long test_rate; - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 last_div = 0; - struct clk *parent; - unsigned long parent_rate; - const char *clk_name; - - parent = __clk_get_parent(clk->hw.clk); - clk_name = __clk_get_name(clk->hw.clk); - parent_rate = __clk_get_rate(parent); - - if (!clk->clksel || !clk->clksel_mask) - return ~0; - - pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk_name, target_rate); - - *new_div = 1; - - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - /* Sanity check */ - if (clkr->div <= last_div) - pr_err("clock: %s: clksel_rate table not sorted\n", - clk_name); - - last_div = clkr->div; - - test_rate = parent_rate / clkr->div; - - if (test_rate <= target_rate) - break; /* found it */ - } - - if (!clkr->div) { - pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n", - clk_name, target_rate, __clk_get_name(parent)); - return ~0; - } - - *new_div = clkr->div; - - pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (parent_rate / clkr->div)); - - return parent_rate / clkr->div; -} - -/* - * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) - */ - -/** - * omap2_clksel_find_parent_index() - return the array index of the current - * hardware parent of @hw - * @hw: struct clk_hw * to find the current hardware parent of - * - * Given a struct clk_hw pointer @hw to the 'hw' member of a struct - * clk_hw_omap record representing a source-selectable hardware clock, - * read the hardware register and determine what its parent is - * currently set to. Intended to be called only by the common clock - * framework struct clk_hw_ops.get_parent function pointer. Return - * the array index of this parent clock upon success -- there is no - * way to return an error, so if we encounter an error, just WARN() - * and pretend that we know that we're doing. - */ -u8 omap2_clksel_find_parent_index(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - struct clk *parent; - const char *clk_name; - int ret = 0, f = 0; - - parent = __clk_get_parent(hw->clk); - clk_name = __clk_get_name(hw->clk); - - /* XXX should be able to return an error */ - WARN((!clk->clksel || !clk->clksel_mask), - "clock: %s: attempt to call on a non-clksel clock", clk_name); - - r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == r) { - found = 1; - ret = f; - } - } - f++; - } - - /* This indicates a data error */ - WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk_name, r); - - return ret; -} - - -/** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * - * - * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this - * function. Returns the clock's current rate, based on its parent's rate - * and its current divisor setting in the hardware. - */ -unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) -{ - unsigned long rate; - u32 div = 0; - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - if (!parent_rate) - return 0; - - div = _read_divisor(clk); - if (!div) - rate = parent_rate; - else - rate = parent_rate / div; - - pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, - __clk_get_name(hw->clk), rate, div); - - return rate; -} - -/** - * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * - * This function is intended to be called only by the clock framework. - * Finds best target rate based on the source clock and possible dividers. - * rates. The divider array must be sorted with smallest divider first. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 new_div; - - return omap2_clksel_round_rate_div(clk, target_rate, &new_div); -} - -/** - * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate - * @rate: target rate to program - * - * This function is intended to be called only by the clock framework. - * Program @clk's rate to @rate in the hardware. The clock can be - * either enabled or disabled when this happens, although if the clock - * is enabled, some downstream devices may glitch or behave - * unpredictably when the clock rate is changed - this depends on the - * hardware. This function does not currently check the usecount of - * the clock, so if multiple drivers are using the clock, and the rate - * is changed, they will all be affected without any notification. - * Returns -EINVAL upon error, or 0 upon success. - */ -int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 field_val, validrate, new_div = 0; - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; - - field_val = _divisor_to_clksel(clk, new_div); - if (field_val == ~0) - return -EINVAL; - - _write_clksel_reg(clk, field_val); - - pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), - __clk_get_rate(hw->clk)); - - return 0; -} - -/* - * Clksel parent setting function - not passed in struct clk function - * pointer - instead, the OMAP clock code currently assumes that any - * parent-setting clock is a clksel clock, and calls - * omap2_clksel_set_parent() by default - */ - -/** - * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock - * - * This function is intended to be called only by the clock framework. - * Change the parent clock of clock @clk to @new_parent. This is - * intended to be used while @clk is disabled. This function does not - * currently check the usecount of the clock, so if multiple drivers - * are using the clock, and the parent is changed, they will all be - * affected without any notification. Returns -EINVAL upon error, or - * 0 upon success. - */ -int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - _write_clksel_reg(clk, field_val); - return 0; -} diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c deleted file mode 100644 index f251a14cbf16..000000000000 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * OMAP2/3/4 DPLL clock functions - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk-provider.h> -#include <linux/io.h> - -#include <asm/div64.h> - -#include "clock.h" - -/* DPLL rate rounding: minimum DPLL multiplier, divider values */ -#define DPLL_MIN_MULTIPLIER 2 -#define DPLL_MIN_DIVIDER 1 - -/* Possible error results from _dpll_test_mult */ -#define DPLL_MULT_UNDERFLOW -1 - -/* - * Scale factor to mitigate roundoff errors in DPLL rate rounding. - * The higher the scale factor, the greater the risk of arithmetic overflow, - * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR - * must be a power of DPLL_SCALE_BASE. - */ -#define DPLL_SCALE_FACTOR 64 -#define DPLL_SCALE_BASE 2 -#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ - (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) - -/* - * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. - * From device data manual section 4.3 "DPLL and DLL Specifications". - */ -#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 -#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 - -/* _dpll_test_fint() return codes */ -#define DPLL_FINT_UNDERFLOW -1 -#define DPLL_FINT_INVALID -2 - -/* Private functions */ - -/* - * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test - * @n: divider value (N) to test - * - * Tests whether a particular divider @n will result in a valid DPLL - * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter - * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate - * (assuming that it is counting N upwards), or -2 if the enclosing loop - * should skip to the next iteration (again assuming N is increasing). - */ -static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) -{ - struct dpll_data *dd; - long fint, fint_min, fint_max; - int ret = 0; - - dd = clk->dpll_data; - - /* DPLL divider must result in a valid jitter correction val */ - fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; - - if (dd->flags & DPLL_J_TYPE) { - fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; - fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; - } else { - fint_min = ti_clk_features.fint_min; - fint_max = ti_clk_features.fint_max; - } - - if (!fint_min || !fint_max) { - WARN(1, "No fint limits available!\n"); - return DPLL_FINT_INVALID; - } - - if (fint < ti_clk_features.fint_min) { - pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", - n); - dd->max_divider = n; - ret = DPLL_FINT_UNDERFLOW; - } else if (fint > ti_clk_features.fint_max) { - pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", - n); - dd->min_divider = n; - ret = DPLL_FINT_INVALID; - } else if (fint > ti_clk_features.fint_band1_max && - fint < ti_clk_features.fint_band2_min) { - pr_debug("rejecting n=%d due to Fint failure\n", n); - ret = DPLL_FINT_INVALID; - } - - return ret; -} - -static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, - unsigned int m, unsigned int n) -{ - unsigned long long num; - - num = (unsigned long long)parent_rate * m; - do_div(num, n); - return num; -} - -/* - * _dpll_test_mult - test a DPLL multiplier value - * @m: pointer to the DPLL m (multiplier) value under test - * @n: current DPLL n (divider) value under test - * @new_rate: pointer to storage for the resulting rounded rate - * @target_rate: the desired DPLL rate - * @parent_rate: the DPLL's parent clock rate - * - * This code tests a DPLL multiplier value, ensuring that the - * resulting rate will not be higher than the target_rate, and that - * the multiplier value itself is valid for the DPLL. Initially, the - * integer pointed to by the m argument should be prescaled by - * multiplying by DPLL_SCALE_FACTOR. The code will replace this with - * a non-scaled m upon return. This non-scaled m will result in a - * new_rate as close as possible to target_rate (but not greater than - * target_rate) given the current (parent_rate, n, prescaled m) - * triple. Returns DPLL_MULT_UNDERFLOW in the event that the - * non-scaled m attempted to underflow, which can allow the calling - * function to bail out early; or 0 upon success. - */ -static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, - unsigned long target_rate, - unsigned long parent_rate) -{ - int r = 0, carry = 0; - - /* Unscale m and round if necessary */ - if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) - carry = 1; - *m = (*m / DPLL_SCALE_FACTOR) + carry; - - /* - * The new rate must be <= the target rate to avoid programming - * a rate that is impossible for the hardware to handle - */ - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - if (*new_rate > target_rate) { - (*m)--; - *new_rate = 0; - } - - /* Guard against m underflow */ - if (*m < DPLL_MIN_MULTIPLIER) { - *m = DPLL_MIN_MULTIPLIER; - *new_rate = 0; - r = DPLL_MULT_UNDERFLOW; - } - - if (*new_rate == 0) - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - - return r; -} - -/** - * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not - * @v: bitfield value of the DPLL enable - * - * Checks given DPLL enable bitfield to see whether the DPLL is in bypass - * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. - */ -static int _omap2_dpll_is_in_bypass(u32 v) -{ - u8 mask, val; - - mask = ti_clk_features.dpll_bypass_vals; - - /* - * Each set bit in the mask corresponds to a bypass value equal - * to the bitshift. Go through each set-bit in the mask and - * compare against the given register value. - */ - while (mask) { - val = __ffs(mask); - mask ^= (1 << val); - if (v == val) - return 1; - } - - return 0; -} - -/* Public functions */ -u8 omap2_init_dpll_parent(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - v = omap2_clk_readl(clk, dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* Reparent the struct clk in case the dpll is in bypass */ - if (_omap2_dpll_is_in_bypass(v)) - return 1; - - return 0; -} - -/** - * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL - * - * DPLLs can be locked or bypassed - basically, enabled or disabled. - * When locked, the DPLL output depends on the M and N values. When - * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock - * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and - * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively - * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. - * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is - * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 - * if the clock @clk is not a DPLL. - */ -unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) -{ - long long dpll_clk; - u32 dpll_mult, dpll_div, v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return 0; - - /* Return bypass rate if DPLL is bypassed */ - v = omap2_clk_readl(clk, dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - if (_omap2_dpll_is_in_bypass(v)) - return __clk_get_rate(dd->clk_bypass); - - v = omap2_clk_readl(clk, dd->mult_div1_reg); - dpll_mult = v & dd->mult_mask; - dpll_mult >>= __ffs(dd->mult_mask); - dpll_div = v & dd->div1_mask; - dpll_div >>= __ffs(dd->div1_mask); - - dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; - do_div(dpll_clk, dpll_div + 1); - - return dpll_clk; -} - -/* DPLL rate rounding code */ - -/** - * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL - * @target_rate: desired DPLL clock rate - * - * Given a DPLL and a desired target rate, round the target rate to a - * possible, programmable rate for this DPLL. Attempts to select the - * minimum possible n. Stores the computed (m, n) in the DPLL's - * dpll_data structure so set_rate() will not need to call this - * (expensive) function again. Returns ~0 if the target rate cannot - * be rounded, or the rounded rate upon success. - */ -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int m, n, r, scaled_max_m; - int min_delta_m = INT_MAX, min_delta_n = INT_MAX; - unsigned long scaled_rt_rp; - unsigned long new_rate = 0; - struct dpll_data *dd; - unsigned long ref_rate; - long delta; - long prev_min_delta = LONG_MAX; - const char *clk_name; - - if (!clk || !clk->dpll_data) - return ~0; - - dd = clk->dpll_data; - - ref_rate = __clk_get_rate(dd->clk_ref); - clk_name = __clk_get_name(hw->clk); - pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", - clk_name, target_rate); - - scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); - scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; - - dd->last_rounded_rate = 0; - - for (n = dd->min_divider; n <= dd->max_divider; n++) { - - /* Is the (input clk, divider) pair valid for the DPLL? */ - r = _dpll_test_fint(clk, n); - if (r == DPLL_FINT_UNDERFLOW) - break; - else if (r == DPLL_FINT_INVALID) - continue; - - /* Compute the scaled DPLL multiplier, based on the divider */ - m = scaled_rt_rp * n; - - /* - * Since we're counting n up, a m overflow means we - * can bail out completely (since as n increases in - * the next iteration, there's no way that m can - * increase beyond the current m) - */ - if (m > scaled_max_m) - break; - - r = _dpll_test_mult(&m, n, &new_rate, target_rate, - ref_rate); - - /* m can't be set low enough for this n - try with a larger n */ - if (r == DPLL_MULT_UNDERFLOW) - continue; - - /* skip rates above our target rate */ - delta = target_rate - new_rate; - if (delta < 0) - continue; - - if (delta < prev_min_delta) { - prev_min_delta = delta; - min_delta_m = m; - min_delta_n = n; - } - - pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", - clk_name, m, n, new_rate); - - if (delta == 0) - break; - } - - if (prev_min_delta == LONG_MAX) { - pr_debug("clock: %s: cannot round to rate %lu\n", - clk_name, target_rate); - return ~0; - } - - dd->last_rounded_m = min_delta_m; - dd->last_rounded_n = min_delta_n; - dd->last_rounded_rate = target_rate - prev_min_delta; - - return dd->last_rounded_rate; -} - diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c deleted file mode 100644 index 55eb579aeae1..000000000000 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * OMAP2/3 interface clock control - * - * Copyright (C) 2011 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/clk-provider.h> -#include <linux/io.h> - -#include "clock.h" - -/* Register offsets */ -#define CM_AUTOIDLE 0x30 -#define CM_ICLKEN 0x10 - -/* Private functions */ - -/* XXX */ -void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) -{ - u32 v; - void __iomem *r; - - r = (__force void __iomem *) - ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - - v = omap2_clk_readl(clk, r); - v |= (1 << clk->enable_bit); - omap2_clk_writel(v, clk, r); -} - -/* XXX */ -void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) -{ - u32 v; - void __iomem *r; - - r = (__force void __iomem *) - ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - - v = omap2_clk_readl(clk, r); - v &= ~(1 << clk->enable_bit); - omap2_clk_writel(v, clk, r); -} - -/* Public data */ - -const struct clk_hw_omap_ops clkhwops_iclk = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; - -const struct clk_hw_omap_ops clkhwops_iclk_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap2_clk_dflt_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - - - diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a699d7169307..acb60ed17273 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,12 +20,11 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bitops.h> -#include <linux/regmap.h> #include <linux/of_address.h> -#include <linux/bootmem.h> #include <asm/cpu.h> #include <trace/events/power.h> @@ -40,19 +39,8 @@ #include "cm-regbits-34xx.h" #include "common.h" -/* - * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait - * for a module to indicate that it is no longer in idle - */ -#define MAX_MODULE_ENABLE_WAIT 100000 - u16 cpu_mask; -/* - * Clock features setup. Used instead of CPU type checks. - */ -struct ti_clk_features ti_clk_features; - /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 @@ -66,119 +54,24 @@ struct ti_clk_features ti_clk_features; #define OMAP3PLUS_DPLL_FINT_MIN 32000 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 -/* - * clkdm_control: if true, then when a clock is enabled in the - * hardware, its clockdomain will first be enabled; and when a clock - * is disabled in the hardware, its clockdomain will be disabled - * afterwards. - */ -static bool clkdm_control = true; - -static LIST_HEAD(clk_hw_omap_clocks); - -struct clk_iomap { - struct regmap *regmap; - void __iomem *mem; -}; - -static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; - -static void clk_memmap_writel(u32 val, void __iomem *reg) -{ - struct clk_omap_reg *r = (struct clk_omap_reg *)® - struct clk_iomap *io = clk_memmaps[r->index]; - - if (io->regmap) - regmap_write(io->regmap, r->offset, val); - else - writel_relaxed(val, io->mem + r->offset); -} - -static u32 clk_memmap_readl(void __iomem *reg) -{ - u32 val; - struct clk_omap_reg *r = (struct clk_omap_reg *)® - struct clk_iomap *io = clk_memmaps[r->index]; - - if (io->regmap) - regmap_read(io->regmap, r->offset, &val); - else - val = readl_relaxed(io->mem + r->offset); - - return val; -} - -void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) -{ - if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) - writel_relaxed(val, reg); - else - clk_memmap_writel(val, reg); -} - -u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) -{ - if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) - return readl_relaxed(reg); - else - return clk_memmap_readl(reg); -} - static struct ti_clk_ll_ops omap_clk_ll_ops = { - .clk_readl = clk_memmap_readl, - .clk_writel = clk_memmap_writel, + .clkdm_clk_enable = clkdm_clk_enable, + .clkdm_clk_disable = clkdm_clk_disable, + .cm_wait_module_ready = omap_cm_wait_module_ready, + .cm_split_idlest_reg = cm_split_idlest_reg, }; /** - * omap2_clk_provider_init - initialize a clock provider - * @match_table: DT device table to match for devices to init - * @np: device node pointer for the this clock provider - * @index: index for the clock provider - + @syscon: syscon regmap pointer - * @mem: iomem pointer for the clock provider memory area, only used if - * syscon is not provided + * omap2_clk_setup_ll_ops - setup clock driver low-level ops * - * Initializes a clock provider module (CM/PRM etc.), registering - * the memory mapping at specified index and initializing the - * low level driver infrastructure. Returns 0 in success. + * Sets up clock driver low-level platform ops. These are needed + * for register accesses and various other misc platform operations. + * Returns 0 on success, -EBUSY if low level ops have been registered + * already. */ -int __init omap2_clk_provider_init(struct device_node *np, int index, - struct regmap *syscon, void __iomem *mem) +int __init omap2_clk_setup_ll_ops(void) { - struct clk_iomap *io; - - ti_clk_ll_ops = &omap_clk_ll_ops; - - io = kzalloc(sizeof(*io), GFP_KERNEL); - - io->regmap = syscon; - io->mem = mem; - - clk_memmaps[index] = io; - - ti_dt_clk_init_provider(np, index); - - return 0; -} - -/** - * omap2_clk_legacy_provider_init - initialize a legacy clock provider - * @index: index for the clock provider - * @mem: iomem pointer for the clock provider memory area - * - * Initializes a legacy clock provider memory mapping. - */ -void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) -{ - struct clk_iomap *io; - - ti_clk_ll_ops = &omap_clk_ll_ops; - - io = memblock_virt_alloc(sizeof(*io), 0); - - io->mem = mem; - - clk_memmaps[index] = io; + return ti_clk_setup_ll_ops(&omap_clk_ll_ops); } /* @@ -187,77 +80,6 @@ void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) /* Private functions */ - -/** - * _wait_idlest_generic - wait for a module to leave the idle state - * @clk: module clock to wait for (needed for register offsets) - * @reg: virtual address of module IDLEST register - * @mask: value to mask against to determine if the module is active - * @idlest: idle state indicator (0 or 1) for the clock - * @name: name of the clock (for printk) - * - * Wait for a module to leave idle, where its idle-status register is - * not inside the CM module. Returns 1 if the module left idle - * promptly, or 0 if the module did not leave idle before the timeout - * elapsed. XXX Deprecated - should be moved into drivers for the - * individual IP block that the IDLEST register exists in. - */ -static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, - u32 mask, u8 idlest, const char *name) -{ - int i = 0, ena = 0; - - ena = (idlest) ? 0 : mask; - - omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), - MAX_MODULE_ENABLE_WAIT, i); - - if (i < MAX_MODULE_ENABLE_WAIT) - pr_debug("omap clock: module associated with clock %s ready after %d loops\n", - name, i); - else - pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", - name, MAX_MODULE_ENABLE_WAIT); - - return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; -}; - -/** - * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module - * - * If the necessary clocks for the OMAP hardware IP block that - * corresponds to clock @clk are enabled, then wait for the module to - * indicate readiness (i.e., to leave IDLE). This code does not - * belong in the clock code and will be moved in the medium term to - * module-dependent code. No return value. - */ -static void _omap2_module_wait_ready(struct clk_hw_omap *clk) -{ - void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; - s16 prcm_mod; - int r; - - /* Not all modules have multiple clocks that their IDLEST depends on */ - if (clk->ops->find_companion) { - clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) - return; - } - - clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); - if (r) { - /* IDLEST register not in the CM module */ - _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), - idlest_val, __clk_get_name(clk->hw.clk)); - } else { - omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id, - idlest_bit); - }; -} - /* Public functions */ /** @@ -290,279 +112,6 @@ void omap2_init_clk_clkdm(struct clk_hw *hw) } } -/** - * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable - * - * Prevent the OMAP clock code from calling into the clockdomain code - * when a hardware clock in that clockdomain is enabled or disabled. - * Intended to be called at init time from omap*_clk_init(). No - * return value. - */ -void __init omap2_clk_disable_clkdm_control(void) -{ - clkdm_control = false; -} - -/** - * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of - * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in - * @other_bit: u8 ** to return the companion clock bit shift in - * - * Note: We don't need special code here for INVERT_ENABLE for the - * time being since INVERT_ENABLE only applies to clocks enabled by - * CM_CLKEN_PLL - * - * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's - * just a matter of XORing the bits. - * - * Some clocks don't have companion clocks. For example, modules with - * only an interface clock (such as MAILBOXES) don't have a companion - * clock. Right now, this code relies on the hardware exporting a bit - * in the correct companion register that indicates that the - * nonexistent 'companion clock' is active. Future patches will - * associate this type of code with per-module data structures to - * avoid this issue, and remove the casts. No return value. - */ -void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, u8 *other_bit) -{ - u32 r; - - /* - * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes - * it's just a matter of XORing the bits. - */ - r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); - - *other_reg = (__force void __iomem *)r; - *other_bit = clk->enable_bit; -} - -/** - * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for - * @idlest_reg: void __iomem ** to return the CM_IDLEST va in - * @idlest_bit: u8 * to return the CM_IDLEST bit shift in - * @idlest_val: u8 * to return the idle status indicator - * - * Return the CM_IDLEST register address and bit shift corresponding - * to the module that "owns" this clock. This default code assumes - * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that - * the IDLEST register address ID corresponds to the CM_*CLKEN - * register address ID (e.g., that CM_FCLKEN2 corresponds to - * CM_IDLEST2). This is not true for all modules. No return value. - */ -void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = clk->enable_bit; - - /* - * 24xx uses 0 to indicate not ready, and 1 to indicate ready. - * 34xx reverses this, just to keep us on our toes - * AM35xx uses both, depending on the module. - */ - *idlest_val = ti_clk_features.cm_idlest_val; -} - -/** - * omap2_dflt_clk_enable - enable a clock in the hardware - * @hw: struct clk_hw * of the clock to enable - * - * Enable the clock @hw in the hardware. We first call into the OMAP - * clockdomain code to "enable" the corresponding clockdomain if this - * is the first enabled user of the clockdomain. Then program the - * hardware to enable the clock. Then wait for the IP block that uses - * this clock to leave idle (if applicable). Returns the error value - * from clkdm_clk_enable() if it terminated with an error, or -EINVAL - * if @hw has a null clock enable_reg, or zero upon success. - */ -int omap2_dflt_clk_enable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - u32 v; - int ret = 0; - - clk = to_clk_hw_omap(hw); - - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, hw->clk); - if (ret) { - WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), - clk->clkdm->name, ret); - return ret; - } - } - - if (unlikely(clk->enable_reg == NULL)) { - pr_err("%s: %s missing enable_reg\n", __func__, - __clk_get_name(hw->clk)); - ret = -EINVAL; - goto err; - } - - /* FIXME should not have INVERT_ENABLE bit here */ - v = omap2_clk_readl(clk, clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v &= ~(1 << clk->enable_bit); - else - v |= (1 << clk->enable_bit); - omap2_clk_writel(v, clk, clk->enable_reg); - v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ - - if (clk->ops && clk->ops->find_idlest) - _omap2_module_wait_ready(clk); - - return 0; - -err: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); - return ret; -} - -/** - * omap2_dflt_clk_disable - disable a clock in the hardware - * @hw: struct clk_hw * of the clock to disable - * - * Disable the clock @hw in the hardware, and call into the OMAP - * clockdomain code to "disable" the corresponding clockdomain if all - * clocks/hwmods in that clockdomain are now disabled. No return - * value. - */ -void omap2_dflt_clk_disable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - u32 v; - - clk = to_clk_hw_omap(hw); - if (!clk->enable_reg) { - /* - * 'independent' here refers to a clock which is not - * controlled by its parent. - */ - pr_err("%s: independent clock %s has no enable_reg\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - v = omap2_clk_readl(clk, clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v |= (1 << clk->enable_bit); - else - v &= ~(1 << clk->enable_bit); - omap2_clk_writel(v, clk, clk->enable_reg); - /* No OCP barrier needed here since it is a disable operation */ - - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); -} - -/** - * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw - * @hw: struct clk_hw * of the clock being enabled - * - * Increment the usecount of the clockdomain of the clock pointed to - * by @hw; if the usecount is 1, the clockdomain will be "enabled." - * Only needed for clocks that don't use omap2_dflt_clk_enable() as - * their enable function pointer. Passes along the return value of - * clkdm_clk_enable(), -EINVAL if @hw is not associated with a - * clockdomain, or 0 if clock framework-based clockdomain control is - * not implemented. - */ -int omap2_clkops_enable_clkdm(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - int ret = 0; - - clk = to_clk_hw_omap(hw); - - if (unlikely(!clk->clkdm)) { - pr_err("%s: %s: no clkdm set ?!\n", __func__, - __clk_get_name(hw->clk)); - return -EINVAL; - } - - if (unlikely(clk->enable_reg)) - pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, - __clk_get_name(hw->clk)); - - if (!clkdm_control) { - pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", - __func__, __clk_get_name(hw->clk)); - return 0; - } - - ret = clkdm_clk_enable(clk->clkdm, hw->clk); - WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); - - return ret; -} - -/** - * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw - * @hw: struct clk_hw * of the clock being disabled - * - * Decrement the usecount of the clockdomain of the clock pointed to - * by @hw; if the usecount is 0, the clockdomain will be "disabled." - * Only needed for clocks that don't use omap2_dflt_clk_disable() as their - * disable function pointer. No return value. - */ -void omap2_clkops_disable_clkdm(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - - clk = to_clk_hw_omap(hw); - - if (unlikely(!clk->clkdm)) { - pr_err("%s: %s: no clkdm set ?!\n", __func__, - __clk_get_name(hw->clk)); - return; - } - - if (unlikely(clk->enable_reg)) - pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, - __clk_get_name(hw->clk)); - - if (!clkdm_control) { - pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - clkdm_clk_disable(clk->clkdm, hw->clk); -} - -/** - * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? - * @hw: struct clk_hw * to check - * - * Return 1 if the clock represented by @hw is enabled in the - * hardware, or 0 otherwise. Intended for use in the struct - * clk_ops.is_enabled function pointer. - */ -int omap2_dflt_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - - v = omap2_clk_readl(clk, clk->enable_reg); - - if (clk->flags & INVERT_ENABLE) - v ^= BIT(clk->enable_bit); - - v &= BIT(clk->enable_bit); - - return v ? 1 : 0; -} - static int __initdata mpurate; /* @@ -584,178 +133,6 @@ static int __init omap_clk_setup(char *str) __setup("mpurate=", omap_clk_setup); /** - * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize - * - * Add an OMAP clock @clk to the internal list of OMAP clocks. Used - * temporarily for autoidle handling, until this support can be - * integrated into the common clock framework code in some way. No - * return value. - */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - list_add(&c->node, &clk_hw_omap_clocks); -} - -/** - * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that - * support it - * - * Enable clock autoidle on all OMAP clocks that have allow_idle - * function pointers associated with them. This function is intended - * to be temporary until support for this is added to the common clock - * code. Returns 0. - */ -int omap2_clk_enable_autoidle_all(void) -{ - struct clk_hw_omap *c; - - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); - - of_ti_clk_allow_autoidle_all(); - - return 0; -} - -/** - * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that - * support it - * - * Disable clock autoidle on all OMAP clocks that have allow_idle - * function pointers associated with them. This function is intended - * to be temporary until support for this is added to the common clock - * code. Returns 0. - */ -int omap2_clk_disable_autoidle_all(void) -{ - struct clk_hw_omap *c; - - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); - - of_ti_clk_deny_autoidle_all(); - - return 0; -} - -/** - * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for - * - * Disable autoidle on an OMAP clock. - */ -int omap2_clk_deny_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); - return 0; -} - -/** - * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for - * - * Enable autoidle on an OMAP clock. - */ -int omap2_clk_allow_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); - return 0; -} - -/** - * omap2_clk_enable_init_clocks - prepare & enable a list of clocks - * @clk_names: ptr to an array of strings of clock names to enable - * @num_clocks: number of clock names in @clk_names - * - * Prepare and enable a list of clocks, named by @clk_names. No - * return value. XXX Deprecated; only needed until these clocks are - * properly claimed and enabled by the drivers or core code that uses - * them. XXX What code disables & calls clk_put on these clocks? - */ -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) -{ - struct clk *init_clk; - int i; - - for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", - clk_names[i])) - continue; - clk_prepare_enable(init_clk); - } -} - -const struct clk_hw_omap_ops clkhwops_wait = { - .find_idlest = omap2_clk_dflt_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument - * @mpurate_ck_name: clk name of the clock to change rate - * - * Change the ARM MPU clock rate to the rate specified on the command - * line, if one was specified. @mpurate_ck_name should be - * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. - * XXX Does not handle voltage scaling - on OMAP2xxx this is currently - * handled by the virt_prcm_set clock, but this should be handled by - * the OPP layer. XXX This is intended to be handled by the OPP layer - * code in the near future and should be removed from the clock code. - * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name - * cannot be found, or 0 upon success. - */ -int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) -{ - struct clk *mpurate_ck; - int r; - - if (!mpurate) - return -EINVAL; - - mpurate_ck = clk_get(NULL, mpurate_ck_name); - if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) - return -ENOENT; - - r = clk_set_rate(mpurate_ck, mpurate); - if (r < 0) { - WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); - return -EINVAL; - } - - calibrate_delay(); - clk_put(mpurate_ck); - - return 0; -} - -/** * omap2_clk_print_new_rates - print summary of current clock tree rates * @hfclkin_ck_name: clk name for the off-chip HF oscillator * @core_ck_name: clk name for the on-chip CORE_CLK @@ -801,29 +178,30 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, */ void __init ti_clk_init_features(void) { + struct ti_clk_features features = { 0 }; /* Fint setup for DPLLs */ if (cpu_is_omap3430()) { - ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; - ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; - ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; - ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; } else { - ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; - ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; } /* Bypass value setup for DPLLs */ if (cpu_is_omap24xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); } else if (cpu_is_omap34xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || soc_is_omap54xx() || soc_is_dra7xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); @@ -831,7 +209,7 @@ void __init ti_clk_init_features(void) /* Jitter correction only available on OMAP343X */ if (cpu_is_omap343x()) - ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; + features.flags |= TI_CLK_DPLL_HAS_FREQSEL; /* Idlest value for interface clocks. * 24xx uses 0 to indicate not ready, and 1 to indicate ready. @@ -839,11 +217,13 @@ void __init ti_clk_init_features(void) * AM35xx uses both, depending on the module. */ if (cpu_is_omap24xx()) - ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; + features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; else if (cpu_is_omap34xx()) - ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; + features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ if (omap_rev() == OMAP3430_REV_ES1_0) - ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + + ti_clk_setup_features(&features); } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 652ed0ab86ec..67da640ba1c7 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -23,90 +23,6 @@ #include <linux/clk-provider.h> #include <linux/clk/ti.h> -struct omap_clk { - u16 cpu; - struct clk_lookup lk; -}; - -#define CLK(dev, con, ck) \ - { \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - }, \ - } - -struct clockdomain; - -#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk_core _name##_core = { \ - .name = #_name, \ - .hw = &_name##_hw.hw, \ - .parent_names = _parent_array_name, \ - .num_parents = ARRAY_SIZE(_parent_array_name), \ - .ops = &_clkops_name, \ - }; \ - static struct clk _name = { \ - .core = &_name##_core, \ - }; - -#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ - _clkops_name, _flags) \ - static struct clk_core _name##_core = { \ - .name = #_name, \ - .hw = &_name##_hw.hw, \ - .parent_names = _parent_array_name, \ - .num_parents = ARRAY_SIZE(_parent_array_name), \ - .ops = &_clkops_name, \ - .flags = _flags, \ - }; \ - static struct clk _name = { \ - .core = &_name##_core, \ - }; - -#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clkdm_name = _clkdm_name, \ - }; - -#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ - _clksel_reg, _clksel_mask, \ - _parent_names, _ops) \ - static struct clk _name; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clksel = _clksel, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .clkdm_name = _clkdm_name, \ - }; \ - DEFINE_STRUCT_CLK(_name, _parent_names, _ops); - -#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ - _clksel_reg, _clksel_mask, \ - _enable_reg, _enable_bit, \ - _hwops, _parent_names, _ops) \ - static struct clk _name; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .ops = _hwops, \ - .enable_reg = _enable_reg, \ - .enable_bit = _enable_bit, \ - .clksel = _clksel, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .clkdm_name = _clkdm_name, \ - }; \ - DEFINE_STRUCT_CLK(_name, _parent_names, _ops); - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -127,38 +43,6 @@ struct clockdomain; /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) - -/** - * struct clksel_rate - register bitfield values corresponding to clk divisors - * @val: register bitfield value (shifted to bit 0) - * @div: clock divisor corresponding to @val - * @flags: (see "struct clksel_rate.flags possibilities" above) - * - * @val should match the value of a read from struct clk.clksel_reg - * AND'ed with struct clk.clksel_mask, shifted right to bit 0. - * - * @div is the divisor that should be applied to the parent clock's rate - * to produce the current clock's rate. - */ -struct clksel_rate { - u32 val; - u8 div; - u16 flags; -}; - -/** - * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock - * @rates: available divisors for this parent clock - * - * A struct clksel is always associated with one or more struct clks - * and one or more struct clksel_rates. - */ -struct clksel { - struct clk *parent; - const struct clksel_rate *rates; -}; - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 @@ -180,105 +64,18 @@ struct clksel { #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 -u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); -void omap3_dpll_allow_idle(struct clk_hw_omap *clk); -void omap3_dpll_deny_idle(struct clk_hw_omap *clk); -void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); -void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); - -void __init omap2_clk_disable_clkdm_control(void); - -/* clkt_clksel.c public functions */ -u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, - unsigned long target_rate, - u32 *new_div); -u8 omap2_clksel_find_parent_index(struct clk_hw *hw); -unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); -long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); -int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); -int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); - -/* clkt_iclk.c public functions */ -extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); -extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); - -unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); - -void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); -int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); -int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); -u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg); -void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); - extern u16 cpu_mask; -/* - * Clock features setup. Used instead of CPU type checks. - */ -struct ti_clk_features { - u32 flags; - long fint_min; - long fint_max; - long fint_band1_max; - long fint_band2_min; - u8 dpll_bypass_vals; - u8 cm_idlest_val; -}; - -#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) -#define TI_CLK_DPLL4_DENY_REPROGRAM (1 << 1) - -extern struct ti_clk_features ti_clk_features; - extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt; extern struct clk_functions omap2_clk_functions; -extern const struct clksel_rate gpt_32k_rates[]; -extern const struct clksel_rate gpt_sys_rates[]; -extern const struct clksel_rate gfx_l3_rates[]; -extern const struct clksel_rate dsp_ick_rates[]; - -extern const struct clk_hw_omap_ops clkhwops_iclk_wait; -extern const struct clk_hw_omap_ops clkhwops_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -extern const struct clk_hw_omap_ops clkhwops_apll54; -extern const struct clk_hw_omap_ops clkhwops_apll96; - -/* clksel_rate blocks shared between OMAP44xx and AM33xx */ -extern const struct clksel_rate div_1_0_rates[]; -extern const struct clksel_rate div3_1to4_rates[]; -extern const struct clksel_rate div_1_1_rates[]; -extern const struct clksel_rate div_1_2_rates[]; -extern const struct clksel_rate div_1_3_rates[]; -extern const struct clksel_rate div_1_4_rates[]; -extern const struct clksel_rate div31_1to31_rates[]; - -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); - -struct regmap; - -int __init omap2_clk_provider_init(struct device_node *np, int index, - struct regmap *syscon, void __iomem *mem); -void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem); +int __init omap2_clk_setup_ll_ops(void); void __init ti_clk_init_features(void); #endif diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c deleted file mode 100644 index cef0c8d1de52..000000000000 --- a/arch/arm/mach-omap2/clock2430.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * clock2430.c - OMAP2430-specific clock integration code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "cm2xxx.h" -#include "cm-regbits-24xx.h" - -/** - * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the - * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function - * passes back the correct CM_IDLEST register address for I2CHS - * modules. No return value. - */ -static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST); - *idlest_bit = clk->enable_bit; - *idlest_val = OMAP24XX_CM_IDLEST_VAL; -} - -/* 2430 I2CHS has non-standard IDLEST register */ -const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { - .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c deleted file mode 100644 index b870f6a9e283..000000000000 --- a/arch/arm/mach-omap2/clock2xxx.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * clock2xxx.c - OMAP2xxx-specific clock integration code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "soc.h" -#include "clock.h" -#include "clock2xxx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" - -struct clk_hw *dclk_hw; -/* - * Omap24xx specific clock functions - */ - -/* - * Switch the MPU rate if specified on cmdline. We cannot do this - * early until cmdline is parsed. XXX This should be removed from the - * clock code and handled by the OPP layer code in the near future. - */ -static int __init omap2xxx_clk_arch_init(void) -{ - int ret; - - if (!cpu_is_omap24xx()) - return 0; - - ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set"); - if (!ret) - omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck"); - - return ret; -} - -omap_arch_initcall(omap2xxx_clk_arch_init); - - diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c deleted file mode 100644 index 4596468e50ab..000000000000 --- a/arch/arm/mach-omap2/clock34xx.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * OMAP3-specific clock framework functions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2011 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "clock.h" -#include "clock34xx.h" -#include "cm3xxx.h" -#include "cm-regbits-34xx.h" - -/** - * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift - * from the CM_{I,F}CLKEN bit. Pass back the correct info via - * @idlest_reg and @idlest_bit. No return value. - */ -static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} -const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * Some OMAP modules on OMAP3 ES2+ chips have both initiator and - * target IDLEST bits. For our purposes, we are concerned with the - * target IDLEST bits, which exist at a different bit position than - * the *CLKEN bit position for these modules (DSS and USBHOST) (The - * default find_idlest code assumes that they are at the same - * position.) No return value. - */ -static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - /* USBHOST_IDLE has same shift */ - *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different - * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via - * @idlest_reg and @idlest_bit. No return value. - */ -static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h deleted file mode 100644 index 084ba71b2b31..000000000000 --- a/arch/arm/mach-omap2/clock34xx.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * OMAP34xx clock function prototypes and macros - * - * Copyright (C) 2007-2010 Texas Instruments, Inc. - * Copyright (C) 2007-2011 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H - -extern const struct clkops clkops_omap3430es2_ssi_wait; -extern const struct clkops clkops_omap3430es2_iclk_ssi_wait; -extern const struct clkops clkops_omap3430es2_hsotgusb_wait; -extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait; -extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; -extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait; - -#endif diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c deleted file mode 100644 index 4d79ae2c0241..000000000000 --- a/arch/arm/mach-omap2/clock3517.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * OMAP3517/3505-specific clock framework functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2011 Nokia Corporation - * - * Ranjith Lohithakshan - * Paul Walmsley - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "clock.h" -#include "clock3517.h" -#include "cm3xxx.h" -#include "cm-regbits-34xx.h" - -/* - * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported - * in the same register at a bit offset of 0x8. The EN_ACK for ICK is - * at an offset of 4 from ICK enable bit. - */ -#define AM35XX_IPSS_ICK_MASK 0xF -#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 -#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 -#define AM35XX_IPSS_CLK_IDLEST_VAL 0 - -/** - * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The interface clocks on AM35xx IPSS reflects the clock idle status - * in the enable register itsel at a bit offset of 4 from the enable - * bit. A value of 1 indicates that clock is enabled. - */ -static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - *idlest_reg = (__force void __iomem *)(clk->enable_reg); - *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; - *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; -} - -/** - * am35xx_clk_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of - * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in - * @other_bit: u8 ** to return the companion clock bit shift in - * - * Some clocks don't have companion clocks. For example, modules with - * only an interface clock (such as HECC) don't have a companion - * clock. Right now, this code relies on the hardware exporting a bit - * in the correct companion register that indicates that the - * nonexistent 'companion clock' is active. Future patches will - * associate this type of code with per-module data structures to - * avoid this issue, and remove the casts. No return value. - */ -static void am35xx_clk_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit) -{ - *other_reg = (__force void __iomem *)(clk->enable_reg); - if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) - *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; - else - *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; -} -const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { - .find_idlest = am35xx_clk_find_idlest, - .find_companion = am35xx_clk_find_companion, -}; - -/** - * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The IPSS target CM_IDLEST bit is at a different shift from the - * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg - * and @idlest_bit. No return value. - */ -static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = AM35XX_ST_IPSS_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = am35xx_clk_ipss_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h deleted file mode 100644 index ca5e5a64c2e2..000000000000 --- a/arch/arm/mach-omap2/clock3517.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * OMAP3517/3505 clock function prototypes and macros - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H - -extern const struct clkops clkops_am35xx_ipss_module_wait; -extern const struct clkops clkops_am35xx_ipss_wait; - -#endif diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c deleted file mode 100644 index 91ccb962e09e..000000000000 --- a/arch/arm/mach-omap2/clock36xx.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * OMAP36xx-specific clkops - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * - * Mike Turquette - * Vijaykumar GN - * Paul Walmsley - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/io.h> - -#include "clock.h" -#include "clock36xx.h" -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - -/** - * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering - * from HSDivider PWRDN problem Implements Errata ID: i556. - * @clk: DPLL output struct clk - * - * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, - * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset - * valueafter their respective PWRDN bits are set. Any dummy write - * (Any other value different from the Read value) to the - * corresponding CM_CLKSEL register will refresh the dividers. - */ -int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) -{ - struct clk_divider *parent; - struct clk_hw *parent_hw; - u32 dummy_v, orig_v; - struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk); - int ret; - - /* Clear PWRDN bit of HSDIVIDER */ - ret = omap2_dflt_clk_enable(clk); - - parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); - parent = to_clk_divider(parent_hw); - - /* Restore the dividers */ - if (!ret) { - orig_v = omap2_clk_readl(omap_clk, parent->reg); - dummy_v = orig_v; - - /* Write any other value different from the Read value */ - dummy_v ^= (1 << parent->shift); - omap2_clk_writel(dummy_v, omap_clk, parent->reg); - - /* Write the original divider */ - omap2_clk_writel(orig_v, omap_clk, parent->reg); - } - - return ret; -} diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h deleted file mode 100644 index 945bb7f083e9..000000000000 --- a/arch/arm/mach-omap2/clock36xx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * OMAP36xx clock function prototypes and macros - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H - -extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw); - -#endif diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c deleted file mode 100644 index a9e86db5daf9..000000000000 --- a/arch/arm/mach-omap2/clock3xxx.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * OMAP3-specific clock framework functions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "soc.h" -#include "clock.h" -#include "clock3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-34xx.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" - -/* - * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks - * that are sourced by DPLL5, and both of these require this clock - * to be at 120 MHz for proper operation. - */ -#define DPLL5_FREQ_FOR_USBHOST 120000000 - -/* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; - -/** - * omap3_dpll4_set_rate - set rate for omap3 per-dpll - * @hw: clock to change - * @rate: target rate for clock - * @parent_rate: rate of the parent clock - * - * Check if the current SoC supports the per-dpll reprogram operation - * or not, and then do the rate change if supported. Returns -EINVAL - * if not supported, 0 for success, and potential error codes from the - * clock rate change. - */ -int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - /* - * According to the 12-5 CDP code from TI, "Limitation 2.5" - * on 3430ES1 prevents us from changing DPLL multipliers or dividers - * on DPLL4. - */ - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { - pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); - return -EINVAL; - } - - return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); -} - -/** - * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll - * @hw: clock to change - * @rate: target rate for clock - * @parent_rate: rate of the parent clock - * @index: parent index, 0 - reference clock, 1 - bypass clock - * - * Check if the current SoC support the per-dpll reprogram operation - * or not, and then do the rate + parent change if supported. Returns - * -EINVAL if not supported, 0 for success, and potential error codes - * from the clock rate change. - */ -int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate, u8 index) -{ - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { - pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); - return -EINVAL; - } - - return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate, - index); -} - -void __init omap3_clk_lock_dpll5(void) -{ - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; - - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); - - /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); - return; -} - -/* Common clock code */ - -/* - * Switch the MPU rate if specified on cmdline. We cannot do this - * early until cmdline is parsed. XXX This should be removed from the - * clock code and handled by the OPP layer code in the near future. - */ -static int __init omap3xxx_clk_arch_init(void) -{ - int ret; - - if (!cpu_is_omap34xx()) - return 0; - - ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); - if (!ret) - omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); - - return ret; -} - -omap_arch_initcall(omap3xxx_clk_arch_init); - - diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h deleted file mode 100644 index 287a46f78d97..000000000000 --- a/arch/arm/mach-omap2/clock44xx.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * OMAP4 clock function prototypes and macros - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H - -/* - * OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is - * set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM - * vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters") - */ -#define OMAP4430_REGM4XEN_MULT 4 - -int omap4xxx_clk_init(void); - -#endif diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c deleted file mode 100644 index 61b60dfb14ce..000000000000 --- a/arch/arm/mach-omap2/clock_common_data.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/clock_common_data.c - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains clock data that is common to both the OMAP2xxx and - * OMAP3xxx clock definition files. - */ - -#include "clock.h" - -/* clksel_rate data common to 24xx/343x */ -const struct clksel_rate gpt_32k_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate gpt_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate gfx_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate dsp_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_243X }, - { .div = 0 }, -}; - - -/* clksel_rate blocks shared between OMAP44xx and AM33xx */ - -const struct clksel_rate div_1_0_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_2_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_3_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_4_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 77bab5fb6814..2c398ce1a0f2 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -216,7 +216,8 @@ extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); -extern void __init ti81xx_clockdomains_init(void); +extern void __init ti814x_clockdomains_init(void); +extern void __init ti816x_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void __init omap54xx_clockdomains_init(void); extern void __init dra7xx_clockdomains_init(void); diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 57d5df0c1fbd..7581e036bda6 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -331,7 +331,7 @@ static struct clockdomain l4per2_7xx_clkdm = { .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT, .wkdep_srcs = l4per2_wkup_sleep_deps, .sleepdep_srcs = l4per2_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain mpu0_7xx_clkdm = { diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c index ce2a82001d0d..53442c86a820 100644 --- a/arch/arm/mach-omap2/clockdomains81xx_data.c +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c @@ -165,7 +165,24 @@ static struct clockdomain default_l3_slow_816x_clkdm = { .flags = CLKDM_CAN_SWSUP, }; -static struct clockdomain *clockdomains_ti81xx[] __initdata = { +static struct clockdomain *clockdomains_ti814x[] __initdata = { + &alwon_l3_slow_81xx_clkdm, + &alwon_l3_med_81xx_clkdm, + &alwon_l3_fast_81xx_clkdm, + &alwon_ethernet_81xx_clkdm, + &mmu_81xx_clkdm, + &mmu_cfg_81xx_clkdm, + NULL, +}; + +void __init ti814x_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&am33xx_clkdm_operations); + clkdm_register_clkdms(clockdomains_ti814x); + clkdm_complete_init(); +} + +static struct clockdomain *clockdomains_ti816x[] __initdata = { &alwon_mpu_816x_clkdm, &alwon_l3_slow_81xx_clkdm, &alwon_l3_med_81xx_clkdm, @@ -185,10 +202,10 @@ static struct clockdomain *clockdomains_ti81xx[] __initdata = { NULL, }; -void __init ti81xx_clockdomains_init(void) +void __init ti816x_clockdomains_init(void) { clkdm_register_platform_funcs(&am33xx_clkdm_operations); - clkdm_register_clkdms(clockdomains_ti81xx); + clkdm_register_clkdms(clockdomains_ti816x); clkdm_complete_init(); } #endif diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index eae6a0e87c90..484cdadfb187 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -30,4 +30,5 @@ int __weak omap_secure_ram_reserve_memblock(void) void __init omap_reserve(void) { omap_secure_ram_reserve_memblock(); + omap_barrier_reserve_memblock(); } diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index cf3cf22ecd42..92e92cfc2775 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -189,6 +189,15 @@ static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd) } #endif +#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER +void omap_barrier_reserve_memblock(void); +void omap_barriers_init(void); +#else +static inline void omap_barrier_reserve_memblock(void) +{ +} +#endif + /* This gets called from mach-omap2/io.c, do not call this */ void __init omap2_set_globals_tap(u32 class, void __iomem *tap); @@ -198,6 +207,7 @@ void __init omap3_map_io(void); void __init am33xx_map_io(void); void __init omap4_map_io(void); void __init omap5_map_io(void); +void __init dra7xx_map_io(void); void __init ti81xx_map_io(void); /** diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index f008930277ed..cf5855174c93 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -652,6 +652,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,am4-scm", .data = &ctrl_data }, { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, + { .compatible = "ti,dm814-scm", .data = &ctrl_data }, { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c deleted file mode 100644 index 44e57ec225d4..000000000000 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - * OMAP3/4 - specific DPLL control functions - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Written by Paul Walmsley - * Testing and integration fixes by Jouni Högander - * - * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth - * Menon - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/bitops.h> -#include <linux/clkdev.h> - -#include "clockdomain.h" -#include "clock.h" - -/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ -#define DPLL_AUTOIDLE_DISABLE 0x0 -#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 - -#define MAX_DPLL_WAIT_TRIES 1000000 - -/* Private functions */ - -/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) -{ - const struct dpll_data *dd; - u32 v; - - dd = clk->dpll_data; - - v = omap2_clk_readl(clk, dd->control_reg); - v &= ~dd->enable_mask; - v |= clken_bits << __ffs(dd->enable_mask); - omap2_clk_writel(v, clk, dd->control_reg); -} - -/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) -{ - const struct dpll_data *dd; - int i = 0; - int ret = -EINVAL; - const char *clk_name; - - dd = clk->dpll_data; - clk_name = __clk_get_name(clk->hw.clk); - - state <<= __ffs(dd->idlest_mask); - - while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) - != state) && i < MAX_DPLL_WAIT_TRIES) { - i++; - udelay(1); - } - - if (i == MAX_DPLL_WAIT_TRIES) { - printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk_name, (state) ? "locked" : "bypassed"); - } else { - pr_debug("clock: %s transition to '%s' in %d loops\n", - clk_name, (state) ? "locked" : "bypassed", i); - - ret = 0; - } - - return ret; -} - -/* From 3430 TRM ES2 4.7.6.2 */ -static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) -{ - unsigned long fint; - u16 f = 0; - - fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; - - pr_debug("clock: fint is %lu\n", fint); - - if (fint >= 750000 && fint <= 1000000) - f = 0x3; - else if (fint > 1000000 && fint <= 1250000) - f = 0x4; - else if (fint > 1250000 && fint <= 1500000) - f = 0x5; - else if (fint > 1500000 && fint <= 1750000) - f = 0x6; - else if (fint > 1750000 && fint <= 2100000) - f = 0x7; - else if (fint > 7500000 && fint <= 10000000) - f = 0xB; - else if (fint > 10000000 && fint <= 12500000) - f = 0xC; - else if (fint > 12500000 && fint <= 15000000) - f = 0xD; - else if (fint > 15000000 && fint <= 17500000) - f = 0xE; - else if (fint > 17500000 && fint <= 21000000) - f = 0xF; - else - pr_debug("clock: unknown freqsel setting for %d\n", n); - - return f; -} - -/* - * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report - * readiness before returning. Will save and restore the DPLL's - * autoidle state across the enable, per the CDP code. If the DPLL - * locked successfully, return 0; if the DPLL did not lock in the time - * allotted, or DPLL3 was passed in, return -EINVAL. - */ -static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u8 ai; - u8 state = 1; - int r = 0; - - pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); - - dd = clk->dpll_data; - state <<= __ffs(dd->idlest_mask); - - /* Check if already locked */ - if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) - goto done; - - ai = omap3_dpll_autoidle_read(clk); - - if (ai) - omap3_dpll_deny_idle(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOCKED); - - r = _omap3_wait_dpll_status(clk, 1); - - if (ai) - omap3_dpll_allow_idle(clk); - -done: - return r; -} - -/* - * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power bypass mode. In - * bypass mode, the DPLL's rate is set equal to its parent clock's - * rate. Waits for the DPLL to report readiness before returning. - * Will save and restore the DPLL's autoidle state across the enable, - * per the CDP code. If the DPLL entered bypass mode successfully, - * return 0; if the DPLL did not enter bypass in the time allotted, or - * DPLL3 was passed in, or the DPLL does not support low-power bypass, - * return -EINVAL. - */ -static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) -{ - int r; - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) - return -EINVAL; - - pr_debug("clock: configuring DPLL %s for low-power bypass\n", - __clk_get_name(clk->hw.clk)); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); - - r = _omap3_wait_dpll_status(clk, 0); - - if (ai) - omap3_dpll_allow_idle(clk); - - return r; -} - -/* - * _omap3_noncore_dpll_stop - instruct a DPLL to stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. Will save and - * restore the DPLL's autoidle state across the stop, per the CDP - * code. If DPLL3 was passed in, or the DPLL does not support - * low-power stop, return -EINVAL; otherwise, return 0. - */ -static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) -{ - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) - return -EINVAL; - - pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); - - if (ai) - omap3_dpll_allow_idle(clk); - - return 0; -} - -/** - * _lookup_dco - Lookup DCO used by j-type DPLL - * @clk: pointer to a DPLL struct clk - * @dco: digital control oscillator selector - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * - * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" - * - * XXX This code is not needed for 3430/AM35xx; can it be optimized - * out in non-multi-OMAP builds for those chips? - */ -static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) -{ - unsigned long fint, clkinp; /* watch out for overflow */ - - clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); - fint = (clkinp / n) * m; - - if (fint < 1000000000) - *dco = 2; - else - *dco = 4; -} - -/** - * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL - * @clk: pointer to a DPLL struct clk - * @sd_div: target sigma-delta divider - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * - * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" - * - * XXX This code is not needed for 3430/AM35xx; can it be optimized - * out in non-multi-OMAP builds for those chips? - */ -static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) -{ - unsigned long clkinp, sd; /* watch out for overflow */ - int mod1, mod2; - - clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); - - /* - * target sigma-delta to near 250MHz - * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] - */ - clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ - mod1 = (clkinp * m) % (250 * n); - sd = (clkinp * m) / (250 * n); - mod2 = sd % 10; - sd /= 10; - - if (mod1 || mod2) - sd++; - *sd_div = sd; -} - -/* - * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set - * @freqsel: FREQSEL value to set - * - * Program the DPLL with the last M, N values calculated, and wait for - * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success. - */ -static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) -{ - struct dpll_data *dd = clk->dpll_data; - u8 dco, sd_div; - u32 v; - - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); - - /* - * Set jitter correction. Jitter correction applicable for OMAP343X - * only since freqsel field is no longer present on other devices. - */ - if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { - v = omap2_clk_readl(clk, dd->control_reg); - v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); - omap2_clk_writel(v, clk, dd->control_reg); - } - - /* Set DPLL multiplier, divider */ - v = omap2_clk_readl(clk, dd->mult_div1_reg); - - /* Handle Duty Cycle Correction */ - if (dd->dcc_mask) { - if (dd->last_rounded_rate >= dd->dcc_rate) - v |= dd->dcc_mask; /* Enable DCC */ - else - v &= ~dd->dcc_mask; /* Disable DCC */ - } - - v &= ~(dd->mult_mask | dd->div1_mask); - v |= dd->last_rounded_m << __ffs(dd->mult_mask); - v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); - - /* Configure dco and sd_div for dplls that have these fields */ - if (dd->dco_mask) { - _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); - v &= ~(dd->dco_mask); - v |= dco << __ffs(dd->dco_mask); - } - if (dd->sddiv_mask) { - _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, - dd->last_rounded_n); - v &= ~(dd->sddiv_mask); - v |= sd_div << __ffs(dd->sddiv_mask); - } - - omap2_clk_writel(v, clk, dd->mult_div1_reg); - - /* Set 4X multiplier and low-power mode */ - if (dd->m4xen_mask || dd->lpmode_mask) { - v = omap2_clk_readl(clk, dd->control_reg); - - if (dd->m4xen_mask) { - if (dd->last_rounded_m4xen) - v |= dd->m4xen_mask; - else - v &= ~dd->m4xen_mask; - } - - if (dd->lpmode_mask) { - if (dd->last_rounded_lpmode) - v |= dd->lpmode_mask; - else - v &= ~dd->lpmode_mask; - } - - omap2_clk_writel(v, clk, dd->control_reg); - } - - /* We let the clock framework set the other output dividers later */ - - /* REVISIT: Set ramp-up delay? */ - - _omap3_noncore_dpll_lock(clk); - - return 0; -} - -/* Public functions */ - -/** - * omap3_dpll_recalc - recalculate DPLL rate - * @clk: DPLL struct clk - * - * Recalculate and propagate the DPLL rate. - */ -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - return omap2_get_dpll_rate(clk); -} - -/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ - -/** - * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. - * The choice of modes depends on the DPLL's programmed rate: if it is - * the same as the DPLL's parent clock, it will enter bypass; - * otherwise, it will enter lock. This code will wait for the DPLL to - * indicate readiness before returning, unless the DPLL takes too long - * to enter the target state. Intended to be used as the struct clk's - * enable function. If DPLL3 was passed in, or the DPLL does not - * support low-power stop, or if the DPLL took too long to enter - * bypass or lock, return -EINVAL; otherwise, return 0. - */ -int omap3_noncore_dpll_enable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int r; - struct dpll_data *dd; - struct clk_hw *parent; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (clk->clkdm) { - r = clkdm_clk_enable(clk->clkdm, hw->clk); - if (r) { - WARN(1, - "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), - clk->clkdm->name, r); - return r; - } - } - - parent = __clk_get_hw(__clk_get_parent(hw->clk)); - - if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { - WARN_ON(parent != __clk_get_hw(dd->clk_bypass)); - r = _omap3_noncore_dpll_bypass(clk); - } else { - WARN_ON(parent != __clk_get_hw(dd->clk_ref)); - r = _omap3_noncore_dpll_lock(clk); - } - - return r; -} - -/** - * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. This function is - * intended for use in struct clkops. No return value. - */ -void omap3_noncore_dpll_disable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - _omap3_noncore_dpll_stop(clk); - if (clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); -} - - -/* Non-CORE DPLL rate set code */ - -/** - * omap3_noncore_dpll_determine_rate - determine rate for a DPLL - * @hw: pointer to the clock to determine rate for - * @rate: target rate for the DPLL - * @best_parent_rate: pointer for returning best parent rate - * @best_parent_clk: pointer for returning best parent clock - * - * Determines which DPLL mode to use for reaching a desired target rate. - * Checks whether the DPLL shall be in bypass or locked mode, and if - * locked, calculates the M,N values for the DPLL via round-rate. - * Returns a positive clock rate with success, negative error value - * in failure. - */ -long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_rate(dd->clk_bypass) == rate && - (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - *best_parent_clk = __clk_get_hw(dd->clk_bypass); - } else { - rate = omap2_dpll_round_rate(hw, rate, best_parent_rate); - *best_parent_clk = __clk_get_hw(dd->clk_ref); - } - - *best_parent_rate = rate; - - return rate; -} - -/** - * omap3_noncore_dpll_set_parent - set parent for a DPLL clock - * @hw: pointer to the clock to set parent for - * @index: parent index to select - * - * Sets parent for a DPLL clock. This sets the DPLL into bypass or - * locked mode. Returns 0 with success, negative error value otherwise. - */ -int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int ret; - - if (!hw) - return -EINVAL; - - if (index) - ret = _omap3_noncore_dpll_bypass(clk); - else - ret = _omap3_noncore_dpll_lock(clk); - - return ret; -} - -/** - * omap3_noncore_dpll_set_rate - set rate for a DPLL clock - * @hw: pointer to the clock to set parent for - * @rate: target rate for the clock - * @parent_rate: rate of the parent clock - * - * Sets rate for a DPLL clock. First checks if the clock parent is - * reference clock (in bypass mode, the rate of the clock can't be - * changed) and proceeds with the rate change operation. Returns 0 - * with success, negative error value otherwise. - */ -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - u16 freqsel = 0; - int ret; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_hw(__clk_get_parent(hw->clk)) != - __clk_get_hw(dd->clk_ref)) - return -EINVAL; - - if (dd->last_rounded_rate == 0) - return -EINVAL; - - /* Freqsel is available only on OMAP343X devices */ - if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { - freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); - WARN_ON(!freqsel); - } - - pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__, - __clk_get_name(hw->clk), rate); - - ret = omap3_noncore_dpll_program(clk, freqsel); - - return ret; -} - -/** - * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock - * @hw: pointer to the clock to set rate and parent for - * @rate: target rate for the DPLL - * @parent_rate: clock rate of the DPLL parent - * @index: new parent index for the DPLL, 0 - reference, 1 - bypass - * - * Sets rate and parent for a DPLL clock. If new parent is the bypass - * clock, only selects the parent. Otherwise proceeds with a rate - * change, as this will effectively also change the parent as the - * DPLL is put into locked mode. Returns 0 with success, negative error - * value otherwise. - */ -int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate, - u8 index) -{ - int ret; - - if (!hw || !rate) - return -EINVAL; - - /* - * clk-ref at index[0], in which case we only need to set rate, - * the parent will be changed automatically with the lock sequence. - * With clk-bypass case we only need to change parent. - */ - if (index) - ret = omap3_noncore_dpll_set_parent(hw, index); - else - ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate); - - return ret; -} - -/* DPLL autoidle read/set code */ - -/** - * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read - * - * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not - * appear to refer to a DPLL. - */ -u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return -EINVAL; - - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= dd->autoidle_mask; - v >>= __ffs(dd->autoidle_mask); - - return v; -} - -/** - * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on - * - * Enable DPLL automatic idle control. This automatic idle mode - * switching takes effect only when the DPLL is locked, at least on - * OMAP3430. The DPLL will enter low-power stop when its downstream - * clocks are gated. No return value. - */ -void omap3_dpll_allow_idle(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return; - - /* - * REVISIT: CORE DPLL can optionally enter low-power bypass - * by writing 0x5 instead of 0x1. Add some mechanism to - * optionally enter this mode. - */ - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - omap2_clk_writel(v, clk, dd->autoidle_reg); - -} - -/** - * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on - * - * Disable DPLL automatic idle control. No return value. - */ -void omap3_dpll_deny_idle(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return; - - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - omap2_clk_writel(v, clk, dd->autoidle_reg); - -} - -/* Clock control for DPLL outputs */ - -/* Find the parent DPLL for the given clkoutx2 clock */ -static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) -{ - struct clk_hw_omap *pclk = NULL; - struct clk *parent; - - /* Walk up the parents of clk, looking for a DPLL */ - do { - do { - parent = __clk_get_parent(hw->clk); - hw = __clk_get_hw(parent); - } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); - if (!hw) - break; - pclk = to_clk_hw_omap(hw); - } while (pclk && !pclk->dpll_data); - - /* clk does not have a DPLL as a parent? error in the clock data */ - if (!pclk) { - WARN_ON(1); - return NULL; - } - - return pclk; -} - -/** - * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate - * @clk: DPLL output struct clk - * - * Using parent clock DPLL data, look up DPLL state. If locked, set our - * rate to the dpll_clk * 2; otherwise, just use dpll_clk. - */ -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - const struct dpll_data *dd; - unsigned long rate; - u32 v; - struct clk_hw_omap *pclk = NULL; - - if (!parent_rate) - return 0; - - pclk = omap3_find_clkoutx2_dpll(hw); - - if (!pclk) - return 0; - - dd = pclk->dpll_data; - - WARN_ON(!dd->enable_mask); - - v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); - if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) - rate = parent_rate; - else - rate = parent_rate * 2; - return rate; -} - -int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - return 0; -} - -long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - const struct dpll_data *dd; - u32 v; - struct clk_hw_omap *pclk = NULL; - - if (!*prate) - return 0; - - pclk = omap3_find_clkoutx2_dpll(hw); - - if (!pclk) - return 0; - - dd = pclk->dpll_data; - - /* TYPE J does not have a clkoutx2 */ - if (dd->flags & DPLL_J_TYPE) { - *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate); - return *prate; - } - - WARN_ON(!dd->enable_mask); - - v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* If in bypass, the rate is fixed to the bypass rate*/ - if (v != OMAP3XXX_EN_DPLL_LOCKED) - return *prate; - - if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { - unsigned long best_parent; - - best_parent = (rate / 2); - *prate = __clk_round_rate(__clk_get_parent(hw->clk), - best_parent); - } - - return *prate * 2; -} - -/* OMAP3/4 non-CORE DPLL clkops */ -const struct clk_hw_omap_ops clkhwops_omap3_dpll = { - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c deleted file mode 100644 index f231be05b9a6..000000000000 --- a/arch/arm/mach-omap2/dpll44xx.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * OMAP4-specific DPLL control functions - * - * Copyright (C) 2011 Texas Instruments, Inc. - * Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/bitops.h> - -#include "clock.h" - -/* - * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that - * can supported when using the DPLL low-power mode. Frequencies are - * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, - * Status, and Low-Power Operation Mode". - */ -#define OMAP4_DPLL_LP_FINT_MAX 1000000 -#define OMAP4_DPLL_LP_FOUT_MAX 100000000 - -/* - * Bitfield declarations - */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) - -/* Static rate multiplier for OMAP4 REGM4XEN clocks */ -#define OMAP4430_REGM4XEN_MULT 4 - -void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) -{ - u32 v; - u32 mask; - - if (!clk || !clk->clksel_reg) - return; - - mask = clk->flags & CLOCK_CLKOUTX2 ? - OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : - OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - - v = omap2_clk_readl(clk, clk->clksel_reg); - /* Clear the bit to allow gatectrl */ - v &= ~mask; - omap2_clk_writel(v, clk, clk->clksel_reg); -} - -void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) -{ - u32 v; - u32 mask; - - if (!clk || !clk->clksel_reg) - return; - - mask = clk->flags & CLOCK_CLKOUTX2 ? - OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : - OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - - v = omap2_clk_readl(clk, clk->clksel_reg); - /* Set the bit to deny gatectrl */ - v |= mask; - omap2_clk_writel(v, clk, clk->clksel_reg); -} - -const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { - .allow_idle = omap4_dpllmx_allow_gatectrl, - .deny_idle = omap4_dpllmx_deny_gatectrl, -}; - -/** - * omap4_dpll_lpmode_recalc - compute DPLL low-power setting - * @dd: pointer to the dpll data structure - * - * Calculates if low-power mode can be enabled based upon the last - * multiplier and divider values calculated. If low-power mode can be - * enabled, then the bit to enable low-power mode is stored in the - * last_rounded_lpmode variable. This implementation is based upon the - * criteria for enabling low-power mode as described in the OMAP4430/60 - * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power - * Operation Mode". - */ -static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) -{ - long fint, fout; - - fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); - fout = fint * dd->last_rounded_m; - - if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) - dd->last_rounded_lpmode = 1; - else - dd->last_rounded_lpmode = 0; -} - -/** - * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for - * - * Compute the output rate for the OMAP4 DPLL represented by @clk. - * Takes the REGM4XEN bit into consideration, which is needed for the - * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) - * upon success, or 0 upon error. - */ -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - unsigned long rate; - struct dpll_data *dd; - - if (!clk || !clk->dpll_data) - return 0; - - dd = clk->dpll_data; - - rate = omap2_get_dpll_rate(clk); - - /* regm4xen adds a multiplier of 4 to DPLL calculations */ - v = omap2_clk_readl(clk, dd->control_reg); - if (v & OMAP4430_DPLL_REGM4XEN_MASK) - rate *= OMAP4430_REGM4XEN_MULT; - - return rate; -} - -/** - * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for - * @target_rate: the desired rate of the DPLL - * - * Compute the rate that would be programmed into the DPLL hardware - * for @clk if set_rate() were to be provided with the rate - * @target_rate. Takes the REGM4XEN bit into consideration, which is - * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before - * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or - * ~0 if an error occurred in omap2_dpll_round_rate(). - */ -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - long r; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd = clk->dpll_data; - - dd->last_rounded_m4xen = 0; - - /* - * First try to compute the DPLL configuration for - * target rate without using the 4X multiplier. - */ - r = omap2_dpll_round_rate(hw, target_rate, NULL); - if (r != ~0) - goto out; - - /* - * If we did not find a valid DPLL configuration, try again, but - * this time see if using the 4X multiplier can help. Enabling the - * 4X multiplier is equivalent to dividing the target rate by 4. - */ - r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, - NULL); - if (r == ~0) - return r; - - dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; - dd->last_rounded_m4xen = 1; - -out: - omap4_dpll_lpmode_recalc(dd); - - return dd->last_rounded_rate; -} - -/** - * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL - * @hw: pointer to the clock to determine rate for - * @rate: target rate for the DPLL - * @best_parent_rate: pointer for returning best parent rate - * @best_parent_clk: pointer for returning best parent clock - * - * Determines which DPLL mode to use for reaching a desired rate. - * Checks whether the DPLL shall be in bypass or locked mode, and if - * locked, calculates the M,N values for the DPLL via round-rate. - * Returns a positive clock rate with success, negative error value - * in failure. - */ -long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_rate(dd->clk_bypass) == rate && - (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - *best_parent_clk = __clk_get_hw(dd->clk_bypass); - } else { - rate = omap4_dpll_regm4xen_round_rate(hw, rate, - best_parent_rate); - *best_parent_clk = __clk_get_hw(dd->clk_ref); - } - - *best_parent_rate = rate; - - return rate; -} diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h deleted file mode 100644 index 1c582a8592b9..000000000000 --- a/arch/arm/mach-omap2/include/mach/barriers.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * OMAP memory barrier header. - * - * Copyright (C) 2011 Texas Instruments, Inc. - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __MACH_BARRIERS_H -#define __MACH_BARRIERS_H - -#include <asm/outercache.h> - -extern void omap_bus_sync(void); - -#define rmb() dsb() -#define wmb() do { dsb(); outer_sync(); omap_bus_sync(); } while (0) -#define mb() wmb() - -#endif /* __MACH_BARRIERS_H */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 820dde8b5b04..980c9372e6fd 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -37,7 +37,6 @@ #include "clock.h" #include "clock2xxx.h" #include "clock3xxx.h" -#include "clock44xx.h" #include "omap-pm.h" #include "sdrc.h" #include "control.h" @@ -236,7 +235,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif -#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) +#ifdef CONFIG_SOC_OMAP5 static struct map_desc omap54xx_io_desc[] __initdata = { { .virtual = L3_54XX_VIRT, @@ -265,6 +264,53 @@ static struct map_desc omap54xx_io_desc[] __initdata = { }; #endif +#ifdef CONFIG_SOC_DRA7XX +static struct map_desc dra7xx_io_desc[] __initdata = { + { + .virtual = L4_CFG_MPU_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), + .length = L4_CFG_MPU_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L3_MAIN_SN_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), + .length = L3_MAIN_SN_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_PER1_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), + .length = L4_PER1_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_PER2_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), + .length = L4_PER2_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_PER3_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), + .length = L4_PER3_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_CFG_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), + .length = L4_CFG_DRA7XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_WKUP_DRA7XX_VIRT, + .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), + .length = L4_WKUP_DRA7XX_SIZE, + .type = MT_DEVICE, + }, +}; +#endif + #ifdef CONFIG_SOC_OMAP2420 void __init omap242x_map_io(void) { @@ -306,13 +352,22 @@ void __init am33xx_map_io(void) void __init omap4_map_io(void) { iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); + omap_barriers_init(); } #endif -#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) +#ifdef CONFIG_SOC_OMAP5 void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); + omap_barriers_init(); +} +#endif + +#ifdef CONFIG_SOC_DRA7XX +void __init dra7xx_map_io(void) +{ + iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); } #endif /* @@ -554,11 +609,11 @@ void __init ti814x_init_early(void) omap2_prcm_base_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); - ti81xx_clockdomains_init(); - ti81xx_hwmod_init(); + ti814x_clockdomains_init(); + dm814x_hwmod_init(); omap_hwmod_init_postsetup(); if (of_have_populated_dt()) - omap_clk_soc_init = ti81xx_dt_clk_init; + omap_clk_soc_init = dm814x_dt_clk_init; } void __init ti816x_init_early(void) @@ -571,11 +626,11 @@ void __init ti816x_init_early(void) omap2_prcm_base_init(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); - ti81xx_clockdomains_init(); - ti81xx_hwmod_init(); + ti816x_clockdomains_init(); + dm816x_hwmod_init(); omap_hwmod_init_postsetup(); if (of_have_populated_dt()) - omap_clk_soc_init = ti81xx_dt_clk_init; + omap_clk_soc_init = dm816x_dt_clk_init; } #endif @@ -723,6 +778,8 @@ int __init omap_clk_init(void) ti_clk_init_features(); + omap2_clk_setup_ll_ops(); + if (of_have_populated_dt()) { ret = omap_control_init(); if (ret) diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h index cce2b65039f1..6191d244438a 100644 --- a/arch/arm/mach-omap2/iomap.h +++ b/arch/arm/mach-omap2/iomap.h @@ -194,3 +194,66 @@ #define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ #define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_PER_54XX_SIZE SZ_4M + +/* + * ---------------------------------------------------------------------------- + * DRA7xx specific IO mapping + * ---------------------------------------------------------------------------- + */ +/* + * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000 + * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping + * everything is just inefficient, since, there are too many address holes. + */ +#define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE +#define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET) +#define L3_MAIN_SN_DRA7XX_SIZE SZ_1M + +/* + * L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB) + * (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000) + */ +#define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE +#define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER1_DRA7XX_SIZE SZ_1M + +/* + * L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB) + * (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000) + * NOTE: This is a bit of an orphan memory map sitting isolated in TRM + */ +#define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE +#define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_CFG_MPU_DRA7XX_SIZE SZ_1M + +/* + * L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB) + * (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000) + */ +#define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE +#define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER2_DRA7XX_SIZE SZ_1M + +/* + * L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB) + * (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000) + */ +#define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE +#define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER3_DRA7XX_SIZE SZ_2M + +/* + * L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)? + * (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000) + */ +#define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE +#define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M) + +/* + * L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)? + * (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000) + */ +#define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE +#define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WKUP_DRA7XX_SIZE SZ_1M diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 4068350f9059..8867eb4025bf 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -11,7 +11,6 @@ */ #include <linux/of.h> -#include <linux/module.h> #include <linux/platform_device.h> #include <linux/err.h> #include <linux/slab.h> @@ -63,15 +62,5 @@ static int __init omap_iommu_init(void) return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL); } -/* must be ready before omap3isp is probed */ omap_subsys_initcall(omap_iommu_init); - -static void __exit omap_iommu_exit(void) -{ - /* Do nothing */ -} -module_exit(omap_iommu_exit); - -MODULE_AUTHOR("Hiroshi DOYU"); -MODULE_DESCRIPTION("omap iommu: omap device registration"); -MODULE_LICENSE("GPL v2"); +/* must be ready before omap3isp is probed */ diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 79f49d904a06..65024af169d3 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -105,7 +105,7 @@ static void dummy_cpu_resume(void) static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) {} -struct cpu_pm_ops omap_pm_ops = { +static struct cpu_pm_ops omap_pm_ops = { .finish_suspend = default_finish_suspend, .resume = dummy_cpu_resume, .scu_prepare = dummy_scu_prepare, diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c index 103a49f68bcb..4bdd22edb96b 100644 --- a/arch/arm/mach-omap2/omap3-restart.c +++ b/arch/arm/mach-omap2/omap3-restart.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/reboot.h> +#include "common.h" #include "control.h" #include "prm.h" diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 16350eefa66c..949696b6f17b 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -51,6 +51,127 @@ static void __iomem *twd_base; #define IRQ_LOCALTIMER 29 +#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER + +/* Used to implement memory barrier on DRAM path */ +#define OMAP4_DRAM_BARRIER_VA 0xfe600000 + +static void __iomem *dram_sync, *sram_sync; +static phys_addr_t dram_sync_paddr; +static u32 dram_sync_size; + +/* + * The OMAP4 bus structure contains asynchrnous bridges which can buffer + * data writes from the MPU. These asynchronous bridges can be found on + * paths between the MPU to EMIF, and the MPU to L3 interconnects. + * + * We need to be careful about re-ordering which can happen as a result + * of different accesses being performed via different paths, and + * therefore different asynchronous bridges. + */ + +/* + * OMAP4 interconnect barrier which is called for each mb() and wmb(). + * This is to ensure that normal paths to DRAM (normal memory, cacheable + * accesses) are properly synchronised with writes to DMA coherent memory + * (normal memory, uncacheable) and device writes. + * + * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF + * path, as we need to ensure that data is visible to other system + * masters prior to writes to those system masters being seen. + * + * Note: the SRAM path is not synchronised via mb() and wmb(). + */ +static void omap4_mb(void) +{ + if (dram_sync) + writel_relaxed(0, dram_sync); +} + +/* + * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI. + * + * If a data is stalled inside asynchronous bridge because of back + * pressure, it may be accepted multiple times, creating pointer + * misalignment that will corrupt next transfers on that data path until + * next reset of the system. No recovery procedure once the issue is hit, + * the path remains consistently broken. + * + * Async bridges can be found on paths between MPU to EMIF and MPU to L3 + * interconnects. + * + * This situation can happen only when the idle is initiated by a Master + * Request Disconnection (which is trigged by software when executing WFI + * on the CPU). + * + * The work-around for this errata needs all the initiators connected + * through an async bridge to ensure that data path is properly drained + * before issuing WFI. This condition will be met if one Strongly ordered + * access is performed to the target right before executing the WFI. + * + * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. + * IO barrier ensure that there is no synchronisation loss on initiators + * operating on both interconnect port simultaneously. + * + * This is a stronger version of the OMAP4 memory barrier below, and + * operates on both the MPU->MA->EMIF path but also the MPU->OCP path + * as well, and is necessary prior to executing a WFI. + */ +void omap_interconnect_sync(void) +{ + if (dram_sync && sram_sync) { + writel_relaxed(readl_relaxed(dram_sync), dram_sync); + writel_relaxed(readl_relaxed(sram_sync), sram_sync); + isb(); + } +} + +static int __init omap4_sram_init(void) +{ + struct device_node *np; + struct gen_pool *sram_pool; + + np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); + if (!np) + pr_warn("%s:Unable to allocate sram needed to handle errata I688\n", + __func__); + sram_pool = of_gen_pool_get(np, "sram", 0); + if (!sram_pool) + pr_warn("%s:Unable to get sram pool needed to handle errata I688\n", + __func__); + else + sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE); + + return 0; +} +omap_arch_initcall(omap4_sram_init); + +/* Steal one page physical memory for barrier implementation */ +void __init omap_barrier_reserve_memblock(void) +{ + dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M); + dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M); +} + +void __init omap_barriers_init(void) +{ + struct map_desc dram_io_desc[1]; + + dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; + dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr); + dram_io_desc[0].length = dram_sync_size; + dram_io_desc[0].type = MT_MEMORY_RW_SO; + iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); + dram_sync = (void __iomem *) dram_io_desc[0].virtual; + + pr_info("OMAP4: Map %pa to %p for dram barrier\n", + &dram_sync_paddr, dram_sync); + + soc_mb = omap4_mb; +} + +#endif + void gic_dist_disable(void) { if (gic_dist_base_addr) diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c index a99e7f7fb5be..e17136a50e27 100644 --- a/arch/arm/mach-omap2/omap4-restart.c +++ b/arch/arm/mach-omap2/omap4-restart.c @@ -9,6 +9,7 @@ #include <linux/types.h> #include <linux/reboot.h> +#include "common.h" #include "prm.h" /** diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index 2d35c5709408..0ca8e938096b 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h @@ -30,6 +30,14 @@ #define OMAP54XX_CTRL_BASE 0x4a002800 #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 +/* DRA7 specific base addresses */ +#define L3_MAIN_SN_DRA7XX_BASE 0x44000000 +#define L4_PER1_DRA7XX_BASE 0x48000000 +#define L4_CFG_MPU_DRA7XX_BASE 0x48210000 +#define L4_PER2_DRA7XX_BASE 0x48400000 +#define L4_PER3_DRA7XX_BASE 0x48800000 +#define L4_CFG_DRA7XX_BASE 0x4A000000 +#define L4_WKUP_DRA7XX_BASE 0x4ae00000 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 #define DRA7XX_CTRL_BASE 0x4a003400 #define DRA7XX_TAP_BASE 0x4ae0c000 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 486cc4ded190..cc8a987149e2 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -130,6 +130,7 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> @@ -299,7 +300,20 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) /* Module might have lost context, always update cache and register */ oh->_sysc_cache = v; + + /* + * Some IP blocks (such as RTC) require unlocking of IP before + * accessing its registers. If a function pointer is present + * to unlock, then call it before accessing sysconfig and + * call lock after writing sysconfig. + */ + if (oh->class->unlock) + oh->class->unlock(oh); + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); + + if (oh->class->lock) + oh->class->lock(oh); } /** @@ -3886,7 +3900,8 @@ void __init omap_hwmod_init(void) soc_ops.init_clkdm = _init_clkdm; soc_ops.update_context_lost = _omap4_update_context_lost; soc_ops.get_context_lost = _omap4_get_context_lost; - } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) { + } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || + soc_is_am43xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index b5d27ec81610..ca6df1a73475 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -576,6 +576,8 @@ struct omap_hwmod_omap4_prcm { * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown * @reset: ptr to fn to be executed in place of the standard hwmod reset fn * @enable_preprogram: ptr to fn to be executed during device enable + * @lock: ptr to fn to be executed to lock IP registers + * @unlock: ptr to fn to be executed to unlock IP registers * * Represent the class of a OMAP hardware "modules" (e.g. timer, * smartreflex, gpio, uart...) @@ -600,6 +602,8 @@ struct omap_hwmod_class { int (*pre_shutdown)(struct omap_hwmod *oh); int (*reset)(struct omap_hwmod *oh); int (*enable_preprogram)(struct omap_hwmod *oh); + void (*lock)(struct omap_hwmod *oh); + void (*unlock)(struct omap_hwmod *oh); }; /** @@ -755,7 +759,8 @@ extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); -extern int ti81xx_hwmod_init(void); +extern int dm814x_hwmod_init(void); +extern int dm816x_hwmod_init(void); extern int dra7xx_hwmod_init(void); int am43xx_hwmod_init(void); diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 6dcfd03ced8f..36bcd2e75422 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -20,7 +20,7 @@ #include "prm-regbits-24xx.h" #include "wd_timer.h" -struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { +static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { { .name = "dispc", .dma_req = 5 }, { .dma_req = -1, }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 215d5efa0dba..e97a894b5f88 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -480,7 +480,7 @@ static struct omap_hwmod am43xx_dss_core_hwmod = { /* dispc */ -struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { +static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { .manager_count = 1, .has_framedonetv_irq = 0 }; diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index c92413769144..b1288f56d509 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -32,21 +32,59 @@ */ /* - * The alwon .clkctrl_offs field is offset from the CM_ALWON, that's - * TRM 18.7.17 CM_ALWON device register values minus 0x1400. + * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" + * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. */ +#define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 +#define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 +#define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 +#define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c +#define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 +#define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 +#define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 +#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c +#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 +#define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 +#define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 +#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c +#define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 +#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 +#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 +#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c +#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 +#define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 +#define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 +#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 +#define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 +#define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 +#define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec +#define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 +#define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 +#define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 +#define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc +#define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 +#define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 + +/* Registers specific to dm814x */ +#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c +#define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 +#define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 +#define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 +#define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 +#define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 +#define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 +#define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 +#define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 +#define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc +#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 +#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 +#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c +#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 +#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 +#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 + +/* Registers specific to dm816x */ #define DM816X_DM_ALWON_BASE 0x1400 -#define DM816X_CM_ALWON_MCASP0_CLKCTRL (0x1540 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MCASP1_CLKCTRL (0x1544 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MCASP2_CLKCTRL (0x1548 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MCBSP_CLKCTRL (0x154c - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_UART_0_CLKCTRL (0x1550 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_UART_1_CLKCTRL (0x1554 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_UART_2_CLKCTRL (0x1558 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_GPIO_0_CLKCTRL (0x155c - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_GPIO_1_CLKCTRL (0x1560 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_I2C_0_CLKCTRL (0x1564 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_I2C_1_CLKCTRL (0x1568 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) @@ -54,29 +92,11 @@ #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_SPI_CLKCTRL (0x1590 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_MMUCFG_CLKCTRL (0x15a8 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_CONTRL_CLKCTRL (0x15c4 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_GPMC_CLKCTRL (0x15d0 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_L3_CLKCTRL (0x15e4 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_L4HS_CLKCTRL (0x15e8 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_L4LS_CLKCTRL (0x15ec - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_RTC_CLKCTRL (0x15f0 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_TPCC_CLKCTRL (0x15f4 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_TPTC0_CLKCTRL (0x15f8 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_TPTC1_CLKCTRL (0x15fc - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_TPTC2_CLKCTRL (0x1600 - DM816X_DM_ALWON_BASE) -#define DM816X_CM_ALWON_TPTC3_CLKCTRL (0x1604 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) @@ -88,28 +108,28 @@ #define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ -static struct omap_hwmod dm816x_alwon_l3_slow_hwmod = { +static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { .name = "alwon_l3_slow", .clkdm_name = "alwon_l3s_clkdm", .class = &l3_hwmod_class, .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod dm816x_default_l3_slow_hwmod = { +static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { .name = "default_l3_slow", .clkdm_name = "default_l3_slow_clkdm", .class = &l3_hwmod_class, .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod dm816x_alwon_l3_med_hwmod = { +static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { .name = "l3_med", .clkdm_name = "alwon_l3_med_clkdm", .class = &l3_hwmod_class, .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = { +static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { .name = "l3_fast", .clkdm_name = "alwon_l3_fast_clkdm", .class = &l3_hwmod_class, @@ -120,7 +140,7 @@ static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = { * L4 standard peripherals, see TRM table 1-12 for devices using this. * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. */ -static struct omap_hwmod dm816x_l4_ls_hwmod = { +static struct omap_hwmod dm81xx_l4_ls_hwmod = { .name = "l4_ls", .clkdm_name = "alwon_l3s_clkdm", .class = &l4_hwmod_class, @@ -131,27 +151,54 @@ static struct omap_hwmod dm816x_l4_ls_hwmod = { * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM * table 1-73 for devices using 250MHz SYSCLK5 clock. */ -static struct omap_hwmod dm816x_l4_hs_hwmod = { +static struct omap_hwmod dm81xx_l4_hs_hwmod = { .name = "l4_hs", .clkdm_name = "alwon_l3_med_clkdm", .class = &l4_hwmod_class, }; /* L3 slow -> L4 ls peripheral interface running at 125MHz */ -static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls = { - .master = &dm816x_alwon_l3_slow_hwmod, - .slave = &dm816x_l4_ls_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { + .master = &dm81xx_alwon_l3_slow_hwmod, + .slave = &dm81xx_l4_ls_hwmod, .user = OCP_USER_MPU, }; /* L3 med -> L4 fast peripheral interface running at 250MHz */ -static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs = { - .master = &dm816x_alwon_l3_med_hwmod, - .slave = &dm816x_l4_hs_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { + .master = &dm81xx_alwon_l3_med_hwmod, + .slave = &dm81xx_l4_hs_hwmod, .user = OCP_USER_MPU, }; /* MPU */ +static struct omap_hwmod dm814x_mpu_hwmod = { + .name = "mpu", + .clkdm_name = "alwon_l3s_clkdm", + .class = &mpu_hwmod_class, + .flags = HWMOD_INIT_NO_IDLE, + .main_clk = "mpu_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { + .master = &dm814x_mpu_hwmod, + .slave = &dm81xx_alwon_l3_slow_hwmod, + .user = OCP_USER_MPU, +}; + +/* L3 med peripheral interface running at 200MHz */ +static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { + .master = &dm814x_mpu_hwmod, + .slave = &dm81xx_alwon_l3_med_hwmod, + .user = OCP_USER_MPU, +}; + static struct omap_hwmod dm816x_mpu_hwmod = { .name = "mpu", .clkdm_name = "alwon_mpu_clkdm", @@ -168,14 +215,14 @@ static struct omap_hwmod dm816x_mpu_hwmod = { static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { .master = &dm816x_mpu_hwmod, - .slave = &dm816x_alwon_l3_slow_hwmod, + .slave = &dm81xx_alwon_l3_slow_hwmod, .user = OCP_USER_MPU, }; /* L3 med peripheral interface running at 250MHz */ static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { .master = &dm816x_mpu_hwmod, - .slave = &dm816x_alwon_l3_med_hwmod, + .slave = &dm81xx_alwon_l3_med_hwmod, .user = OCP_USER_MPU, }; @@ -197,13 +244,13 @@ static struct omap_hwmod_class uart_class = { .sysc = &uart_sysc, }; -static struct omap_hwmod dm816x_uart1_hwmod = { +static struct omap_hwmod dm81xx_uart1_hwmod = { .name = "uart1", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_UART_0_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -211,20 +258,20 @@ static struct omap_hwmod dm816x_uart1_hwmod = { .flags = DEBUG_TI81XXUART1_FLAGS, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_uart1_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_uart1_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod dm816x_uart2_hwmod = { +static struct omap_hwmod dm81xx_uart2_hwmod = { .name = "uart2", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_UART_1_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -232,20 +279,20 @@ static struct omap_hwmod dm816x_uart2_hwmod = { .flags = DEBUG_TI81XXUART2_FLAGS, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_uart2_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_uart2_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod dm816x_uart3_hwmod = { +static struct omap_hwmod dm81xx_uart3_hwmod = { .name = "uart3", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_UART_2_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -253,9 +300,9 @@ static struct omap_hwmod dm816x_uart3_hwmod = { .flags = DEBUG_TI81XXUART3_FLAGS, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_uart3_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_uart3_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; @@ -276,23 +323,23 @@ static struct omap_hwmod_class wd_timer_class = { .reset = &omap2_wd_timer_reset, }; -static struct omap_hwmod dm816x_wd_timer_hwmod = { +static struct omap_hwmod dm81xx_wd_timer_hwmod = { .name = "wd_timer", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk18_ck", .flags = HWMOD_NO_IDLEST, .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_WDTIMER_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, .class = &wd_timer_class, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_wd_timer_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_wd_timer_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; @@ -320,27 +367,27 @@ static struct omap_hwmod dm81xx_i2c1_hwmod = { .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, .class = &i2c_class, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1 = { - .master = &dm816x_l4_ls_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { + .master = &dm81xx_l4_ls_hwmod, .slave = &dm81xx_i2c1_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod dm816x_i2c2_hwmod = { +static struct omap_hwmod dm81xx_i2c2_hwmod = { .name = "i2c2", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -358,9 +405,9 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_i2c2_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_i2c2_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; @@ -378,7 +425,7 @@ static struct omap_hwmod dm81xx_elm_hwmod = { }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm81xx_elm_hwmod, .user = OCP_USER_MPU, }; @@ -417,7 +464,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = { .main_clk = "sysclk6_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_GPIO_0_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -427,7 +474,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = { }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm81xx_gpio1_hwmod, .user = OCP_USER_MPU, }; @@ -443,7 +490,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = { .main_clk = "sysclk6_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_GPIO_1_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -453,7 +500,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = { }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm81xx_gpio2_hwmod, .user = OCP_USER_MPU, }; @@ -482,14 +529,14 @@ static struct omap_hwmod dm81xx_gpmc_hwmod = { .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { - .master = &dm816x_alwon_l3_slow_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { + .master = &dm81xx_alwon_l3_slow_hwmod, .slave = &dm81xx_gpmc_hwmod, .user = OCP_USER_MPU, }; @@ -522,7 +569,7 @@ static struct omap_hwmod dm81xx_usbss_hwmod = { }; static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { - .master = &dm816x_default_l3_slow_hwmod, + .master = &dm81xx_default_l3_slow_hwmod, .slave = &dm81xx_usbss_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -547,6 +594,22 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { .timer_capability = OMAP_TIMER_ALWON, }; +static struct omap_hwmod dm814x_timer1_hwmod = { + .name = "timer1", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer_sys_ck", + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm814x_timer1_hwmod, + .clk = "timer_sys_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod dm816x_timer1_hwmod = { .name = "timer1", .clkdm_name = "alwon_l3s_clkdm", @@ -562,12 +625,28 @@ static struct omap_hwmod dm816x_timer1_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer1_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; +static struct omap_hwmod dm814x_timer2_hwmod = { + .name = "timer2", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "timer_sys_ck", + .dev_attr = &capability_alwon_dev_attr, + .class = &dm816x_timer_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm814x_timer2_hwmod, + .clk = "timer_sys_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod dm816x_timer2_hwmod = { .name = "timer2", .clkdm_name = "alwon_l3s_clkdm", @@ -583,7 +662,7 @@ static struct omap_hwmod dm816x_timer2_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer2_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -604,7 +683,7 @@ static struct omap_hwmod dm816x_timer3_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer3_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -625,7 +704,7 @@ static struct omap_hwmod dm816x_timer4_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer4_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -646,7 +725,7 @@ static struct omap_hwmod dm816x_timer5_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer5_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -667,7 +746,7 @@ static struct omap_hwmod dm816x_timer6_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer6_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -688,12 +767,68 @@ static struct omap_hwmod dm816x_timer7_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_timer7_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; +/* CPSW on dm814x */ +static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS, + .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO, + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { + .name = "cpgmac0", + .sysc = &dm814x_cpgmac_sysc, +}; + +static struct omap_hwmod dm814x_cpgmac0_hwmod = { + .name = "cpgmac0", + .class = &dm814x_cpgmac0_hwmod_class, + .clkdm_name = "alwon_ethernet_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "cpsw_125mhz_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_class dm814x_mdio_hwmod_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod dm814x_mdio_hwmod = { + .name = "davinci_mdio", + .class = &dm814x_mdio_hwmod_class, + .clkdm_name = "alwon_ethernet_clkdm", + .main_clk = "cpsw_125mhz_gclk", +}; + +static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { + .master = &dm81xx_l4_hs_hwmod, + .slave = &dm814x_cpgmac0_hwmod, + .clk = "cpsw_125mhz_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { + .master = &dm814x_cpgmac0_hwmod, + .slave = &dm814x_mdio_hwmod, + .user = OCP_USER_MPU, + .flags = HWMOD_NO_IDLEST, +}; + /* EMAC Ethernet */ static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { .rev_offs = 0x0, @@ -717,21 +852,21 @@ static struct omap_hwmod dm816x_emac0_hwmod = { .class = &dm816x_emac_hwmod_class, }; -static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0 = { - .master = &dm816x_l4_hs_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { + .master = &dm81xx_l4_hs_hwmod, .slave = &dm816x_emac0_hwmod, .clk = "sysclk5_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod_class dm816x_mdio_hwmod_class = { +static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { .name = "davinci_mdio", .sysc = &dm816x_emac_sysc, }; -struct omap_hwmod dm816x_emac0_mdio_hwmod = { +static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { .name = "davinci_mdio", - .class = &dm816x_mdio_hwmod_class, + .class = &dm81xx_mdio_hwmod_class, .clkdm_name = "alwon_ethernet_clkdm", .main_clk = "sysclk24_ck", .flags = HWMOD_NO_IDLEST, @@ -741,15 +876,15 @@ struct omap_hwmod dm816x_emac0_mdio_hwmod = { */ .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_0_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_emac0__mdio = { - .master = &dm816x_l4_hs_hwmod, - .slave = &dm816x_emac0_mdio_hwmod, +static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { + .master = &dm81xx_l4_hs_hwmod, + .slave = &dm81xx_emac0_mdio_hwmod, .user = OCP_USER_MPU, }; @@ -768,7 +903,7 @@ static struct omap_hwmod dm816x_emac1_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { - .master = &dm816x_l4_hs_hwmod, + .master = &dm81xx_l4_hs_hwmod, .slave = &dm816x_emac1_hwmod, .clk = "sysclk5_ck", .user = OCP_USER_MPU, @@ -815,7 +950,7 @@ static struct omap_hwmod dm816x_mmc1_hwmod = { }; static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { - .master = &dm816x_l4_ls_hwmod, + .master = &dm81xx_l4_ls_hwmod, .slave = &dm816x_mmc1_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, @@ -843,13 +978,13 @@ static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { .num_chipselect = 4, }; -static struct omap_hwmod dm816x_mcspi1_hwmod = { +static struct omap_hwmod dm81xx_mcspi1_hwmod = { .name = "mcspi1", .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk10_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_SPI_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -857,14 +992,14 @@ static struct omap_hwmod dm816x_mcspi1_hwmod = { .dev_attr = &dm816x_mcspi1_dev_attr, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1 = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_mcspi1_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_mcspi1_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = { +static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { .rev_offs = 0x000, .sysc_offs = 0x010, .syss_offs = 0x014, @@ -874,55 +1009,55 @@ static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class dm816x_mailbox_hwmod_class = { +static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { .name = "mailbox", - .sysc = &dm816x_mailbox_sysc, + .sysc = &dm81xx_mailbox_sysc, }; -static struct omap_hwmod dm816x_mailbox_hwmod = { +static struct omap_hwmod dm81xx_mailbox_hwmod = { .name = "mailbox", .clkdm_name = "alwon_l3s_clkdm", - .class = &dm816x_mailbox_hwmod_class, + .class = &dm81xx_mailbox_hwmod_class, .main_clk = "sysclk6_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_MAILBOX_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox = { - .master = &dm816x_l4_ls_hwmod, - .slave = &dm816x_mailbox_hwmod, +static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_mailbox_hwmod, .user = OCP_USER_MPU, }; -static struct omap_hwmod_class dm816x_tpcc_hwmod_class = { +static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { .name = "tpcc", }; -struct omap_hwmod dm816x_tpcc_hwmod = { +static struct omap_hwmod dm81xx_tpcc_hwmod = { .name = "tpcc", - .class = &dm816x_tpcc_hwmod_class, + .class = &dm81xx_tpcc_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk4_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TPCC_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc = { - .master = &dm816x_alwon_l3_fast_hwmod, - .slave = &dm816x_tpcc_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { + .master = &dm81xx_alwon_l3_fast_hwmod, + .slave = &dm81xx_tpcc_hwmod, .clk = "sysclk4_ck", .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = { +static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { { .pa_start = 0x49800000, .pa_end = 0x49800000 + SZ_8K - 1, @@ -931,40 +1066,40 @@ static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = { { }, }; -static struct omap_hwmod_class dm816x_tptc0_hwmod_class = { +static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { .name = "tptc0", }; -struct omap_hwmod dm816x_tptc0_hwmod = { +static struct omap_hwmod dm81xx_tptc0_hwmod = { .name = "tptc0", - .class = &dm816x_tptc0_hwmod_class, + .class = &dm81xx_tptc0_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk4_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TPTC0_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0 = { - .master = &dm816x_alwon_l3_fast_hwmod, - .slave = &dm816x_tptc0_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { + .master = &dm81xx_alwon_l3_fast_hwmod, + .slave = &dm81xx_tptc0_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc0_addr_space, + .addr = dm81xx_tptc0_addr_space, .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast = { - .master = &dm816x_tptc0_hwmod, - .slave = &dm816x_alwon_l3_fast_hwmod, +static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { + .master = &dm81xx_tptc0_hwmod, + .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc0_addr_space, + .addr = dm81xx_tptc0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = { +static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { { .pa_start = 0x49900000, .pa_end = 0x49900000 + SZ_8K - 1, @@ -973,40 +1108,40 @@ static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = { { }, }; -static struct omap_hwmod_class dm816x_tptc1_hwmod_class = { +static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { .name = "tptc1", }; -struct omap_hwmod dm816x_tptc1_hwmod = { +static struct omap_hwmod dm81xx_tptc1_hwmod = { .name = "tptc1", - .class = &dm816x_tptc1_hwmod_class, + .class = &dm81xx_tptc1_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk4_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TPTC1_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1 = { - .master = &dm816x_alwon_l3_fast_hwmod, - .slave = &dm816x_tptc1_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { + .master = &dm81xx_alwon_l3_fast_hwmod, + .slave = &dm81xx_tptc1_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc1_addr_space, + .addr = dm81xx_tptc1_addr_space, .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast = { - .master = &dm816x_tptc1_hwmod, - .slave = &dm816x_alwon_l3_fast_hwmod, +static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { + .master = &dm81xx_tptc1_hwmod, + .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc1_addr_space, + .addr = dm81xx_tptc1_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = { +static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { { .pa_start = 0x49a00000, .pa_end = 0x49a00000 + SZ_8K - 1, @@ -1015,40 +1150,40 @@ static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = { { }, }; -static struct omap_hwmod_class dm816x_tptc2_hwmod_class = { +static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { .name = "tptc2", }; -struct omap_hwmod dm816x_tptc2_hwmod = { +static struct omap_hwmod dm81xx_tptc2_hwmod = { .name = "tptc2", - .class = &dm816x_tptc2_hwmod_class, + .class = &dm81xx_tptc2_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk4_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TPTC2_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2 = { - .master = &dm816x_alwon_l3_fast_hwmod, - .slave = &dm816x_tptc2_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { + .master = &dm81xx_alwon_l3_fast_hwmod, + .slave = &dm81xx_tptc2_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc2_addr_space, + .addr = dm81xx_tptc2_addr_space, .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast = { - .master = &dm816x_tptc2_hwmod, - .slave = &dm816x_alwon_l3_fast_hwmod, +static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { + .master = &dm81xx_tptc2_hwmod, + .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc2_addr_space, + .addr = dm81xx_tptc2_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = { +static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { { .pa_start = 0x49b00000, .pa_end = 0x49b00000 + SZ_8K - 1, @@ -1057,50 +1192,96 @@ static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = { { }, }; -static struct omap_hwmod_class dm816x_tptc3_hwmod_class = { +static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { .name = "tptc3", }; -struct omap_hwmod dm816x_tptc3_hwmod = { +static struct omap_hwmod dm81xx_tptc3_hwmod = { .name = "tptc3", - .class = &dm816x_tptc3_hwmod_class, + .class = &dm81xx_tptc3_hwmod_class, .clkdm_name = "alwon_l3s_clkdm", .main_clk = "sysclk4_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TPTC3_CLKCTRL, + .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, }; -struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3 = { - .master = &dm816x_alwon_l3_fast_hwmod, - .slave = &dm816x_tptc3_hwmod, +static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { + .master = &dm81xx_alwon_l3_fast_hwmod, + .slave = &dm81xx_tptc3_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc3_addr_space, + .addr = dm81xx_tptc3_addr_space, .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast = { - .master = &dm816x_tptc3_hwmod, - .slave = &dm816x_alwon_l3_fast_hwmod, +static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { + .master = &dm81xx_tptc3_hwmod, + .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm816x_tptc3_addr_space, + .addr = dm81xx_tptc3_addr_space, .user = OCP_USER_MPU, }; +/* + * REVISIT: Test and enable the following once clocks work: + * dm81xx_l4_ls__gpio1 + * dm81xx_l4_ls__gpio2 + * dm81xx_l4_ls__mailbox + * dm81xx_alwon_l3_slow__gpmc + * dm81xx_default_l3_slow__usbss + * + * Also note that some devices share a single clkctrl_offs.. + * For example, i2c1 and 3 share one, and i2c2 and 4 share one. + */ +static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { + &dm814x_mpu__alwon_l3_slow, + &dm814x_mpu__alwon_l3_med, + &dm81xx_alwon_l3_slow__l4_ls, + &dm81xx_alwon_l3_slow__l4_hs, + &dm81xx_l4_ls__uart1, + &dm81xx_l4_ls__uart2, + &dm81xx_l4_ls__uart3, + &dm81xx_l4_ls__wd_timer1, + &dm81xx_l4_ls__i2c1, + &dm81xx_l4_ls__i2c2, + &dm81xx_l4_ls__elm, + &dm81xx_l4_ls__mcspi1, + &dm81xx_alwon_l3_fast__tpcc, + &dm81xx_alwon_l3_fast__tptc0, + &dm81xx_alwon_l3_fast__tptc1, + &dm81xx_alwon_l3_fast__tptc2, + &dm81xx_alwon_l3_fast__tptc3, + &dm81xx_tptc0__alwon_l3_fast, + &dm81xx_tptc1__alwon_l3_fast, + &dm81xx_tptc2__alwon_l3_fast, + &dm81xx_tptc3__alwon_l3_fast, + &dm814x_l4_ls__timer1, + &dm814x_l4_ls__timer2, + &dm814x_l4_hs__cpgmac0, + &dm814x_cpgmac0__mdio, + NULL, +}; + +int __init dm814x_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); +} + static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm816x_mpu__alwon_l3_slow, &dm816x_mpu__alwon_l3_med, - &dm816x_alwon_l3_slow__l4_ls, - &dm816x_alwon_l3_slow__l4_hs, - &dm816x_l4_ls__uart1, - &dm816x_l4_ls__uart2, - &dm816x_l4_ls__uart3, - &dm816x_l4_ls__wd_timer1, - &dm816x_l4_ls__i2c1, - &dm816x_l4_ls__i2c2, + &dm81xx_alwon_l3_slow__l4_ls, + &dm81xx_alwon_l3_slow__l4_hs, + &dm81xx_l4_ls__uart1, + &dm81xx_l4_ls__uart2, + &dm81xx_l4_ls__uart3, + &dm81xx_l4_ls__wd_timer1, + &dm81xx_l4_ls__i2c1, + &dm81xx_l4_ls__i2c2, &dm81xx_l4_ls__gpio1, &dm81xx_l4_ls__gpio2, &dm81xx_l4_ls__elm, @@ -1112,26 +1293,26 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm816x_l4_ls__timer5, &dm816x_l4_ls__timer6, &dm816x_l4_ls__timer7, - &dm816x_l4_ls__mcspi1, - &dm816x_l4_ls__mailbox, - &dm816x_l4_hs__emac0, - &dm816x_emac0__mdio, + &dm81xx_l4_ls__mcspi1, + &dm81xx_l4_ls__mailbox, + &dm81xx_l4_hs__emac0, + &dm81xx_emac0__mdio, &dm816x_l4_hs__emac1, - &dm816x_alwon_l3_fast__tpcc, - &dm816x_alwon_l3_fast__tptc0, - &dm816x_alwon_l3_fast__tptc1, - &dm816x_alwon_l3_fast__tptc2, - &dm816x_alwon_l3_fast__tptc3, - &dm816x_tptc0__alwon_l3_fast, - &dm816x_tptc1__alwon_l3_fast, - &dm816x_tptc2__alwon_l3_fast, - &dm816x_tptc3__alwon_l3_fast, + &dm81xx_alwon_l3_fast__tpcc, + &dm81xx_alwon_l3_fast__tptc0, + &dm81xx_alwon_l3_fast__tptc1, + &dm81xx_alwon_l3_fast__tptc2, + &dm81xx_alwon_l3_fast__tptc3, + &dm81xx_tptc0__alwon_l3_fast, + &dm81xx_tptc1__alwon_l3_fast, + &dm81xx_tptc2__alwon_l3_fast, + &dm81xx_tptc3__alwon_l3_fast, &dm81xx_alwon_l3_slow__gpmc, &dm81xx_default_l3_slow__usbss, NULL, }; -int __init ti81xx_hwmod_init(void) +int __init dm816x_hwmod_init(void) { omap_hwmod_init(); return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 821171cf6b7d..ea56397599c2 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -14,9 +14,18 @@ #include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/ti_wilink_st.h> +#include <linux/wl12xx.h> +#include <linux/mmc/card.h> +#include <linux/mmc/host.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> #include <linux/platform_data/pinctrl-single.h> #include <linux/platform_data/iommu-omap.h> +#include <linux/platform_data/wkup_m3.h> + +#include <asm/siginfo.h> +#include <asm/signal.h> #include "common.h" #include "common-board-devices.h" @@ -25,13 +34,14 @@ #include "omap_device.h" #include "omap-secure.h" #include "soc.h" +#include "hsmmc.h" struct pdata_init { const char *compatible; void (*fn)(void); }; -struct of_dev_auxdata omap_auxdata_lookup[]; +static struct of_dev_auxdata omap_auxdata_lookup[]; static struct twl4030_gpio_platform_data twl_gpio_auxdata; #ifdef CONFIG_MACH_NOKIA_N8X0 @@ -128,7 +138,7 @@ static void __init omap3_sbc_t3530_legacy_init(void) omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub"); } -struct ti_st_plat_data wilink_pdata = { +static struct ti_st_plat_data wilink_pdata = { .nshutdown_gpio = 137, .dev_name = "/dev/ttyO1", .flow_cntrl = 1, @@ -268,8 +278,136 @@ static void __init omap3_tao3530_legacy_init(void) { hsmmc2_internal_input_clk(); } + +/* omap3pandora legacy devices */ +#define PANDORA_WIFI_IRQ_GPIO 21 +#define PANDORA_WIFI_NRESET_GPIO 23 + +static struct platform_device pandora_backlight = { + .name = "pandora-backlight", + .id = -1, +}; + +static struct regulator_consumer_supply pandora_vmmc3_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"), +}; + +static struct regulator_init_data pandora_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply), + .consumer_supplies = pandora_vmmc3_supply, +}; + +static struct fixed_voltage_config pandora_vwlan = { + .supply_name = "vwlan", + .microvolts = 1800000, /* 1.8V */ + .gpio = PANDORA_WIFI_NRESET_GPIO, + .startup_delay = 50000, /* 50ms */ + .enable_high = 1, + .init_data = &pandora_vmmc3, +}; + +static struct platform_device pandora_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &pandora_vwlan, + }, +}; + +static void pandora_wl1251_init_card(struct mmc_card *card) +{ + /* + * We have TI wl1251 attached to MMC3. Pass this information to + * SDIO core because it can't be probed by normal methods. + */ + if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) { + card->quirks |= MMC_QUIRK_NONSTD_SDIO; + card->cccr.wide_bus = 1; + card->cis.vendor = 0x104c; + card->cis.device = 0x9066; + card->cis.blksize = 512; + card->cis.max_dtr = 24000000; + card->ocr = 0x80; + } +} + +static struct omap2_hsmmc_info pandora_mmc3[] = { + { + .mmc = 3, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .init_card = pandora_wl1251_init_card, + }, + {} /* Terminator */ +}; + +static void __init pandora_wl1251_init(void) +{ + struct wl1251_platform_data pandora_wl1251_pdata; + int ret; + + memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata)); + + pandora_wl1251_pdata.power_gpio = -1; + + ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq"); + if (ret < 0) + goto fail; + + pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); + if (pandora_wl1251_pdata.irq < 0) + goto fail_irq; + + pandora_wl1251_pdata.use_eeprom = true; + ret = wl1251_set_platform_data(&pandora_wl1251_pdata); + if (ret < 0) + goto fail_irq; + + return; + +fail_irq: + gpio_free(PANDORA_WIFI_IRQ_GPIO); +fail: + pr_err("wl1251 board initialisation failed\n"); +} + +static void __init omap3_pandora_legacy_init(void) +{ + platform_device_register(&pandora_backlight); + platform_device_register(&pandora_vwlan_device); + omap_hsmmc_init(pandora_mmc3); + omap_hsmmc_late_init(pandora_mmc3); + pandora_wl1251_init(); +} #endif /* CONFIG_ARCH_OMAP3 */ +#ifdef CONFIG_SOC_TI81XX +static int fault_fixed_up; + +static int t410_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + if ((fsr == 0x406 || fsr == 0xc06) && !fault_fixed_up) { + pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", + addr, fsr); + fault_fixed_up = 1; + return 0; + } + + return 1; +} + +static void __init t410_abort_init(void) +{ + hook_fault_code(16 + 6, t410_abort_handler, SIGBUS, BUS_OBJERR, + "imprecise external abort"); +} +#endif + #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) static struct iommu_platform_data omap4_iommu_pdata = { .reset_name = "mmu_cache", @@ -278,6 +416,14 @@ static struct iommu_platform_data omap4_iommu_pdata = { }; #endif +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +static struct wkup_m3_platform_data wkup_m3_data = { + .reset_name = "wkup_m3", + .assert_reset = omap_device_assert_hardreset, + .deassert_reset = omap_device_deassert_hardreset, +}; +#endif + #ifdef CONFIG_SOC_OMAP5 static void __init omap5_uevm_legacy_init(void) { @@ -323,7 +469,7 @@ static struct pdata_init auxdata_quirks[] __initdata = { { /* sentinel */ }, }; -struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { #ifdef CONFIG_MACH_NOKIA_N8X0 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data), @@ -340,6 +486,10 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", &am35xx_emac_pdata), #endif +#ifdef CONFIG_SOC_AM33XX + OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3", + &wkup_m3_data), +#endif #ifdef CONFIG_ARCH_OMAP4 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), @@ -353,6 +503,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { #endif #ifdef CONFIG_SOC_AM43XX OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3", + &wkup_m3_data), #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", @@ -381,6 +533,11 @@ static struct pdata_init pdata_quirks[] __initdata = { { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, }, + { "openpandora,omap3-pandora-600mhz", omap3_pandora_legacy_init, }, + { "openpandora,omap3-pandora-1ghz", omap3_pandora_legacy_init, }, +#endif +#ifdef CONFIG_SOC_TI81XX + { "hp,t410", t410_abort_init, }, #endif #ifdef CONFIG_SOC_OMAP5 { "ti,omap5-uevm", omap5_uevm_legacy_init, }, diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index b1aad7e1426c..2a1a4180d5d0 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -25,6 +25,7 @@ #include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/irq.h> #include <linux/time.h> diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 70bc7066a4c2..d31c495175c1 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -349,6 +349,41 @@ static struct powerdomain device_81xx_pwrdm = { .voltdm = { .name = "core" }, }; +static struct powerdomain gem_814x_pwrdm = { + .name = "gem_pwrdm", + .prcm_offs = TI814X_PRM_DSP_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "dsp" }, +}; + +static struct powerdomain ivahd_814x_pwrdm = { + .name = "ivahd_pwrdm", + .prcm_offs = TI814X_PRM_HDVICP_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "iva" }, +}; + +static struct powerdomain hdvpss_814x_pwrdm = { + .name = "hdvpss_pwrdm", + .prcm_offs = TI814X_PRM_HDVPSS_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "dsp" }, +}; + +static struct powerdomain sgx_814x_pwrdm = { + .name = "sgx_pwrdm", + .prcm_offs = TI814X_PRM_GFX_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain isp_814x_pwrdm = { + .name = "isp_pwrdm", + .prcm_offs = TI814X_PRM_ISP_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + static struct powerdomain active_816x_pwrdm = { .name = "active_pwrdm", .prcm_offs = TI816X_PRM_ACTIVE_MOD, @@ -448,7 +483,18 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { NULL }; -static struct powerdomain *powerdomains_ti81xx[] __initdata = { +static struct powerdomain *powerdomains_ti814x[] __initdata = { + &alwon_81xx_pwrdm, + &device_81xx_pwrdm, + &gem_814x_pwrdm, + &ivahd_814x_pwrdm, + &hdvpss_814x_pwrdm, + &sgx_814x_pwrdm, + &isp_814x_pwrdm, + NULL +}; + +static struct powerdomain *powerdomains_ti816x[] __initdata = { &alwon_81xx_pwrdm, &device_81xx_pwrdm, &active_816x_pwrdm, @@ -460,6 +506,73 @@ static struct powerdomain *powerdomains_ti81xx[] __initdata = { NULL }; +/* TI81XX specific ops */ +#define TI81XX_PM_PWSTCTRL 0x0000 +#define TI81XX_RM_RSTCTRL 0x0010 +#define TI81XX_PM_PWSTST 0x0004 + +static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL); + return 0; +} + +static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + TI81XX_PM_PWSTCTRL, + OMAP_POWERSTATE_MASK); +} + +static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : + TI81XX_PM_PWSTST, + OMAP_POWERSTATEST_MASK); +} + +static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : + TI81XX_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); +} + +static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, + (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : + TI81XX_PM_PWSTST) & + OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s timeout waiting for transition\n", + pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */ +static struct pwrdm_ops ti81xx_pwrdm_operations = { + .pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst, + .pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst, + .pwrdm_wait_transition = ti81xx_pwrdm_wait_transition, +}; + void __init omap3xxx_powerdomains_init(void) { unsigned int rev; @@ -467,15 +580,22 @@ void __init omap3xxx_powerdomains_init(void) if (!cpu_is_omap34xx() && !cpu_is_ti81xx()) return; - pwrdm_register_platform_funcs(&omap3_pwrdm_operations); + /* Only 81xx needs custom pwrdm_operations */ + if (!cpu_is_ti81xx()) + pwrdm_register_platform_funcs(&omap3_pwrdm_operations);; rev = omap_rev(); if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { pwrdm_register_pwrdms(powerdomains_am35x); + } else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 || + rev == TI8148_REV_ES2_1) { + pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_ti814x); } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1 || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) { - pwrdm_register_pwrdms(powerdomains_ti81xx); + pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_ti816x); } else { pwrdm_register_pwrdms(powerdomains_omap3430_common); diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6ae0b3a1781e..c8f590b7c32d 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -51,6 +51,12 @@ /* * TI81XX PRM module offsets */ +#define TI814X_PRM_DSP_MOD 0x0a00 +#define TI814X_PRM_HDVICP_MOD 0x0c00 +#define TI814X_PRM_ISP_MOD 0x0d00 +#define TI814X_PRM_HDVPSS_MOD 0x0e00 +#define TI814X_PRM_GFX_MOD 0x0f00 + #define TI81XX_PRM_DEVICE_MOD 0x0000 #define TI816X_PRM_ACTIVE_MOD 0x0a00 #define TI81XX_PRM_DEFAULT_MOD 0x0b00 @@ -472,6 +478,7 @@ struct omap_prcm_irq { * struct omap_prcm_irq_setup - PRCM interrupt controller details * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register + * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers * @nr_irqs: number of entries in the @irqs array * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) @@ -494,6 +501,7 @@ struct omap_prcm_irq { struct omap_prcm_irq_setup { u16 ack; u16 mask; + u16 pm_ctrl; u8 nr_regs; u8 nr_irqs; const struct omap_prcm_irq *irqs; diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 7eebc27fa892..7c34c44eb0ae 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -25,6 +25,13 @@ #define AM43XX_PRM_WKUP_INST 0x2000 #define AM43XX_PRM_DEVICE_INST 0x4000 +/* PRM_IRQ offsets */ +#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 +#define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 + +/* Other PRM offsets */ +#define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 + /* RM RSTCTRL offsets */ #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 4541700f743a..30768003f854 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -18,13 +18,14 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/of_irq.h> - +#include <linux/of.h> #include "soc.h" #include "iomap.h" #include "common.h" #include "vp.h" #include "prm44xx.h" +#include "prcm43xx.h" #include "prm-regbits-44xx.h" #include "prcm44xx.h" #include "prminst44xx.h" @@ -45,6 +46,7 @@ static const struct omap_prcm_irq omap4_prcm_irqs[] = { static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, + .pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET, .nr_regs = 2, .irqs = omap4_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), @@ -216,11 +218,11 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) */ static void omap44xx_prm_read_pending_irqs(unsigned long *events) { - events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, - OMAP4_PRM_IRQSTATUS_MPU_OFFSET); + int i; - events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, - OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); + for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) + events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask + + i * 4, omap4_prcm_irq_setup.ack + i * 4); } /** @@ -250,17 +252,17 @@ static void omap44xx_prm_ocp_barrier(void) */ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) { - saved_mask[0] = - omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_OFFSET); - saved_mask[1] = - omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); + int i; + u16 reg; + + for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) { + reg = omap4_prcm_irq_setup.mask + i * 4; - omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_OFFSET); - omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); + saved_mask[i] = + omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, + reg); + omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg); + } /* OCP barrier */ omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, @@ -279,10 +281,12 @@ static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) */ static void omap44xx_prm_restore_irqen(u32 *saved_mask) { - omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_OFFSET); - omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST, - OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); + int i; + + for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) + omap4_prm_write_inst_reg(saved_mask[i], + OMAP4430_PRM_OCP_SOCKET_INST, + omap4_prcm_irq_setup.mask + i * 4); } /** @@ -306,10 +310,10 @@ static void omap44xx_prm_reconfigure_io_chain(void) omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, OMAP4430_WUCLK_CTRL_MASK, inst, - OMAP4_PRM_IO_PMCTRL_OFFSET); + omap4_prcm_irq_setup.pm_ctrl); omap_test_timeout( (((omap4_prm_read_inst_reg(inst, - OMAP4_PRM_IO_PMCTRL_OFFSET) & + omap4_prcm_irq_setup.pm_ctrl) & OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_SHIFT) == 1), MAX_IOPAD_LATCH_TIME, i); @@ -319,10 +323,10 @@ static void omap44xx_prm_reconfigure_io_chain(void) /* Trigger WUCLKIN disable */ omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, inst, - OMAP4_PRM_IO_PMCTRL_OFFSET); + omap4_prcm_irq_setup.pm_ctrl); omap_test_timeout( (((omap4_prm_read_inst_reg(inst, - OMAP4_PRM_IO_PMCTRL_OFFSET) & + omap4_prcm_irq_setup.pm_ctrl) & OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_SHIFT) == 0), MAX_IOPAD_LATCH_TIME, i); @@ -350,7 +354,7 @@ static void __init omap44xx_prm_enable_io_wakeup(void) omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_GLOBAL_WUEN_MASK, inst, - OMAP4_PRM_IO_PMCTRL_OFFSET); + omap4_prcm_irq_setup.pm_ctrl); } /** @@ -719,6 +723,15 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data) omap4_prminst_set_prm_dev_inst(data->device_inst_offset); + /* Add AM437X specific differences */ + if (of_device_is_compatible(data->np, "ti,am4-prcm")) { + omap4_prcm_irq_setup.nr_irqs = 1; + omap4_prcm_irq_setup.nr_regs = 1; + omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET; + omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET; + omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET; + } + return prm_register(&omap44xx_prm_ll_data); } diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 7add7994dbfc..257e98c26618 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -696,6 +696,7 @@ static struct omap_prcm_init_data am4_prm_data __initdata = { .index = TI_CLKM_PRM, .init = omap44xx_prm_init, .device_inst_offset = AM43XX_PRM_DEVICE_INST, + .flags = PRM_HAS_IO_WAKEUP, }; #endif @@ -705,7 +706,7 @@ static struct omap_prcm_init_data scrm_data __initdata = { }; #endif -static const struct of_device_id omap_prcm_dt_match_table[] __initconst = { +static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = { #ifdef CONFIG_SOC_AM33XX { .compatible = "ti,am3-prcm", .data = &am3_prm_data }, #endif diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index ad1bb9431e94..9b09d85d811a 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -333,14 +333,12 @@ ENDPROC(omap4_cpu_resume) #endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */ -ENTRY(omap_bus_sync) - ret lr -ENDPROC(omap_bus_sync) - ENTRY(omap_do_wfi) stmfd sp!, {lr} +#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER /* Drain interconnect write buffers. */ - bl omap_bus_sync + bl omap_interconnect_sync +#endif /* * Execute an ISB instruction to ensure that all of the diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index cac46d852da1..e4d8701f99f9 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -102,38 +102,38 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles, return 0; } -static void omap2_gp_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +static int omap2_gp_timer_shutdown(struct clock_event_device *evt) +{ + __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); + return 0; +} + +static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) { u32 period; __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - period = clkev.rate / HZ; - period -= 1; - /* Looks like we need to first set the load value separately */ - __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, - 0xffffffff - period, OMAP_TIMER_POSTED); - __omap_dm_timer_load_start(&clkev, - OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, - 0xffffffff - period, OMAP_TIMER_POSTED); - break; - case CLOCK_EVT_MODE_ONESHOT: - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - break; - } + period = clkev.rate / HZ; + period -= 1; + /* Looks like we need to first set the load value separately */ + __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, + OMAP_TIMER_POSTED); + __omap_dm_timer_load_start(&clkev, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, + 0xffffffff - period, OMAP_TIMER_POSTED); + return 0; } static struct clock_event_device clockevent_gpt = { - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = omap2_gp_timer_set_next_event, - .set_mode = omap2_gp_timer_set_mode, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_next_event = omap2_gp_timer_set_next_event, + .set_state_shutdown = omap2_gp_timer_shutdown, + .set_state_periodic = omap2_gp_timer_set_periodic, + .set_state_oneshot = omap2_gp_timer_shutdown, + .tick_resume = omap2_gp_timer_shutdown, }; static struct property device_disabled = { @@ -208,8 +208,7 @@ static void __init omap_dmtimer_init(void) /* If we are a secure device, remove any secure timer nodes */ if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); - if (np) - of_node_put(np); + of_node_put(np); } } @@ -649,23 +648,10 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); - /* Local timers are not supprted on OMAP4430 ES1.0 */ - if (omap_rev() != OMAP4430_REV_ES1_0) { - int err; - - if (of_have_populated_dt()) { - clocksource_of_init(); - return; - } - - err = twd_local_timer_register(&twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); - } + clocksource_of_init(); } #else void __init omap4_local_timer_init(void) diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 076fd20d7e5a..e5a35f6b83a7 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -563,7 +563,7 @@ struct i2c_init_data { u8 hsscll_12; }; -static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = { +static const struct i2c_init_data const omap4_i2c_timing_data[] __initconst = { { .load = 50, .loadbits = 0x3, diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index 261bb7cb4e60..307676d8c53c 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -95,7 +95,7 @@ static struct voltagedomain *voltagedomains_am35xx[] __initdata = { }; -static const char *sys_clk_name __initdata = "sys_ck"; +static const char *const sys_clk_name __initconst = "sys_ck"; void __init omap3xxx_voltagedomains_init(void) { diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c index 48b22a0a0c88..9b1f245b57d6 100644 --- a/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c @@ -92,7 +92,7 @@ static struct voltagedomain *voltagedomains_omap4[] __initdata = { NULL, }; -static const char *sys_clk_name __initdata = "sys_clkin_ck"; +static const char *const sys_clk_name __initconst = "sys_clkin_ck"; void __init omap44xx_voltagedomains_init(void) { diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c index 33d22b87252d..af5ff6496441 100644 --- a/arch/arm/mach-omap2/voltagedomains54xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c @@ -78,7 +78,7 @@ static struct voltagedomain *voltagedomains_omap5[] __initdata = { NULL, }; -static const char *sys_clk_name __initdata = "sys_clkin"; +static const char *const sys_clk_name __initconst = "sys_clkin"; void __init omap54xx_voltagedomains_init(void) { diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 2412efb6cdd9..08d2be2ea41f 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -78,11 +78,11 @@ config MACH_LINKSTATION_LSCHL Buffalo Linkstation Live v3 (LS-CHL) platform. config MACH_LINKSTATION_MINI - bool "Buffalo Linkstation Mini" - select I2C_BOARDINFO + bool "Buffalo Linkstation Mini (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the - Buffalo Linkstation Mini platform. + Buffalo Linkstation Mini (LS-WSGL) platform. config MACH_LINKSTATION_LS_HGL bool "Buffalo Linkstation LS-HGL" diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index a40b5c9a58c4..a1e0fbe6a7a1 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o -obj-$(CONFIG_MACH_LINKSTATION_MINI) += lsmini-setup.o obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 79f033b1ddff..d0871786dd8a 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -16,7 +16,6 @@ #include <linux/of_platform.h> #include <linux/cpu.h> #include <linux/mbus.h> -#include <linux/clk-provider.h> #include <linux/clocksource.h> #include <asm/system_misc.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 09d2a26985da..f267e58a8283 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -236,9 +236,7 @@ static int __init dns323_read_mac_addr(void) } iounmap(mac_page); - printk("DNS-323: Found ethernet MAC address: "); - for (i = 0; i < 6; i++) - printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); + printk("DNS-323: Found ethernet MAC address: %pM\n", addr); memcpy(dns323_eth_data.mac_addr, addr, 6); diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h index a6fa9d8f12d8..2431d9923427 100644 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ b/arch/arm/mach-orion5x/include/mach/irqs.h @@ -16,42 +16,42 @@ /* * Orion Main Interrupt Controller */ -#define IRQ_ORION5X_BRIDGE 0 -#define IRQ_ORION5X_DOORBELL_H2C 1 -#define IRQ_ORION5X_DOORBELL_C2H 2 -#define IRQ_ORION5X_UART0 3 -#define IRQ_ORION5X_UART1 4 -#define IRQ_ORION5X_I2C 5 -#define IRQ_ORION5X_GPIO_0_7 6 -#define IRQ_ORION5X_GPIO_8_15 7 -#define IRQ_ORION5X_GPIO_16_23 8 -#define IRQ_ORION5X_GPIO_24_31 9 -#define IRQ_ORION5X_PCIE0_ERR 10 -#define IRQ_ORION5X_PCIE0_INT 11 -#define IRQ_ORION5X_USB1_CTRL 12 -#define IRQ_ORION5X_DEV_BUS_ERR 14 -#define IRQ_ORION5X_PCI_ERR 15 -#define IRQ_ORION5X_USB_BR_ERR 16 -#define IRQ_ORION5X_USB0_CTRL 17 -#define IRQ_ORION5X_ETH_RX 18 -#define IRQ_ORION5X_ETH_TX 19 -#define IRQ_ORION5X_ETH_MISC 20 -#define IRQ_ORION5X_ETH_SUM 21 -#define IRQ_ORION5X_ETH_ERR 22 -#define IRQ_ORION5X_IDMA_ERR 23 -#define IRQ_ORION5X_IDMA_0 24 -#define IRQ_ORION5X_IDMA_1 25 -#define IRQ_ORION5X_IDMA_2 26 -#define IRQ_ORION5X_IDMA_3 27 -#define IRQ_ORION5X_CESA 28 -#define IRQ_ORION5X_SATA 29 -#define IRQ_ORION5X_XOR0 30 -#define IRQ_ORION5X_XOR1 31 +#define IRQ_ORION5X_BRIDGE (1 + 0) +#define IRQ_ORION5X_DOORBELL_H2C (1 + 1) +#define IRQ_ORION5X_DOORBELL_C2H (1 + 2) +#define IRQ_ORION5X_UART0 (1 + 3) +#define IRQ_ORION5X_UART1 (1 + 4) +#define IRQ_ORION5X_I2C (1 + 5) +#define IRQ_ORION5X_GPIO_0_7 (1 + 6) +#define IRQ_ORION5X_GPIO_8_15 (1 + 7) +#define IRQ_ORION5X_GPIO_16_23 (1 + 8) +#define IRQ_ORION5X_GPIO_24_31 (1 + 9) +#define IRQ_ORION5X_PCIE0_ERR (1 + 10) +#define IRQ_ORION5X_PCIE0_INT (1 + 11) +#define IRQ_ORION5X_USB1_CTRL (1 + 12) +#define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) +#define IRQ_ORION5X_PCI_ERR (1 + 15) +#define IRQ_ORION5X_USB_BR_ERR (1 + 16) +#define IRQ_ORION5X_USB0_CTRL (1 + 17) +#define IRQ_ORION5X_ETH_RX (1 + 18) +#define IRQ_ORION5X_ETH_TX (1 + 19) +#define IRQ_ORION5X_ETH_MISC (1 + 20) +#define IRQ_ORION5X_ETH_SUM (1 + 21) +#define IRQ_ORION5X_ETH_ERR (1 + 22) +#define IRQ_ORION5X_IDMA_ERR (1 + 23) +#define IRQ_ORION5X_IDMA_0 (1 + 24) +#define IRQ_ORION5X_IDMA_1 (1 + 25) +#define IRQ_ORION5X_IDMA_2 (1 + 26) +#define IRQ_ORION5X_IDMA_3 (1 + 27) +#define IRQ_ORION5X_CESA (1 + 28) +#define IRQ_ORION5X_SATA (1 + 29) +#define IRQ_ORION5X_XOR0 (1 + 30) +#define IRQ_ORION5X_XOR1 (1 + 31) /* * Orion General Purpose Pins */ -#define IRQ_ORION5X_GPIO_START 32 +#define IRQ_ORION5X_GPIO_START 33 #define NR_GPIO_IRQS 32 #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index cd4bac4d7e43..086ecb87d885 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -42,7 +42,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) stat = readl_relaxed(MAIN_IRQ_CAUSE); stat &= readl_relaxed(MAIN_IRQ_MASK); if (stat) { - unsigned int hwirq = __fls(stat); + unsigned int hwirq = 1 + __fls(stat); handle_IRQ(hwirq, regs); return; } @@ -51,7 +51,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) void __init orion5x_init_irq(void) { - orion_irq_init(0, MAIN_IRQ_MASK); + orion_irq_init(1, MAIN_IRQ_MASK); #ifdef CONFIG_MULTI_IRQ_HANDLER set_handle_irq(orion5x_legacy_handle_irq); diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c deleted file mode 100644 index a6493e76f96d..000000000000 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * arch/arm/mach-orion5x/lsmini-setup.c - * - * Maintainer: Alexey Kopytko <alexey@kopytko.ru> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/orion5x.h> -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * Linkstation Mini Info - ****************************************************************************/ - -/* - * 256K NOR flash Device bus boot chip select - */ - -#define LSMINI_NOR_BOOT_BASE 0xf4000000 -#define LSMINI_NOR_BOOT_SIZE SZ_256K - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data lsmini_nor_flash_data = { - .width = 1, -}; - -static struct resource lsmini_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = LSMINI_NOR_BOOT_BASE, - .end = LSMINI_NOR_BOOT_BASE + LSMINI_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device lsmini_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &lsmini_nor_flash_data, - }, - .num_resources = 1, - .resource = &lsmini_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data lsmini_eth_data = { - .phy_addr = 8, -}; - -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ - -static struct i2c_board_info __initdata lsmini_i2c_rtc = { - I2C_BOARD_INFO("rs5c372a", 0x32), -}; - -/***************************************************************************** - * LEDs attached to GPIO - ****************************************************************************/ - -#define LSMINI_GPIO_LED_ALARM 2 -#define LSMINI_GPIO_LED_INFO 3 -#define LSMINI_GPIO_LED_FUNC 9 -#define LSMINI_GPIO_LED_PWR 14 - -static struct gpio_led lsmini_led_pins[] = { - { - .name = "alarm:red", - .gpio = LSMINI_GPIO_LED_ALARM, - .active_low = 1, - }, { - .name = "info:amber", - .gpio = LSMINI_GPIO_LED_INFO, - .active_low = 1, - }, { - .name = "func:blue:top", - .gpio = LSMINI_GPIO_LED_FUNC, - .active_low = 1, - }, { - .name = "power:blue:bottom", - .gpio = LSMINI_GPIO_LED_PWR, - }, -}; - -static struct gpio_led_platform_data lsmini_led_data = { - .leds = lsmini_led_pins, - .num_leds = ARRAY_SIZE(lsmini_led_pins), -}; - -static struct platform_device lsmini_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &lsmini_led_data, - }, -}; - -/**************************************************************************** - * GPIO Attached Keys - ****************************************************************************/ - -#define LSMINI_GPIO_KEY_FUNC 15 -#define LSMINI_GPIO_KEY_POWER 18 -#define LSMINI_GPIO_KEY_AUTOPOWER 17 - -#define LSMINI_SW_POWER 0x00 -#define LSMINI_SW_AUTOPOWER 0x01 - -static struct gpio_keys_button lsmini_buttons[] = { - { - .code = KEY_OPTION, - .gpio = LSMINI_GPIO_KEY_FUNC, - .desc = "Function Button", - .active_low = 1, - }, { - .type = EV_SW, - .code = LSMINI_SW_POWER, - .gpio = LSMINI_GPIO_KEY_POWER, - .desc = "Power-on Switch", - .active_low = 1, - }, { - .type = EV_SW, - .code = LSMINI_SW_AUTOPOWER, - .gpio = LSMINI_GPIO_KEY_AUTOPOWER, - .desc = "Power-auto Switch", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data lsmini_button_data = { - .buttons = lsmini_buttons, - .nbuttons = ARRAY_SIZE(lsmini_buttons), -}; - -static struct platform_device lsmini_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &lsmini_button_data, - }, -}; - - -/***************************************************************************** - * SATA - ****************************************************************************/ -static struct mv_sata_platform_data lsmini_sata_data = { - .n_ports = 2, -}; - - -/***************************************************************************** - * Linkstation Mini specific power off method: reboot - ****************************************************************************/ -/* - * On the Linkstation Mini, the shutdown process is following: - * - Userland monitors key events until the power switch goes to off position - * - The board reboots - * - U-boot starts and goes into an idle mode waiting for the user - * to move the switch to ON position - */ - -static void lsmini_power_off(void) -{ - orion5x_restart(REBOOT_HARD, NULL); -} - - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -#define LSMINI_GPIO_USB_POWER 16 -#define LSMINI_GPIO_AUTO_POWER 17 -#define LSMINI_GPIO_POWER 18 - -#define LSMINI_GPIO_HDD_POWER0 1 -#define LSMINI_GPIO_HDD_POWER1 19 - -static unsigned int lsmini_mpp_modes[] __initdata = { - MPP0_UNUSED, /* LED_RESERVE1 (unused) */ - MPP1_GPIO, /* HDD_PWR */ - MPP2_GPIO, /* LED_ALARM */ - MPP3_GPIO, /* LED_INFO */ - MPP4_UNUSED, - MPP5_UNUSED, - MPP6_UNUSED, - MPP7_UNUSED, - MPP8_UNUSED, - MPP9_GPIO, /* LED_FUNC */ - MPP10_UNUSED, - MPP11_UNUSED, /* LED_ETH (dummy) */ - MPP12_UNUSED, - MPP13_UNUSED, - MPP14_GPIO, /* LED_PWR */ - MPP15_GPIO, /* FUNC */ - MPP16_GPIO, /* USB_PWR */ - MPP17_GPIO, /* AUTO_POWER */ - MPP18_GPIO, /* POWER */ - MPP19_GPIO, /* HDD_PWR1 */ - 0, -}; - -static void __init lsmini_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(lsmini_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&lsmini_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&lsmini_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - LSMINI_NOR_BOOT_BASE, - LSMINI_NOR_BOOT_SIZE); - platform_device_register(&lsmini_nor_flash); - - platform_device_register(&lsmini_button_device); - - platform_device_register(&lsmini_leds); - - i2c_register_board_info(0, &lsmini_i2c_rtc, 1); - - /* enable USB power */ - gpio_set_value(LSMINI_GPIO_USB_POWER, 1); - - /* register power-off method */ - pm_power_off = lsmini_power_off; - - pr_info("%s: finished\n", __func__); -} - -#ifdef CONFIG_MACH_LINKSTATION_MINI -MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") - /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */ - .atag_offset = 0x100, - .init_machine = lsmini_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c index 7189827d641d..24b2959719fa 100644 --- a/arch/arm/mach-orion5x/tsx09-common.c +++ b/arch/arm/mach-orion5x/tsx09-common.c @@ -101,9 +101,7 @@ static int __init qnap_tsx09_check_mac_addr(const char *addr_str) addr[i] = byte; } - printk(KERN_INFO "tsx09: found ethernet mac address "); - for (i = 0; i < 6; i++) - printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); + printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr); memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6); diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index d99d08eeb966..83e94c95e314 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -16,6 +16,7 @@ #include <linux/of_platform.h> #include <linux/io.h> #include <linux/rtc/sirfsoc_rtciobrg.h> +#include <asm/outercache.h> #include <asm/suspend.h> #include <asm/hardware/cache-l2x0.h> diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d897292712eb..70366b35d299 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -496,18 +496,18 @@ static struct irq_chip balloon3_irq_chip = { .irq_unmask = balloon3_unmask_irq, }; -static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) +static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc) { unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) & balloon3_irq_enabled; do { - /* clear useless edge notification */ - if (desc->irq_data.chip->irq_ack) { - struct irq_data *d; + struct irq_data *d = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_chip(d); + unsigned int irq; - d = irq_get_irq_data(BALLOON3_AUX_NIRQ); - desc->irq_data.chip->irq_ack(d); - } + /* clear useless edge notification */ + if (chip->irq_ack) + chip->irq_ack(d); while (pending) { irq = BALLOON3_IRQ(0) + __ffs(pending); @@ -528,7 +528,7 @@ static void __init balloon3_init_irq(void) for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { irq_set_chip_and_handler(irq, &balloon3_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index d8f816c24a2f..1fa79f1f832d 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -29,8 +29,9 @@ void __iomem *it8152_base_address; static int cmx2xx_it8152_irq_gpio; -static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) +static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq = irq_desc_get_irq(desc); /* clear our parent irq */ desc->irq_data.chip->irq_ack(&desc->irq_data); diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 35434662dc7c..c62473235a13 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -17,6 +17,7 @@ #include <linux/platform_data/camera-pxa.h> #include <mach/audio.h> #include <mach/hardware.h> +#include <linux/platform_data/mmp_dma.h> #include <linux/platform_data/mtd-nand-pxa3xx.h> #include "devices.h" @@ -439,25 +440,11 @@ struct platform_device pxa_device_rtc = { .resource = pxa_rtc_resources, }; -static struct resource sa1100_rtc_resources[] = { - { - .start = IRQ_RTC1Hz, - .end = IRQ_RTC1Hz, - .name = "rtc 1Hz", - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_RTCAlrm, - .end = IRQ_RTCAlrm, - .name = "rtc alarm", - .flags = IORESOURCE_IRQ, - }, -}; - struct platform_device sa1100_device_rtc = { .name = "sa1100-rtc", .id = -1, - .num_resources = ARRAY_SIZE(sa1100_rtc_resources), - .resource = sa1100_rtc_resources, + .num_resources = ARRAY_SIZE(pxa_rtc_resources), + .resource = pxa_rtc_resources, }; static struct resource pxa_ac97_resources[] = { @@ -1193,3 +1180,39 @@ void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info) pd->dev.platform_data = info; platform_device_add(pd); } + +static struct mmp_dma_platdata pxa_dma_pdata = { + .dma_channels = 0, +}; + +static struct resource pxa_dma_resource[] = { + [0] = { + .start = 0x40000000, + .end = 0x4000ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DMA, + .end = IRQ_DMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 pxadma_dmamask = 0xffffffffUL; + +static struct platform_device pxa2xx_pxa_dma = { + .name = "pxa-dma", + .id = 0, + .dev = { + .dma_mask = &pxadma_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxa_dma_resource), + .resource = pxa_dma_resource, +}; + +void __init pxa2xx_set_dmac_info(int nb_channels) +{ + pxa_dma_pdata.dma_channels = nb_channels; + pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata); +} diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 98608c5575cb..9c10248fadcc 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -133,7 +133,6 @@ static int pxa_irq_map(struct irq_domain *h, unsigned int virq, irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, handle_level_irq); irq_set_chip_data(virq, base); - set_irq_flags(virq, IRQF_VALID); return 0; } diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index eaee2c20b189..b070167deef2 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -120,8 +120,9 @@ static struct irq_chip lpd270_irq_chip = { .irq_unmask = lpd270_unmask_irq, }; -static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) +static void lpd270_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq; unsigned long pending; pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; @@ -151,7 +152,7 @@ static void __init lpd270_init_irq(void) for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { irq_set_chip_and_handler(irq, &lpd270_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler); irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 2897da2a5df6..9a0c8affdadb 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -284,8 +284,9 @@ static struct irq_chip pcm990_irq_chip = { .irq_unmask = pcm990_unmask_irq, }; -static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) +static void pcm990_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq; unsigned long pending; pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR); @@ -311,7 +312,7 @@ static void __init pcm990_init_irq(void) for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { irq_set_chip_and_handler(irq, &pcm990_irq_chip, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); } /* disable all Interrupts */ diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c index 7e0e5bd0c9de..8e0e62ccdced 100644 --- a/arch/arm/mach-pxa/pxa-dt.c +++ b/arch/arm/mach-pxa/pxa-dt.c @@ -19,7 +19,7 @@ #include "generic.h" #ifdef CONFIG_PXA3xx -static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = { +static const struct of_dev_auxdata const pxa3xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL), OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL), OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), @@ -39,7 +39,7 @@ static void __init pxa3xx_dt_init(void) pxa3xx_auxdata_lookup, NULL); } -static const char *pxa3xx_dt_board_compat[] __initdata = { +static const char *const pxa3xx_dt_board_compat[] __initconst = { "marvell,pxa300", "marvell,pxa310", "marvell,pxa320", diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 23a90c62ec11..1dc85ffc3e20 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -206,6 +206,7 @@ static int __init pxa25x_init(void) register_syscore_ops(&pxa_irq_syscore_ops); register_syscore_ops(&pxa2xx_mfp_syscore_ops); + pxa2xx_set_dmac_info(16); pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index b5abdeb5bb2d..221260d5d109 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -282,7 +282,6 @@ static struct platform_device *devices[] __initdata = { &pxa_device_asoc_ssp2, &pxa_device_asoc_ssp3, &pxa_device_asoc_platform, - &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, &pxa27x_device_ssp2, @@ -310,6 +309,7 @@ static int __init pxa27x_init(void) if (!of_have_populated_dt()) { pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info); + pxa2xx_set_dmac_info(32); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index bd4cbef15ccf..ce0f8d6242e2 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -325,7 +325,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID); + irq_clear_status_flags(irq, IRQ_NOREQUEST); } pxa_ext_wakeup_chip.irq_set_wake = fn; @@ -394,7 +394,6 @@ static struct platform_device *devices[] __initdata = { &pxa_device_asoc_ssp3, &pxa_device_asoc_ssp4, &pxa_device_asoc_platform, - &sa1100_device_rtc, &pxa_device_rtc, &pxa3xx_device_ssp1, &pxa3xx_device_ssp2, @@ -431,6 +430,7 @@ static int __init pxa3xx_init(void) if (of_have_populated_dt()) return 0; + pxa2xx_set_dmac_info(32); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if (ret) return ret; diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 051a6555cbf9..bdc0c41bc4fd 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -841,11 +841,9 @@ static int sharpsl_pm_probe(struct platform_device *pdev) sharpsl_pm.charge_mode = CHRG_OFF; sharpsl_pm.flags = 0; - init_timer(&sharpsl_pm.ac_timer); - sharpsl_pm.ac_timer.function = sharpsl_ac_timer; + setup_timer(&sharpsl_pm.ac_timer, sharpsl_ac_timer, 0UL); - init_timer(&sharpsl_pm.chrg_full_timer); - sharpsl_pm.chrg_full_timer.function = sharpsl_chrg_full_timer; + setup_timer(&sharpsl_pm.chrg_full_timer, sharpsl_chrg_full_timer, 0UL); led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger); diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c index 685deff861d2..e0a53208880a 100644 --- a/arch/arm/mach-pxa/tosa-bt.c +++ b/arch/arm/mach-pxa/tosa-bt.c @@ -131,17 +131,4 @@ static struct platform_driver tosa_bt_driver = { .name = "tosa-bt", }, }; - - -static int __init tosa_bt_init(void) -{ - return platform_driver_register(&tosa_bt_driver); -} - -static void __exit tosa_bt_exit(void) -{ - platform_driver_unregister(&tosa_bt_driver); -} - -module_init(tosa_bt_init); -module_exit(tosa_bt_exit); +module_platform_driver(tosa_bt_driver); diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index de3b08073fe7..4841d6cefe76 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -276,8 +276,9 @@ static inline unsigned long viper_irq_pending(void) viper_irq_enabled_mask; } -static void viper_irq_handler(unsigned int irq, struct irq_desc *desc) +static void viper_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq; unsigned long pending; pending = viper_irq_pending(); @@ -313,7 +314,7 @@ static void __init viper_init_irq(void) isa_irq = viper_bit_to_irq(level); irq_set_chip_and_handler(isa_irq, &viper_irq_chip, handle_edge_irq); - set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE); } irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 6158566fa0f7..6f94dd7b4dee 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -105,8 +105,9 @@ static inline unsigned long zeus_irq_pending(void) return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask; } -static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) +static void zeus_irq_handler(unsigned int __irq, struct irq_desc *desc) { + unsigned int irq; unsigned long pending; pending = zeus_irq_pending(); @@ -151,7 +152,7 @@ static void __init zeus_init_irq(void) isa_irq = zeus_bit_to_irq(level); irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, handle_edge_irq); - set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE); } irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c index cc28b89dd48f..382cc1b90519 100644 --- a/arch/arm/mach-realview/realview-dt.c +++ b/arch/arm/mach-realview/realview-dt.c @@ -13,7 +13,7 @@ #include <asm/hardware/cache-l2x0.h> #include "core.h" -static const char *realview_dt_platform_compat[] __initconst = { +static const char *const realview_dt_platform_compat[] __initconst = { "arm,realview-eb", "arm,realview-pb1176", "arm,realview-pb11mp", diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 8fcec1cc101e..3e7a4b761a95 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -72,29 +72,22 @@ static struct reset_control *rockchip_get_core_reset(int cpu) static int pmu_set_power_domain(int pd, bool on) { u32 val = (on) ? 0 : BIT(pd); + struct reset_control *rstc = rockchip_get_core_reset(pd); int ret; + if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { + pr_err("%s: could not get reset control for core %d\n", + __func__, pd); + return PTR_ERR(rstc); + } + /* * We need to soft reset the cpu when we turn off the cpu power domain, * or else the active processors might be stalled when the individual * processor is powered down. */ - if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - struct reset_control *rstc = rockchip_get_core_reset(pd); - - if (IS_ERR(rstc)) { - pr_err("%s: could not get reset control for core %d\n", - __func__, pd); - return PTR_ERR(rstc); - } - - if (on) - reset_control_deassert(rstc); - else - reset_control_assert(rstc); - - reset_control_put(rstc); - } + if (!IS_ERR(rstc) && !on) + reset_control_assert(rstc); ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); if (ret < 0) { @@ -107,11 +100,17 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } + if (!IS_ERR(rstc)) { + if (on) + reset_control_deassert(rstc); + reset_control_put(rstc); + } + return 0; } @@ -130,7 +129,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -140,14 +139,19 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) return ret; if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - /* We communicate with the bootrom to active the cpus other + /* + * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will * stay at wfe state, once they are actived, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc - * */ - udelay(10); + * The cpu0 need to wait the other cpus other than cpu0 entering + * the wfe state.The wait time is affected by many aspects. + * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) + */ + mdelay(1); /* ensure the cpus other than cpu0 to startup */ + writel(virt_to_phys(secondary_startup), sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); @@ -317,6 +321,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) #ifdef CONFIG_HOTPLUG_CPU static int rockchip_cpu_kill(unsigned int cpu) { + /* + * We need a delay here to ensure that the dying CPU can finish + * executing v7_coherency_exit() and reach the WFI/WFE state + * prior to having the power domain disabled. + */ + mdelay(1); + pmu_set_power_domain(0 + cpu, false); return 1; } @@ -324,7 +335,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -337,4 +348,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index b0dcbe28f78c..bee8c8051929 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -45,9 +45,11 @@ static phys_addr_t rk3288_bootram_phy; static struct regmap *pmu_regmap; static struct regmap *sgrf_regmap; +static struct regmap *grf_regmap; static u32 rk3288_pmu_pwr_mode_con; static u32 rk3288_sgrf_soc_con0; +static u32 rk3288_sgrf_cpu_con0; static inline u32 rk3288_l2_config(void) { @@ -66,10 +68,37 @@ static void rk3288_config_bootdata(void) rkpm_bootdata_l2ctlr = rk3288_l2_config(); } +#define GRF_UOC0_CON0 0x320 +#define GRF_UOC1_CON0 0x334 +#define GRF_UOC2_CON0 0x348 +#define GRF_SIDDQ BIT(13) + +static bool rk3288_slp_disable_osc(void) +{ + static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, + GRF_UOC2_CON0 }; + u32 reg, i; + + /* + * if any usb phy is still on(GRF_SIDDQ==0), that means we need the + * function of usb wakeup, so do not switch to 32khz, since the usb phy + * clk does not connect to 32khz osc + */ + for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { + regmap_read(grf_regmap, reg_offset[i], ®); + if (!(reg & GRF_SIDDQ)) + return false; + } + + return true; +} + static void rk3288_slp_mode_set(int level) { u32 mode_set, mode_set1; + bool osc_disable = rk3288_slp_disable_osc(); + regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, @@ -94,9 +123,6 @@ static void rk3288_slp_mode_set(int level) regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, rk3288_bootram_phy); - regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, - PMU_ARMINT_WAKEUP_EN); - mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | @@ -107,13 +133,31 @@ static void rk3288_slp_mode_set(int level) if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { /* arm off, logic deep sleep */ - mode_set |= BIT(PMU_BUS_PD_EN) | + mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | - BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) | BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); + if (osc_disable) + mode_set |= BIT(PMU_OSC_24M_DIS); + mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); + + regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, + PMU_ARMINT_WAKEUP_EN); + + /* + * In deep suspend we use PMU_PMU_USE_LF to let the rk3288 + * switch its main clock supply to the alternative 32kHz + * source. Therefore set 30ms on a 32kHz clock for pmic + * stabilization. Similar 30ms on 24MHz for the other + * mode below. + */ + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); + + /* only wait for stabilization, if we turned the osc off */ + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, + osc_disable ? 32 * 30 : 0); } else { /* * arm off, logic normal @@ -121,6 +165,15 @@ static void rk3288_slp_mode_set(int level) * wakeup will be error */ mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); + + regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, + PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN); + + /* 30ms on a 24MHz clock for pmic stabilization */ + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); + + /* oscillator is still running, so no need to wait */ + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0); } regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); @@ -129,6 +182,9 @@ static void rk3288_slp_mode_set(int level) static void rk3288_slp_mode_set_resume(void) { + regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, + rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); + regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, rk3288_pmu_pwr_mode_con); @@ -190,7 +246,14 @@ static int rk3288_suspend_init(struct device_node *np) "rockchip,rk3288-sgrf"); if (IS_ERR(sgrf_regmap)) { pr_err("%s: could not find sgrf regmap\n", __func__); - return PTR_ERR(pmu_regmap); + return PTR_ERR(sgrf_regmap); + } + + grf_regmap = syscon_regmap_lookup_by_compatible( + "rockchip,rk3288-grf"); + if (IS_ERR(grf_regmap)) { + pr_err("%s: could not find grf regmap\n", __func__); + return PTR_ERR(grf_regmap); } sram_np = of_find_compatible_node(NULL, NULL, @@ -221,9 +284,6 @@ static int rk3288_suspend_init(struct device_node *np) memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, rk3288_bootram_sz); - regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH); - regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH); - return 0; } diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 3e8d39c0c3d5..b5af26f8336e 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -59,19 +59,9 @@ static inline void rockchip_suspend_init(void) #define SGRF_DAPDEVICEEN BIT(0) #define SGRF_DAPDEVICEEN_WRITE BIT(16) -#define RK3288_CRU_MODE_CON 0x50 -#define RK3288_CRU_SEL0_CON 0x60 -#define RK3288_CRU_SEL1_CON 0x64 -#define RK3288_CRU_SEL10_CON 0x88 -#define RK3288_CRU_SEL33_CON 0xe4 -#define RK3288_CRU_SEL37_CON 0xf4 - /* PMU_WAKEUP_CFG1 bits */ #define PMU_ARMINT_WAKEUP_EN BIT(0) - -/* wait 30ms for OSC stable and 30ms for pmic stable */ -#define OSC_STABL_CNT_THRESH (32 * 30) -#define PMU_STABL_CNT_THRESH (32 * 30) +#define PMU_GPIOINT_WAKEUP_EN BIT(3) enum rk3288_pwr_mode_con { PMU_PWR_MODE_EN = 0, diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index fcb1d59f7aec..f726d4c4e6dd 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -946,7 +946,7 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type) irq_set_chip_and_handler(ec->irq, &ecard_chip, handle_level_irq); irq_set_chip_data(ec->irq, ec); - set_irq_flags(ec->irq, IRQF_VALID); + irq_clear_status_flags(ec->irq, IRQ_NOREQUEST); } #ifdef CONFIG_ARCH_RPC diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 3e4fa849c64d..66502e6207fe 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -117,7 +117,7 @@ extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; void __init rpc_init_irq(void) { - unsigned int irq, flags; + unsigned int irq, clr, set = 0; iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKB); @@ -128,37 +128,37 @@ void __init rpc_init_irq(void) &rpc_default_fiq_end - &rpc_default_fiq_start); for (irq = 0; irq < NR_IRQS; irq++) { - flags = IRQF_VALID; + clr = IRQ_NOREQUEST; if (irq <= 6 || (irq >= 9 && irq <= 15)) - flags |= IRQF_PROBE; + clr |= IRQ_NOPROBE; if (irq == 21 || (irq >= 16 && irq <= 19) || irq == IRQ_KEYBOARDTX) - flags |= IRQF_NOAUTOEN; + set |= IRQ_NOAUTOEN; switch (irq) { case 0 ... 7: irq_set_chip_and_handler(irq, &iomd_a_chip, handle_level_irq); - set_irq_flags(irq, flags); + irq_modify_status(irq, clr, set); break; case 8 ... 15: irq_set_chip_and_handler(irq, &iomd_b_chip, handle_level_irq); - set_irq_flags(irq, flags); + irq_modify_status(irq, clr, set); break; case 16 ... 21: irq_set_chip_and_handler(irq, &iomd_dma_chip, handle_level_irq); - set_irq_flags(irq, flags); + irq_modify_status(irq, clr, set); break; case 64 ... 71: irq_set_chip(irq, &iomd_fiq_chip); - set_irq_flags(irq, IRQF_VALID); + irq_modify_status(irq, clr, set); break; } } diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 23bec3a85b22..ef68ecb27396 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -124,6 +124,11 @@ config S3C24XX_PLL This also means that the PLL tables for the selected CPU(s) will be built which may increase the size of the kernel image. +config S3C_SETUP_CAMIF + bool + help + Compile in common setup code for S3C CAMIF devices + # cpu frequency items common between s3c2410 and s3c2440/s3c2442 config S3C2410_IOTIMING diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 05920c8a5764..8ac2f58a3480 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -99,3 +99,4 @@ obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o +obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c index cb1b791954de..ced1ab86ac83 100644 --- a/arch/arm/mach-s3c24xx/bast-irq.c +++ b/arch/arm/mach-s3c24xx/bast-irq.c @@ -147,7 +147,7 @@ static __init int bast_irq_init(void) irq_set_chip_and_handler(irqno, &bast_pc104_chip, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); + irq_clear_status_flags(irqno, IRQ_NOREQUEST); } } diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/mach-s3c24xx/fb-core.h index bca383efcf6d..103bdbaddd55 100644 --- a/arch/arm/plat-samsung/include/plat/fb-core.h +++ b/arch/arm/mach-s3c24xx/fb-core.h @@ -1,6 +1,4 @@ /* - * arch/arm/plat-samsung/include/plat/fb-core.h - * * Copyright 2010 Samsung Electronics Co., Ltd. * Pawel Osciak <p.osciak@samsung.com> * diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c index f886478b88c5..5f028ff84cfe 100644 --- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c +++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c @@ -39,7 +39,7 @@ static void __init s3c2416_dt_machine_init(void) s3c_pm_init(); } -static char const *s3c2416_dt_compat[] __initdata = { +static const char *const s3c2416_dt_compat[] __initconst = { "samsung,s3c2416", "samsung,s3c2450", NULL diff --git a/arch/arm/plat-samsung/include/plat/nand-core.h b/arch/arm/mach-s3c24xx/nand-core.h index 6de20789a95e..7e811fe1cf41 100644 --- a/arch/arm/plat-samsung/include/plat/nand-core.h +++ b/arch/arm/mach-s3c24xx/nand-core.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-samsung/include/plat/nand-core.h - * +/* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 64a13605cfc3..fb5ee8d38913 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c @@ -40,11 +40,11 @@ #include <plat/cpu.h> #include <plat/cpu-freq.h> #include <plat/devs.h> -#include <plat/nand-core.h> #include <plat/pm.h> #include <plat/regs-spi.h> #include "common.h" +#include "nand-core.h" #include "regs-dsc.h" #include "s3c2412-power.h" diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c index 3f8ca2a3ef17..621b8648a7ef 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c24xx/s3c2416.c @@ -59,12 +59,12 @@ #include <plat/pm.h> #include <plat/iic-core.h> -#include <plat/fb-core.h> -#include <plat/nand-core.h> #include <plat/adc-core.h> -#include <plat/spi-core.h> #include "common.h" +#include "fb-core.h" +#include "nand-core.h" +#include "spi-core.h" static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c index 87b6b89d8ee7..b559d378cf43 100644 --- a/arch/arm/mach-s3c24xx/s3c2443.c +++ b/arch/arm/mach-s3c24xx/s3c2443.c @@ -41,10 +41,11 @@ #include <plat/gpio-cfg-helpers.h> #include <plat/devs.h> #include <plat/cpu.h> -#include <plat/fb-core.h> -#include <plat/nand-core.h> #include <plat/adc-core.h> -#include <plat/spi-core.h> + +#include "fb-core.h" +#include "nand-core.h" +#include "spi-core.h" static struct map_desc s3c2443_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index b14119585dc7..31fd273269c2 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c @@ -41,9 +41,9 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pm.h> -#include <plat/nand-core.h> #include "common.h" +#include "nand-core.h" #include "regs-dsc.h" static struct map_desc s3c244x_iodesc[] __initdata = { diff --git a/arch/arm/plat-samsung/setup-camif.c b/arch/arm/mach-s3c24xx/setup-camif.c index 72d8edb8927a..72d8edb8927a 100644 --- a/arch/arm/plat-samsung/setup-camif.c +++ b/arch/arm/mach-s3c24xx/setup-camif.c diff --git a/arch/arm/plat-samsung/include/plat/spi-core.h b/arch/arm/mach-s3c24xx/spi-core.h index 0b9428ab3fc3..0b9428ab3fc3 100644 --- a/arch/arm/plat-samsung/include/plat/spi-core.h +++ b/arch/arm/mach-s3c24xx/spi-core.h diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index eff95e950d81..28c7097e8506 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -34,6 +34,12 @@ config S3C64XX_DEV_ONENAND1 help Compile in platform device definition for OneNAND1 controller +config SAMSUNG_DEV_BACKLIGHT + bool + depends on SAMSUNG_DEV_PWM + help + Compile in platform device definition LCD backlight with PWM Timer + # platform specific device setup config S3C64XX_SETUP_I2C0 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 17f4b07ec763..bb233f342f31 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -40,6 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o +obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o + # Machine support obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o diff --git a/arch/arm/plat-samsung/include/plat/ata-core.h b/arch/arm/mach-s3c64xx/ata-core.h index f5a4ec7141b1..5951f24a9ec8 100644 --- a/arch/arm/plat-samsung/include/plat/ata-core.h +++ b/arch/arm/mach-s3c64xx/ata-core.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-samsung/include/plat/ata-core.h - * +/* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com * diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/mach-s3c64xx/backlight.h index ad530c78fe8c..8dcacac523a2 100644 --- a/arch/arm/plat-samsung/include/plat/backlight.h +++ b/arch/arm/mach-s3c64xx/backlight.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-samsung/include/plat/backlight.h - * +/* * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 16547f2641a3..fd63ecfb2f81 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -21,7 +21,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> -#include <linux/clk-provider.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> @@ -48,12 +47,12 @@ #include <plat/devs.h> #include <plat/pm.h> #include <plat/gpio-cfg.h> -#include <plat/irq-uart.h> #include <plat/pwm-core.h> #include <plat/regs-irqtype.h> -#include <plat/watchdog-reset.h> #include "common.h" +#include "irq-uart.h" +#include "watchdog-reset.h" /* External clock frequency */ static unsigned long xtal_f = 12000000, xusbxti_f = 48000000; @@ -420,7 +419,7 @@ static int __init s3c64xx_init_irq_eint(void) for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); - set_irq_flags(irq, IRQF_VALID); + irq_clear_status_flags(irq, IRQ_NOREQUEST); } irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/mach-s3c64xx/dev-backlight.c index 2157c5b539e6..38c323e68e3f 100644 --- a/arch/arm/plat-samsung/dev-backlight.c +++ b/arch/arm/mach-s3c64xx/dev-backlight.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-samsung/dev-backlight.c - * +/* * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * @@ -18,7 +17,8 @@ #include <plat/devs.h> #include <plat/gpio-cfg.h> -#include <plat/backlight.h> + +#include "backlight.h" struct samsung_bl_drvdata { struct platform_pwm_backlight_data plat_data; diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/mach-s3c64xx/irq-uart.h index a9331e49bea3..4b296132962f 100644 --- a/arch/arm/plat-samsung/include/plat/irq-uart.h +++ b/arch/arm/mach-s3c64xx/irq-uart.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-samsung/include/plat/irq-uart.h - * +/* * Copyright (c) 2010 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c index 2fddf38192df..bbf74edd3dd9 100644 --- a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c +++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c @@ -15,11 +15,10 @@ #include <asm/system_misc.h> #include <plat/cpu.h> -#include <plat/watchdog-reset.h> - #include <mach/map.h> #include "common.h" +#include "watchdog-reset.h" /* * IO mapping for shared system controller IP. @@ -61,7 +60,7 @@ static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd) soft_restart(0); } -static char const *s3c64xx_dt_compat[] __initdata = { +static const char *const s3c64xx_dt_compat[] __initconst = { "samsung,s3c6400", "samsung,s3c6410", NULL diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index b7447a92276e..d590b88bd8a8 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -68,9 +68,9 @@ #include <plat/adc.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <plat/keypad.h> -#include <plat/backlight.h> #include <plat/samsung-time.h> +#include "backlight.h" #include "common.h" #include "regs-modem.h" #include "regs-srom.h" diff --git a/arch/arm/plat-samsung/include/plat/onenand-core.h b/arch/arm/mach-s3c64xx/onenand-core.h index 7701cb7020c8..925eb13bbb60 100644 --- a/arch/arm/plat-samsung/include/plat/onenand-core.h +++ b/arch/arm/mach-s3c64xx/onenand-core.h @@ -1,6 +1,4 @@ /* - * linux/arch/arm/plat-samsung/onenand-core.h - * * Copyright (c) 2010 Samsung Electronics * Kyungmin Park <kyungmin.park@samsung.com> * Marek Szyprowski <m.szyprowski@samsung.com> diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h index fcf279662067..eae3c311e590 100644 --- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h +++ b/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h - * +/* * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 1ce48c54cd9c..33273abef669 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -41,9 +41,9 @@ #include <plat/devs.h> #include <plat/sdhci.h> #include <plat/iic-core.h> -#include <plat/onenand-core.h> #include "common.h" +#include "onenand-core.h" void __init s3c6400_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index b2a7930548d9..eadc48dee0e4 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -41,12 +41,12 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> -#include <plat/ata-core.h> #include <plat/adc-core.h> #include <plat/iic-core.h> -#include <plat/onenand-core.h> +#include "ata-core.h" #include "common.h" +#include "onenand-core.h" void __init s3c6410_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c index ca960bda02fd..2b17b7f5152f 100644 --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c @@ -16,10 +16,10 @@ #include <linux/platform_device.h> #include <mach/map.h> #include <plat/cpu.h> -#include <plat/regs-usb-hsotg-phy.h> #include <plat/usb-phy.h> #include "regs-sys.h" +#include "regs-usb-hsotg-phy.h" static int s3c_usb_otgphy_init(struct platform_device *pdev) { diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/mach-s3c64xx/watchdog-reset.h index 0386b8f76623..42707dfbda9c 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/mach-s3c64xx/watchdog-reset.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/watchdog-reset.h - * +/* * Copyright (c) 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 0ac6cc08a19c..7972617cca64 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -858,40 +858,6 @@ /* - * Real-Time Clock (RTC) control registers - * - * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). - * - * Clocks - * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). - * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). - */ - -#define RTAR __REG(0x90010000) /* RTC Alarm Reg. */ -#define RCNR __REG(0x90010004) /* RTC CouNt Reg. */ -#define RTTR __REG(0x90010008) /* RTC Trim Reg. */ -#define RTSR __REG(0x90010010) /* RTC Status Reg. */ - -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ - /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ - /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ - -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ - - -/* * Power Manager (PM) control registers * * Registers diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 99d9a3b1bf34..6d237b4f7a8e 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -320,10 +320,10 @@ static int neponset_probe(struct platform_device *dev) irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, handle_simple_irq); - set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE); irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, handle_simple_irq); - set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); + irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE); irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 45006479d461..926e336d6aeb 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -4,6 +4,7 @@ config ARCH_SHMOBILE config PM_RCAR bool + select PM_GENERIC_DOMAINS if PM config PM_RMOBILE bool @@ -50,6 +51,7 @@ config ARCH_EMEV2 config ARCH_R7S72100 bool "RZ/A1H (R7S72100)" + select PM_GENERIC_DOMAINS if PM select SYS_SUPPORTS_SH_MTU2 config ARCH_R8A73A4 @@ -80,6 +82,11 @@ config ARCH_R8A7791 select ARCH_RCAR_GEN2 select I2C +config ARCH_R8A7793 + bool "R-Car M2-N (R8A7793)" + select ARCH_RCAR_GEN2 + select I2C + config ARCH_R8A7794 bool "R-Car E2 (R8A77940)" select ARCH_RCAR_GEN2 @@ -89,13 +96,6 @@ config ARCH_SH73A0 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN -comment "Renesas ARM SoCs Board Type" - -config MACH_MARZEN - bool "MARZEN board" - depends on ARCH_R8A7779 - select REGULATOR_FIXED_VOLTAGE if REGULATOR - comment "Renesas ARM SoCs System Configuration" endif @@ -103,22 +103,6 @@ if ARCH_SHMOBILE_LEGACY comment "Renesas ARM SoCs System Type" -config ARCH_SH73A0 - bool "SH-Mobile AG5 (R8A73A00)" - select ARCH_RMOBILE - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select I2C - select SH_INTC - select RENESAS_INTC_IRQPIN - -config ARCH_R8A7740 - bool "R-Mobile A1 (R8A77400)" - select ARCH_RMOBILE - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select RENESAS_INTC_IRQPIN - config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1 @@ -133,15 +117,6 @@ config ARCH_R8A7779 comment "Renesas ARM SoCs Board Type" -config MACH_ARMADILLO800EVA - bool "Armadillo-800 EVA board" - depends on ARCH_R8A7740 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SMSC_PHY if SH_ETH - select SND_SOC_WM8978 if SND_SIMPLE_CARD && I2C - select USE_OF - config MACH_BOCKW bool "BOCK-W platform" depends on ARCH_R8A7778 @@ -164,21 +139,6 @@ config MACH_BOCKW_REFERENCE This is intended to aid developers -config MACH_MARZEN - bool "MARZEN board" - depends on ARCH_R8A7779 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select USE_OF - -config MACH_KZM9G - bool "KZM-A9-GT board" - depends on ARCH_SH73A0 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SND_SOC_AK4642 if SND_SIMPLE_CARD - select USE_OF - comment "Renesas ARM SoCs System Configuration" config CPU_HAS_INTEVT diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 89e463de4479..476de30798d7 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -6,13 +6,14 @@ obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o +obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o -obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o +obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o +obj-$(CONFIG_ARCH_R8A7793) += setup-r8a7793.o obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o @@ -20,10 +21,7 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o # Clock objects ifndef CONFIG_COMMON_CLK obj-y += clock.o -obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o -obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o -obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o endif # CPU reset vector handling objects @@ -34,6 +32,7 @@ obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y) CFLAGS_setup-rcar-gen2.o += -march=armv7-a obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o +obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o # SMP objects smp-y := $(cpu-y) @@ -51,14 +50,9 @@ obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o # Board objects -ifdef CONFIG_ARCH_SHMOBILE_MULTI -obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o -else +ifndef CONFIG_ARCH_SHMOBILE_MULTI obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o -obj-$(CONFIG_MACH_MARZEN) += board-marzen.o -obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o -obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o endif # Framework support diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index e1ef19cef89c..a489fe9a76cd 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -1,10 +1,7 @@ # per-board load address for uImage loadaddr-y := -loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 -loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 -loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 __ZRELADDR := $(sort $(loadaddr-y)) zreladdr-y += $(__ZRELADDR) diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c deleted file mode 100644 index bf37e3c532f6..000000000000 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ /dev/null @@ -1,1365 +0,0 @@ -/* - * armadillo 800 eva board support - * - * Copyright (C) 2012 Renesas Solutions Corp. - * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/i2c-gpio.h> -#include <linux/input.h> -#include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/mfd/tmio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mmcif.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/pinctrl/machine.h> -#include <linux/platform_data/st1232_pdata.h> -#include <linux/platform_device.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/reboot.h> -#include <linux/regulator/driver.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/gpio-regulator.h> -#include <linux/regulator/machine.h> -#include <linux/sh_eth.h> -#include <linux/usb/renesas_usbhs.h> -#include <linux/videodev2.h> - -#include <asm/hardware/cache-l2x0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/page.h> -#include <media/mt9t112.h> -#include <media/sh_mobile_ceu.h> -#include <media/soc_camera.h> -#include <sound/sh_fsi.h> -#include <sound/simple_card.h> -#include <video/sh_mobile_hdmi.h> -#include <video/sh_mobile_lcdc.h> - -#include "common.h" -#include "irqs.h" -#include "pm-rmobile.h" -#include "r8a7740.h" -#include "sh-gpio.h" - -/* - * CON1 Camera Module - * CON2 Extension Bus - * CON3 HDMI Output - * CON4 Composite Video Output - * CON5 H-UDI JTAG - * CON6 ARM JTAG - * CON7 SD1 - * CON8 SD2 - * CON9 RTC BackUp - * CON10 Monaural Mic Input - * CON11 Stereo Headphone Output - * CON12 Audio Line Output(L) - * CON13 Audio Line Output(R) - * CON14 AWL13 Module - * CON15 Extension - * CON16 LCD1 - * CON17 LCD2 - * CON19 Power Input - * CON20 USB1 - * CON21 USB2 - * CON22 Serial - * CON23 LAN - * CON24 USB3 - * LED1 Camera LED(Yellow) - * LED2 Power LED (Green) - * ED3-LED6 User LED(Yellow) - * LED7 LAN link LED(Green) - * LED8 LAN activity LED(Yellow) - */ - -/* - * DipSwitch - * - * SW1 - * - * -12345678-+---------------+---------------------------- - * 1 | boot | hermit - * 0 | boot | OS auto boot - * -12345678-+---------------+---------------------------- - * 00 | boot device | eMMC - * 10 | boot device | SDHI0 (CON7) - * 01 | boot device | - - * 11 | boot device | Extension Buss (CS0) - * -12345678-+---------------+---------------------------- - * 0 | Extension Bus | D8-D15 disable, eMMC enable - * 1 | Extension Bus | D8-D15 enable, eMMC disable - * -12345678-+---------------+---------------------------- - * 0 | SDHI1 | COM8 disable, COM14 enable - * 1 | SDHI1 | COM8 enable, COM14 disable - * -12345678-+---------------+---------------------------- - * 0 | USB0 | COM20 enable, COM24 disable - * 1 | USB0 | COM20 disable, COM24 enable - * -12345678-+---------------+---------------------------- - * 00 | JTAG | SH-X2 - * 10 | JTAG | ARM - * 01 | JTAG | - - * 11 | JTAG | Boundary Scan - *-----------+---------------+---------------------------- - */ - -/* - * FSI-WM8978 - * - * this command is required when playback. - * - * # amixer set "Headphone" 50 - * - * this command is required when capture. - * - * # amixer set "Input PGA" 15 - * # amixer set "Left Input Mixer MicP" on - * # amixer set "Left Input Mixer MicN" on - * # amixer set "Right Input Mixer MicN" on - * # amixer set "Right Input Mixer MicP" on - */ - -/* - * USB function - * - * When you use USB Function, - * set SW1.6 ON, and connect cable to CN24. - * - * USBF needs workaround on R8A7740 chip. - * These are a little bit complex. - * see - * usbhsf_power_ctrl() - */ -#define IRQ7 irq_pin(7) -#define USBCR1 IOMEM(0xe605810a) -#define USBH 0xC6700000 -#define USBH_USBCTR 0x10834 - -struct usbhsf_private { - struct clk *phy; - struct clk *usb24; - struct clk *pci; - struct clk *func; - struct clk *host; - void __iomem *usbh_base; - struct renesas_usbhs_platform_info info; -}; - -#define usbhsf_get_priv(pdev) \ - container_of(renesas_usbhs_get_info(pdev), \ - struct usbhsf_private, info) - -static int usbhsf_get_id(struct platform_device *pdev) -{ - return USBHS_GADGET; -} - -static int usbhsf_power_ctrl(struct platform_device *pdev, - void __iomem *base, int enable) -{ - struct usbhsf_private *priv = usbhsf_get_priv(pdev); - - /* - * Work around for USB Function. - * It needs USB host clock, and settings - */ - if (enable) { - /* - * enable all the related usb clocks - * for usb workaround - */ - clk_enable(priv->usb24); - clk_enable(priv->pci); - clk_enable(priv->host); - clk_enable(priv->func); - clk_enable(priv->phy); - - /* - * set USBCR1 - * - * Port1 is driven by USB function, - * Port2 is driven by USB HOST - * One HOST (Port1 or Port2 is HOST) - * USB PLL input clock = 24MHz - */ - __raw_writew(0xd750, USBCR1); - mdelay(1); - - /* - * start USB Host - */ - __raw_writel(0x0000000c, priv->usbh_base + USBH_USBCTR); - __raw_writel(0x00000008, priv->usbh_base + USBH_USBCTR); - mdelay(10); - - /* - * USB PHY Power ON - */ - __raw_writew(0xd770, USBCR1); - __raw_writew(0x4000, base + 0x102); /* USBF :: SUSPMODE */ - - } else { - __raw_writel(0x0000010f, priv->usbh_base + USBH_USBCTR); - __raw_writew(0xd7c0, USBCR1); /* GPIO */ - - clk_disable(priv->phy); - clk_disable(priv->func); /* usb work around */ - clk_disable(priv->host); /* usb work around */ - clk_disable(priv->pci); /* usb work around */ - clk_disable(priv->usb24); /* usb work around */ - } - - return 0; -} - -static int usbhsf_get_vbus(struct platform_device *pdev) -{ - return gpio_get_value(209); -} - -static irqreturn_t usbhsf_interrupt(int irq, void *data) -{ - struct platform_device *pdev = data; - - renesas_usbhs_call_notify_hotplug(pdev); - - return IRQ_HANDLED; -} - -static int usbhsf_hardware_exit(struct platform_device *pdev) -{ - struct usbhsf_private *priv = usbhsf_get_priv(pdev); - - if (!IS_ERR(priv->phy)) - clk_put(priv->phy); - if (!IS_ERR(priv->usb24)) - clk_put(priv->usb24); - if (!IS_ERR(priv->pci)) - clk_put(priv->pci); - if (!IS_ERR(priv->host)) - clk_put(priv->host); - if (!IS_ERR(priv->func)) - clk_put(priv->func); - if (priv->usbh_base) - iounmap(priv->usbh_base); - - priv->phy = NULL; - priv->usb24 = NULL; - priv->pci = NULL; - priv->host = NULL; - priv->func = NULL; - priv->usbh_base = NULL; - - free_irq(IRQ7, pdev); - - return 0; -} - -static int usbhsf_hardware_init(struct platform_device *pdev) -{ - struct usbhsf_private *priv = usbhsf_get_priv(pdev); - int ret; - - priv->phy = clk_get(&pdev->dev, "phy"); - priv->usb24 = clk_get(&pdev->dev, "usb24"); - priv->pci = clk_get(&pdev->dev, "pci"); - priv->func = clk_get(&pdev->dev, "func"); - priv->host = clk_get(&pdev->dev, "host"); - priv->usbh_base = ioremap_nocache(USBH, 0x20000); - - if (IS_ERR(priv->phy) || - IS_ERR(priv->usb24) || - IS_ERR(priv->pci) || - IS_ERR(priv->host) || - IS_ERR(priv->func) || - !priv->usbh_base) { - dev_err(&pdev->dev, "USB clock setting failed\n"); - usbhsf_hardware_exit(pdev); - return -EIO; - } - - ret = request_irq(IRQ7, usbhsf_interrupt, IRQF_TRIGGER_NONE, - dev_name(&pdev->dev), pdev); - if (ret) { - dev_err(&pdev->dev, "request_irq err\n"); - return ret; - } - irq_set_irq_type(IRQ7, IRQ_TYPE_EDGE_BOTH); - - /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */ - clk_set_rate(priv->usb24, - clk_get_rate(clk_get_parent(priv->usb24))); - - return 0; -} - -static struct usbhsf_private usbhsf_private = { - .info = { - .platform_callback = { - .get_id = usbhsf_get_id, - .get_vbus = usbhsf_get_vbus, - .hardware_init = usbhsf_hardware_init, - .hardware_exit = usbhsf_hardware_exit, - .power_ctrl = usbhsf_power_ctrl, - }, - .driver_param = { - .buswait_bwait = 5, - .detection_delay = 5, - .d0_rx_id = SHDMA_SLAVE_USBHS_RX, - .d1_tx_id = SHDMA_SLAVE_USBHS_TX, - }, - } -}; - -static struct resource usbhsf_resources[] = { - { - .name = "USBHS", - .start = 0xe6890000, - .end = 0xe6890104 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = gic_spi(51), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usbhsf_device = { - .name = "renesas_usbhs", - .dev = { - .platform_data = &usbhsf_private.info, - }, - .id = -1, - .num_resources = ARRAY_SIZE(usbhsf_resources), - .resource = usbhsf_resources, -}; - -/* Ether */ -static struct sh_eth_plat_data sh_eth_platdata = { - .phy = 0x00, /* LAN8710A */ - .edmac_endian = EDMAC_LITTLE_ENDIAN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct resource sh_eth_resources[] = { - { - .start = 0xe9a00000, - .end = 0xe9a00800 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = 0xe9a01800, - .end = 0xe9a02000 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = gic_spi(110), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sh_eth_device = { - .name = "r8a7740-gether", - .id = -1, - .dev = { - .platform_data = &sh_eth_platdata, - .dma_mask = &sh_eth_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = sh_eth_resources, - .num_resources = ARRAY_SIZE(sh_eth_resources), -}; - -/* PWM */ -static struct resource pwm_resources[] = { - [0] = { - .start = 0xe6600000, - .end = 0xe66000ff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device pwm_device = { - .name = "renesas-tpu-pwm", - .id = -1, - .num_resources = ARRAY_SIZE(pwm_resources), - .resource = pwm_resources, -}; - -static struct pwm_lookup pwm_lookup[] = { - PWM_LOOKUP("renesas-tpu-pwm", 2, "pwm-backlight.0", NULL, - 33333, PWM_POLARITY_INVERSED), -}; - -/* LCDC and backlight */ -static struct platform_pwm_backlight_data pwm_backlight_data = { - .lth_brightness = 50, - .max_brightness = 255, - .dft_brightness = 255, - .pwm_period_ns = 33333, /* 30kHz */ - .enable_gpio = 61, -}; - -static struct platform_device pwm_backlight_device = { - .name = "pwm-backlight", - .dev = { - .platform_data = &pwm_backlight_data, - }, -}; - -static struct fb_videomode lcdc0_mode = { - .name = "AMPIER/AM-800480", - .xres = 800, - .yres = 480, - .left_margin = 88, - .right_margin = 40, - .hsync_len = 128, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .sync = 0, -}; - -static struct sh_mobile_lcdc_info lcdc0_info = { - .clock_source = LCDC_CLK_BUS, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .clock_divider = 5, - .flags = 0, - .lcd_modes = &lcdc0_mode, - .num_modes = 1, - .panel_cfg = { - .width = 111, - .height = 68, - }, - }, -}; - -static struct resource lcdc0_resources[] = { - [0] = { - .name = "LCD0", - .start = 0xfe940000, - .end = 0xfe943fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(177), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc0_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc0_resources), - .resource = lcdc0_resources, - .id = 0, - .dev = { - .platform_data = &lcdc0_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* - * LCDC1/HDMI - */ -static struct sh_mobile_hdmi_info hdmi_info = { - .flags = HDMI_OUTPUT_PUSH_PULL | - HDMI_OUTPUT_POLARITY_HI | - HDMI_32BIT_REG | - HDMI_HAS_HTOP1 | - HDMI_SND_SRC_SPDIF, -}; - -static struct resource hdmi_resources[] = { - [0] = { - .name = "HDMI", - .start = 0xe6be0000, - .end = 0xe6be03ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(131), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "HDMI emma3pf", - .start = 0xe6be4000, - .end = 0xe6be43ff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device hdmi_device = { - .name = "sh-mobile-hdmi", - .num_resources = ARRAY_SIZE(hdmi_resources), - .resource = hdmi_resources, - .id = -1, - .dev = { - .platform_data = &hdmi_info, - }, -}; - -static const struct fb_videomode lcdc1_mode = { - .name = "HDMI 720p", - .xres = 1280, - .yres = 720, - .pixclock = 13468, - .left_margin = 220, - .right_margin = 110, - .hsync_len = 40, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .refresh = 60, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, -}; - -static struct sh_mobile_lcdc_info hdmi_lcdc_info = { - .clock_source = LCDC_CLK_PERIPHERAL, /* HDMI clock */ - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .clock_divider = 1, - .flags = LCDC_FLAGS_DWPOL, - .lcd_modes = &lcdc1_mode, - .num_modes = 1, - .tx_dev = &hdmi_device, - .panel_cfg = { - .width = 1280, - .height = 720, - }, - }, -}; - -static struct resource hdmi_lcdc_resources[] = { - [0] = { - .name = "LCDC1", - .start = 0xfe944000, - .end = 0xfe948000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(178), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device hdmi_lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), - .resource = hdmi_lcdc_resources, - .id = 1, - .dev = { - .platform_data = &hdmi_lcdc_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* LEDS */ -static struct gpio_led gpio_leds[] = { - { - .name = "LED3", - .gpio = 102, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "LED4", - .gpio = 111, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "LED5", - .gpio = 110, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "LED6", - .gpio = 177, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, -}; - -static struct gpio_led_platform_data leds_gpio_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &leds_gpio_info, - }, -}; - -/* GPIO KEY */ -#define GPIO_KEY(c, g, d, ...) \ - { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } - -static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1), - GPIO_KEY(KEY_BACK, 100, "SW4"), - GPIO_KEY(KEY_MENU, 97, "SW5"), - GPIO_KEY(KEY_HOME, 98, "SW6"), -}; - -static struct gpio_keys_platform_data gpio_key_info = { - .buttons = gpio_buttons, - .nbuttons = ARRAY_SIZE(gpio_buttons), -}; - -static struct platform_device gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &gpio_key_info, - }, -}; - -/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */ -static struct regulator_consumer_supply fixed3v3_power_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sh_mmcif"), - REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), -}; - -/* Fixed 3.3V regulator used by LCD backlight */ -static struct regulator_consumer_supply fixed5v0_power_consumers[] = { - REGULATOR_SUPPLY("power", "pwm-backlight.0"), -}; - -/* Fixed 3.3V regulator to be used by SDHI0 */ -static struct regulator_consumer_supply vcc_sdhi0_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_init_data vcc_sdhi0_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), - .consumer_supplies = vcc_sdhi0_consumers, -}; - -static struct fixed_voltage_config vcc_sdhi0_info = { - .supply_name = "SDHI0 Vcc", - .microvolts = 3300000, - .gpio = 75, - .enable_high = 1, - .init_data = &vcc_sdhi0_init_data, -}; - -static struct platform_device vcc_sdhi0 = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &vcc_sdhi0_info, - }, -}; - -/* 1.8 / 3.3V SDHI0 VccQ regulator */ -static struct regulator_consumer_supply vccq_sdhi0_consumers[] = { - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_init_data vccq_sdhi0_init_data = { - .constraints = { - .input_uV = 3300000, - .min_uV = 1800000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers), - .consumer_supplies = vccq_sdhi0_consumers, -}; - -static struct gpio vccq_sdhi0_gpios[] = { - {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, -}; - -static struct gpio_regulator_state vccq_sdhi0_states[] = { - { .value = 3300000, .gpios = (0 << 0) }, - { .value = 1800000, .gpios = (1 << 0) }, -}; - -static struct gpio_regulator_config vccq_sdhi0_info = { - .supply_name = "vqmmc", - - .enable_gpio = 74, - .enable_high = 1, - .enabled_at_boot = 0, - - .gpios = vccq_sdhi0_gpios, - .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios), - - .states = vccq_sdhi0_states, - .nr_states = ARRAY_SIZE(vccq_sdhi0_states), - - .type = REGULATOR_VOLTAGE, - .init_data = &vccq_sdhi0_init_data, -}; - -static struct platform_device vccq_sdhi0 = { - .name = "gpio-regulator", - .id = -1, - .dev = { - .platform_data = &vccq_sdhi0_info, - }, -}; - -/* Fixed 3.3V regulator to be used by SDHI1 */ -static struct regulator_consumer_supply vcc_sdhi1_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), -}; - -static struct regulator_init_data vcc_sdhi1_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers), - .consumer_supplies = vcc_sdhi1_consumers, -}; - -static struct fixed_voltage_config vcc_sdhi1_info = { - .supply_name = "SDHI1 Vcc", - .microvolts = 3300000, - .gpio = 16, - .enable_high = 1, - .init_data = &vcc_sdhi1_init_data, -}; - -static struct platform_device vcc_sdhi1 = { - .name = "reg-fixed-voltage", - .id = 2, - .dev = { - .platform_data = &vcc_sdhi1_info, - }, -}; - -/* SDHI0 */ -static struct tmio_mmc_data sdhi0_info = { - .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX, - .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_POWER_OFF_CARD, - .flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, - .cd_gpio = 167, -}; - -static struct resource sdhi0_resources[] = { - { - .name = "SDHI0", - .start = 0xe6850000, - .end = 0xe6850100 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * no SH_MOBILE_SDHI_IRQ_CARD_DETECT here - */ - { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = gic_spi(118), - .flags = IORESOURCE_IRQ, - }, - { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = gic_spi(119), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .id = 0, - .dev = { - .platform_data = &sdhi0_info, - }, - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, -}; - -/* SDHI1 */ -static struct tmio_mmc_data sdhi1_info = { - .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX, - .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_POWER_OFF_CARD, - .flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, - /* Port72 cannot generate IRQs, will be used in polling mode. */ - .cd_gpio = 72, -}; - -static struct resource sdhi1_resources[] = { - [0] = { - .name = "SDHI1", - .start = 0xe6860000, - .end = 0xe6860100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(121), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = gic_spi(122), - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = gic_spi(123), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi1_device = { - .name = "sh_mobile_sdhi", - .id = 1, - .dev = { - .platform_data = &sdhi1_info, - }, - .num_resources = ARRAY_SIZE(sdhi1_resources), - .resource = sdhi1_resources, -}; - -static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = { - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_ctrl", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_cd", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_wp", "sdhi1"), -}; - -/* MMCIF */ -static struct sh_mmcif_plat_data sh_mmcif_plat = { - .sup_pclk = 0, - .caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_NONREMOVABLE, - .ccs_unsupported = true, - .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, -}; - -static struct resource sh_mmcif_resources[] = { - [0] = { - .name = "MMCIF", - .start = 0xe6bd0000, - .end = 0xe6bd0100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* MMC ERR */ - .start = gic_spi(56), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* MMC NOR */ - .start = gic_spi(57), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sh_mmcif_device = { - .name = "sh_mmcif", - .id = -1, - .dev = { - .platform_data = &sh_mmcif_plat, - }, - .num_resources = ARRAY_SIZE(sh_mmcif_resources), - .resource = sh_mmcif_resources, -}; - -/* Camera */ -static int mt9t111_power(struct device *dev, int mode) -{ - struct clk *mclk = clk_get(NULL, "video1"); - - if (IS_ERR(mclk)) { - dev_err(dev, "can't get video1 clock\n"); - return -EINVAL; - } - - if (mode) { - /* video1 (= CON1 camera) expect 24MHz */ - clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); - clk_enable(mclk); - gpio_set_value(158, 1); - } else { - gpio_set_value(158, 0); - clk_disable(mclk); - } - - clk_put(mclk); - - return 0; -} - -static struct i2c_board_info i2c_camera_mt9t111 = { - I2C_BOARD_INFO("mt9t112", 0x3d), -}; - -static struct mt9t112_camera_info mt9t111_info = { - .divider = { 16, 0, 0, 7, 0, 10, 14, 7, 7 }, -}; - -static struct soc_camera_link mt9t111_link = { - .i2c_adapter_id = 0, - .bus_id = 0, - .board_info = &i2c_camera_mt9t111, - .power = mt9t111_power, - .priv = &mt9t111_info, -}; - -static struct platform_device camera_device = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &mt9t111_link, - }, -}; - -/* CEU0 */ -static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { - .flags = SH_CEU_FLAG_LOWER_8BIT, -}; - -static struct resource ceu0_resources[] = { - [0] = { - .name = "CEU", - .start = 0xfe910000, - .end = 0xfe91009f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(160), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* place holder for contiguous memory */ - }, -}; - -static struct platform_device ceu0_device = { - .name = "sh_mobile_ceu", - .id = 0, - .num_resources = ARRAY_SIZE(ceu0_resources), - .resource = ceu0_resources, - .dev = { - .platform_data = &sh_mobile_ceu0_info, - .coherent_dma_mask = 0xffffffff, - }, -}; - -/* FSI */ -static struct sh_fsi_platform_info fsi_info = { - /* FSI-WM8978 */ - .port_a = { - .tx_id = SHDMA_SLAVE_FSIA_TX, - }, - /* FSI-HDMI */ - .port_b = { - .flags = SH_FSI_FMT_SPDIF | - SH_FSI_ENABLE_STREAM_MODE | - SH_FSI_CLK_CPG, - .tx_id = SHDMA_SLAVE_FSIB_TX, - } -}; - -static struct resource fsi_resources[] = { - [0] = { - .name = "FSI", - .start = 0xfe1f0000, - .end = 0xfe1f0400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(9), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device fsi_device = { - .name = "sh_fsi2", - .id = -1, - .num_resources = ARRAY_SIZE(fsi_resources), - .resource = fsi_resources, - .dev = { - .platform_data = &fsi_info, - }, -}; - -/* FSI-WM8978 */ -static struct asoc_simple_card_info fsi_wm8978_info = { - .name = "wm8978", - .card = "FSI2A-WM8978", - .codec = "wm8978.0-001a", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, - .cpu_dai = { - .name = "fsia-dai", - }, - .codec_dai = { - .name = "wm8978-hifi", - .sysclk = 12288000, - }, -}; - -static struct platform_device fsi_wm8978_device = { - .name = "asoc-simple-card", - .id = 0, - .dev = { - .platform_data = &fsi_wm8978_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &fsi_wm8978_device.dev.coherent_dma_mask, - }, -}; - -/* FSI-HDMI */ -static struct asoc_simple_card_info fsi2_hdmi_info = { - .name = "HDMI", - .card = "FSI2B-HDMI", - .codec = "sh-mobile-hdmi", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_CBS_CFS, - .cpu_dai = { - .name = "fsib-dai", - }, - .codec_dai = { - .name = "sh_mobile_hdmi-hifi", - }, -}; - -static struct platform_device fsi_hdmi_device = { - .name = "asoc-simple-card", - .id = 1, - .dev = { - .platform_data = &fsi2_hdmi_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &fsi_hdmi_device.dev.coherent_dma_mask, - }, -}; - -/* RTC: RTC connects i2c-gpio. */ -static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 208, - .scl_pin = 91, - .udelay = 5, /* 100 kHz */ -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 2, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; - -/* I2C */ -static struct st1232_pdata st1232_i2c0_pdata = { - .reset_gpio = 166, -}; - -static struct i2c_board_info i2c0_devices[] = { - { - I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = irq_pin(10), - .platform_data = &st1232_i2c0_pdata, - }, - { - I2C_BOARD_INFO("wm8978", 0x1a), - }, -}; - -static struct i2c_board_info i2c2_devices[] = { - { - I2C_BOARD_INFO("s35390a", 0x30), - .type = "s35390a", - }, -}; - -/* - * board devices - */ -static struct platform_device *eva_devices[] __initdata = { - &lcdc0_device, - &pwm_device, - &pwm_backlight_device, - &leds_gpio_device, - &gpio_keys_device, - &sh_eth_device, - &vcc_sdhi0, - &vccq_sdhi0, - &sdhi0_device, - &sh_mmcif_device, - &hdmi_device, - &hdmi_lcdc_device, - &camera_device, - &ceu0_device, - &fsi_device, - &fsi_wm8978_device, - &fsi_hdmi_device, - &i2c_gpio_device, -}; - -static const struct pinctrl_map eva_pinctrl_map[] = { - /* CEU0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", - "ceu0_data_0_7", "ceu0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", - "ceu0_clk_0", "ceu0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", - "ceu0_sync", "ceu0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", - "ceu0_field", "ceu0"), - /* FSIA */ - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", - "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", - "fsia_mclk_out", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", - "fsia_data_in_1", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", - "fsia_data_out_0", "fsia"), - /* FSIB */ - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", - "fsib_mclk_in", "fsib"), - /* GETHER */ - PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", - "gether_mii", "gether"), - PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740", - "gether_int", "gether"), - /* HDMI */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", - "hdmi", "hdmi"), - /* LCD0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_data24_0", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_lclk_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_sync", "lcd0"), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", - "mmc0_data8_1", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", - "mmc0_ctrl_1", "mmc0"), - /* SCIFA1 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", - "scifa1_data", "scifa1"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_wp", "sdhi0"), - /* ST1232 */ - PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", - "intc_irq10", "intc"), - /* TPU0 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm", "pfc-r8a7740", - "tpu0_to2_1", "tpu0"), - /* USBHS */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", - "intc_irq7_1", "intc"), -}; - -static void __init eva_clock_init(void) -{ - struct clk *system = clk_get(NULL, "system_clk"); - struct clk *xtal1 = clk_get(NULL, "extal1"); - struct clk *usb24s = clk_get(NULL, "usb24s"); - struct clk *fsibck = clk_get(NULL, "fsibck"); - - if (IS_ERR(system) || - IS_ERR(xtal1) || - IS_ERR(usb24s) || - IS_ERR(fsibck)) { - pr_err("armadillo800eva board clock init failed\n"); - goto clock_error; - } - - /* armadillo 800 eva extal1 is 24MHz */ - clk_set_rate(xtal1, 24000000); - - /* usb24s use extal1 (= system) clock (= 24MHz) */ - clk_set_parent(usb24s, system); - - /* FSIBCK is 12.288MHz, and it is parent of FSI-B */ - clk_set_rate(fsibck, 12288000); - -clock_error: - if (!IS_ERR(system)) - clk_put(system); - if (!IS_ERR(xtal1)) - clk_put(xtal1); - if (!IS_ERR(usb24s)) - clk_put(usb24s); - if (!IS_ERR(fsibck)) - clk_put(fsibck); -} - -/* - * board init - */ -#define GPIO_PORT7CR IOMEM(0xe6050007) -#define GPIO_PORT8CR IOMEM(0xe6050008) -static void __init eva_init(void) -{ - static struct pm_domain_device domain_devices[] __initdata = { - { "A4LC", &lcdc0_device }, - { "A4LC", &hdmi_lcdc_device }, - { "A4MP", &hdmi_device }, - { "A4MP", &fsi_device }, - { "A4R", &ceu0_device }, - { "A4S", &sh_eth_device }, - { "A3SP", &pwm_device }, - { "A3SP", &sdhi0_device }, - { "A3SP", &sh_mmcif_device }, - }; - struct platform_device *usb = NULL, *sdhi1 = NULL; - - regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - regulator_register_always_on(3, "fixed-5.0V", fixed5v0_power_consumers, - ARRAY_SIZE(fixed5v0_power_consumers), 5000000); - - pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); - pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup)); - - r8a7740_pinmux_init(); - r8a7740_meram_workaround(); - - /* GETHER */ - gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ - - /* USB */ - gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ - - if (gpio_get_value(159)) { - /* USB Host */ - } else { - /* USB Func */ - /* - * The USBHS interrupt handlers needs to read the IRQ pin value - * (HI/LOW) to diffentiate USB connection and disconnection - * events (usbhsf_get_vbus()). We thus need to select both the - * intc_irq7_1 pin group and GPIO 209 here. - */ - gpio_request_one(209, GPIOF_IN, NULL); - - platform_device_register(&usbhsf_device); - usb = &usbhsf_device; - } - - /* CON1/CON15 Camera */ - gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ - gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ - /* see mt9t111_power() */ - gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ - - /* FSI-WM8978 */ - gpio_request(7, NULL); - gpio_request(8, NULL); - gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ - gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ - - /* - * CAUTION - * - * DBGMD/LCDC0/FSIA MUX - * DBGMD_SELECT_B should be set after setting PFC Function. - */ - gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL); - - /* - * We can switch CON8/CON14 by SW1.5, - * but it needs after DBGMD_SELECT_B - */ - gpio_request_one(6, GPIOF_IN, NULL); - if (gpio_get_value(6)) { - /* CON14 enable */ - } else { - /* CON8 (SDHI1) enable */ - pinctrl_register_mappings(eva_sdhi1_pinctrl_map, - ARRAY_SIZE(eva_sdhi1_pinctrl_map)); - - platform_device_register(&vcc_sdhi1); - platform_device_register(&sdhi1_device); - sdhi1 = &sdhi1_device; - } - - -#ifdef CONFIG_CACHE_L2X0 - /* Shared attribute override enable, 32K*8way */ - l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); -#endif - - i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); - i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices)); - - r8a7740_add_standard_devices(); - - platform_add_devices(eva_devices, - ARRAY_SIZE(eva_devices)); - - rmobile_add_devices_to_domains(domain_devices, - ARRAY_SIZE(domain_devices)); - if (usb) - rmobile_add_device_to_domain("A3SP", usb); - if (sdhi1) - rmobile_add_device_to_domain("A3SP", sdhi1); - - r8a7740_pm_init(); -} - -static void __init eva_earlytimer_init(void) -{ - r8a7740_clock_init(MD_CK0 | MD_CK2); - shmobile_earlytimer_init(); - - /* the rate of extal1 clock must be set before late_time_init */ - eva_clock_init(); -} - -#define RESCNT2 IOMEM(0xe6188020) -static void eva_restart(enum reboot_mode mode, const char *cmd) -{ - /* Do soft power on reset */ - writel((1 << 31), RESCNT2); -} - -static const char *eva_boards_compat_dt[] __initdata = { - "renesas,armadillo800eva", - NULL, -}; - -DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") - .map_io = r8a7740_map_io, - .init_early = r8a7740_add_early_devices, - .init_irq = r8a7740_init_irq_of, - .init_machine = eva_init, - .init_late = shmobile_init_late, - .init_time = eva_earlytimer_init, - .dt_compat = eva_boards_compat_dt, - .restart = eva_restart, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index 9a74efda3d18..4f78296f7d04 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -72,7 +72,7 @@ static void __init bockw_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char *bockw_boards_compat_dt[] __initdata = { +static const char *const bockw_boards_compat_dt[] __initconst = { "renesas,bockw-reference", NULL, }; diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 25558d1f417f..25a0e7233fe4 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -723,7 +723,7 @@ static void __init bockw_init_late(void) ADD_USB_FUNC_DEVICE_IF_POSSIBLE(); } -static const char *bockw_boards_compat_dt[] __initdata = { +static const char *const bockw_boards_compat_dt[] __initconst = { "renesas,bockw", NULL, }; diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c deleted file mode 100644 index 260d8319fd82..000000000000 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ /dev/null @@ -1,916 +0,0 @@ -/* - * KZM-A9-GT board support - * - * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/i2c/pcf857x.h> -#include <linux/input.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mmcif.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/mfd/as3711.h> -#include <linux/mfd/tmio.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_device.h> -#include <linux/reboot.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <linux/usb/r8a66597.h> -#include <linux/usb/renesas_usbhs.h> -#include <linux/videodev2.h> - -#include <sound/sh_fsi.h> -#include <sound/simple_card.h> -#include <asm/hardware/cache-l2x0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <video/sh_mobile_lcdc.h> - -#include "common.h" -#include "intc.h" -#include "irqs.h" -#include "sh73a0.h" - -/* - * external GPIO - */ -#define GPIO_PCF8575_BASE (310) -#define GPIO_PCF8575_PORT10 (GPIO_PCF8575_BASE + 8) -#define GPIO_PCF8575_PORT11 (GPIO_PCF8575_BASE + 9) -#define GPIO_PCF8575_PORT12 (GPIO_PCF8575_BASE + 10) -#define GPIO_PCF8575_PORT13 (GPIO_PCF8575_BASE + 11) -#define GPIO_PCF8575_PORT14 (GPIO_PCF8575_BASE + 12) -#define GPIO_PCF8575_PORT15 (GPIO_PCF8575_BASE + 13) -#define GPIO_PCF8575_PORT16 (GPIO_PCF8575_BASE + 14) - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x.0"), - REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), -}; - -/* - * FSI-AK4648 - * - * this command is required when playback. - * - * # amixer set "LINEOUT Mixer DACL" on - */ - -/* SMSC 9221 */ -static struct resource smsc9221_resources[] = { - [0] = { - .start = 0x10000000, /* CS4 */ - .end = 0x100000ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = irq_pin(3), /* IRQ3 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc9221_platdata = { - .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device smsc_device = { - .name = "smsc911x", - .dev = { - .platform_data = &smsc9221_platdata, - }, - .resource = smsc9221_resources, - .num_resources = ARRAY_SIZE(smsc9221_resources), -}; - -/* USB external chip */ -static struct r8a66597_platdata usb_host_data = { - .on_chip = 0, - .xtal = R8A66597_PLATDATA_XTAL_48MHZ, -}; - -static struct resource usb_resources[] = { - [0] = { - .start = 0x10010000, - .end = 0x1001ffff - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = irq_pin(1), /* IRQ1 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usb_host_device = { - .name = "r8a66597_hcd", - .dev = { - .platform_data = &usb_host_data, - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(usb_resources), - .resource = usb_resources, -}; - -/* USB Func CN17 */ -struct usbhs_private { - void __iomem *phy; - void __iomem *cr2; - struct renesas_usbhs_platform_info info; -}; - -#define IRQ15 irq_pin(15) -#define USB_PHY_MODE (1 << 4) -#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) -#define USB_PHY_ON (1 << 1) -#define USB_PHY_OFF (1 << 0) -#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF) - -#define usbhs_get_priv(pdev) \ - container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info) - -static int usbhs_get_vbus(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - return !((1 << 7) & __raw_readw(priv->cr2)); -} - -static int usbhs_phy_reset(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - /* init phy */ - __raw_writew(0x8a0a, priv->cr2); - - return 0; -} - -static int usbhs_get_id(struct platform_device *pdev) -{ - return USBHS_GADGET; -} - -static irqreturn_t usbhs_interrupt(int irq, void *data) -{ - struct platform_device *pdev = data; - struct usbhs_private *priv = usbhs_get_priv(pdev); - - renesas_usbhs_call_notify_hotplug(pdev); - - /* clear status */ - __raw_writew(__raw_readw(priv->phy) | USB_PHY_INT_CLR, priv->phy); - - return IRQ_HANDLED; -} - -static int usbhs_hardware_init(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - int ret; - - /* clear interrupt status */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy); - - ret = request_irq(IRQ15, usbhs_interrupt, IRQF_TRIGGER_HIGH, - dev_name(&pdev->dev), pdev); - if (ret) { - dev_err(&pdev->dev, "request_irq err\n"); - return ret; - } - - /* enable USB phy interrupt */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->phy); - - return 0; -} - -static int usbhs_hardware_exit(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - /* clear interrupt status */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy); - - free_irq(IRQ15, pdev); - - return 0; -} - -static u32 usbhs_pipe_cfg[] = { - USB_ENDPOINT_XFER_CONTROL, - USB_ENDPOINT_XFER_ISOC, - USB_ENDPOINT_XFER_ISOC, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, -}; - -static struct usbhs_private usbhs_private = { - .phy = IOMEM(0xe60781e0), /* USBPHYINT */ - .cr2 = IOMEM(0xe605810c), /* USBCR2 */ - .info = { - .platform_callback = { - .hardware_init = usbhs_hardware_init, - .hardware_exit = usbhs_hardware_exit, - .get_id = usbhs_get_id, - .phy_reset = usbhs_phy_reset, - .get_vbus = usbhs_get_vbus, - }, - .driver_param = { - .buswait_bwait = 4, - .has_otg = 1, - .pipe_type = usbhs_pipe_cfg, - .pipe_size = ARRAY_SIZE(usbhs_pipe_cfg), - }, - }, -}; - -static struct resource usbhs_resources[] = { - [0] = { - .start = 0xE6890000, - .end = 0xE68900e6 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(62), - .end = gic_spi(62), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usbhs_device = { - .name = "renesas_usbhs", - .id = -1, - .dev = { - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - .platform_data = &usbhs_private.info, - }, - .num_resources = ARRAY_SIZE(usbhs_resources), - .resource = usbhs_resources, -}; - -/* LCDC */ -static struct fb_videomode kzm_lcdc_mode = { - .name = "WVGA Panel", - .xres = 800, - .yres = 480, - .left_margin = 220, - .right_margin = 110, - .hsync_len = 70, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .sync = 0, -}; - -static struct sh_mobile_lcdc_info lcdc_info = { - .clock_source = LCDC_CLK_BUS, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .lcd_modes = &kzm_lcdc_mode, - .num_modes = 1, - .clock_divider = 5, - .flags = 0, - .panel_cfg = { - .width = 152, - .height = 91, - }, - } -}; - -static struct resource lcdc_resources[] = { - [0] = { - .name = "LCDC", - .start = 0xfe940000, - .end = 0xfe943fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x580), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc_resources), - .resource = lcdc_resources, - .dev = { - .platform_data = &lcdc_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* Fixed 1.8V regulator to be used by MMCIF */ -static struct regulator_consumer_supply fixed1v8_power_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), -}; - -/* MMCIF */ -static struct resource sh_mmcif_resources[] = { - [0] = { - .name = "MMCIF", - .start = 0xe6bd0000, - .end = 0xe6bd00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(140), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = gic_spi(141), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct sh_mmcif_plat_data sh_mmcif_platdata = { - .ocr = MMC_VDD_165_195, - .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .ccs_unsupported = true, - .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, -}; - -static struct platform_device mmc_device = { - .name = "sh_mmcif", - .dev = { - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - .platform_data = &sh_mmcif_platdata, - }, - .num_resources = ARRAY_SIZE(sh_mmcif_resources), - .resource = sh_mmcif_resources, -}; - -/* Fixed 3.3V regulators to be used by SDHI0 */ -static struct regulator_consumer_supply vcc_sdhi0_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_init_data vcc_sdhi0_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), - .consumer_supplies = vcc_sdhi0_consumers, -}; - -static struct fixed_voltage_config vcc_sdhi0_info = { - .supply_name = "SDHI0 Vcc", - .microvolts = 3300000, - .gpio = 15, - .enable_high = 1, - .init_data = &vcc_sdhi0_init_data, -}; - -static struct platform_device vcc_sdhi0 = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &vcc_sdhi0_info, - }, -}; - -/* Fixed 3.3V regulators to be used by SDHI2 */ -static struct regulator_consumer_supply vcc_sdhi2_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"), -}; - -static struct regulator_init_data vcc_sdhi2_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers), - .consumer_supplies = vcc_sdhi2_consumers, -}; - -static struct fixed_voltage_config vcc_sdhi2_info = { - .supply_name = "SDHI2 Vcc", - .microvolts = 3300000, - .gpio = 14, - .enable_high = 1, - .init_data = &vcc_sdhi2_init_data, -}; - -static struct platform_device vcc_sdhi2 = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &vcc_sdhi2_info, - }, -}; - -/* SDHI */ -static struct tmio_mmc_data sdhi0_info = { - .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX, - .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX, - .flags = TMIO_MMC_HAS_IDLE_WAIT, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_POWER_OFF_CARD, -}; - -static struct resource sdhi0_resources[] = { - [0] = { - .name = "SDHI0", - .start = 0xee100000, - .end = 0xee1000ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = gic_spi(83), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = gic_spi(84), - .flags = IORESOURCE_IRQ, - }, - [3] = { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = gic_spi(85), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, - .dev = { - .platform_data = &sdhi0_info, - }, -}; - -/* Micro SD */ -static struct tmio_mmc_data sdhi2_info = { - .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI2_TX, - .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI2_RX, - .flags = TMIO_MMC_HAS_IDLE_WAIT | - TMIO_MMC_USE_GPIO_CD | - TMIO_MMC_WRPROTECT_DISABLE, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD, - .cd_gpio = 13, -}; - -static struct resource sdhi2_resources[] = { - [0] = { - .name = "SDHI2", - .start = 0xee140000, - .end = 0xee1400ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, - .start = gic_spi(103), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = gic_spi(104), - .flags = IORESOURCE_IRQ, - }, - [3] = { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = gic_spi(105), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi2_device = { - .name = "sh_mobile_sdhi", - .id = 2, - .num_resources = ARRAY_SIZE(sdhi2_resources), - .resource = sdhi2_resources, - .dev = { - .platform_data = &sdhi2_info, - }, -}; - -/* KEY */ -#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } - -static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_BACK, GPIO_PCF8575_PORT10, "SW3"), - GPIO_KEY(KEY_RIGHT, GPIO_PCF8575_PORT11, "SW2-R"), - GPIO_KEY(KEY_LEFT, GPIO_PCF8575_PORT12, "SW2-L"), - GPIO_KEY(KEY_ENTER, GPIO_PCF8575_PORT13, "SW2-P"), - GPIO_KEY(KEY_UP, GPIO_PCF8575_PORT14, "SW2-U"), - GPIO_KEY(KEY_DOWN, GPIO_PCF8575_PORT15, "SW2-D"), - GPIO_KEY(KEY_HOME, GPIO_PCF8575_PORT16, "SW1"), -}; - -static struct gpio_keys_platform_data gpio_key_info = { - .buttons = gpio_buttons, - .nbuttons = ARRAY_SIZE(gpio_buttons), -}; - -static struct platform_device gpio_keys_device = { - .name = "gpio-keys", - .dev = { - .platform_data = &gpio_key_info, - }, -}; - -/* FSI-AK4648 */ -static struct sh_fsi_platform_info fsi_info = { - .port_a = { - .tx_id = SHDMA_SLAVE_FSI2A_TX, - }, -}; - -static struct resource fsi_resources[] = { - [0] = { - .name = "FSI", - .start = 0xEC230000, - .end = 0xEC230400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(146), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device fsi_device = { - .name = "sh_fsi2", - .id = -1, - .num_resources = ARRAY_SIZE(fsi_resources), - .resource = fsi_resources, - .dev = { - .platform_data = &fsi_info, - }, -}; - -static struct asoc_simple_card_info fsi2_ak4648_info = { - .name = "AK4648", - .card = "FSI2A-AK4648", - .codec = "ak4642-codec.0-0012", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM, - .cpu_dai = { - .name = "fsia-dai", - }, - .codec_dai = { - .name = "ak4642-hifi", - .sysclk = 11289600, - }, -}; - -static struct platform_device fsi_ak4648_device = { - .name = "asoc-simple-card", - .dev = { - .platform_data = &fsi2_ak4648_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &fsi_ak4648_device.dev.coherent_dma_mask, - }, -}; - -/* I2C */ - -/* StepDown1 is used to supply 1.315V to the CPU */ -static struct regulator_init_data as3711_sd1 = { - .constraints = { - .name = "1.315V CPU", - .boot_on = 1, - .always_on = 1, - .min_uV = 1315000, - .max_uV = 1335000, - }, -}; - -/* StepDown2 is used to supply 1.8V to the CPU and to the board */ -static struct regulator_init_data as3711_sd2 = { - .constraints = { - .name = "1.8V", - .boot_on = 1, - .always_on = 1, - .min_uV = 1800000, - .max_uV = 1800000, - }, -}; - -/* - * StepDown3 is switched in parallel with StepDown2, seems to be off, - * according to read-back pre-set register values - */ - -/* StepDown4 is used to supply 1.215V to the CPU and to the board */ -static struct regulator_init_data as3711_sd4 = { - .constraints = { - .name = "1.215V", - .boot_on = 1, - .always_on = 1, - .min_uV = 1215000, - .max_uV = 1235000, - }, -}; - -/* LDO1 is unused and unconnected */ - -/* LDO2 is used to supply 2.8V to the CPU */ -static struct regulator_init_data as3711_ldo2 = { - .constraints = { - .name = "2.8V CPU", - .boot_on = 1, - .always_on = 1, - .min_uV = 2800000, - .max_uV = 2800000, - }, -}; - -/* LDO3 is used to supply 3.0V to the CPU */ -static struct regulator_init_data as3711_ldo3 = { - .constraints = { - .name = "3.0V CPU", - .boot_on = 1, - .always_on = 1, - .min_uV = 3000000, - .max_uV = 3000000, - }, -}; - -/* LDO4 is used to supply 2.8V to the board */ -static struct regulator_init_data as3711_ldo4 = { - .constraints = { - .name = "2.8V", - .boot_on = 1, - .always_on = 1, - .min_uV = 2800000, - .max_uV = 2800000, - }, -}; - -/* LDO5 is switched parallel to LDO4, also set to 2.8V */ -static struct regulator_init_data as3711_ldo5 = { - .constraints = { - .name = "2.8V #2", - .boot_on = 1, - .always_on = 1, - .min_uV = 2800000, - .max_uV = 2800000, - }, -}; - -/* LDO6 is unused and unconnected */ - -/* LDO7 is used to supply 1.15V to the CPU */ -static struct regulator_init_data as3711_ldo7 = { - .constraints = { - .name = "1.15V CPU", - .boot_on = 1, - .always_on = 1, - .min_uV = 1150000, - .max_uV = 1150000, - }, -}; - -/* LDO8 is switched parallel to LDO7, also set to 1.15V */ -static struct regulator_init_data as3711_ldo8 = { - .constraints = { - .name = "1.15V CPU #2", - .boot_on = 1, - .always_on = 1, - .min_uV = 1150000, - .max_uV = 1150000, - }, -}; - -static struct as3711_platform_data as3711_pdata = { - .regulator = { - .init_data = { - [AS3711_REGULATOR_SD_1] = &as3711_sd1, - [AS3711_REGULATOR_SD_2] = &as3711_sd2, - [AS3711_REGULATOR_SD_4] = &as3711_sd4, - [AS3711_REGULATOR_LDO_2] = &as3711_ldo2, - [AS3711_REGULATOR_LDO_3] = &as3711_ldo3, - [AS3711_REGULATOR_LDO_4] = &as3711_ldo4, - [AS3711_REGULATOR_LDO_5] = &as3711_ldo5, - [AS3711_REGULATOR_LDO_7] = &as3711_ldo7, - [AS3711_REGULATOR_LDO_8] = &as3711_ldo8, - }, - }, - .backlight = { - .su2_fb = "sh_mobile_lcdc_fb.0", - .su2_max_uA = 36000, - .su2_feedback = AS3711_SU2_CURR_AUTO, - .su2_fbprot = AS3711_SU2_GPIO4, - .su2_auto_curr1 = true, - .su2_auto_curr2 = true, - .su2_auto_curr3 = true, - }, -}; - -static struct pcf857x_platform_data pcf8575_pdata = { - .gpio_base = GPIO_PCF8575_BASE, -}; - -static struct i2c_board_info i2c0_devices[] = { - { - I2C_BOARD_INFO("ak4648", 0x12), - }, - { - I2C_BOARD_INFO("r2025sd", 0x32), - }, - { - I2C_BOARD_INFO("ak8975", 0x0c), - .irq = irq_pin(28), /* IRQ28 */ - }, - { - I2C_BOARD_INFO("adxl34x", 0x1d), - .irq = irq_pin(26), /* IRQ26 */ - }, - { - I2C_BOARD_INFO("as3711", 0x40), - .irq = intcs_evt2irq(0x3300), /* IRQ24 */ - .platform_data = &as3711_pdata, - }, -}; - -static struct i2c_board_info i2c1_devices[] = { - { - I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = irq_pin(8), /* IRQ8 */ - }, -}; - -static struct i2c_board_info i2c3_devices[] = { - { - I2C_BOARD_INFO("pcf8575", 0x20), - .irq = irq_pin(19), /* IRQ19 */ - .platform_data = &pcf8575_pdata, - }, -}; - -static struct platform_device *kzm_devices[] __initdata = { - &smsc_device, - &usb_host_device, - &usbhs_device, - &lcdc_device, - &mmc_device, - &vcc_sdhi0, - &vcc_sdhi2, - &sdhi0_device, - &sdhi2_device, - &gpio_keys_device, - &fsi_device, - &fsi_ak4648_device, -}; - -static unsigned long pin_pullup_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), -}; - -static const struct pinctrl_map kzm_pinctrl_map[] = { - /* FSIA (AK4648) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", - "fsia_mclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", - "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", - "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", - "fsia_data_out", "fsia"), - /* I2C3 */ - PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", - "i2c3_1", "i2c3"), - /* LCD */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", - "lcd_data24", "lcd"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", - "lcd_sync", "lcd"), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", pin_pullup_conf), - /* SCIFA4 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_data", "scifa4"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_ctrl", "scifa4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_wp", "sdhi0"), - /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", - "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", - "sdhi2_ctrl", "sdhi2"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_cs4", "bsc"), - /* USB */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0", - "usb_vbus", "usb"), -}; - -static void __init kzm_init(void) -{ - regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers, - ARRAY_SIZE(fixed1v8_power_consumers), 1800000); - regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); - - sh73a0_pinmux_init(); - - /* SMSC */ - gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ - - /* LCDC */ - gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ - gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ - - /* Touchscreen */ - gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ - -#ifdef CONFIG_CACHE_L2X0 - /* Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); -#endif - - i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); - i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices)); - i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices)); - - sh73a0_add_standard_devices(); - platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices)); - - sh73a0_pm_init(); -} - -static void kzm9g_restart(enum reboot_mode mode, const char *cmd) -{ -#define RESCNT2 IOMEM(0xe6188020) - /* Do soft power on reset */ - writel((1 << 31), RESCNT2); -} - -static const char *kzm9g_boards_compat_dt[] __initdata = { - "renesas,kzm9g", - NULL, -}; - -DT_MACHINE_START(KZM9G_DT, "kzm9g") - .smp = smp_ops(sh73a0_smp_ops), - .map_io = sh73a0_map_io, - .init_early = sh73a0_add_early_devices, - .init_irq = sh73a0_init_irq, - .init_machine = kzm_init, - .init_late = shmobile_init_late, - .init_time = sh73a0_earlytimer_init, - .restart = kzm9g_restart, - .dt_compat = kzm9g_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c deleted file mode 100644 index b15eb923263f..000000000000 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * marzen board support - Reference DT implementation - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Magnus Damm - * Copyright (C) 2013 Simon Horman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/clk/shmobile.h> -#include <linux/clocksource.h> -#include <linux/of_platform.h> - -#include <asm/irq.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "irqs.h" -#include "r8a7779.h" - -static void __init marzen_init_timer(void) -{ - r8a7779_clocks_init(r8a7779_read_mode_pins()); - clocksource_of_init(); -} - -static void __init marzen_init(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ -} - -static const char *marzen_boards_compat_dt[] __initdata = { - "renesas,marzen", - "renesas,marzen-reference", - NULL, -}; - -DT_MACHINE_START(MARZEN, "marzen") - .smp = smp_ops(r8a7779_smp_ops), - .map_io = r8a7779_map_io, - .init_early = shmobile_init_delay, - .init_time = marzen_init_timer, - .init_irq = r8a7779_init_irq_dt, - .init_machine = marzen_init, - .init_late = shmobile_init_late, - .dt_compat = marzen_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c deleted file mode 100644 index 51db288f192a..000000000000 --- a/arch/arm/mach-shmobile/board-marzen.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * marzen board support - * - * Copyright (C) 2011, 2013 Renesas Solutions Corp. - * Copyright (C) 2011 Magnus Damm - * Copyright (C) 2013 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/leds.h> -#include <linux/dma-mapping.h> -#include <linux/pinctrl/machine.h> -#include <linux/platform_data/camera-rcar.h> -#include <linux/platform_data/gpio-rcar.h> -#include <linux/platform_data/usb-rcar-phy.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <linux/spi/spi.h> -#include <linux/spi/sh_hspi.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/mfd/tmio.h> - -#include <media/soc_camera.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/traps.h> - -#include "common.h" -#include "irqs.h" -#include "r8a7779.h" - -/* Fixed 3.3V regulator to be used by SDHI0 */ -static struct regulator_consumer_supply fixed3v3_power_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), -}; - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* USB PHY */ -static struct resource usb_phy_resources[] = { - [0] = { - .start = 0xffe70800, - .end = 0xffe70900 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct rcar_phy_platform_data usb_phy_platform_data; - -static struct platform_device usb_phy = { - .name = "rcar_usb_phy", - .id = -1, - .dev = { - .platform_data = &usb_phy_platform_data, - }, - .resource = usb_phy_resources, - .num_resources = ARRAY_SIZE(usb_phy_resources), -}; - -/* SMSC LAN89218 */ -static struct resource smsc911x_resources[] = { - [0] = { - .start = 0x18000000, /* ExCS0 */ - .end = 0x180000ff, /* A1->A7 */ - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = irq_pin(1), /* IRQ 1 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc911x_platdata = { - .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device eth_device = { - .name = "smsc911x", - .id = -1, - .dev = { - .platform_data = &smsc911x_platdata, - }, - .resource = smsc911x_resources, - .num_resources = ARRAY_SIZE(smsc911x_resources), -}; - -static struct resource sdhi0_resources[] = { - [0] = { - .name = "sdhi0", - .start = 0xffe4c000, - .end = 0xffe4c0ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x88), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct tmio_mmc_data sdhi0_platform_data = { - .chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX, - .chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX, - .flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, - .capabilities = MMC_CAP_SD_HIGHSPEED, -}; - -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, - .id = 0, - .dev = { - .platform_data = &sdhi0_platform_data, - } -}; - -/* Thermal */ -static struct resource thermal_resources[] = { - [0] = { - .start = 0xFFC48000, - .end = 0xFFC48038 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device thermal_device = { - .name = "rcar_thermal", - .resource = thermal_resources, - .num_resources = ARRAY_SIZE(thermal_resources), -}; - -/* HSPI */ -static struct resource hspi_resources[] = { - [0] = { - .start = 0xFFFC7000, - .end = 0xFFFC7018 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device hspi_device = { - .name = "sh-hspi", - .id = 0, - .resource = hspi_resources, - .num_resources = ARRAY_SIZE(hspi_resources), -}; - -/* LEDS */ -static struct gpio_led marzen_leds[] = { - { - .name = "led2", - .gpio = RCAR_GP_PIN(4, 29), - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "led3", - .gpio = RCAR_GP_PIN(4, 30), - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "led4", - .gpio = RCAR_GP_PIN(4, 31), - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, -}; - -static struct gpio_led_platform_data marzen_leds_pdata = { - .leds = marzen_leds, - .num_leds = ARRAY_SIZE(marzen_leds), -}; - -static struct platform_device leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &marzen_leds_pdata, - }, -}; - -/* VIN */ -static struct rcar_vin_platform_data vin_platform_data __initdata = { - .flags = RCAR_VIN_BT656, -}; - -#define MARZEN_VIN(idx) \ -static struct resource vin##idx##_resources[] __initdata = { \ - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ - DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ -}; \ - \ -static struct platform_device_info vin##idx##_info __initdata = { \ - .name = "r8a7779-vin", \ - .id = idx, \ - .res = vin##idx##_resources, \ - .num_res = ARRAY_SIZE(vin##idx##_resources), \ - .dma_mask = DMA_BIT_MASK(32), \ - .data = &vin_platform_data, \ - .size_data = sizeof(vin_platform_data), \ -} -MARZEN_VIN(1); -MARZEN_VIN(3); - -#define MARZEN_CAMERA(idx) \ -static struct i2c_board_info camera##idx##_info = { \ - I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ -}; \ - \ -static struct soc_camera_link iclink##idx##_adv7180 = { \ - .bus_id = 1 + 2 * (idx), \ - .i2c_adapter_id = 0, \ - .board_info = &camera##idx##_info, \ -}; \ - \ -static struct platform_device camera##idx##_device = { \ - .name = "soc-camera-pdrv", \ - .id = idx, \ - .dev = { \ - .platform_data = &iclink##idx##_adv7180, \ - }, \ -}; - -MARZEN_CAMERA(0); -MARZEN_CAMERA(1); - -static struct platform_device *marzen_devices[] __initdata = { - ð_device, - &sdhi0_device, - &thermal_device, - &hspi_device, - &leds_device, - &usb_phy, - &camera0_device, - &camera1_device, -}; - -static const struct pinctrl_map marzen_pinctrl_map[] = { - /* DU (CN10: ARGB0, CN13: LVDS) */ - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_rgb888", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_sync_1", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_clk_out_0", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_rgb666", "du1"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_sync_1", "du1"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_clk_out", "du1"), - /* HSPI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", - "hspi0", "hspi0"), - /* SCIF2 (CN18: DEBUG0) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", - "scif2_data_c", "scif2"), - /* SCIF4 (CN19: DEBUG1) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", - "scif4_data", "scif4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_cd", "sdhi0"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "intc_irq1_b", "intc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "lbsc_ex_cs0", "lbsc"), - /* USB0 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", - "usb0", "usb0"), - /* USB1 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", - "usb1", "usb1"), - /* USB2 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", - "usb2", "usb2"), - /* VIN1 */ - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", - "vin1_clk", "vin1"), - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", - "vin1_data8", "vin1"), - /* VIN3 */ - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", - "vin3_clk", "vin3"), - PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", - "vin3_data8", "vin3"), -}; - -static void __init marzen_init(void) -{ - regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - regulator_register_fixed(1, dummy_supplies, - ARRAY_SIZE(dummy_supplies)); - - pinctrl_register_mappings(marzen_pinctrl_map, - ARRAY_SIZE(marzen_pinctrl_map)); - r8a7779_pinmux_init(); - r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ - - r8a7779_add_standard_devices(); - platform_device_register_full(&vin1_info); - platform_device_register_full(&vin3_info); - platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); -} - -static const char *marzen_boards_compat_dt[] __initdata = { - "renesas,marzen", - NULL, -}; - -DT_MACHINE_START(MARZEN, "marzen") - .smp = smp_ops(r8a7779_smp_ops), - .map_io = r8a7779_map_io, - .init_early = r8a7779_add_early_devices, - .init_irq = r8a7779_init_irq_dt, - .init_machine = marzen_init, - .init_late = r8a7779_init_late, - .dt_compat = marzen_boards_compat_dt, - .init_time = r8a7779_earlytimer_init, -MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c deleted file mode 100644 index 9cac8247c72b..000000000000 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * R8A7740 processor support - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> - -#include "clock.h" -#include "common.h" -#include "r8a7740.h" - -/* - * | MDx | XTAL1/EXTAL1 | System | EXTALR | - * Clock |-------+-----------------+ clock | 32.768 | RCLK - * Mode | 2/1/0 | src MHz | source | KHz | source - * -------+-------+-----------------+-----------+--------+---------- - * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR - * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR - * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR - * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR - * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024 - * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024 - * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 - * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 - */ - -/* CPG registers */ -#define FRQCRA IOMEM(0xe6150000) -#define FRQCRB IOMEM(0xe6150004) -#define VCLKCR1 IOMEM(0xE6150008) -#define VCLKCR2 IOMEM(0xE615000c) -#define FRQCRC IOMEM(0xe61500e0) -#define FSIACKCR IOMEM(0xe6150018) -#define PLLC01CR IOMEM(0xe6150028) - -#define SUBCKCR IOMEM(0xe6150080) -#define USBCKCR IOMEM(0xe615008c) - -#define MSTPSR0 IOMEM(0xe6150030) -#define MSTPSR1 IOMEM(0xe6150038) -#define MSTPSR2 IOMEM(0xe6150040) -#define MSTPSR3 IOMEM(0xe6150048) -#define MSTPSR4 IOMEM(0xe615004c) -#define FSIBCKCR IOMEM(0xe6150090) -#define HDMICKCR IOMEM(0xe6150094) -#define SMSTPCR0 IOMEM(0xe6150130) -#define SMSTPCR1 IOMEM(0xe6150134) -#define SMSTPCR2 IOMEM(0xe6150138) -#define SMSTPCR3 IOMEM(0xe615013c) -#define SMSTPCR4 IOMEM(0xe6150140) - -#define FSIDIVA IOMEM(0xFE1F8000) -#define FSIDIVB IOMEM(0xFE1F8008) - -/* Fixed 32 KHz root clock from EXTALR pin */ -static struct clk extalr_clk = { - .rate = 32768, -}; - -/* - * 25MHz default rate for the EXTAL1 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -static struct clk extal1_clk = { - .rate = 25000000, -}; - -/* - * 48MHz default rate for the EXTAL2 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -static struct clk extal2_clk = { - .rate = 48000000, -}; - -/* - * 27MHz default rate for the DV_CLKI root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -static struct clk dv_clk = { - .rate = 27000000, -}; - -SH_CLK_RATIO(div2, 1, 2); -SH_CLK_RATIO(div1k, 1, 1024); - -SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k); -SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k); -SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); - -static struct sh_clk_ops followparent_clk_ops = { - .recalc = followparent_recalc, -}; - -/* Main clock */ -static struct clk system_clk = { - .ops = &followparent_clk_ops, -}; - -SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2); - -/* r_clk */ -static struct clk r_clk = { - .ops = &followparent_clk_ops, -}; - -/* PLLC0/PLLC1 */ -static unsigned long pllc01_recalc(struct clk *clk) -{ - unsigned long mult = 1; - - if (__raw_readl(PLLC01CR) & (1 << 14)) - mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; - - return clk->parent->rate * mult; -} - -static struct sh_clk_ops pllc01_clk_ops = { - .recalc = pllc01_recalc, -}; - -static struct clk pllc0_clk = { - .ops = &pllc01_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &system_clk, - .enable_reg = (void __iomem *)FRQCRC, -}; - -static struct clk pllc1_clk = { - .ops = &pllc01_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &system_div2_clk, - .enable_reg = (void __iomem *)FRQCRA, -}; - -/* PLLC1 / 2 */ -SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); - -/* USB clock */ -/* - * USBCKCR is controlling usb24 clock - * bit[7] : parent clock - * bit[6] : clock divide rate - * And this bit[7] is used as a "usb24s" from other devices. - * (Video clock / Sub clock / SPU clock) - * You can controll this clock as a below. - * - * struct clk *usb24 = clk_get(dev, "usb24"); - * struct clk *usb24s = clk_get(NULL, "usb24s"); - * struct clk *system = clk_get(NULL, "system_clk"); - * int rate = clk_get_rate(system); - * - * clk_set_parent(usb24s, system); // for bit[7] - * clk_set_rate(usb24, rate / 2); // for bit[6] - */ -static struct clk *usb24s_parents[] = { - [0] = &system_clk, - [1] = &extal2_clk -}; - -static int usb24s_enable(struct clk *clk) -{ - __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR); - - return 0; -} - -static void usb24s_disable(struct clk *clk) -{ - __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR); -} - -static int usb24s_set_parent(struct clk *clk, struct clk *parent) -{ - int i, ret; - u32 val; - - if (!clk->parent_table || !clk->parent_num) - return -EINVAL; - - /* Search the parent */ - for (i = 0; i < clk->parent_num; i++) - if (clk->parent_table[i] == parent) - break; - - if (i == clk->parent_num) - return -ENODEV; - - ret = clk_reparent(clk, parent); - if (ret < 0) - return ret; - - val = __raw_readl(USBCKCR); - val &= ~(1 << 7); - val |= i << 7; - __raw_writel(val, USBCKCR); - - return 0; -} - -static struct sh_clk_ops usb24s_clk_ops = { - .recalc = followparent_recalc, - .enable = usb24s_enable, - .disable = usb24s_disable, - .set_parent = usb24s_set_parent, -}; - -static struct clk usb24s_clk = { - .ops = &usb24s_clk_ops, - .parent_table = usb24s_parents, - .parent_num = ARRAY_SIZE(usb24s_parents), - .parent = &system_clk, -}; - -static unsigned long usb24_recalc(struct clk *clk) -{ - return clk->parent->rate / - ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2); -}; - -static int usb24_set_rate(struct clk *clk, unsigned long rate) -{ - u32 val; - - /* closer to which ? parent->rate or parent->rate/2 */ - val = __raw_readl(USBCKCR); - val &= ~(1 << 6); - val |= (rate > (clk->parent->rate / 4) * 3) << 6; - __raw_writel(val, USBCKCR); - - return 0; -} - -static struct sh_clk_ops usb24_clk_ops = { - .recalc = usb24_recalc, - .set_rate = usb24_set_rate, -}; - -static struct clk usb24_clk = { - .ops = &usb24_clk_ops, - .parent = &usb24s_clk, -}; - -/* External FSIACK/FSIBCK clock */ -static struct clk fsiack_clk = { -}; - -static struct clk fsibck_clk = { -}; - -static struct clk *main_clks[] = { - &extalr_clk, - &extal1_clk, - &extal2_clk, - &extal1_div2_clk, - &extal1_div1024_clk, - &extal1_div2048_clk, - &extal2_div2_clk, - &dv_clk, - &system_clk, - &system_div2_clk, - &r_clk, - &pllc0_clk, - &pllc1_clk, - &pllc1_div2_clk, - &usb24s_clk, - &usb24_clk, - &fsiack_clk, - &fsibck_clk, -}; - -/* DIV4 clocks */ -static void div4_kick(struct clk *clk) -{ - unsigned long value; - - /* set KICK bit in FRQCRB to update hardware setting */ - value = __raw_readl(FRQCRB); - value |= (1 << 31); - __raw_writel(value, FRQCRB); -} - -static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, - 24, 32, 36, 48, 0, 72, 96, 0 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, - .kick = div4_kick, -}; - -enum { - DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, - DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, - DIV4_NR -}; - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), - [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), - [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), - [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), - [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), - [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), - [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), -}; - -/* DIV6 reparent */ -enum { - DIV6_HDMI, - DIV6_VCLK1, DIV6_VCLK2, - DIV6_FSIA, DIV6_FSIB, - DIV6_REPARENT_NR, -}; - -static struct clk *hdmi_parent[] = { - [0] = &pllc1_div2_clk, - [1] = &system_clk, - [2] = &dv_clk -}; - -static struct clk *vclk_parents[8] = { - [0] = &pllc1_div2_clk, - [2] = &dv_clk, - [3] = &usb24s_clk, - [4] = &extal1_div2_clk, - [5] = &extalr_clk, -}; - -static struct clk *fsia_parents[] = { - [0] = &pllc1_div2_clk, - [1] = &fsiack_clk, /* external clock */ -}; - -static struct clk *fsib_parents[] = { - [0] = &pllc1_div2_clk, - [1] = &fsibck_clk, /* external clock */ -}; - -static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { - [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0, - hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), - [DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0, - vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3), - [DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0, - vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3), - [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, - fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), - [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, - fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), -}; - -/* DIV6 clocks */ -enum { - DIV6_SUB, - DIV6_NR -}; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), -}; - -/* HDMI1/2 clock */ -static unsigned long hdmi12_recalc(struct clk *clk) -{ - u32 val = __raw_readl(HDMICKCR); - int shift = (int)clk->priv; - - val >>= shift; - val &= 0x3; - - return clk->parent->rate / (1 << val); -}; - -static int hdmi12_set_rate(struct clk *clk, unsigned long rate) -{ - u32 val, mask; - int i, shift; - - for (i = 0; i < 3; i++) - if (rate == clk->parent->rate / (1 << i)) - goto find; - return -ENODEV; - -find: - shift = (int)clk->priv; - - val = __raw_readl(HDMICKCR); - mask = ~(0x3 << shift); - val = (val & mask) | i << shift; - __raw_writel(val, HDMICKCR); - - return 0; -}; - -static struct sh_clk_ops hdmi12_clk_ops = { - .recalc = hdmi12_recalc, - .set_rate = hdmi12_set_rate, -}; - -static struct clk hdmi1_clk = { - .ops = &hdmi12_clk_ops, - .priv = (void *)9, - .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */ -}; - -static struct clk hdmi2_clk = { - .ops = &hdmi12_clk_ops, - .priv = (void *)11, - .parent = &div6_reparent_clks[DIV6_HDMI], /* late install */ -}; - -static struct clk *late_main_clks[] = { - &hdmi1_clk, - &hdmi2_clk, -}; - -/* FSI DIV */ -enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR }; - -static struct clk fsidivs[] = { - [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]), - [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]), -}; - -/* MSTP */ -enum { - MSTP128, MSTP127, MSTP125, - MSTP116, MSTP111, MSTP100, MSTP117, - - MSTP230, MSTP229, - MSTP222, - MSTP218, MSTP217, MSTP216, MSTP214, - MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, - - MSTP329, MSTP328, MSTP323, MSTP320, - MSTP314, MSTP313, MSTP312, - MSTP309, MSTP304, - - MSTP416, MSTP415, MSTP407, MSTP406, - - MSTP_NR -}; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */ - [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ - [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ - [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ - [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */ - [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ - [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ - - [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ - [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */ - [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ - [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ - [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ - [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */ - [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */ - [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ - [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ - [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ - [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ - [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ - - [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ - [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */ - [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ - [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */ - [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ - [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ - [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ - [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ - [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */ - - [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ - [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ - [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */ - [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */ -}; - -static struct clk_lookup lookups[] = { - /* main clocks */ - CLKDEV_CON_ID("extalr", &extalr_clk), - CLKDEV_CON_ID("extal1", &extal1_clk), - CLKDEV_CON_ID("extal2", &extal2_clk), - CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), - CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk), - CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk), - CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), - CLKDEV_CON_ID("dv_clk", &dv_clk), - CLKDEV_CON_ID("system_clk", &system_clk), - CLKDEV_CON_ID("system_div2_clk", &system_div2_clk), - CLKDEV_CON_ID("r_clk", &r_clk), - CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), - CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), - CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), - CLKDEV_CON_ID("usb24s", &usb24s_clk), - CLKDEV_CON_ID("hdmi1", &hdmi1_clk), - CLKDEV_CON_ID("hdmi2", &hdmi2_clk), - CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]), - CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]), - CLKDEV_CON_ID("fsiack", &fsiack_clk), - CLKDEV_CON_ID("fsibck", &fsibck_clk), - - /* DIV4 clocks */ - CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), - CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), - CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), - CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), - CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), - CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]), - CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]), - CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), - CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]), - CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), - - /* DIV6 clocks */ - CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), - - /* MSTP32 clocks */ - CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), - CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), - CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), - CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), - CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), - CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), - - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), - CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), - CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), - CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), - CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), - CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), - CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), - CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), - CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]), - CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]), - CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]), - CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]), - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), - CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), - - CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), - CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]), - CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), - CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), - CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), - CLKDEV_DEV_ID("e9a00000.ethernet", &mstp_clks[MSTP309]), - CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), - CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), - - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), - CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]), - - /* ICK */ - CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]), - CLKDEV_ICK_ID("fck", "fff90000.timer", &mstp_clks[MSTP111]), - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), - CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]), - CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), - CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), - CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), - CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]), - CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]), - CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]), - CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk), - CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), - - CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), - CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), - CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]), - CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]), - CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk), - CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk), -}; - -void __init r8a7740_clock_init(u8 md_ck) -{ - int k, ret = 0; - - /* detect system clock parent */ - if (md_ck & MD_CK1) - system_clk.parent = &extal1_div2_clk; - else - system_clk.parent = &extal1_clk; - - /* detect RCLK parent */ - switch (md_ck & (MD_CK2 | MD_CK1)) { - case MD_CK2 | MD_CK1: - r_clk.parent = &extal1_div2048_clk; - break; - case MD_CK2: - r_clk.parent = &extal1_div1024_clk; - break; - case MD_CK1: - default: - r_clk.parent = &extalr_clk; - break; - } - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - - if (!ret) - ret = sh_clk_div6_register(div6_clks, DIV6_NR); - - if (!ret) - ret = sh_clk_div6_reparent_register(div6_reparent_clks, - DIV6_REPARENT_NR); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) - ret = clk_register(late_main_clks[k]); - - if (!ret) - ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a7740 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c deleted file mode 100644 index fa8ab2cc9187..000000000000 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * r8a7779 clock framework support - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/bitops.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include <linux/sh_timer.h> - -#include "clock.h" -#include "common.h" -#include "r8a7779.h" - -/* - * MD1 = 1 MD1 = 0 - * (PLLA = 1500) (PLLA = 1600) - * (MHz) (MHz) - *------------------------------------------------+-------------------- - * clkz 1000 (2/3) 800 (1/2) - * clkzs 250 (1/6) 200 (1/8) - * clki 750 (1/2) 800 (1/2) - * clks 250 (1/6) 200 (1/8) - * clks1 125 (1/12) 100 (1/16) - * clks3 187.5 (1/8) 200 (1/8) - * clks4 93.7 (1/16) 100 (1/16) - * clkp 62.5 (1/24) 50 (1/32) - * clkg 62.5 (1/24) 66.6 (1/24) - * clkb, CLKOUT - * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) - * (MD2 = 1) 41.6 (1/36) 50 (1/32) -*/ - -#define MD(nr) BIT(nr) - -#define MSTPCR0 IOMEM(0xffc80030) -#define MSTPCR1 IOMEM(0xffc80034) -#define MSTPCR3 IOMEM(0xffc8003c) -#define MSTPSR1 IOMEM(0xffc80044) - -/* ioremap() through clock mapping mandatory to avoid - * collision with ARM coherent DMA virtual memory range. - */ - -static struct clk_mapping cpg_mapping = { - .phys = 0xffc80000, - .len = 0x80, -}; - -/* - * Default rate for the root input clock, reset this with clk_set_rate() - * from the platform code. - */ -static struct clk plla_clk = { - /* .rate will be updated on r8a7779_clock_init() */ - .mapping = &cpg_mapping, -}; - -/* - * clock ratio of these clock will be updated - * on r8a7779_clock_init() - */ -SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1); - -static struct clk *main_clks[] = { - &plla_clk, - &clkz_clk, - &clkzs_clk, - &clki_clk, - &clks_clk, - &clks1_clk, - &clks3_clk, - &clks4_clk, - &clkb_clk, - &clkout_clk, - &clkp_clk, - &clkg_clk, -}; - -enum { MSTP323, MSTP322, MSTP321, MSTP320, - MSTP120, - MSTP116, MSTP115, MSTP114, - MSTP110, MSTP109, MSTP108, - MSTP103, MSTP101, MSTP100, - MSTP030, - MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, - MSTP016, MSTP015, MSTP014, - MSTP007, - MSTP_NR }; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */ - [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ - [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ - [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ - [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */ - [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */ - [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */ - [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */ - [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */ - [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */ - [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */ - [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */ - [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */ - [MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */ - [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ - [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ - [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ - [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */ - [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */ - [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */ - [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */ -}; - -static struct clk_lookup lookups[] = { - /* main clocks */ - CLKDEV_CON_ID("plla_clk", &plla_clk), - CLKDEV_CON_ID("clkz_clk", &clkz_clk), - CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), - - /* DIV4 clocks */ - CLKDEV_CON_ID("shyway_clk", &clks_clk), - CLKDEV_CON_ID("bus_clk", &clkout_clk), - CLKDEV_CON_ID("shyway4_clk", &clks4_clk), - CLKDEV_CON_ID("shyway3_clk", &clks3_clk), - CLKDEV_CON_ID("shyway1_clk", &clks1_clk), - CLKDEV_CON_ID("peripheral_clk", &clkp_clk), - - /* MSTP32 clocks */ - CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */ - CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ - CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ - CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ - CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ - CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ - CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ - CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */ - CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ - CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ - CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ - CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), /* TMU0 */ - CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ - CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ - CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ - CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ - CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ - CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ - CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ - CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ - CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ - CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ - CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ - CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ - CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ - CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ - CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ - CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ - CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ - CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */ - CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ -}; - -void __init r8a7779_clock_init(void) -{ - u32 mode = r8a7779_read_mode_pins(); - int k, ret = 0; - - if (mode & MD(1)) { - plla_clk.rate = 1500000000; - - SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); - if (mode & MD(2)) { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36); - } else { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); - } - } else { - plla_clk.rate = 1600000000; - - SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32); - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); - if (mode & MD(2)) { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32); - } else { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); - } - } - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a7779 clocks\n"); -} - -/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ -void __init __weak r8a7779_register_twd(void) { } - -void __init r8a7779_earlytimer_init(void) -{ - r8a7779_clock_init(); - r8a7779_register_twd(); - shmobile_earlytimer_init(); -} diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c deleted file mode 100644 index 3855fb024fdb..000000000000 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ /dev/null @@ -1,752 +0,0 @@ -/* - * sh73a0 clock framework support - * - * Copyright (C) 2010 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include <asm/processor.h> -#include "clock.h" -#include "common.h" - -#define FRQCRA IOMEM(0xe6150000) -#define FRQCRB IOMEM(0xe6150004) -#define FRQCRD IOMEM(0xe61500e4) -#define VCLKCR1 IOMEM(0xe6150008) -#define VCLKCR2 IOMEM(0xe615000C) -#define VCLKCR3 IOMEM(0xe615001C) -#define ZBCKCR IOMEM(0xe6150010) -#define FLCKCR IOMEM(0xe6150014) -#define SD0CKCR IOMEM(0xe6150074) -#define SD1CKCR IOMEM(0xe6150078) -#define SD2CKCR IOMEM(0xe615007C) -#define FSIACKCR IOMEM(0xe6150018) -#define FSIBCKCR IOMEM(0xe6150090) -#define SUBCKCR IOMEM(0xe6150080) -#define SPUACKCR IOMEM(0xe6150084) -#define SPUVCKCR IOMEM(0xe6150094) -#define MSUCKCR IOMEM(0xe6150088) -#define HSICKCR IOMEM(0xe615008C) -#define MFCK1CR IOMEM(0xe6150098) -#define MFCK2CR IOMEM(0xe615009C) -#define DSITCKCR IOMEM(0xe6150060) -#define DSI0PCKCR IOMEM(0xe6150064) -#define DSI1PCKCR IOMEM(0xe6150068) -#define DSI0PHYCR 0xe615006C -#define DSI1PHYCR 0xe6150070 -#define PLLECR IOMEM(0xe61500d0) -#define PLL0CR IOMEM(0xe61500d8) -#define PLL1CR IOMEM(0xe6150028) -#define PLL2CR IOMEM(0xe615002c) -#define PLL3CR IOMEM(0xe61500dc) -#define SMSTPCR0 IOMEM(0xe6150130) -#define SMSTPCR1 IOMEM(0xe6150134) -#define SMSTPCR2 IOMEM(0xe6150138) -#define SMSTPCR3 IOMEM(0xe615013c) -#define SMSTPCR4 IOMEM(0xe6150140) -#define SMSTPCR5 IOMEM(0xe6150144) -#define CKSCR IOMEM(0xe61500c0) - -/* Fixed 32 KHz root clock from EXTALR pin */ -static struct clk r_clk = { - .rate = 32768, -}; - -/* - * 26MHz default rate for the EXTAL1 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -struct clk sh73a0_extal1_clk = { - .rate = 26000000, -}; - -/* - * 48MHz default rate for the EXTAL2 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -struct clk sh73a0_extal2_clk = { - .rate = 48000000, -}; - -static struct sh_clk_ops main_clk_ops = { - .recalc = followparent_recalc, -}; - -/* Main clock */ -static struct clk main_clk = { - /* .parent wll be set on sh73a0_clock_init() */ - .ops = &main_clk_ops, -}; - -/* PLL0, PLL1, PLL2, PLL3 */ -static unsigned long pll_recalc(struct clk *clk) -{ - unsigned long mult = 1; - - if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) { - mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); - /* handle CFG bit for PLL1 and PLL2 */ - switch (clk->enable_bit) { - case 1: - case 2: - if (__raw_readl(clk->enable_reg) & (1 << 20)) - mult *= 2; - } - } - - return clk->parent->rate * mult; -} - -static struct sh_clk_ops pll_clk_ops = { - .recalc = pll_recalc, -}; - -static struct clk pll0_clk = { - .ops = &pll_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &main_clk, - .enable_reg = (void __iomem *)PLL0CR, - .enable_bit = 0, -}; - -static struct clk pll1_clk = { - .ops = &pll_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &main_clk, - .enable_reg = (void __iomem *)PLL1CR, - .enable_bit = 1, -}; - -static struct clk pll2_clk = { - .ops = &pll_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &main_clk, - .enable_reg = (void __iomem *)PLL2CR, - .enable_bit = 2, -}; - -static struct clk pll3_clk = { - .ops = &pll_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &main_clk, - .enable_reg = (void __iomem *)PLL3CR, - .enable_bit = 3, -}; - -/* A fixed divide block */ -SH_CLK_RATIO(div2, 1, 2); -SH_CLK_RATIO(div7, 1, 7); -SH_CLK_RATIO(div13, 1, 13); - -SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2); -SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); -SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); -SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7); -SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13); - -/* External input clock */ -struct clk sh73a0_extcki_clk = { -}; - -struct clk sh73a0_extalr_clk = { -}; - -static struct clk *main_clks[] = { - &r_clk, - &sh73a0_extal1_clk, - &sh73a0_extal2_clk, - &extal1_div2_clk, - &extal2_div2_clk, - &main_clk, - &main_div2_clk, - &pll0_clk, - &pll1_clk, - &pll2_clk, - &pll3_clk, - &pll1_div2_clk, - &pll1_div7_clk, - &pll1_div13_clk, - &sh73a0_extcki_clk, - &sh73a0_extalr_clk, -}; - -static int frqcr_kick(void) -{ - int i; - - /* set KICK bit in FRQCRB to update hardware setting, check success */ - __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); - for (i = 1000; i; i--) - if (__raw_readl(FRQCRB) & (1 << 31)) - cpu_relax(); - else - return i; - - return -ETIMEDOUT; -} - -static void div4_kick(struct clk *clk) -{ - frqcr_kick(); -} - -static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, - 24, 0, 36, 48, 7 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, - .kick = div4_kick, -}; - -enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, - DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; - -#define DIV4(_reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), - /* - * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to - * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and - * 239.2MHz for VDD_DVFS=1.315V. - */ - [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), - [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), - [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), - [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), - [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), - [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), -}; - -static unsigned long twd_recalc(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 4; -} - -static struct sh_clk_ops twd_clk_ops = { - .recalc = twd_recalc, -}; - -static struct clk twd_clk = { - .parent = &div4_clks[DIV4_Z], - .ops = &twd_clk_ops, -}; - -static struct sh_clk_ops zclk_ops, kicker_ops; -static const struct sh_clk_ops *div4_clk_ops; - -static int zclk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - - if (!clk->parent || !__clk_get(clk->parent)) - return -ENODEV; - - if (readl(FRQCRB) & (1 << 31)) - return -EBUSY; - - if (rate == clk_get_rate(clk->parent)) { - /* 1:1 - switch off divider */ - __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); - /* nullify the divider to prepare for the next time */ - ret = div4_clk_ops->set_rate(clk, rate / 2); - if (!ret) - ret = frqcr_kick(); - if (ret > 0) - ret = 0; - } else { - /* Enable the divider */ - __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); - - ret = frqcr_kick(); - if (ret >= 0) - /* - * set the divider - call the DIV4 method, it will kick - * FRQCRB too - */ - ret = div4_clk_ops->set_rate(clk, rate); - if (ret < 0) - goto esetrate; - } - -esetrate: - __clk_put(clk->parent); - return ret; -} - -static long zclk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), - parent_freq = clk_get_rate(clk->parent); - - if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) - return parent_freq; - - return div_freq; -} - -static unsigned long zclk_recalc(struct clk *clk) -{ - /* - * Must recalculate frequencies in case PLL0 has been changed, even if - * the divisor is unused ATM! - */ - unsigned long div_freq = div4_clk_ops->recalc(clk); - - if (__raw_readl(FRQCRB) & (1 << 28)) - return div_freq; - - return clk_get_rate(clk->parent); -} - -static int kicker_set_rate(struct clk *clk, unsigned long rate) -{ - if (__raw_readl(FRQCRB) & (1 << 31)) - return -EBUSY; - - return div4_clk_ops->set_rate(clk, rate); -} - -static void div4_clk_extend(void) -{ - int i; - - div4_clk_ops = div4_clks[0].ops; - - /* Add a kicker-busy check before changing the rate */ - kicker_ops = *div4_clk_ops; - /* We extend the DIV4 clock with a 1:1 pass-through case */ - zclk_ops = *div4_clk_ops; - - kicker_ops.set_rate = kicker_set_rate; - zclk_ops.set_rate = zclk_set_rate; - zclk_ops.round_rate = zclk_round_rate; - zclk_ops.recalc = zclk_recalc; - - for (i = 0; i < DIV4_NR; i++) - div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; -} - -enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, - DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, - DIV6_FSIA, DIV6_FSIB, DIV6_SUB, - DIV6_SPUA, DIV6_SPUV, DIV6_MSU, - DIV6_HSI, DIV6_MFG1, DIV6_MFG2, - DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, - DIV6_NR }; - -static struct clk *vck_parent[8] = { - [0] = &pll1_div2_clk, - [1] = &pll2_clk, - [2] = &sh73a0_extcki_clk, - [3] = &sh73a0_extal2_clk, - [4] = &main_div2_clk, - [5] = &sh73a0_extalr_clk, - [6] = &main_clk, -}; - -static struct clk *pll_parent[4] = { - [0] = &pll1_div2_clk, - [1] = &pll2_clk, - [2] = &pll1_div13_clk, -}; - -static struct clk *hsi_parent[4] = { - [0] = &pll1_div2_clk, - [1] = &pll2_clk, - [2] = &pll1_div7_clk, -}; - -static struct clk *pll_extal2_parent[] = { - [0] = &pll1_div2_clk, - [1] = &pll2_clk, - [2] = &sh73a0_extal2_clk, - [3] = &sh73a0_extal2_clk, -}; - -static struct clk *dsi_parent[8] = { - [0] = &pll1_div2_clk, - [1] = &pll2_clk, - [2] = &main_clk, - [3] = &sh73a0_extal2_clk, - [4] = &sh73a0_extcki_clk, -}; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0, - vck_parent, ARRAY_SIZE(vck_parent), 12, 3), - [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0, - vck_parent, ARRAY_SIZE(vck_parent), 12, 3), - [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0, - vck_parent, ARRAY_SIZE(vck_parent), 12, 3), - [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 6, 2), - [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 6, 2), - [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 6, 2), - [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 6, 1), - [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 6, 1), - [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0, - pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), - [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0, - pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), - [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0, - pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), - [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0, - hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2), - [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0, - pll_parent, ARRAY_SIZE(pll_parent), 7, 1), - [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0, - dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), - [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0, - dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), -}; - -/* DSI DIV */ -static unsigned long dsiphy_recalc(struct clk *clk) -{ - u32 value; - - value = __raw_readl(clk->mapping->base); - - /* FIXME */ - if (!(value & 0x000B8000)) - return clk->parent->rate; - - value &= 0x3f; - value += 1; - - if ((value < 12) || - (value > 33)) { - pr_err("DSIPHY has wrong value (%d)", value); - return 0; - } - - return clk->parent->rate / value; -} - -static long dsiphy_round_rate(struct clk *clk, unsigned long rate) -{ - return clk_rate_mult_range_round(clk, 12, 33, rate); -} - -static void dsiphy_disable(struct clk *clk) -{ - u32 value; - - value = __raw_readl(clk->mapping->base); - value &= ~0x000B8000; - - __raw_writel(value , clk->mapping->base); -} - -static int dsiphy_enable(struct clk *clk) -{ - u32 value; - int multi; - - value = __raw_readl(clk->mapping->base); - multi = (value & 0x3f) + 1; - - if ((multi < 12) || (multi > 33)) - return -EIO; - - __raw_writel(value | 0x000B8000, clk->mapping->base); - - return 0; -} - -static int dsiphy_set_rate(struct clk *clk, unsigned long rate) -{ - u32 value; - int idx; - - idx = rate / clk->parent->rate; - if ((idx < 12) || (idx > 33)) - return -EINVAL; - - idx += -1; - - value = __raw_readl(clk->mapping->base); - value = (value & ~0x3f) + idx; - - __raw_writel(value, clk->mapping->base); - - return 0; -} - -static struct sh_clk_ops dsiphy_clk_ops = { - .recalc = dsiphy_recalc, - .round_rate = dsiphy_round_rate, - .set_rate = dsiphy_set_rate, - .enable = dsiphy_enable, - .disable = dsiphy_disable, -}; - -static struct clk_mapping dsi0phy_clk_mapping = { - .phys = DSI0PHYCR, - .len = 4, -}; - -static struct clk_mapping dsi1phy_clk_mapping = { - .phys = DSI1PHYCR, - .len = 4, -}; - -static struct clk dsi0phy_clk = { - .ops = &dsiphy_clk_ops, - .parent = &div6_clks[DIV6_DSI0P], /* late install */ - .mapping = &dsi0phy_clk_mapping, -}; - -static struct clk dsi1phy_clk = { - .ops = &dsiphy_clk_ops, - .parent = &div6_clks[DIV6_DSI1P], /* late install */ - .mapping = &dsi1phy_clk_mapping, -}; - -static struct clk *late_main_clks[] = { - &dsi0phy_clk, - &dsi1phy_clk, - &twd_clk, -}; - -enum { MSTP001, - MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100, - MSTP219, MSTP218, MSTP217, - MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, - MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, - MSTP314, MSTP313, MSTP312, MSTP311, - MSTP304, MSTP303, MSTP302, MSTP301, MSTP300, - MSTP411, MSTP410, MSTP403, - MSTP508, - MSTP_NR }; - -#define MSTP(_parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_parent, _reg, _bit, _flags) - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */ - [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */ - [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */ - [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */ - [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */ - [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ - [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ - [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ - [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */ - [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ - [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ - [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ - [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */ - [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ - [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ - [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ - [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ - [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ - [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ - [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ - [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/ - [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ - [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ - [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */ - [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */ - [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ - [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ - [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */ - [MSTP304] = MSTP(&main_div2_clk, SMSTPCR3, 4, 0), /* TPU0 */ - [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */ - [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */ - [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */ - [MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */ - [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ - [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ - [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ - [MSTP508] = MSTP(&div4_clks[DIV4_HP], SMSTPCR5, 8, 0), /* INTCA0 */ -}; - -/* The lookups structure below includes duplicate entries for some clocks - * with alternate names. - * - The traditional name used when a device is initialised with platform data - * - The name used when a device is initialised using device tree - * The longer-term aim is to remove these duplicates, and indeed the - * lookups table entirely, by describing clocks using device tree. - */ -static struct clk_lookup lookups[] = { - /* main clocks */ - CLKDEV_CON_ID("r_clk", &r_clk), - CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ - - /* DIV4 clocks */ - CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]), - - /* DIV6 clocks */ - CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), - CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), - CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), - CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]), - CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]), - CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]), - - /* MSTP32 clocks */ - CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ - CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */ - CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */ - CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */ - CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */ - CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */ - CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ - CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ - CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */ - CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ - CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ - CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP219]), /* SCIFA7 */ - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */ - CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */ - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ - CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */ - CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ - CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ - CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */ - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ - CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), /* SCIFA1 */ - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ - CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), /* SCIFA2 */ - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ - CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), /* SCIFA3 */ - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ - CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), /* SCIFA4 */ - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ - CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP331]), /* SCIFA6 */ - CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ - CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */ - CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ - CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ - CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ - CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ - CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ - CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */ - CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ - CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ - CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ - CLKDEV_DEV_ID("renesas-tpu-pwm.3", &mstp_clks[MSTP301]), /* TPU3 */ - CLKDEV_DEV_ID("renesas-tpu-pwm.4", &mstp_clks[MSTP300]), /* TPU4 */ - CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ - CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */ - CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ - CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */ - CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ - CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("e6900000.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("e6900004.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("e6900008.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP508]), /* INTCA0 */ - CLKDEV_DEV_ID("e690000c.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */ - - /* ICK */ - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), - CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */ - CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), /* CMT1 */ - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */ -}; - -void __init sh73a0_clock_init(void) -{ - int k, ret = 0; - - /* Set SDHI clocks to a known state */ - __raw_writel(0x108, SD0CKCR); - __raw_writel(0x108, SD1CKCR); - __raw_writel(0x108, SD2CKCR); - - /* detect main clock parent */ - switch ((__raw_readl(CKSCR) >> 28) & 0x03) { - case 0: - main_clk.parent = &sh73a0_extal1_clk; - break; - case 1: - main_clk.parent = &extal1_div2_clk; - break; - case 2: - main_clk.parent = &sh73a0_extal2_clk; - break; - case 3: - main_clk.parent = &extal2_div2_clk; - break; - } - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) { - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - if (!ret) - div4_clk_extend(); - } - - if (!ret) - ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) - ret = clk_register(late_main_clks[k]); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup sh73a0 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index 476092b86c6e..8d27ec546a35 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -13,7 +13,7 @@ extern void shmobile_smp_boot(void); extern void shmobile_smp_sleep(void); extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg); -extern int shmobile_smp_cpu_disable(unsigned int cpu); +extern bool shmobile_smp_cpu_can_disable(unsigned int cpu); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); extern void shmobile_smp_scu_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-shmobile/dma-register.h b/arch/arm/mach-shmobile/dma-register.h deleted file mode 100644 index 52a2f66e600f..000000000000 --- a/arch/arm/mach-shmobile/dma-register.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * SH-ARM CPU-specific DMA definitions, used by both DMA drivers - * - * Copyright (C) 2012 Renesas Solutions Corp - * - * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h - * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef DMA_REGISTER_H -#define DMA_REGISTER_H - -/* - * Direct Memory Access Controller - */ - -/* Transmit sizes and respective CHCR register values */ -enum { - XMIT_SZ_8BIT = 0, - XMIT_SZ_16BIT = 1, - XMIT_SZ_32BIT = 2, - XMIT_SZ_64BIT = 7, - XMIT_SZ_128BIT = 3, - XMIT_SZ_256BIT = 4, - XMIT_SZ_512BIT = 5, -}; - -/* log2(size / 8) - used to calculate number of transfers */ -static const unsigned int dma_ts_shift[] = { - [XMIT_SZ_8BIT] = 0, - [XMIT_SZ_16BIT] = 1, - [XMIT_SZ_32BIT] = 2, - [XMIT_SZ_64BIT] = 3, - [XMIT_SZ_128BIT] = 4, - [XMIT_SZ_256BIT] = 5, - [XMIT_SZ_512BIT] = 6, -}; - -#define TS_LOW_BIT 0x3 /* --xx */ -#define TS_HI_BIT 0xc /* xx-- */ - -#define TS_LOW_SHIFT (3) -#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */ - -#define TS_INDEX2VAL(i) \ - ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ - (((i) & TS_HI_BIT) << TS_HI_SHIFT)) - -#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz))) -#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz))) - - -/* - * USB High-Speed DMAC - */ -/* Transmit sizes and respective CHCR register values */ -enum { - USBTS_XMIT_SZ_8BYTE = 0, - USBTS_XMIT_SZ_16BYTE = 1, - USBTS_XMIT_SZ_32BYTE = 2, -}; - -/* log2(size / 8) - used to calculate number of transfers */ -static const unsigned int dma_usbts_shift[] = { - [USBTS_XMIT_SZ_8BYTE] = 3, - [USBTS_XMIT_SZ_16BYTE] = 4, - [USBTS_XMIT_SZ_32BYTE] = 5, -}; - -#define USBTS_LOW_BIT 0x3 /* --xx */ -#define USBTS_HI_BIT 0x0 /* ---- */ - -#define USBTS_LOW_SHIFT 6 -#define USBTS_HI_SHIFT 0 - -#define USBTS_INDEX2VAL(i) (((i) & 3) << 6) - -#endif /* DMA_REGISTER_H */ diff --git a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt deleted file mode 100644 index 9531f46a822a..000000000000 --- a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt +++ /dev/null @@ -1,410 +0,0 @@ -LIST "KZM9G low-level initialization routine." -LIST "Adapted from u-boot KZM9G support code." - -LIST "Copyright (C) 2013 Ulrich Hecht" - -LIST "This program is free software; you can redistribute it and/or modify" -LIST "it under the terms of the GNU General Public License version 2 as" -LIST "published by the Free Software Foundation." - -LIST "This program is distributed in the hope that it will be useful," -LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of" -LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the" -LIST "GNU General Public License for more details." - - -LIST "Register definitions:" - -LIST "Secure control register" -#define LIFEC_SEC_SRC (0xE6110008) - -LIST "RWDT" -#define RWDT_BASE (0xE6020000) -#define RWTCSRA0 (RWDT_BASE + 0x04) - -LIST "HPB Semaphore Control Registers" -#define HPBSCR_BASE (0xE6000000) -#define HPBCTRL6 (HPBSCR_BASE + 0x1030) - -#define SBSC1_BASE (0xFE400000) -#define SDCR0A (SBSC1_BASE + 0x0008) -#define SDCR1A (SBSC1_BASE + 0x000C) -#define SDPCRA (SBSC1_BASE + 0x0010) -#define SDCR0SA (SBSC1_BASE + 0x0018) -#define SDCR1SA (SBSC1_BASE + 0x001C) -#define RTCSRA (SBSC1_BASE + 0x0020) -#define RTCORA (SBSC1_BASE + 0x0028) -#define RTCORHA (SBSC1_BASE + 0x002C) -#define SDWCRC0A (SBSC1_BASE + 0x0040) -#define SDWCRC1A (SBSC1_BASE + 0x0044) -#define SDWCR00A (SBSC1_BASE + 0x0048) -#define SDWCR01A (SBSC1_BASE + 0x004C) -#define SDWCR10A (SBSC1_BASE + 0x0050) -#define SDWCR11A (SBSC1_BASE + 0x0054) -#define SDWCR2A (SBSC1_BASE + 0x0060) -#define SDWCRC2A (SBSC1_BASE + 0x0064) -#define ZQCCRA (SBSC1_BASE + 0x0068) -#define SDMRACR0A (SBSC1_BASE + 0x0084) -#define SDMRTMPCRA (SBSC1_BASE + 0x008C) -#define SDMRTMPMSKA (SBSC1_BASE + 0x0094) -#define SDGENCNTA (SBSC1_BASE + 0x009C) -#define SDDRVCR0A (SBSC1_BASE + 0x00B4) -#define DLLCNT0A (SBSC1_BASE + 0x0354) - -#define SDMRA1 (0xFE500000) -#define SDMRA2 (0xFE5C0000) -#define SDMRA3 (0xFE504000) - -#define SBSC2_BASE (0xFB400000) -#define SDCR0B (SBSC2_BASE + 0x0008) -#define SDCR1B (SBSC2_BASE + 0x000C) -#define SDPCRB (SBSC2_BASE + 0x0010) -#define SDCR0SB (SBSC2_BASE + 0x0018) -#define SDCR1SB (SBSC2_BASE + 0x001C) -#define RTCSRB (SBSC2_BASE + 0x0020) -#define RTCORB (SBSC2_BASE + 0x0028) -#define RTCORHB (SBSC2_BASE + 0x002C) -#define SDWCRC0B (SBSC2_BASE + 0x0040) -#define SDWCRC1B (SBSC2_BASE + 0x0044) -#define SDWCR00B (SBSC2_BASE + 0x0048) -#define SDWCR01B (SBSC2_BASE + 0x004C) -#define SDWCR10B (SBSC2_BASE + 0x0050) -#define SDWCR11B (SBSC2_BASE + 0x0054) -#define SDPDCR0B (SBSC2_BASE + 0x0058) -#define SDWCR2B (SBSC2_BASE + 0x0060) -#define SDWCRC2B (SBSC2_BASE + 0x0064) -#define ZQCCRB (SBSC2_BASE + 0x0068) -#define SDMRACR0B (SBSC2_BASE + 0x0084) -#define SDMRTMPCRB (SBSC2_BASE + 0x008C) -#define SDMRTMPMSKB (SBSC2_BASE + 0x0094) -#define SDGENCNTB (SBSC2_BASE + 0x009C) -#define DPHYCNT0B (SBSC2_BASE + 0x00A0) -#define DPHYCNT1B (SBSC2_BASE + 0x00A4) -#define DPHYCNT2B (SBSC2_BASE + 0x00A8) -#define SDDRVCR0B (SBSC2_BASE + 0x00B4) -#define DLLCNT0B (SBSC2_BASE + 0x0354) - -#define SDMRB1 (0xFB500000) -#define SDMRB2 (0xFB5C0000) -#define SDMRB3 (0xFB504000) - -#define CPG_BASE (0xE6150000) -#define FRQCRA (CPG_BASE + 0x0000) -#define FRQCRB (CPG_BASE + 0x0004) -#define FRQCRD (CPG_BASE + 0x00E4) -#define VCLKCR1 (CPG_BASE + 0x0008) -#define VCLKCR2 (CPG_BASE + 0x000C) -#define VCLKCR3 (CPG_BASE + 0x001C) -#define ZBCKCR (CPG_BASE + 0x0010) -#define FLCKCR (CPG_BASE + 0x0014) -#define SD0CKCR (CPG_BASE + 0x0074) -#define SD1CKCR (CPG_BASE + 0x0078) -#define SD2CKCR (CPG_BASE + 0x007C) -#define FSIACKCR (CPG_BASE + 0x0018) -#define SUBCKCR (CPG_BASE + 0x0080) -#define SPUACKCR (CPG_BASE + 0x0084) -#define SPUVCKCR (CPG_BASE + 0x0094) -#define MSUCKCR (CPG_BASE + 0x0088) -#define HSICKCR (CPG_BASE + 0x008C) -#define FSIBCKCR (CPG_BASE + 0x0090) -#define MFCK1CR (CPG_BASE + 0x0098) -#define MFCK2CR (CPG_BASE + 0x009C) -#define DSITCKCR (CPG_BASE + 0x0060) -#define DSI0PCKCR (CPG_BASE + 0x0064) -#define DSI1PCKCR (CPG_BASE + 0x0068) -#define DSI0PHYCR (CPG_BASE + 0x006C) -#define DVFSCR3 (CPG_BASE + 0x0174) -#define DVFSCR4 (CPG_BASE + 0x0178) -#define DVFSCR5 (CPG_BASE + 0x017C) -#define MPMODE (CPG_BASE + 0x00CC) - -#define PLLECR (CPG_BASE + 0x00D0) -#define PLL0CR (CPG_BASE + 0x00D8) -#define PLL1CR (CPG_BASE + 0x0028) -#define PLL2CR (CPG_BASE + 0x002C) -#define PLL3CR (CPG_BASE + 0x00DC) -#define PLL0STPCR (CPG_BASE + 0x00F0) -#define PLL1STPCR (CPG_BASE + 0x00C8) -#define PLL2STPCR (CPG_BASE + 0x00F8) -#define PLL3STPCR (CPG_BASE + 0x00FC) -#define RMSTPCR0 (CPG_BASE + 0x0110) -#define RMSTPCR1 (CPG_BASE + 0x0114) -#define RMSTPCR2 (CPG_BASE + 0x0118) -#define RMSTPCR3 (CPG_BASE + 0x011C) -#define RMSTPCR4 (CPG_BASE + 0x0120) -#define RMSTPCR5 (CPG_BASE + 0x0124) -#define SMSTPCR0 (CPG_BASE + 0x0130) -#define SMSTPCR2 (CPG_BASE + 0x0138) -#define SMSTPCR3 (CPG_BASE + 0x013C) -#define CPGXXCR4 (CPG_BASE + 0x0150) -#define SRCR0 (CPG_BASE + 0x80A0) -#define SRCR2 (CPG_BASE + 0x80B0) -#define SRCR3 (CPG_BASE + 0x80A8) -#define VREFCR (CPG_BASE + 0x00EC) -#define PCLKCR (CPG_BASE + 0x1020) - -#define PORT32CR (0xE6051020) -#define PORT33CR (0xE6051021) -#define PORT34CR (0xE6051022) -#define PORT35CR (0xE6051023) - -LIST "DRAM initialization code:" - -EW RWTCSRA0, 0xA507 - -ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF - -ED_AND SMSTPCR3,0xFFFF7FFF -ED_AND SRCR3, 0xFFFF7FFF -ED_AND SMSTPCR2,0xFFFBFFFF -ED_AND SRCR2, 0xFFFBFFFF -ED PLLECR, 0x00000000 - -WAIT_MASK PLLECR, 0x00000F00, 0x00000000 -WAIT_MASK FRQCRB, 0x80000000, 0x00000000 - -ED PLL0CR, 0x2D000000 -ED PLL1CR, 0x17100000 -ED FRQCRB, 0x96235880 -WAIT_MASK FRQCRB, 0x80000000, 0x00000000 - -ED FLCKCR, 0x0000000B -ED_AND SMSTPCR0, 0xFFFFFFFD - -ED_AND SRCR0, 0xFFFFFFFD -ED 0xE6001628, 0x514 -ED 0xE6001648, 0x514 -ED 0xE6001658, 0x514 -ED 0xE6001678, 0x514 - -ED DVFSCR4, 0x00092000 -ED DVFSCR5, 0x000000DC -ED PLLECR, 0x00000000 -WAIT_MASK PLLECR, 0x00000F00, 0x00000000 - -ED FRQCRA, 0x0012453C -ED FRQCRB, 0x80431350 -WAIT_MASK FRQCRB, 0x80000000, 0x00000000 -ED FRQCRD, 0x00000B0B -WAIT_MASK FRQCRD, 0x80000000, 0x00000000 - -ED PCLKCR, 0x00000003 -ED VCLKCR1, 0x0000012F -ED VCLKCR2, 0x00000119 -ED VCLKCR3, 0x00000119 -ED ZBCKCR, 0x00000002 -ED FLCKCR, 0x00000005 -ED SD0CKCR, 0x00000080 -ED SD1CKCR, 0x00000080 -ED SD2CKCR, 0x00000080 -ED FSIACKCR, 0x0000003F -ED FSIBCKCR, 0x0000003F -ED SUBCKCR, 0x00000080 -ED SPUACKCR, 0x0000000B -ED SPUVCKCR, 0x0000000B -ED MSUCKCR, 0x0000013F -ED HSICKCR, 0x00000080 -ED MFCK1CR, 0x0000003F -ED MFCK2CR, 0x0000003F -ED DSITCKCR, 0x00000107 -ED DSI0PCKCR, 0x00000313 -ED DSI1PCKCR, 0x0000130D -ED DSI0PHYCR, 0x2A800E0E -ED PLL0CR, 0x1E000000 -ED PLL0CR, 0x2D000000 -ED PLL1CR, 0x17100000 -ED PLL2CR, 0x27000080 -ED PLL3CR, 0x1D000000 -ED PLL0STPCR, 0x00080000 -ED PLL1STPCR, 0x000120C0 -ED PLL2STPCR, 0x00012000 -ED PLL3STPCR, 0x00000030 -ED PLLECR, 0x0000000B -WAIT_MASK PLLECR, 0x00000B00, 0x00000B00 - -ED DVFSCR3, 0x000120F0 -ED MPMODE, 0x00000020 -ED VREFCR, 0x0000028A -ED RMSTPCR0, 0xE4628087 -ED RMSTPCR1, 0xFFFFFFFF -ED RMSTPCR2, 0x53FFFFFF -ED RMSTPCR3, 0xFFFFFFFF -ED RMSTPCR4, 0x00800D3D -ED RMSTPCR5, 0xFFFFF3FF -ED SMSTPCR2, 0x00000000 -ED SRCR2, 0x00040000 -ED_AND PLLECR, 0xFFFFFFF7 -WAIT_MASK PLLECR, 0x00000800, 0x00000000 - -LIST "set SBSC operational" -ED HPBCTRL6, 0x00000001 -WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001 - -LIST "set SBSC operating frequency" -ED FRQCRD, 0x00001414 -WAIT_MASK FRQCRD, 0x80000000, 0x00000000 -ED PLL3CR, 0x1D000000 -ED_OR PLLECR, 0x00000008 -WAIT_MASK PLLECR, 0x00000800, 0x00000800 - -LIST "enable DLL oscillation in DDRPHY" -ED_OR DLLCNT0A, 0x00000002 - -LIST "wait >= 100 ns" -ED SDGENCNTA, 0x00000005 -WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 - -LIST "target LPDDR2 device settings" -ED SDCR0A, 0xACC90159 -ED SDCR1A, 0x00010059 -ED SDWCRC0A, 0x50874114 -ED SDWCRC1A, 0x33199B37 -ED SDWCRC2A, 0x008F2313 -ED SDWCR00A, 0x31020707 -ED SDWCR01A, 0x0017040A -ED SDWCR10A, 0x31020707 -ED SDWCR11A, 0x0017040A - -ED SDDRVCR0A, 0x055557ff - -ED SDWCR2A, 0x30000000 - -LIST "drive CKE high" -ED_OR SDPCRA, 0x00000080 -WAIT_MASK SDPCRA, 0x00000080, 0x00000080 - -LIST "wait >= 200 us" -ED SDGENCNTA, 0x00002710 -WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 - -LIST "issue reset command to LPDDR2 device" -ED SDMRACR0A, 0x0000003F -ED SDMRA1, 0x00000000 - -LIST "wait >= 10 (or 1) us (docs inconsistent)" -ED SDGENCNTA, 0x000001F4 -WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 - -LIST "MRW ZS initialization calibration command" -ED SDMRACR0A, 0x0000FF0A -ED SDMRA3, 0x00000000 - -LIST "wait >= 1 us" -ED SDGENCNTA, 0x00000032 -WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 - -LIST "specify operating mode in LPDDR2" -ED SDMRACR0A, 0x00002201 -ED SDMRA1, 0x00000000 -ED SDMRACR0A, 0x00000402 -ED SDMRA1, 0x00000000 -ED SDMRACR0A, 0x00000203 -ED SDMRA1, 0x00000000 - -LIST "initialize DDR interface" -ED SDMRA2, 0x00000000 - -LIST "temperature sensor control" -ED SDMRTMPCRA, 0x88800004 -ED SDMRTMPMSKA,0x00000004 - -LIST "auto-refreshing control" -ED RTCORA, 0xA55A0032 -ED RTCORHA, 0xA55A000C -ED RTCSRA, 0xA55A2048 - -ED_OR SDCR0A, 0x00000800 -ED_OR SDCR1A, 0x00000400 - -LIST "auto ZQ calibration control" -ED ZQCCRA, 0xFFF20000 - -ED_OR DLLCNT0B, 0x00000002 -ED SDGENCNTB, 0x00000005 -WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 - -ED SDCR0B, 0xACC90159 -ED SDCR1B, 0x00010059 -ED SDWCRC0B, 0x50874114 -ED SDWCRC1B, 0x33199B37 -ED SDWCRC2B, 0x008F2313 -ED SDWCR00B, 0x31020707 -ED SDWCR01B, 0x0017040A -ED SDWCR10B, 0x31020707 -ED SDWCR11B, 0x0017040A -ED SDDRVCR0B, 0x055557ff -ED SDWCR2B, 0x30000000 -ED_OR SDPCRB, 0x00000080 -WAIT_MASK SDPCRB, 0x00000080, 0x00000080 - -ED SDGENCNTB, 0x00002710 -WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 -ED SDMRACR0B, 0x0000003F - -LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does" -LIST "not seem to make a lot of sense..." -ED SDMRB1, 0x00000000 - -ED SDGENCNTB, 0x000001F4 -WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 - -ED SDMRACR0B, 0x0000FF0A -ED SDMRB3, 0x00000000 -ED SDGENCNTB, 0x00000032 -WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 - -ED SDMRACR0B, 0x00002201 -ED SDMRB1, 0x00000000 -ED SDMRACR0B, 0x00000402 -ED SDMRB1, 0x00000000 -ED SDMRACR0B, 0x00000203 -ED SDMRB1, 0x00000000 -ED SDMRB2, 0x00000000 -ED SDMRTMPCRB, 0x88800004 -ED SDMRTMPMSKB, 0x00000004 -ED RTCORB, 0xA55A0032 -ED RTCORHB, 0xA55A000C -ED RTCSRB, 0xA55A2048 -ED_OR SDCR0B, 0x00000800 -ED_OR SDCR1B, 0x00000400 -ED ZQCCRB, 0xFFF20000 -ED_OR SDPDCR0B, 0x00030000 -ED DPHYCNT1B, 0xA5390000 -ED DPHYCNT0B, 0x00001200 -ED DPHYCNT1B, 0x07CE0000 -ED DPHYCNT0B, 0x00001247 -WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000 - -ED_AND SDPDCR0B, 0xFFFCFFFF - -ED FRQCRD, 0x00000B0B -WAIT_MASK FRQCRD, 0x80000000, 0x00000000 - -ED CPGXXCR4, 0xfffffffc - -LIST "Setup SCIF4 / workaround" -EB PORT32CR, 0x12 -EB PORT33CR, 0x22 -EB PORT34CR, 0x12 -EB PORT35CR, 0x22 - -EW 0xE6C80000, 0 -EB 0xE6C80004, 0x19 -EW 0xE6C80008, 0x0030 -EW 0xE6C80018, 0 -EW 0xE6C80030, 0x0014 - -LIST "Magic to avoid hangs and corruption on DRAM writes." - -LIST "It has been observed that the system would most often hang while" -LIST "decompressing the kernel, and if it didn't it would always write" -LIST "a corrupt image to DRAM." -LIST "This problem does not occur in u-boot, and the reason is that" -LIST "u-boot performs an additional cache invalidation after setting up" -LIST "the DRAM controller. Such an invalidation should not be necessary at" -LIST "this point, and attempts at removing parts of the routine to arrive" -LIST "at the minimal snippet of code necessary to avoid the DRAM stability" -LIST "problem yielded the following:" - -MRC p15, 0, r0, c1, c0, 0 -MCR p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h deleted file mode 100644 index 175ee05465da..000000000000 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef ZBOOT_H -#define ZBOOT_H - -#include <mach/zboot_macros.h> - -/************************************************** - * - * board specific settings - * - **************************************************/ - -#ifdef CONFIG_MACH_KZM9G -#define MEMORY_START 0x43000000 -#include "mach/head-kzm9g.txt" -#else -#error "unsupported board." -#endif - -#endif /* ZBOOT_H */ diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h deleted file mode 100644 index 14fd3d538e9a..000000000000 --- a/arch/arm/mach-shmobile/include/mach/zboot_macros.h +++ /dev/null @@ -1,108 +0,0 @@ -#ifndef __ZBOOT_MACRO_H -#define __ZBOOT_MACRO_H - -/* The LIST command is used to include comments in the script */ -.macro LIST comment -.endm - -/* The ED command is used to write a 32-bit word */ -.macro ED, addr, data - LDR r0, 1f - LDR r1, 2f - STR r1, [r0] - B 3f -1 : .long \addr -2 : .long \data -3 : -.endm - -/* The EW command is used to write a 16-bit word */ -.macro EW, addr, data - LDR r0, 1f - LDR r1, 2f - STRH r1, [r0] - B 3f -1 : .long \addr -2 : .long \data -3 : -.endm - -/* The EB command is used to write an 8-bit word */ -.macro EB, addr, data - LDR r0, 1f - LDR r1, 2f - STRB r1, [r0] - B 3f -1 : .long \addr -2 : .long \data -3 : -.endm - -/* The WAIT command is used to delay the execution */ -.macro WAIT, time, reg - LDR r1, 1f - LDR r0, 2f - STR r0, [r1] -10 : - LDR r0, [r1] - CMP r0, #0x00000000 - BNE 10b - NOP - B 3f -1 : .long \reg -2 : .long \time * 100 -3 : -.endm - -/* The DD command is used to read a 32-bit word */ -.macro DD, start, end - LDR r1, 1f - B 2f -1 : .long \start -2 : -.endm - -/* loop until a given value has been read (with mask) */ -.macro WAIT_MASK, addr, data, cmp - LDR r0, 2f - LDR r1, 3f - LDR r2, 4f -1: - LDR r3, [r0, #0] - AND r3, r1, r3 - CMP r2, r3 - BNE 1b - B 5f -2: .long \addr -3: .long \data -4: .long \cmp -5: -.endm - -/* read 32-bit value from addr, "or" an immediate and write back */ -.macro ED_OR, addr, data - LDR r4, 1f - LDR r5, 2f - LDR r6, [r4] - ORR r5, r6, r5 - STR r5, [r4] - B 3f -1: .long \addr -2: .long \data -3: -.endm - -/* read 32-bit value from addr, "and" an immediate and write back */ -.macro ED_AND, addr, data - LDR r4, 1f - LDR r5, 2f - LDR r6, [r4] - AND r5, r6, r5 - STR r5, [r4] - B 3f -1: .long \addr -2: .long \data -3: -.endm - -#endif /* __ZBOOT_MACRO_H */ diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c deleted file mode 100644 index fd63ae6532fc..000000000000 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * sh73a0 processor support - INTC hardware block - * - * Copyright (C) 2010 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/module.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/irqchip.h> -#include <linux/irqchip/arm-gic.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "intc.h" -#include "irqs.h" -#include "sh73a0.h" - -enum { - UNUSED = 0, - - /* interrupt sources INTCS */ - PINTCS_PINT1, PINTCS_PINT2, - RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, - CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, - RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, - KEYSC_KEY, VINT, MSIOF, - TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, - CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, - CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, - RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, - RTDMAC_3_DEI10, RTDMAC_3_DEI11, - FRC, GCU, LCDC1, CSIRX, - DSITX0_DSITX00, DSITX0_DSITX01, - SPU2_SPU0, SPU2_SPU1, FSI, - TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, - TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, - VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, - DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, - MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, - SPUV, - - /* interrupt groups INTCS */ - RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, - DSITX0, SPU2, TMU1, MSU, -}; - -static struct intc_vect intcs_vectors[] = { - INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), - INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), - INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), - INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), - INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), - INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), - INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), - INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), - INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), - INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), - INTCS_VECT(MSIOF, 0x0d20), - INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), - INTCS_VECT(TMU0_TUNI02, 0x0ec0), - INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), - INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), - INTCS_VECT(MSUG, 0x0f80), - INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), - INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), - INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), - INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), - INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), - INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), - INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), - INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), - INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), - INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), - INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), - INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), - INTCS_VECT(FSI, 0x1840), - INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), - INTCS_VECT(TMU1_TUNI12, 0x1940), - INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), - INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), - INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), - INTCS_VECT(SCUW, 0x1b40), - INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), - INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), - INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), - INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), - INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), - INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), - INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), - INTCS_VECT(SPUV, 0x2300), -}; - -static struct intc_group intcs_groups[] __initdata = { - INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, - RTDMAC_0_DEI2, RTDMAC_0_DEI3), - INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), - INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, - RTDMAC_2_DEI8, RTDMAC_2_DEI9), - INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), - INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), - INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), - INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), - INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), -}; - -static struct intc_mask_reg intcs_mask_registers[] = { - { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ - { 0, 0, 0, CEU, - 0, 0, 0, 0 } }, - { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ - { 0, 0, 0, VPU, - BBIF2, 0, 0, MFI } }, - { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ - { 0, 0, 0, _2DDMAC_2DDM0, - 0, ASA, PEP, ICB } }, - { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ - { 0, 0, 0, CTI, - JPU_JPEG, 0, LCRC, LCDC } }, - { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ - { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, - RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, - { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ - { 0, 0, MSIOF, 0, - _3DG_SGX543, 0, 0, 0 } }, - { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ - { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, - 0, 0, 0, 0 } }, - { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ - { 0, 0, 0, 0, - 0, MSU_MSU, MSU_MSU2, MSUG } }, - { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ - { 0, RWDT0, CMT2, CMT0, - 0, 0, 0, 0 } }, - { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ - { 0, 0, 0, 0, - 0, TSIF1, LMB, TSIF0 } }, - { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ - { 0, 0, 0, 0, - 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, - { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ - { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, - RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, - { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ - { FRC, 0, 0, GCU, - LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, - { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ - { SPU2_SPU0, SPU2_SPU1, FSI, 0, - 0, 0, 0, 0 } }, - { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ - { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, - TSIF2, CMT4, 0, 0 } }, - { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ - { MFIS2, CPORTS2R, 0, 0, - 0, 0, 0, TSG } }, - { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ - { DMASCH1, 0, SCUW, VIO60, - VIO61, CEU21, 0, CSI21 } }, - { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ - { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, - EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, - { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ - { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, - 0, 0, 0, 0 } }, - { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ - { SPUV, 0, 0, 0, - 0, 0, 0, 0 } }, -}; - -/* Priority is needed for INTCA to receive the INTCS interrupt */ -static struct intc_prio_reg intcs_prio_registers[] = { - { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, - { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, - { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, - { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, - 0, 0 } }, - { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, - { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, - CMT2, CMT0 } }, - { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, - TMU0_TUNI02, TSIF1 } }, - { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, - { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, - { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, - { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, - { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, - { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, - { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, - { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, - { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, - { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, - { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, - { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, - { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, - { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, - { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, - { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, - DISP, DSRV } }, - { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, - MSTIF0_MST00I, MSTIF0_MST01I } }, - { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, - 0, 0 } }, - { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, -}; - -static struct resource intcs_resources[] __initdata = { - [0] = { - .start = 0xffd20000, - .end = 0xffd201ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xffd50000, - .end = 0xffd501ff, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = 0xffd60000, - .end = 0xffd601ff, - .flags = IORESOURCE_MEM, - } -}; - -static struct intc_desc intcs_desc __initdata = { - .name = "sh73a0-intcs", - .resource = intcs_resources, - .num_resources = ARRAY_SIZE(intcs_resources), - .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, - intcs_prio_registers, NULL, NULL), -}; - -static struct irqaction sh73a0_intcs_cascade; - -static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) -{ - unsigned int evtcodeas = ioread32((void __iomem *)dev_id); - - generic_handle_irq(intcs_evt2irq(evtcodeas)); - - return IRQ_HANDLED; -} - -#define PINTER0_PHYS 0xe69000a0 -#define PINTER1_PHYS 0xe69000a4 -#define PINTER0_VIRT IOMEM(0xe69000a0) -#define PINTER1_VIRT IOMEM(0xe69000a4) -#define PINTRR0 IOMEM(0xe69000d0) -#define PINTRR1 IOMEM(0xe69000d4) - -#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) -#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) -#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) -#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) -#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) - -INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \ - INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ - INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ - INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ - INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ - INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); - -INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \ - INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ - INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ - INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ - INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ - INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); - -static struct irqaction sh73a0_pint0_cascade; -static struct irqaction sh73a0_pint1_cascade; - -static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq) -{ - unsigned long value = ioread32(rr) & ioread32(er); - int k; - - for (k = 0; k < 32; k++) { - if (value & (1 << (31 - k))) { - generic_handle_irq(base_irq + k); - iowrite32(~(1 << (31 - k)), rr); - } - } -} - -static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) -{ - pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0)); - return IRQ_HANDLED; -} - -static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) -{ - pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0)); - return IRQ_HANDLED; -} - -void __init sh73a0_init_irq(void) -{ - void __iomem *gic_dist_base = IOMEM(0xf0001000); - void __iomem *gic_cpu_base = IOMEM(0xf0000100); - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); - - gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); - gic_init(0, 29, gic_dist_base, gic_cpu_base); - - register_intc_controller(&intcs_desc); - register_intc_controller(&intc_pint0_desc); - register_intc_controller(&intc_pint1_desc); - - /* demux using INTEVTSA */ - sh73a0_intcs_cascade.name = "INTCS cascade"; - sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; - sh73a0_intcs_cascade.dev_id = intevtsa; - setup_irq(gic_spi(50), &sh73a0_intcs_cascade); - - /* PINT pins are sanely tied to the GIC as SPI */ - sh73a0_pint0_cascade.name = "PINT0 cascade"; - sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; - setup_irq(gic_spi(33), &sh73a0_pint0_cascade); - - sh73a0_pint1_cascade.name = "PINT1 cascade"; - sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; - setup_irq(gic_spi(34), &sh73a0_pint1_cascade); -} diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index b0790fc32282..4e54512bee30 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -46,7 +46,7 @@ static int __maybe_unused apmu_power_on(void __iomem *p, int bit) return 0; } -static int apmu_power_off(void __iomem *p, int bit) +static int __maybe_unused apmu_power_off(void __iomem *p, int bit) { /* request Core Standby for next WFI */ writel_relaxed(3, p + CPUNCR_OFFS(bit)); @@ -67,7 +67,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) return 0; } -static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) +static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) { void __iomem *p = apmu_cpus[cpu].iomem; diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 3923e09e966d..b23378f3d7e1 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -31,8 +31,8 @@ void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg) } #ifdef CONFIG_HOTPLUG_CPU -int shmobile_smp_cpu_disable(unsigned int cpu) +bool shmobile_smp_cpu_can_disable(unsigned int cpu) { - return 0; /* Hotplug of any CPU is supported */ + return true; /* Hotplug of any CPU is supported */ } #endif diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c deleted file mode 100644 index 34608fcf0648..000000000000 --- a/arch/arm/mach-shmobile/pm-r8a7740.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * r8a7740 power management support - * - * Copyright (C) 2012 Renesas Solutions Corp. - * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/console.h> -#include <linux/io.h> -#include <linux/suspend.h> - -#include "common.h" -#include "pm-rmobile.h" - -#define SYSC_BASE IOMEM(0xe6180000) - -#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM) -static int r8a7740_pd_a3sm_suspend(void) -{ - /* - * The A3SM domain contains the CPU core and therefore it should - * only be turned off if the CPU is not in use. - */ - return -EBUSY; -} - -static int r8a7740_pd_a3sp_suspend(void) -{ - /* - * Serial consoles make use of SCIF hardware located in A3SP, - * keep such power domain on if "no_console_suspend" is set. - */ - return console_suspend_enabled ? 0 : -EBUSY; -} - -static int r8a7740_pd_d4_suspend(void) -{ - /* - * The D4 domain contains the Coresight-ETM hardware block and - * therefore it should only be turned off if the debug module is - * not in use. - */ - return -EBUSY; -} - -static struct rmobile_pm_domain r8a7740_pm_domains[] = { - { - .genpd.name = "A4LC", - .base = SYSC_BASE, - .bit_shift = 1, - }, { - .genpd.name = "A4MP", - .base = SYSC_BASE, - .bit_shift = 2, - }, { - .genpd.name = "D4", - .base = SYSC_BASE, - .bit_shift = 3, - .gov = &pm_domain_always_on_gov, - .suspend = r8a7740_pd_d4_suspend, - }, { - .genpd.name = "A4R", - .base = SYSC_BASE, - .bit_shift = 5, - }, { - .genpd.name = "A3RV", - .base = SYSC_BASE, - .bit_shift = 6, - }, { - .genpd.name = "A4S", - .base = SYSC_BASE, - .bit_shift = 10, - .no_debug = true, - }, { - .genpd.name = "A3SP", - .base = SYSC_BASE, - .bit_shift = 11, - .gov = &pm_domain_always_on_gov, - .no_debug = true, - .suspend = r8a7740_pd_a3sp_suspend, - }, { - .genpd.name = "A3SM", - .base = SYSC_BASE, - .bit_shift = 12, - .gov = &pm_domain_always_on_gov, - .suspend = r8a7740_pd_a3sm_suspend, - }, { - .genpd.name = "A3SG", - .base = SYSC_BASE, - .bit_shift = 13, - }, { - .genpd.name = "A4SU", - .base = SYSC_BASE, - .bit_shift = 20, - }, -}; - -void __init r8a7740_init_pm_domains(void) -{ - rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains)); - pm_genpd_add_subdomain_names("A4R", "A3RV"); - pm_genpd_add_subdomain_names("A4S", "A3SP"); - pm_genpd_add_subdomain_names("A4S", "A3SM"); - pm_genpd_add_subdomain_names("A4S", "A3SG"); -} -#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */ - -#ifdef CONFIG_SUSPEND -static int r8a7740_enter_suspend(suspend_state_t suspend_state) -{ - cpu_do_idle(); - return 0; -} - -static void r8a7740_suspend_init(void) -{ - shmobile_suspend_ops.enter = r8a7740_enter_suspend; -} -#else -static void r8a7740_suspend_init(void) {} -#endif - -void __init r8a7740_pm_init(void) -{ - r8a7740_suspend_init(); -} diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c index 44a74c4c5a01..47a862e7f8ba 100644 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ b/arch/arm/mach-shmobile/pm-r8a7779.c @@ -35,7 +35,8 @@ struct r8a7779_pm_domain { struct rcar_sysc_ch ch; }; -static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) +static inline +const struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) { return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; } @@ -83,7 +84,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) { struct generic_pm_domain *genpd = &r8a7779_pd->genpd; - genpd->flags = GENPD_FLAG_PM_CLK; pm_genpd_init(genpd, NULL, false); genpd->dev_ops.active_wakeup = pd_active_wakeup; genpd->power_off = pd_power_down; diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c index 00022ee56f80..0af05d288b09 100644 --- a/arch/arm/mach-shmobile/pm-rcar.c +++ b/arch/arm/mach-shmobile/pm-rcar.c @@ -12,35 +12,61 @@ #include <linux/err.h> #include <linux/mm.h> #include <linux/spinlock.h> -#include <asm/io.h> +#include <linux/io.h> #include "pm-rcar.h" -/* SYSC */ -#define SYSCSR 0x00 -#define SYSCISR 0x04 -#define SYSCISCR 0x08 +/* SYSC Common */ +#define SYSCSR 0x00 /* SYSC Status Register */ +#define SYSCISR 0x04 /* Interrupt Status Register */ +#define SYSCISCR 0x08 /* Interrupt Status Clear Register */ +#define SYSCIER 0x0c /* Interrupt Enable Register */ +#define SYSCIMR 0x10 /* Interrupt Mask Register */ -#define PWRSR_OFFS 0x00 -#define PWROFFCR_OFFS 0x04 -#define PWRONCR_OFFS 0x0c -#define PWRER_OFFS 0x14 +/* SYSC Status Register */ +#define SYSCSR_PONENB 1 /* Ready for power resume requests */ +#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */ -#define SYSCSR_RETRIES 100 -#define SYSCSR_DELAY_US 1 +/* + * Power Control Register Offsets inside the register block for each domain + * Note: The "CR" registers for ARM cores exist on H1 only + * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2 + */ +#define PWRSR_OFFS 0x00 /* Power Status Register */ +#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */ +#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */ +#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */ +#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */ +#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */ + + +#define SYSCSR_RETRIES 100 +#define SYSCSR_DELAY_US 1 + +#define PWRER_RETRIES 100 +#define PWRER_DELAY_US 1 -#define SYSCISR_RETRIES 1000 -#define SYSCISR_DELAY_US 1 +#define SYSCISR_RETRIES 1000 +#define SYSCISR_DELAY_US 1 static void __iomem *rcar_sysc_base; static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ -static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, - int sr_bit, int reg_offs) +static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on) { + unsigned int sr_bit, reg_offs; int k; + if (on) { + sr_bit = SYSCSR_PONENB; + reg_offs = PWRONCR_OFFS; + } else { + sr_bit = SYSCSR_POFFENB; + reg_offs = PWROFFCR_OFFS; + } + + /* Wait until SYSC is ready to accept a power request */ for (k = 0; k < SYSCSR_RETRIES; k++) { - if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit)) + if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit)) break; udelay(SYSCSR_DELAY_US); } @@ -48,27 +74,17 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, if (k == SYSCSR_RETRIES) return -EAGAIN; - iowrite32(1 << sysc_ch->chan_bit, + /* Submit power shutoff or power resume request */ + iowrite32(BIT(sysc_ch->chan_bit), rcar_sysc_base + sysc_ch->chan_offs + reg_offs); return 0; } -static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch) -{ - return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS); -} - -static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch) +static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) { - return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS); -} - -static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, - int (*on_off_fn)(struct rcar_sysc_ch *)) -{ - unsigned int isr_mask = 1 << sysc_ch->isr_bit; - unsigned int chan_mask = 1 << sysc_ch->chan_bit; + unsigned int isr_mask = BIT(sysc_ch->isr_bit); + unsigned int chan_mask = BIT(sysc_ch->chan_bit); unsigned int status; unsigned long flags; int ret = 0; @@ -78,15 +94,26 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); - do { - ret = on_off_fn(sysc_ch); + /* Submit power shutoff or resume request until it was accepted */ + for (k = 0; k < PWRER_RETRIES; k++) { + ret = rcar_sysc_pwr_on_off(sysc_ch, on); if (ret) goto out; status = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRER_OFFS); - } while (status & chan_mask); + if (!(status & chan_mask)) + break; + + udelay(PWRER_DELAY_US); + } + + if (k == PWRER_RETRIES) { + ret = -EIO; + goto out; + } + /* Wait until the power shutoff or resume request has completed * */ for (k = 0; k < SYSCISR_RETRIES; k++) { if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask) break; @@ -106,22 +133,22 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, return ret; } -int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch) +int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) { - return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off); + return rcar_sysc_power(sysc_ch, false); } -int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch) +int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) { - return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on); + return rcar_sysc_power(sysc_ch, true); } -bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch) +bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch) { unsigned int st; st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS); - if (st & (1 << sysc_ch->chan_bit)) + if (st & BIT(sysc_ch->chan_bit)) return true; return false; diff --git a/arch/arm/mach-shmobile/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h index ef3a1ef628f1..1b901db4a24c 100644 --- a/arch/arm/mach-shmobile/pm-rcar.h +++ b/arch/arm/mach-shmobile/pm-rcar.h @@ -2,14 +2,14 @@ #define PM_RCAR_H struct rcar_sysc_ch { - unsigned long chan_offs; - unsigned int chan_bit; - unsigned int isr_bit; + u16 chan_offs; + u8 chan_bit; + u8 isr_bit; }; -int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch); -int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch); -bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch); +int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch); +int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch); +bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch); void __iomem *rcar_sysc_init(phys_addr_t base); #endif /* PM_RCAR_H */ diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index 95018209ff0b..a5b96b990aea 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -34,6 +34,12 @@ #define PSTR_RETRIES 100 #define PSTR_DELAY_US 10 +static inline +struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) +{ + return container_of(d, struct rmobile_pm_domain, genpd); +} + static int rmobile_pd_power_down(struct generic_pm_domain *genpd) { struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); @@ -42,7 +48,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) if (rmobile_pd->bit_shift == ~0) return -EBUSY; - mask = 1 << rmobile_pd->bit_shift; + mask = BIT(rmobile_pd->bit_shift); if (rmobile_pd->suspend) { int ret = rmobile_pd->suspend(); @@ -79,7 +85,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd, if (rmobile_pd->bit_shift == ~0) return 0; - mask = 1 << rmobile_pd->bit_shift; + mask = BIT(rmobile_pd->bit_shift); if (__raw_readl(rmobile_pd->base + PSTR) & mask) goto out; @@ -163,43 +169,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) __rmobile_pd_power_up(rmobile_pd, false); } -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY - -void rmobile_init_domains(struct rmobile_pm_domain domains[], int num) -{ - int j; - - for (j = 0; j < num; j++) - rmobile_init_pm_domain(&domains[j]); -} - -void rmobile_add_device_to_domain_td(const char *domain_name, - struct platform_device *pdev, - struct gpd_timing_data *td) -{ - struct device *dev = &pdev->dev; - - __pm_genpd_name_add_device(domain_name, dev, td); -} - -void rmobile_add_devices_to_domains(struct pm_domain_device data[], - int size) -{ - struct gpd_timing_data latencies = { - .stop_latency_ns = DEFAULT_DEV_LATENCY_NS, - .start_latency_ns = DEFAULT_DEV_LATENCY_NS, - .save_state_latency_ns = DEFAULT_DEV_LATENCY_NS, - .restore_state_latency_ns = DEFAULT_DEV_LATENCY_NS, - }; - int j; - - for (j = 0; j < size; j++) - rmobile_add_device_to_domain_td(data[j].domain_name, - data[j].pdev, &latencies); -} - -#else /* !CONFIG_ARCH_SHMOBILE_LEGACY */ - static int rmobile_pd_suspend_busy(void) { /* @@ -430,5 +399,3 @@ static int __init rmobile_init_pm_domains(void) } core_initcall(rmobile_init_pm_domains); - -#endif /* !CONFIG_ARCH_SHMOBILE_LEGACY */ diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h index 53219786f539..30a4a421ee31 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.h +++ b/arch/arm/mach-shmobile/pm-rmobile.h @@ -26,39 +26,9 @@ struct rmobile_pm_domain { bool no_debug; }; -static inline -struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) -{ - return container_of(d, struct rmobile_pm_domain, genpd); -} - struct pm_domain_device { const char *domain_name; struct platform_device *pdev; }; -#if defined(CONFIG_PM_RMOBILE) && defined(CONFIG_ARCH_SHMOBILE_LEGACY) -extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num); -extern void rmobile_add_device_to_domain_td(const char *domain_name, - struct platform_device *pdev, - struct gpd_timing_data *td); - -static inline void rmobile_add_device_to_domain(const char *domain_name, - struct platform_device *pdev) -{ - rmobile_add_device_to_domain_td(domain_name, pdev, NULL); -} - -extern void rmobile_add_devices_to_domains(struct pm_domain_device data[], - int size); -#else - -#define rmobile_init_domains(domains, num) do { } while (0) -#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0) -#define rmobile_add_device_to_domain(name, pdev) do { } while (0) - -static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[], - int size) {} -#endif /* CONFIG_PM_RMOBILE */ - #endif /* PM_RMOBILE_H */ diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c deleted file mode 100644 index a7e466817965..000000000000 --- a/arch/arm/mach-shmobile/pm-sh73a0.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * sh73a0 Power management support - * - * Copyright (C) 2012 Bastian Hecht <hechtb+renesas@gmail.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include <linux/suspend.h> -#include "common.h" - -#ifdef CONFIG_SUSPEND -static int sh73a0_enter_suspend(suspend_state_t suspend_state) -{ - cpu_do_idle(); - return 0; -} - -static void sh73a0_suspend_init(void) -{ - shmobile_suspend_ops.enter = sh73a0_enter_suspend; -} -#else -static void sh73a0_suspend_init(void) {} -#endif - -void __init sh73a0_pm_init(void) -{ - sh73a0_suspend_init(); -} diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h deleted file mode 100644 index ca7805ad7ea3..000000000000 --- a/arch/arm/mach-shmobile/r8a7740.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_R8A7740_H__ -#define __ASM_R8A7740_H__ - -/* - * MD_CKx pin - */ -#define MD_CK2 (1 << 2) -#define MD_CK1 (1 << 1) -#define MD_CK0 (1 << 0) - -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_SDHI0_RX, - SHDMA_SLAVE_SDHI0_TX, - SHDMA_SLAVE_SDHI1_RX, - SHDMA_SLAVE_SDHI1_TX, - SHDMA_SLAVE_SDHI2_RX, - SHDMA_SLAVE_SDHI2_TX, - SHDMA_SLAVE_FSIA_RX, - SHDMA_SLAVE_FSIA_TX, - SHDMA_SLAVE_FSIB_TX, - SHDMA_SLAVE_USBHS_TX, - SHDMA_SLAVE_USBHS_RX, - SHDMA_SLAVE_MMCIF_TX, - SHDMA_SLAVE_MMCIF_RX, -}; - -extern void r8a7740_meram_workaround(void); -extern void r8a7740_init_irq_of(void); -extern void r8a7740_map_io(void); -extern void r8a7740_add_early_devices(void); -extern void r8a7740_add_standard_devices(void); -extern void r8a7740_clock_init(u8 md_ck); -extern void r8a7740_pinmux_init(void); -extern void r8a7740_pm_init(void); - -#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM) -extern void __init r8a7740_init_pm_domains(void); -#else -static inline void r8a7740_init_pm_domains(void) {} -#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */ - -#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h index 19f97046dd70..db303f76704e 100644 --- a/arch/arm/mach-shmobile/r8a7779.h +++ b/arch/arm/mach-shmobile/r8a7779.h @@ -3,26 +3,7 @@ #include <linux/sh_clk.h> -/* HPB-DMA slave IDs */ -enum { - HPBDMA_SLAVE_DUMMY, - HPBDMA_SLAVE_SDHI0_TX, - HPBDMA_SLAVE_SDHI0_RX, -}; - -extern void r8a7779_init_irq_extpin(int irlm); -extern void r8a7779_init_irq_extpin_dt(int irlm); -extern void r8a7779_init_irq_dt(void); -extern void r8a7779_map_io(void); -extern void r8a7779_earlytimer_init(void); -extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_standard_devices(void); -extern void r8a7779_init_late(void); -extern u32 r8a7779_read_mode_pins(void); -extern void r8a7779_clock_init(void); -extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); -extern void r8a7779_register_twd(void); #ifdef CONFIG_PM extern void __init r8a7779_init_pm_domains(void); diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c index 384e6e934b87..62437b57813e 100644 --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c @@ -123,7 +123,8 @@ static int __init rcar_gen2_regulator_quirk(void) u32 mon; if (!of_machine_is_compatible("renesas,koelsch") && - !of_machine_is_compatible("renesas,lager")) + !of_machine_is_compatible("renesas,lager") && + !of_machine_is_compatible("renesas,gose")) return -ENODEV; irqc = ioremap(IRQC_BASE, PAGE_SIZE); diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index 171174777b6f..d46639fc6849 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -20,7 +20,7 @@ #include "common.h" -static const char *r7s72100_boards_compat_dt[] __initdata = { +static const char *const r7s72100_boards_compat_dt[] __initconst = { "renesas,r7s72100", NULL, }; diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 446cee611902..20173c4f415d 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -20,7 +20,7 @@ #include "common.h" -static const char *r8a73a4_boards_compat_dt[] __initdata = { +static const char *const r8a73a4_boards_compat_dt[] __initconst = { "renesas,r8a73a4", NULL, }; diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 00291cc1772d..0c8f80c5b04d 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -13,31 +13,19 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <linux/dma-mapping.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> #include <linux/irqchip.h> #include <linux/irqchip/arm-gic.h> -#include <linux/platform_data/irq-renesas-intc-irqpin.h> -#include <linux/platform_device.h> #include <linux/of_platform.h> -#include <linux/serial_sci.h> -#include <linux/sh_dma.h> -#include <linux/sh_timer.h> -#include <linux/platform_data/sh_ipmmu.h> -#include <asm/mach-types.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/hardware/cache-l2x0.h> #include "common.h" -#include "dma-register.h" -#include "irqs.h" -#include "pm-rmobile.h" -#include "r8a7740.h" static struct map_desc r8a7740_io_desc[] __initdata = { /* @@ -64,613 +52,12 @@ static struct map_desc r8a7740_io_desc[] __initdata = { #endif }; -void __init r8a7740_map_io(void) +static void __init r8a7740_map_io(void) { debug_ll_io_init(); iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); } -/* PFC */ -static const struct resource pfc_resources[] = { - DEFINE_RES_MEM(0xe6050000, 0x8000), - DEFINE_RES_MEM(0xe605800c, 0x0020), -}; - -void __init r8a7740_pinmux_init(void) -{ - platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); -} - -static struct renesas_intc_irqpin_config irqpin0_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ -}; - -static struct resource irqpin0_resources[] = { - DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ - DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ - DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ - DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ - DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ -}; - -static struct platform_device irqpin0_device = { - .name = "renesas_intc_irqpin", - .id = 0, - .resource = irqpin0_resources, - .num_resources = ARRAY_SIZE(irqpin0_resources), - .dev = { - .platform_data = &irqpin0_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin1_platform_data = { - .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ -}; - -static struct resource irqpin1_resources[] = { - DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ - DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ - DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ - DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ - DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ -}; - -static struct platform_device irqpin1_device = { - .name = "renesas_intc_irqpin", - .id = 1, - .resource = irqpin1_resources, - .num_resources = ARRAY_SIZE(irqpin1_resources), - .dev = { - .platform_data = &irqpin1_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin2_platform_data = { - .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ -}; - -static struct resource irqpin2_resources[] = { - DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ -}; - -static struct platform_device irqpin2_device = { - .name = "renesas_intc_irqpin", - .id = 2, - .resource = irqpin2_resources, - .num_resources = ARRAY_SIZE(irqpin2_resources), - .dev = { - .platform_data = &irqpin2_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin3_platform_data = { - .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ -}; - -static struct resource irqpin3_resources[] = { - DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ -}; - -static struct platform_device irqpin3_device = { - .name = "renesas_intc_irqpin", - .id = 3, - .resource = irqpin3_resources, - .num_resources = ARRAY_SIZE(irqpin3_resources), - .dev = { - .platform_data = &irqpin3_platform_data, - }, -}; - -/* SCIF */ -#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ -static struct plat_sci_port scif##index##_platform_data = { \ - .type = scif_type, \ - .flags = UPF_BOOT_AUTOCONF, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -}; \ - \ -static struct resource scif##index##_resources[] = { \ - DEFINE_RES_MEM(baseaddr, 0x100), \ - DEFINE_RES_IRQ(irq), \ -}; \ - \ -static struct platform_device scif##index##_device = { \ - .name = "sh-sci", \ - .id = index, \ - .resource = scif##index##_resources, \ - .num_resources = ARRAY_SIZE(scif##index##_resources), \ - .dev = { \ - .platform_data = &scif##index##_platform_data, \ - }, \ -} - -R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); -R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); -R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); -R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); -R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); -R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); -R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); -R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); -R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); - -/* CMT */ -static struct sh_timer_config cmt1_platform_data = { - .channels_mask = 0x3f, -}; - -static struct resource cmt1_resources[] = { - DEFINE_RES_MEM(0xe6138000, 0x170), - DEFINE_RES_IRQ(gic_spi(58)), -}; - -static struct platform_device cmt1_device = { - .name = "sh-cmt-48", - .id = 1, - .dev = { - .platform_data = &cmt1_platform_data, - }, - .resource = cmt1_resources, - .num_resources = ARRAY_SIZE(cmt1_resources), -}; - -/* TMU */ -static struct sh_timer_config tmu0_platform_data = { - .channels_mask = 7, -}; - -static struct resource tmu0_resources[] = { - DEFINE_RES_MEM(0xfff80000, 0x2c), - DEFINE_RES_IRQ(gic_spi(198)), - DEFINE_RES_IRQ(gic_spi(199)), - DEFINE_RES_IRQ(gic_spi(200)), -}; - -static struct platform_device tmu0_device = { - .name = "sh-tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, - }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), -}; - -/* IPMMUI (an IPMMU module for ICB/LMB) */ -static struct resource ipmmu_resources[] = { - [0] = { - .name = "IPMMUI", - .start = 0xfe951000, - .end = 0xfe9510ff, - .flags = IORESOURCE_MEM, - }, -}; - -static const char * const ipmmu_dev_names[] = { - "sh_mobile_lcdc_fb.0", - "sh_mobile_lcdc_fb.1", - "sh_mobile_ceu.0", -}; - -static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { - .dev_names = ipmmu_dev_names, - .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), -}; - -static struct platform_device ipmmu_device = { - .name = "ipmmu", - .id = -1, - .dev = { - .platform_data = &ipmmu_platform_data, - }, - .resource = ipmmu_resources, - .num_resources = ARRAY_SIZE(ipmmu_resources), -}; - -static struct platform_device *r8a7740_early_devices[] __initdata = { - &scif0_device, - &scif1_device, - &scif2_device, - &scif3_device, - &scif4_device, - &scif5_device, - &scif6_device, - &scif7_device, - &scif8_device, - &irqpin0_device, - &irqpin1_device, - &irqpin2_device, - &irqpin3_device, - &tmu0_device, - &ipmmu_device, - &cmt1_device, -}; - -/* DMA */ -static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { - { - .slave_id = SHDMA_SLAVE_SDHI0_TX, - .addr = 0xe6850030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc1, - }, { - .slave_id = SHDMA_SLAVE_SDHI0_RX, - .addr = 0xe6850030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xc2, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_TX, - .addr = 0xe6860030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc9, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_RX, - .addr = 0xe6860030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xca, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_TX, - .addr = 0xe6870030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xcd, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_RX, - .addr = 0xe6870030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xce, - }, { - .slave_id = SHDMA_SLAVE_FSIA_TX, - .addr = 0xfe1f0024, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xb1, - }, { - .slave_id = SHDMA_SLAVE_FSIA_RX, - .addr = 0xfe1f0020, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xb2, - }, { - .slave_id = SHDMA_SLAVE_FSIB_TX, - .addr = 0xfe1f0064, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xb5, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_TX, - .addr = 0xe6bd0034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_RX, - .addr = 0xe6bd0034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd2, - }, -}; - -#define DMA_CHANNEL(a, b, c) \ -{ \ - .offset = a, \ - .dmars = b, \ - .dmars_bit = c, \ - .chclr_offset = (0x220 - 0x20) + a \ -} - -static const struct sh_dmae_channel r8a7740_dmae_channels[] = { - DMA_CHANNEL(0x00, 0, 0), - DMA_CHANNEL(0x10, 0, 8), - DMA_CHANNEL(0x20, 4, 0), - DMA_CHANNEL(0x30, 4, 8), - DMA_CHANNEL(0x50, 8, 0), - DMA_CHANNEL(0x60, 8, 8), -}; - -static struct sh_dmae_pdata dma_platform_data = { - .slave = r8a7740_dmae_slaves, - .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves), - .channel = r8a7740_dmae_channels, - .channel_num = ARRAY_SIZE(r8a7740_dmae_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, - .chclr_present = 1, -}; - -/* Resource order important! */ -static struct resource r8a7740_dmae0_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe008020, - .end = 0xfe00828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe009000, - .end = 0xfe00900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = gic_spi(34), - .end = gic_spi(34), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = gic_spi(28), - .end = gic_spi(33), - .flags = IORESOURCE_IRQ, - }, -}; - -/* Resource order important! */ -static struct resource r8a7740_dmae1_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe018020, - .end = 0xfe01828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe019000, - .end = 0xfe01900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = gic_spi(41), - .end = gic_spi(41), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = gic_spi(35), - .end = gic_spi(40), - .flags = IORESOURCE_IRQ, - }, -}; - -/* Resource order important! */ -static struct resource r8a7740_dmae2_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe028020, - .end = 0xfe02828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe029000, - .end = 0xfe02900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = gic_spi(48), - .end = gic_spi(48), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = gic_spi(42), - .end = gic_spi(47), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dma0_device = { - .name = "sh-dma-engine", - .id = 0, - .resource = r8a7740_dmae0_resources, - .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -static struct platform_device dma1_device = { - .name = "sh-dma-engine", - .id = 1, - .resource = r8a7740_dmae1_resources, - .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -static struct platform_device dma2_device = { - .name = "sh-dma-engine", - .id = 2, - .resource = r8a7740_dmae2_resources, - .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -/* USB-DMAC */ -static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = { - { - .offset = 0, - }, { - .offset = 0x20, - }, -}; - -static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = { - { - .slave_id = SHDMA_SLAVE_USBHS_TX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, { - .slave_id = SHDMA_SLAVE_USBHS_RX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, -}; - -static struct sh_dmae_pdata usb_dma_platform_data = { - .slave = r8a7740_usb_dma_slaves, - .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves), - .channel = r8a7740_usb_dma_channels, - .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels), - .ts_low_shift = USBTS_LOW_SHIFT, - .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, - .ts_high_shift = USBTS_HI_SHIFT, - .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, - .ts_shift = dma_usbts_shift, - .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), - .dmaor_init = DMAOR_DME, - .chcr_offset = 0x14, - .chcr_ie_bit = 1 << 5, - .dmaor_is_32bit = 1, - .needs_tend_set = 1, - .no_dmars = 1, - .slave_only = 1, -}; - -static struct resource r8a7740_usb_dma_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xe68a0020, - .end = 0xe68a0064 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* VCR/SWR/DMICR */ - .start = 0xe68a0000, - .end = 0xe68a0014 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* IRQ for channels */ - .start = gic_spi(49), - .end = gic_spi(49), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usb_dma_device = { - .name = "sh-dma-engine", - .id = 3, - .resource = r8a7740_usb_dma_resources, - .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources), - .dev = { - .platform_data = &usb_dma_platform_data, - }, -}; - -/* I2C */ -static struct resource i2c0_resources[] = { - [0] = { - .name = "IIC0", - .start = 0xfff20000, - .end = 0xfff20425 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(201), - .end = gic_spi(204), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - [0] = { - .name = "IIC1", - .start = 0xe6c20000, - .end = 0xe6c20425 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_spi(70), /* IIC1_ALI1 */ - .end = gic_spi(73), /* IIC1_DTEI1 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c0_device = { - .name = "i2c-sh_mobile", - .id = 0, - .resource = i2c0_resources, - .num_resources = ARRAY_SIZE(i2c0_resources), -}; - -static struct platform_device i2c1_device = { - .name = "i2c-sh_mobile", - .id = 1, - .resource = i2c1_resources, - .num_resources = ARRAY_SIZE(i2c1_resources), -}; - -static struct resource pmu_resources[] = { - [0] = { - .start = gic_spi(83), - .end = gic_spi(83), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device pmu_device = { - .name = "armv7-pmu", - .id = -1, - .num_resources = ARRAY_SIZE(pmu_resources), - .resource = pmu_resources, -}; - -static struct platform_device *r8a7740_late_devices[] __initdata = { - &i2c0_device, - &i2c1_device, - &dma0_device, - &dma1_device, - &dma2_device, - &usb_dma_device, - &pmu_device, -}; - /* * r8a7740 chip has lasting errata on MERAM buffer. * this is work-around for it. @@ -678,7 +65,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = { * "Media RAM (MERAM)" on r8a7740 documentation */ #define MEBUFCNTR 0xFE950098 -void __init r8a7740_meram_workaround(void) +static void __init r8a7740_meram_workaround(void) { void __iomem *reg; @@ -689,70 +76,13 @@ void __init r8a7740_meram_workaround(void) } } -void __init r8a7740_add_standard_devices(void) -{ - static struct pm_domain_device domain_devices[] __initdata = { - { "A4R", &tmu0_device }, - { "A4R", &i2c0_device }, - { "A4S", &irqpin0_device }, - { "A4S", &irqpin1_device }, - { "A4S", &irqpin2_device }, - { "A4S", &irqpin3_device }, - { "A3SP", &scif0_device }, - { "A3SP", &scif1_device }, - { "A3SP", &scif2_device }, - { "A3SP", &scif3_device }, - { "A3SP", &scif4_device }, - { "A3SP", &scif5_device }, - { "A3SP", &scif6_device }, - { "A3SP", &scif7_device }, - { "A3SP", &scif8_device }, - { "A3SP", &i2c1_device }, - { "A3SP", &ipmmu_device }, - { "A3SP", &dma0_device }, - { "A3SP", &dma1_device }, - { "A3SP", &dma2_device }, - { "A3SP", &usb_dma_device }, - }; - - r8a7740_init_pm_domains(); - - /* add devices */ - platform_add_devices(r8a7740_early_devices, - ARRAY_SIZE(r8a7740_early_devices)); - platform_add_devices(r8a7740_late_devices, - ARRAY_SIZE(r8a7740_late_devices)); - - /* add devices to PM domain */ - rmobile_add_devices_to_domains(domain_devices, - ARRAY_SIZE(domain_devices)); -} - -void __init r8a7740_add_early_devices(void) -{ - early_platform_add_devices(r8a7740_early_devices, - ARRAY_SIZE(r8a7740_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); -} - -#ifdef CONFIG_USE_OF - -void __init r8a7740_init_irq_of(void) +static void __init r8a7740_init_irq_of(void) { void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY - void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); - void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); - - gic_init(0, 29, gic_dist_base, gic_cpu_base); -#else irqchip_init(); -#endif /* route signals to GIC */ iowrite32(0x0, pfc_inta_ctrl); @@ -787,7 +117,7 @@ static void __init r8a7740_generic_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char *r8a7740_boards_compat_dt[] __initdata = { +static const char *const r8a7740_boards_compat_dt[] __initconst = { "renesas,r8a7740", NULL, }; @@ -800,5 +130,3 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .init_late = shmobile_init_late, .dt_compat = r8a7740_boards_compat_dt, MACHINE_END - -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index c49aa094fe17..b9116c81e54b 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -615,7 +615,7 @@ void __init r8a7778_init_irq_dt(void) iounmap(base); } -static const char *r8a7778_compat_dt[] __initdata = { +static const char *const r8a7778_compat_dt[] __initconst = { "renesas,r8a7778", NULL, }; diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index c03e562be12b..6bfa6407a27c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -14,37 +14,17 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <linux/kernel.h> +#include <linux/clk/shmobile.h> +#include <linux/clocksource.h> #include <linux/init.h> -#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip.h> #include <linux/irqchip/arm-gic.h> -#include <linux/of_platform.h> -#include <linux/platform_data/dma-rcar-hpbdma.h> -#include <linux/platform_data/gpio-rcar.h> -#include <linux/platform_data/irq-renesas-intc-irqpin.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/serial_sci.h> -#include <linux/sh_timer.h> -#include <linux/dma-mapping.h> -#include <linux/usb/otg.h> -#include <linux/usb/hcd.h> -#include <linux/usb/ehci_pdriver.h> -#include <linux/usb/ohci_pdriver.h> -#include <linux/pm_runtime.h> -#include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/time.h> #include <asm/mach/map.h> -#include <asm/hardware/cache-l2x0.h> #include "common.h" -#include "irqs.h" #include "r8a7779.h" static struct map_desc r8a7779_io_desc[] __initdata = { @@ -64,7 +44,7 @@ static struct map_desc r8a7779_io_desc[] __initdata = { }, }; -void __init r8a7779_map_io(void) +static void __init r8a7779_map_io(void) { debug_ll_io_init(); iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); @@ -80,652 +60,10 @@ void __init r8a7779_map_io(void) #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) -static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ - .sense_bitfield_width = 2, -}; - -static struct resource irqpin0_resources[] __initdata = { - DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ - DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ - DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ - DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ - DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ -}; - -void __init r8a7779_init_irq_extpin_dt(int irlm) -{ - void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); - u32 tmp; - - if (!icr0) { - pr_warn("r8a7779: unable to setup external irq pin mode\n"); - return; - } - - tmp = ioread32(icr0); - if (irlm) - tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ - else - tmp &= ~(1 << 23); /* IRL mode - not supported */ - tmp |= (1 << 21); /* LVLMODE = 1 */ - iowrite32(tmp, icr0); - iounmap(icr0); -} - -void __init r8a7779_init_irq_extpin(int irlm) -{ - r8a7779_init_irq_extpin_dt(irlm); - if (irlm) - platform_device_register_resndata( - NULL, "renesas_intc_irqpin", -1, - irqpin0_resources, ARRAY_SIZE(irqpin0_resources), - &irqpin0_platform_data, sizeof(irqpin0_platform_data)); -} - -/* PFC/GPIO */ -static struct resource r8a7779_pfc_resources[] = { - DEFINE_RES_MEM(0xfffc0000, 0x023c), -}; - -static struct platform_device r8a7779_pfc_device = { - .name = "pfc-r8a7779", - .id = -1, - .resource = r8a7779_pfc_resources, - .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), -}; - -#define R8A7779_GPIO(idx, npins) \ -static struct resource r8a7779_gpio##idx##_resources[] = { \ - DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ - DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ -}; \ - \ -static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ - .gpio_base = 32 * (idx), \ - .irq_base = 0, \ - .number_of_pins = npins, \ - .pctl_name = "pfc-r8a7779", \ -}; \ - \ -static struct platform_device r8a7779_gpio##idx##_device = { \ - .name = "gpio_rcar", \ - .id = idx, \ - .resource = r8a7779_gpio##idx##_resources, \ - .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ - .dev = { \ - .platform_data = &r8a7779_gpio##idx##_platform_data, \ - }, \ -} - -R8A7779_GPIO(0, 32); -R8A7779_GPIO(1, 32); -R8A7779_GPIO(2, 32); -R8A7779_GPIO(3, 32); -R8A7779_GPIO(4, 32); -R8A7779_GPIO(5, 32); -R8A7779_GPIO(6, 9); - -static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { - &r8a7779_pfc_device, - &r8a7779_gpio0_device, - &r8a7779_gpio1_device, - &r8a7779_gpio2_device, - &r8a7779_gpio3_device, - &r8a7779_gpio4_device, - &r8a7779_gpio5_device, - &r8a7779_gpio6_device, -}; - -void __init r8a7779_pinmux_init(void) -{ - platform_add_devices(r8a7779_pinctrl_devices, - ARRAY_SIZE(r8a7779_pinctrl_devices)); -} - -/* SCIF */ -#define R8A7779_SCIF(index, baseaddr, irq) \ -static struct plat_sci_port scif##index##_platform_data = { \ - .type = PORT_SCIF, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ -}; \ - \ -static struct resource scif##index##_resources[] = { \ - DEFINE_RES_MEM(baseaddr, 0x100), \ - DEFINE_RES_IRQ(irq), \ -}; \ - \ -static struct platform_device scif##index##_device = { \ - .name = "sh-sci", \ - .id = index, \ - .resource = scif##index##_resources, \ - .num_resources = ARRAY_SIZE(scif##index##_resources), \ - .dev = { \ - .platform_data = &scif##index##_platform_data, \ - }, \ -} - -R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); -R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); -R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); -R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); -R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); -R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); - -/* TMU */ -static struct sh_timer_config tmu0_platform_data = { - .channels_mask = 7, -}; - -static struct resource tmu0_resources[] = { - DEFINE_RES_MEM(0xffd80000, 0x30), - DEFINE_RES_IRQ(gic_iid(0x40)), - DEFINE_RES_IRQ(gic_iid(0x41)), - DEFINE_RES_IRQ(gic_iid(0x42)), -}; - -static struct platform_device tmu0_device = { - .name = "sh-tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, - }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), -}; - -/* I2C */ -static struct resource rcar_i2c0_res[] = { - { - .start = 0xffc70000, - .end = 0xffc70fff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0x6f), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c0_device = { - .name = "i2c-rcar", - .id = 0, - .resource = rcar_i2c0_res, - .num_resources = ARRAY_SIZE(rcar_i2c0_res), -}; - -static struct resource rcar_i2c1_res[] = { - { - .start = 0xffc71000, - .end = 0xffc71fff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0x72), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c1_device = { - .name = "i2c-rcar", - .id = 1, - .resource = rcar_i2c1_res, - .num_resources = ARRAY_SIZE(rcar_i2c1_res), -}; - -static struct resource rcar_i2c2_res[] = { - { - .start = 0xffc72000, - .end = 0xffc72fff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0x70), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c2_device = { - .name = "i2c-rcar", - .id = 2, - .resource = rcar_i2c2_res, - .num_resources = ARRAY_SIZE(rcar_i2c2_res), -}; - -static struct resource rcar_i2c3_res[] = { - { - .start = 0xffc73000, - .end = 0xffc73fff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0x71), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c3_device = { - .name = "i2c-rcar", - .id = 3, - .resource = rcar_i2c3_res, - .num_resources = ARRAY_SIZE(rcar_i2c3_res), -}; - -static struct resource sata_resources[] = { - [0] = { - .name = "rcar-sata", - .start = 0xfc600000, - .end = 0xfc601fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x84), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sata_device = { - .name = "sata_rcar", - .id = -1, - .resource = sata_resources, - .num_resources = ARRAY_SIZE(sata_resources), - .dev = { - .dma_mask = &sata_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* USB */ -static struct usb_phy *phy; - -static int usb_power_on(struct platform_device *pdev) -{ - if (IS_ERR(phy)) - return PTR_ERR(phy); - - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - - usb_phy_init(phy); - - return 0; -} - -static void usb_power_off(struct platform_device *pdev) -{ - if (IS_ERR(phy)) - return; - - usb_phy_shutdown(phy); - - pm_runtime_put_sync(&pdev->dev); - pm_runtime_disable(&pdev->dev); -} - -static int ehci_init_internal_buffer(struct usb_hcd *hcd) +static void __init r8a7779_init_irq_dt(void) { - /* - * Below are recommended values from the datasheet; - * see [USB :: Setting of EHCI Internal Buffer]. - */ - /* EHCI IP internal buffer setting */ - iowrite32(0x00ff0040, hcd->regs + 0x0094); - /* EHCI IP internal buffer enable */ - iowrite32(0x00000001, hcd->regs + 0x009C); - - return 0; -} - -static struct usb_ehci_pdata ehcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, - .pre_setup = ehci_init_internal_buffer, -}; - -static struct resource ehci0_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci0_device = { - .name = "ehci-platform", - .id = 0, - .dev = { - .dma_mask = &ehci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci0_resources), - .resource = ehci0_resources, -}; - -static struct resource ehci1_resources[] = { - [0] = { - .start = 0xfff70000, - .end = 0xfff70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci1_device = { - .name = "ehci-platform", - .id = 1, - .dev = { - .dma_mask = &ehci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci1_resources), - .resource = ehci1_resources, -}; - -static struct usb_ohci_pdata ohcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, -}; - -static struct resource ohci0_resources[] = { - [0] = { - .start = 0xffe70400, - .end = 0xffe70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci0_device = { - .name = "ohci-platform", - .id = 0, - .dev = { - .dma_mask = &ohci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci0_resources), - .resource = ohci0_resources, -}; - -static struct resource ohci1_resources[] = { - [0] = { - .start = 0xfff70400, - .end = 0xfff70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci1_device = { - .name = "ohci-platform", - .id = 1, - .dev = { - .dma_mask = &ohci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci1_resources), - .resource = ohci1_resources, -}; - -/* HPB-DMA */ - -/* Asynchronous mode register bits */ -#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ - -static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { - { - .id = HPBDMA_SLAVE_SDHI0_TX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DMDL | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | - HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, - .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | - HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 21, - }, { - .id = HPBDMA_SLAVE_SDHI0_RX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SMDL | - HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | - HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, - .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | - HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 22, - }, -}; - -static const struct hpb_dmae_channel hpb_dmae_channels[] = { - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ -}; - -static struct hpb_dmae_pdata dma_platform_data __initdata = { - .slaves = hpb_dmae_slaves, - .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), - .channels = hpb_dmae_channels, - .num_channels = ARRAY_SIZE(hpb_dmae_channels), - .ts_shift = { - [XMIT_SZ_8BIT] = 0, - [XMIT_SZ_16BIT] = 1, - [XMIT_SZ_32BIT] = 2, - }, - .num_hw_channels = 44, -}; - -static struct resource hpb_dmae_resources[] __initdata = { - /* Channel registers */ - DEFINE_RES_MEM(0xffc08000, 0x1000), - /* Common registers */ - DEFINE_RES_MEM(0xffc09000, 0x170), - /* Asynchronous reset registers */ - DEFINE_RES_MEM(0xffc00300, 4), - /* Asynchronous mode registers */ - DEFINE_RES_MEM(0xffc00400, 4), - /* IRQ for DMA channels */ - DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), -}; - -static void __init r8a7779_register_hpb_dmae(void) -{ - platform_device_register_resndata(NULL, "hpb-dma-engine", - -1, hpb_dmae_resources, - ARRAY_SIZE(hpb_dmae_resources), - &dma_platform_data, - sizeof(dma_platform_data)); -} - -static struct platform_device *r8a7779_early_devices[] __initdata = { - &tmu0_device, -}; - -static struct platform_device *r8a7779_standard_devices[] __initdata = { - &scif0_device, - &scif1_device, - &scif2_device, - &scif3_device, - &scif4_device, - &scif5_device, - &i2c0_device, - &i2c1_device, - &i2c2_device, - &i2c3_device, - &sata_device, -}; - -void __init r8a7779_add_standard_devices(void) -{ -#ifdef CONFIG_CACHE_L2X0 - /* Shared attribute override enable, 64K*16way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); -#endif - r8a7779_pm_init(); - - r8a7779_init_pm_domains(); - - platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); - platform_add_devices(r8a7779_standard_devices, - ARRAY_SIZE(r8a7779_standard_devices)); - r8a7779_register_hpb_dmae(); -} - -void __init r8a7779_add_early_devices(void) -{ - early_platform_add_devices(r8a7779_early_devices, - ARRAY_SIZE(r8a7779_early_devices)); - - /* Early serial console setup is not included here due to - * memory map collisions. The SCIF serial ports in r8a7779 - * are difficult to identity map 1:1 due to collision with the - * virtual memory range used by the coherent DMA code on ARM. - * - * Anyone wanting to debug early can remove UPF_IOREMAP from - * the sh-sci serial console platform data, adjust mapbase - * to a static M:N virt:phys mapping that needs to be added to - * the mappings passed with iotable_init() above. - * - * Then add a call to shmobile_setup_console() from this function. - * - * As a final step pass earlyprint=sh-sci.2,115200 on the kernel - * command line in case of the marzen board. - */ -} - -static struct platform_device *r8a7779_late_devices[] __initdata = { - &ehci0_device, - &ehci1_device, - &ohci0_device, - &ohci1_device, -}; - -void __init r8a7779_init_late(void) -{ - /* get USB PHY */ - phy = usb_get_phy(USB_PHY_TYPE_USB2); - - shmobile_init_late(); - platform_add_devices(r8a7779_late_devices, - ARRAY_SIZE(r8a7779_late_devices)); -} - -#ifdef CONFIG_USE_OF -void __init r8a7779_init_irq_dt(void) -{ -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY - void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000); - void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000); -#endif - gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); - -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY - gic_init(0, 29, gic_dist_base, gic_cpu_base); -#else irqchip_init(); -#endif + /* route all interrupts to ARM */ __raw_writel(0xffffffff, INT2NTSR0); __raw_writel(0x3fffffff, INT2NTSR1); @@ -740,7 +78,7 @@ void __init r8a7779_init_irq_dt(void) #define MODEMR 0xffcc0020 -u32 __init r8a7779_read_mode_pins(void) +static u32 __init r8a7779_read_mode_pins(void) { static u32 mode; static bool mode_valid; @@ -756,16 +94,23 @@ u32 __init r8a7779_read_mode_pins(void) return mode; } -static const char *r8a7779_compat_dt[] __initdata = { +static void __init r8a7779_init_time(void) +{ + r8a7779_clocks_init(r8a7779_read_mode_pins()); + clocksource_of_init(); +} + +static const char *const r8a7779_compat_dt[] __initconst = { "renesas,r8a7779", NULL, }; DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") + .smp = smp_ops(r8a7779_smp_ops), .map_io = r8a7779_map_io, .init_early = shmobile_init_delay, + .init_time = r8a7779_init_time, .init_irq = r8a7779_init_irq_dt, .init_late = shmobile_init_late, .dt_compat = r8a7779_compat_dt, MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index ef8eb3af586d..3b8dbaf07777 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c @@ -23,7 +23,7 @@ #include "r8a7791.h" #include "rcar-gen2.h" -static const char *r8a7791_boards_compat_dt[] __initdata = { +static const char *const r8a7791_boards_compat_dt[] __initconst = { "renesas,r8a7791", NULL, }; diff --git a/arch/arm/mach-shmobile/setup-r8a7793.c b/arch/arm/mach-shmobile/setup-r8a7793.c new file mode 100644 index 000000000000..1d2825cb7a65 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7793.c @@ -0,0 +1,33 @@ +/* + * r8a7793 processor support + * + * Copyright (C) 2015 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "rcar-gen2.h" + +static const char *r8a7793_boards_compat_dt[] __initconst = { + "renesas,r8a7793", + NULL, +}; + +DT_MACHINE_START(R8A7793_DT, "Generic R8A7793 (Flattened Device Tree)") + .init_early = shmobile_init_delay, + .init_time = rcar_gen2_timer_init, + .init_late = shmobile_init_late, + .reserve = rcar_gen2_reserve, + .dt_compat = r8a7793_boards_compat_dt, +MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 5d13595aa027..aa3339258d9c 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -128,9 +128,7 @@ void __init rcar_gen2_timer_init(void) #endif /* CONFIG_ARM_ARCH_TIMER */ rcar_gen2_clocks_init(mode); -#ifdef CONFIG_ARCH_SHMOBILE_MULTI clocksource_of_init(); -#endif } struct memory_reserve_config { diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index fb2ab7590af8..99a2004cac76 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -18,28 +18,17 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/platform_device.h> #include <linux/of_platform.h> #include <linux/delay.h> #include <linux/input.h> -#include <linux/i2c/i2c-sh_mobile.h> #include <linux/io.h> -#include <linux/serial_sci.h> -#include <linux/sh_dma.h> -#include <linux/sh_timer.h> -#include <linux/platform_data/sh_ipmmu.h> -#include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/mach-types.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "common.h" -#include "dma-register.h" -#include "intc.h" -#include "irqs.h" #include "sh73a0.h" static struct map_desc sh73a0_io_desc[] __initdata = { @@ -54,737 +43,12 @@ static struct map_desc sh73a0_io_desc[] __initdata = { }, }; -void __init sh73a0_map_io(void) +static void __init sh73a0_map_io(void) { debug_ll_io_init(); iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); } -/* PFC */ -static struct resource pfc_resources[] __initdata = { - DEFINE_RES_MEM(0xe6050000, 0x8000), - DEFINE_RES_MEM(0xe605801c, 0x000c), -}; - -void __init sh73a0_pinmux_init(void) -{ - platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); -} - -/* SCIF */ -#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ -static struct plat_sci_port scif##index##_platform_data = { \ - .type = scif_type, \ - .flags = UPF_BOOT_AUTOCONF, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -}; \ - \ -static struct resource scif##index##_resources[] = { \ - DEFINE_RES_MEM(baseaddr, 0x100), \ - DEFINE_RES_IRQ(irq), \ -}; \ - \ -static struct platform_device scif##index##_device = { \ - .name = "sh-sci", \ - .id = index, \ - .resource = scif##index##_resources, \ - .num_resources = ARRAY_SIZE(scif##index##_resources), \ - .dev = { \ - .platform_data = &scif##index##_platform_data, \ - }, \ -} - -SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); -SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); -SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); -SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); -SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); -SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); -SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); -SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); -SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); - -static struct sh_timer_config cmt1_platform_data = { - .channels_mask = 0x3f, -}; - -static struct resource cmt1_resources[] = { - DEFINE_RES_MEM(0xe6138000, 0x200), - DEFINE_RES_IRQ(gic_spi(65)), -}; - -static struct platform_device cmt1_device = { - .name = "sh-cmt-48", - .id = 1, - .dev = { - .platform_data = &cmt1_platform_data, - }, - .resource = cmt1_resources, - .num_resources = ARRAY_SIZE(cmt1_resources), -}; - -/* TMU */ -static struct sh_timer_config tmu0_platform_data = { - .channels_mask = 7, -}; - -static struct resource tmu0_resources[] = { - DEFINE_RES_MEM(0xfff60000, 0x2c), - DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), - DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), - DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), -}; - -static struct platform_device tmu0_device = { - .name = "sh-tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, - }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), -}; - -static struct resource i2c0_resources[] = { - [0] = DEFINE_RES_MEM(0xe6820000, 0x426), - [1] = { - .start = gic_spi(167), - .end = gic_spi(170), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - [0] = DEFINE_RES_MEM(0xe6822000, 0x426), - [1] = { - .start = gic_spi(51), - .end = gic_spi(54), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c2_resources[] = { - [0] = DEFINE_RES_MEM(0xe6824000, 0x426), - [1] = { - .start = gic_spi(171), - .end = gic_spi(174), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c3_resources[] = { - [0] = DEFINE_RES_MEM(0xe6826000, 0x426), - [1] = { - .start = gic_spi(183), - .end = gic_spi(186), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c4_resources[] = { - [0] = DEFINE_RES_MEM(0xe6828000, 0x426), - [1] = { - .start = gic_spi(187), - .end = gic_spi(190), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct i2c_sh_mobile_platform_data i2c_platform_data = { - .clks_per_count = 2, -}; - -static struct platform_device i2c0_device = { - .name = "i2c-sh_mobile", - .id = 0, - .resource = i2c0_resources, - .num_resources = ARRAY_SIZE(i2c0_resources), - .dev = { - .platform_data = &i2c_platform_data, - }, -}; - -static struct platform_device i2c1_device = { - .name = "i2c-sh_mobile", - .id = 1, - .resource = i2c1_resources, - .num_resources = ARRAY_SIZE(i2c1_resources), - .dev = { - .platform_data = &i2c_platform_data, - }, -}; - -static struct platform_device i2c2_device = { - .name = "i2c-sh_mobile", - .id = 2, - .resource = i2c2_resources, - .num_resources = ARRAY_SIZE(i2c2_resources), - .dev = { - .platform_data = &i2c_platform_data, - }, -}; - -static struct platform_device i2c3_device = { - .name = "i2c-sh_mobile", - .id = 3, - .resource = i2c3_resources, - .num_resources = ARRAY_SIZE(i2c3_resources), - .dev = { - .platform_data = &i2c_platform_data, - }, -}; - -static struct platform_device i2c4_device = { - .name = "i2c-sh_mobile", - .id = 4, - .resource = i2c4_resources, - .num_resources = ARRAY_SIZE(i2c4_resources), - .dev = { - .platform_data = &i2c_platform_data, - }, -}; - -static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { - { - .slave_id = SHDMA_SLAVE_SCIF0_TX, - .addr = 0xe6c40020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x21, - }, { - .slave_id = SHDMA_SLAVE_SCIF0_RX, - .addr = 0xe6c40024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x22, - }, { - .slave_id = SHDMA_SLAVE_SCIF1_TX, - .addr = 0xe6c50020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x25, - }, { - .slave_id = SHDMA_SLAVE_SCIF1_RX, - .addr = 0xe6c50024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x26, - }, { - .slave_id = SHDMA_SLAVE_SCIF2_TX, - .addr = 0xe6c60020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x29, - }, { - .slave_id = SHDMA_SLAVE_SCIF2_RX, - .addr = 0xe6c60024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x2a, - }, { - .slave_id = SHDMA_SLAVE_SCIF3_TX, - .addr = 0xe6c70020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x2d, - }, { - .slave_id = SHDMA_SLAVE_SCIF3_RX, - .addr = 0xe6c70024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x2e, - }, { - .slave_id = SHDMA_SLAVE_SCIF4_TX, - .addr = 0xe6c80020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x39, - }, { - .slave_id = SHDMA_SLAVE_SCIF4_RX, - .addr = 0xe6c80024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x3a, - }, { - .slave_id = SHDMA_SLAVE_SCIF5_TX, - .addr = 0xe6cb0020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x35, - }, { - .slave_id = SHDMA_SLAVE_SCIF5_RX, - .addr = 0xe6cb0024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x36, - }, { - .slave_id = SHDMA_SLAVE_SCIF6_TX, - .addr = 0xe6cc0020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x1d, - }, { - .slave_id = SHDMA_SLAVE_SCIF6_RX, - .addr = 0xe6cc0024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x1e, - }, { - .slave_id = SHDMA_SLAVE_SCIF7_TX, - .addr = 0xe6cd0020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x19, - }, { - .slave_id = SHDMA_SLAVE_SCIF7_RX, - .addr = 0xe6cd0024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x1a, - }, { - .slave_id = SHDMA_SLAVE_SCIF8_TX, - .addr = 0xe6c30040, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x3d, - }, { - .slave_id = SHDMA_SLAVE_SCIF8_RX, - .addr = 0xe6c30060, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x3e, - }, { - .slave_id = SHDMA_SLAVE_SDHI0_TX, - .addr = 0xee100030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc1, - }, { - .slave_id = SHDMA_SLAVE_SDHI0_RX, - .addr = 0xee100030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xc2, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_TX, - .addr = 0xee120030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc9, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_RX, - .addr = 0xee120030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xca, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_TX, - .addr = 0xee140030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xcd, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_RX, - .addr = 0xee140030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xce, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_TX, - .addr = 0xe6bd0034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_RX, - .addr = 0xe6bd0034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd2, - }, -}; - -#define DMAE_CHANNEL(_offset) \ - { \ - .offset = _offset - 0x20, \ - .dmars = _offset - 0x20 + 0x40, \ - } - -static const struct sh_dmae_channel sh73a0_dmae_channels[] = { - DMAE_CHANNEL(0x8000), - DMAE_CHANNEL(0x8080), - DMAE_CHANNEL(0x8100), - DMAE_CHANNEL(0x8180), - DMAE_CHANNEL(0x8200), - DMAE_CHANNEL(0x8280), - DMAE_CHANNEL(0x8300), - DMAE_CHANNEL(0x8380), - DMAE_CHANNEL(0x8400), - DMAE_CHANNEL(0x8480), - DMAE_CHANNEL(0x8500), - DMAE_CHANNEL(0x8580), - DMAE_CHANNEL(0x8600), - DMAE_CHANNEL(0x8680), - DMAE_CHANNEL(0x8700), - DMAE_CHANNEL(0x8780), - DMAE_CHANNEL(0x8800), - DMAE_CHANNEL(0x8880), - DMAE_CHANNEL(0x8900), - DMAE_CHANNEL(0x8980), -}; - -static struct sh_dmae_pdata sh73a0_dmae_platform_data = { - .slave = sh73a0_dmae_slaves, - .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), - .channel = sh73a0_dmae_channels, - .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, -}; - -static struct resource sh73a0_dmae_resources[] = { - DEFINE_RES_MEM(0xfe000020, 0x89e0), - { - .name = "error_irq", - .start = gic_spi(129), - .end = gic_spi(129), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-19 */ - .start = gic_spi(109), - .end = gic_spi(128), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dma0_device = { - .name = "sh-dma-engine", - .id = 0, - .resource = sh73a0_dmae_resources, - .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), - .dev = { - .platform_data = &sh73a0_dmae_platform_data, - }, -}; - -/* MPDMAC */ -static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { - { - .slave_id = SHDMA_SLAVE_FSI2A_RX, - .addr = 0xec230020, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd6, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2A_TX, - .addr = 0xec230024, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd5, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2C_RX, - .addr = 0xec230060, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xda, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2C_TX, - .addr = 0xec230064, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd9, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2B_RX, - .addr = 0xec240020, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0x8e, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2B_TX, - .addr = 0xec240024, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0x8d, /* CHECK ME */ - }, { - .slave_id = SHDMA_SLAVE_FSI2D_RX, - .addr = 0xec240060, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0x9a, /* CHECK ME */ - }, -}; - -#define MPDMA_CHANNEL(a, b, c) \ -{ \ - .offset = a, \ - .dmars = b, \ - .dmars_bit = c, \ - .chclr_offset = (0x220 - 0x20) + a \ -} - -static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { - MPDMA_CHANNEL(0x00, 0, 0), - MPDMA_CHANNEL(0x10, 0, 8), - MPDMA_CHANNEL(0x20, 4, 0), - MPDMA_CHANNEL(0x30, 4, 8), - MPDMA_CHANNEL(0x50, 8, 0), - MPDMA_CHANNEL(0x70, 8, 8), -}; - -static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { - .slave = sh73a0_mpdma_slaves, - .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), - .channel = sh73a0_mpdma_channels, - .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, - .chclr_present = 1, -}; - -/* Resource order important! */ -static struct resource sh73a0_mpdma_resources[] = { - /* Channel registers and DMAOR */ - DEFINE_RES_MEM(0xec618020, 0x270), - /* DMARSx */ - DEFINE_RES_MEM(0xec619000, 0xc), - { - .name = "error_irq", - .start = gic_spi(181), - .end = gic_spi(181), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = gic_spi(175), - .end = gic_spi(180), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mpdma0_device = { - .name = "sh-dma-engine", - .id = 1, - .resource = sh73a0_mpdma_resources, - .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), - .dev = { - .platform_data = &sh73a0_mpdma_platform_data, - }, -}; - -static struct resource pmu_resources[] = { - [0] = { - .start = gic_spi(55), - .end = gic_spi(55), - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = gic_spi(56), - .end = gic_spi(56), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device pmu_device = { - .name = "armv7-pmu", - .id = -1, - .num_resources = ARRAY_SIZE(pmu_resources), - .resource = pmu_resources, -}; - -/* an IPMMU module for ICB */ -static struct resource ipmmu_resources[] = { - DEFINE_RES_MEM(0xfe951000, 0x100), -}; - -static const char * const ipmmu_dev_names[] = { - "sh_mobile_lcdc_fb.0", -}; - -static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { - .dev_names = ipmmu_dev_names, - .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), -}; - -static struct platform_device ipmmu_device = { - .name = "ipmmu", - .id = -1, - .dev = { - .platform_data = &ipmmu_platform_data, - }, - .resource = ipmmu_resources, - .num_resources = ARRAY_SIZE(ipmmu_resources), -}; - -static struct renesas_intc_irqpin_config irqpin0_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ - .control_parent = true, -}; - -static struct resource irqpin0_resources[] = { - DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ - DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ - DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ - DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ - DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ -}; - -static struct platform_device irqpin0_device = { - .name = "renesas_intc_irqpin", - .id = 0, - .resource = irqpin0_resources, - .num_resources = ARRAY_SIZE(irqpin0_resources), - .dev = { - .platform_data = &irqpin0_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin1_platform_data = { - .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ - .control_parent = true, /* Disable spurious IRQ10 */ -}; - -static struct resource irqpin1_resources[] = { - DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ - DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ - DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ - DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ - DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ - DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ -}; - -static struct platform_device irqpin1_device = { - .name = "renesas_intc_irqpin", - .id = 1, - .resource = irqpin1_resources, - .num_resources = ARRAY_SIZE(irqpin1_resources), - .dev = { - .platform_data = &irqpin1_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin2_platform_data = { - .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ - .control_parent = true, -}; - -static struct resource irqpin2_resources[] = { - DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ - DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ - DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ - DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ -}; - -static struct platform_device irqpin2_device = { - .name = "renesas_intc_irqpin", - .id = 2, - .resource = irqpin2_resources, - .num_resources = ARRAY_SIZE(irqpin2_resources), - .dev = { - .platform_data = &irqpin2_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin3_platform_data = { - .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ - .control_parent = true, -}; - -static struct resource irqpin3_resources[] = { - DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ - DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ -}; - -static struct platform_device irqpin3_device = { - .name = "renesas_intc_irqpin", - .id = 3, - .resource = irqpin3_resources, - .num_resources = ARRAY_SIZE(irqpin3_resources), - .dev = { - .platform_data = &irqpin3_platform_data, - }, -}; - -static struct platform_device *sh73a0_early_devices[] __initdata = { - &scif0_device, - &scif1_device, - &scif2_device, - &scif3_device, - &scif4_device, - &scif5_device, - &scif6_device, - &scif7_device, - &scif8_device, - &tmu0_device, - &ipmmu_device, - &cmt1_device, -}; - -static struct platform_device *sh73a0_late_devices[] __initdata = { - &i2c0_device, - &i2c1_device, - &i2c2_device, - &i2c3_device, - &i2c4_device, - &dma0_device, - &mpdma0_device, - &pmu_device, - &irqpin0_device, - &irqpin1_device, - &irqpin2_device, - &irqpin3_device, -}; - -#define SRCR2 IOMEM(0xe61580b0) - -void __init sh73a0_add_standard_devices(void) -{ - /* Clear software reset bit on SY-DMAC module */ - __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); - - platform_add_devices(sh73a0_early_devices, - ARRAY_SIZE(sh73a0_early_devices)); - platform_add_devices(sh73a0_late_devices, - ARRAY_SIZE(sh73a0_late_devices)); -} - -/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ -void __init __weak sh73a0_register_twd(void) { } - -void __init sh73a0_earlytimer_init(void) -{ - shmobile_init_delay(); -#ifndef CONFIG_COMMON_CLK - sh73a0_clock_init(); -#endif - shmobile_earlytimer_init(); - sh73a0_register_twd(); -} - -void __init sh73a0_add_early_devices(void) -{ - early_platform_add_devices(sh73a0_early_devices, - ARRAY_SIZE(sh73a0_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); -} - -#ifdef CONFIG_USE_OF - static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 @@ -794,7 +58,7 @@ static void __init sh73a0_generic_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char *sh73a0_boards_compat_dt[] __initdata = { +static const char *const sh73a0_boards_compat_dt[] __initconst = { "renesas,sh73a0", NULL, }; @@ -807,4 +71,3 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .init_late = shmobile_init_late, .dt_compat = sh73a0_boards_compat_dt, MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h index 5a80f18b4fa0..39646806cf64 100644 --- a/arch/arm/mach-shmobile/sh73a0.h +++ b/arch/arm/mach-shmobile/sh73a0.h @@ -1,89 +1,6 @@ #ifndef __ASM_SH73A0_H__ #define __ASM_SH73A0_H__ -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SCIF6_TX, - SHDMA_SLAVE_SCIF6_RX, - SHDMA_SLAVE_SCIF7_TX, - SHDMA_SLAVE_SCIF7_RX, - SHDMA_SLAVE_SCIF8_TX, - SHDMA_SLAVE_SCIF8_RX, - SHDMA_SLAVE_SDHI0_TX, - SHDMA_SLAVE_SDHI0_RX, - SHDMA_SLAVE_SDHI1_TX, - SHDMA_SLAVE_SDHI1_RX, - SHDMA_SLAVE_SDHI2_TX, - SHDMA_SLAVE_SDHI2_RX, - SHDMA_SLAVE_MMCIF_TX, - SHDMA_SLAVE_MMCIF_RX, - SHDMA_SLAVE_FSI2A_TX, - SHDMA_SLAVE_FSI2A_RX, - SHDMA_SLAVE_FSI2B_TX, - SHDMA_SLAVE_FSI2B_RX, - SHDMA_SLAVE_FSI2C_TX, - SHDMA_SLAVE_FSI2C_RX, - SHDMA_SLAVE_FSI2D_RX, -}; - -/* - * SH73A0 IRQ LOCATION TABLE - * - * 416 ----------------------------------------- - * IRQ0-IRQ15 - * 431 ----------------------------------------- - * ... - * 448 ----------------------------------------- - * sh73a0-intcs - * sh73a0-intca-irq-pins - * 680 ----------------------------------------- - * ... - * 700 ----------------------------------------- - * sh73a0-pint0 - * 731 ----------------------------------------- - * 732 ----------------------------------------- - * sh73a0-pint1 - * 739 ----------------------------------------- - * ... - * 800 ----------------------------------------- - * IRQ16-IRQ31 - * 815 ----------------------------------------- - * ... - * 928 ----------------------------------------- - * sh73a0-intca-irq-pins - * 943 ----------------------------------------- - */ - -/* PINT interrupts are located at Linux IRQ 700 and up */ -#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) -#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) - -extern void sh73a0_init_irq(void); -extern void sh73a0_init_irq_dt(void); -extern void sh73a0_map_io(void); -extern void sh73a0_earlytimer_init(void); -extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_standard_devices(void); -extern void sh73a0_clock_init(void); -extern void sh73a0_pinmux_init(void); -extern void sh73a0_pm_init(void); -extern struct clk sh73a0_extal1_clk; -extern struct clk sh73a0_extal2_clk; -extern struct clk sh73a0_extcki_clk; -extern struct clk sh73a0_extalr_clk; extern struct smp_operations sh73a0_smp_ops; #endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 01f792fcb220..353562b8a5ee 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -23,7 +23,6 @@ #include <asm/cacheflush.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> -#include <asm/smp_twd.h> #include "common.h" #include "pm-rcar.h" @@ -32,41 +31,33 @@ #define AVECR IOMEM(0xfe700040) #define R8A7779_SCU_BASE 0xf0000000 -static struct rcar_sysc_ch r8a7779_ch_cpu1 = { +static const struct rcar_sysc_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 1, /* ARM1 */ .isr_bit = 1, /* ARM1 */ }; -static struct rcar_sysc_ch r8a7779_ch_cpu2 = { +static const struct rcar_sysc_ch r8a7779_ch_cpu2 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 2, /* ARM2 */ .isr_bit = 2, /* ARM2 */ }; -static struct rcar_sysc_ch r8a7779_ch_cpu3 = { +static const struct rcar_sysc_ch r8a7779_ch_cpu3 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 3, /* ARM3 */ .isr_bit = 3, /* ARM3 */ }; -static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = { +static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = { [1] = &r8a7779_ch_cpu1, [2] = &r8a7779_ch_cpu2, [3] = &r8a7779_ch_cpu3, }; -#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM) -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); -void __init r8a7779_register_twd(void) -{ - twd_local_timer_register(&twd_local_timer); -} -#endif - static int r8a7779_platform_cpu_kill(unsigned int cpu) { - struct rcar_sysc_ch *ch = NULL; + const struct rcar_sysc_ch *ch = NULL; int ret = -EIO; cpu = cpu_logical_map(cpu); @@ -82,7 +73,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { - struct rcar_sysc_ch *ch = NULL; + const struct rcar_sysc_ch *ch = NULL; unsigned int lcpu = cpu_logical_map(cpu); int ret; diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c index 930f45cbc08a..4b33d432a364 100644 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ b/arch/arm/mach-shmobile/smp-r8a7790.c @@ -26,12 +26,12 @@ #include "rcar-gen2.h" #include "r8a7790.h" -static struct rcar_sysc_ch r8a7790_ca15_scu = { +static const struct rcar_sysc_ch r8a7790_ca15_scu = { .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */ .isr_bit = 12, /* CA15-SCU */ }; -static struct rcar_sysc_ch r8a7790_ca7_scu = { +static const struct rcar_sysc_ch r8a7790_ca7_scu = { .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ .isr_bit = 21, /* CA7-SCU */ }; @@ -64,7 +64,7 @@ struct smp_operations r8a7790_smp_ops __initdata = { .smp_prepare_cpus = r8a7790_smp_prepare_cpus, .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, + .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, .cpu_kill = shmobile_smp_apmu_cpu_kill, #endif diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index 5e2d1db79afa..b2508c0d276b 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c @@ -58,7 +58,7 @@ struct smp_operations r8a7791_smp_ops __initdata = { .smp_prepare_cpus = r8a7791_smp_prepare_cpus, .smp_boot_secondary = r8a7791_smp_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, + .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_apmu_cpu_die, .cpu_kill = shmobile_smp_apmu_cpu_kill, #endif diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 2106d6b76a06..bc2824a036e1 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -33,14 +33,6 @@ #define SH73A0_SCU_BASE 0xf0000000 -#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM) -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); -void __init sh73a0_register_twd(void) -{ - twd_local_timer_register(&twd_local_timer); -} -#endif - static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int lcpu = cpu_logical_map(cpu); @@ -68,7 +60,7 @@ struct smp_operations sh73a0_smp_ops __initdata = { .smp_prepare_cpus = sh73a0_smp_prepare_cpus, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, + .cpu_can_disable = shmobile_smp_cpu_can_disable, .cpu_die = shmobile_smp_scu_cpu_die, .cpu_kill = shmobile_smp_scu_cpu_kill, #endif diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 0edf2a6d2bbe..f1d027aa7a81 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -70,18 +70,6 @@ void __init shmobile_init_delay(void) if (!max_freq) return; -#ifdef CONFIG_ARCH_SHMOBILE_LEGACY - /* Non-multiplatform r8a73a4 SoC cannot use arch timer due - * to GIC being initialized from C and arch timer via DT */ - if (of_machine_is_compatible("renesas,r8a73a4")) - has_arch_timer = false; - - /* Non-multiplatform r8a7790 SoC cannot use arch timer due - * to GIC being initialized from C and arch timer via DT */ - if (of_machine_is_compatible("renesas,r8a7790")) - has_arch_timer = false; -#endif - if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) { if (is_a7_a8_a9) shmobile_setup_delay_hz(max_freq, 1, 3); diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 7259c3732702..5bc6ea87cdf7 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -25,6 +25,7 @@ #define SOCFPGA_RSTMGR_MODPERRST 0x14 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c +#define SOCFPGA_A10_RSTMGR_CTRL 0xC #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 /* System Manager bits */ diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index c6f1df89f9af..15c8ce8965f4 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -106,11 +106,23 @@ static void socfpga_cpu_die(unsigned int cpu) cpu_do_idle(); } +/* + * We need a dummy function so that platform_can_cpu_hotplug() knows + * we support CPU hotplug. However, the function does not need to do + * anything, because CPUs going offline just do WFI. We could reset + * the CPUs but it would increase power consumption. + */ +static int socfpga_cpu_kill(unsigned int cpu) +{ + return 1; +} + static struct smp_operations socfpga_smp_ops __initdata = { .smp_prepare_cpus = socfpga_smp_prepare_cpus, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die, + .cpu_kill = socfpga_cpu_kill, #endif }; @@ -119,6 +131,7 @@ static struct smp_operations socfpga_a10_smp_ops __initdata = { .smp_boot_secondary = socfpga_a10_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die, + .cpu_kill = socfpga_cpu_kill, #endif }; diff --git a/arch/arm/mach-socfpga/pm.c b/arch/arm/mach-socfpga/pm.c index 6a4199f2bffb..c378ab0c2431 100644 --- a/arch/arm/mach-socfpga/pm.c +++ b/arch/arm/mach-socfpga/pm.c @@ -56,7 +56,7 @@ static int socfpga_setup_ocram_self_refresh(void) goto put_node; } - ocram_pool = gen_pool_get(&pdev->dev); + ocram_pool = gen_pool_get(&pdev->dev, NULL); if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 19643a756c48..a1c0efaa8794 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -74,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } +static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) +{ + u32 temp; + + temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); + + if (mode == REBOOT_HARD) + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; + else + temp |= RSTMGR_CTRL_SWWARMRSTREQ; + writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); +} + static const char *altera_dt_match[] = { "altr,socfpga", NULL @@ -86,3 +99,16 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, MACHINE_END + +static const char *altera_a10_dt_match[] = { + "altr,socfpga-arria10", + NULL +}; + +DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .init_irq = socfpga_init_irq, + .restart = socfpga_arria10_restart, + .dt_compat = altera_a10_dt_match, +MACHINE_END diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c index 26fda4ed4d51..9ccffc1d0f28 100644 --- a/arch/arm/mach-spear/time.c +++ b/arch/arm/mach-spear/time.c @@ -66,8 +66,6 @@ static __iomem void *gpt_base; static struct clk *gpt_clk; -static void clockevent_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk_event_dev); static int clockevent_next_event(unsigned long evt, struct clock_event_device *clk_event_dev); @@ -95,54 +93,67 @@ static void __init spear_clocksource_init(void) 200, 16, clocksource_mmio_readw_up); } -static struct clock_event_device clkevt = { - .name = "tmr0", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = clockevent_set_mode, - .set_next_event = clockevent_next_event, - .shift = 0, /* to be computed */ -}; +static inline void timer_shutdown(struct clock_event_device *evt) +{ + u16 val = readw(gpt_base + CR(CLKEVT)); + + /* stop the timer */ + val &= ~CTRL_ENABLE; + writew(val, gpt_base + CR(CLKEVT)); +} + +static int spear_shutdown(struct clock_event_device *evt) +{ + timer_shutdown(evt); + + return 0; +} + +static int spear_set_oneshot(struct clock_event_device *evt) +{ + u16 val; -static void clockevent_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk_event_dev) + /* stop the timer */ + timer_shutdown(evt); + + val = readw(gpt_base + CR(CLKEVT)); + val |= CTRL_ONE_SHOT; + writew(val, gpt_base + CR(CLKEVT)); + + return 0; +} + +static int spear_set_periodic(struct clock_event_device *evt) { u32 period; u16 val; /* stop the timer */ + timer_shutdown(evt); + + period = clk_get_rate(gpt_clk) / HZ; + period >>= CTRL_PRESCALER16; + writew(period, gpt_base + LOAD(CLKEVT)); + val = readw(gpt_base + CR(CLKEVT)); - val &= ~CTRL_ENABLE; + val &= ~CTRL_ONE_SHOT; + val |= CTRL_ENABLE | CTRL_INT_ENABLE; writew(val, gpt_base + CR(CLKEVT)); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - period = clk_get_rate(gpt_clk) / HZ; - period >>= CTRL_PRESCALER16; - writew(period, gpt_base + LOAD(CLKEVT)); - - val = readw(gpt_base + CR(CLKEVT)); - val &= ~CTRL_ONE_SHOT; - val |= CTRL_ENABLE | CTRL_INT_ENABLE; - writew(val, gpt_base + CR(CLKEVT)); - - break; - case CLOCK_EVT_MODE_ONESHOT: - val = readw(gpt_base + CR(CLKEVT)); - val |= CTRL_ONE_SHOT; - writew(val, gpt_base + CR(CLKEVT)); - - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - - break; - default: - pr_err("Invalid mode requested\n"); - break; - } + return 0; } +static struct clock_event_device clkevt = { + .name = "tmr0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = spear_shutdown, + .set_state_periodic = spear_set_periodic, + .set_state_oneshot = spear_set_oneshot, + .tick_resume = spear_shutdown, + .set_next_event = clockevent_next_event, + .shift = 0, /* to be computed */ +}; + static int clockevent_next_event(unsigned long cycles, struct clock_event_device *clk_event_dev) { @@ -193,7 +204,7 @@ static void __init spear_clockevent_init(int irq) setup_irq(irq, &spear_timer_irq); } -const static struct of_device_id timer_of_match[] __initconst = { +static const struct of_device_id const timer_of_match[] __initconst = { { .compatible = "st,spear-timer", }, { }, }; diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c index b373acade338..ae10fb280a78 100644 --- a/arch/arm/mach-sti/board-dt.c +++ b/arch/arm/mach-sti/board-dt.c @@ -14,7 +14,7 @@ #include "smp.h" -static const char *stih41x_dt_match[] __initdata = { +static const char *const stih41x_dt_match[] __initconst = { "st,stih415", "st,stih416", "st,stih407", diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S index 4c09bae86edf..e0ad451700d5 100644 --- a/arch/arm/mach-sti/headsmp.S +++ b/arch/arm/mach-sti/headsmp.S @@ -37,6 +37,7 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup +ENDPROC(sti_secondary_startup) 1: .long . .long pen_release diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index d4b624f8dfcb..c4ad6eae67fa 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/memblock.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -38,8 +39,6 @@ static DEFINE_SPINLOCK(boot_lock); static void sti_secondary_init(unsigned int cpu) { - trace_hardirqs_off(); - /* * let the primary processor know we're out of the * pen, then head off into the C entry point @@ -99,14 +98,62 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init sti_smp_prepare_cpus(unsigned int max_cpus) { - void __iomem *scu_base = NULL; - struct device_node *np = of_find_compatible_node( - NULL, NULL, "arm,cortex-a9-scu"); + struct device_node *np; + void __iomem *scu_base; + u32 __iomem *cpu_strt_ptr; + u32 release_phys; + int cpu; + unsigned long entry_pa = virt_to_phys(sti_secondary_startup); + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (np) { scu_base = of_iomap(np, 0); scu_enable(scu_base); of_node_put(np); } + + if (max_cpus <= 1) + return; + + for_each_possible_cpu(cpu) { + + np = of_get_cpu_node(cpu, NULL); + + if (!np) + continue; + + if (of_property_read_u32(np, "cpu-release-addr", + &release_phys)) { + pr_err("CPU %d: missing or invalid cpu-release-addr " + "property\n", cpu); + continue; + } + + /* + * holding pen is usually configured in SBC DMEM but can also be + * in RAM. + */ + + if (!memblock_is_memory(release_phys)) + cpu_strt_ptr = + ioremap(release_phys, sizeof(release_phys)); + else + cpu_strt_ptr = + (u32 __iomem *)phys_to_virt(release_phys); + + __raw_writel(entry_pa, cpu_strt_ptr); + + /* + * wmb so that data is actually written + * before cache flush is done + */ + smp_wmb(); + sync_cache_w(cpu_strt_ptr); + + if (!memblock_is_memory(release_phys)) + iounmap(cpu_strt_ptr); + } } struct smp_operations __initdata sti_smp_ops = { diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h index 1871b72b1a7e..ae22707d301f 100644 --- a/arch/arm/mach-sti/smp.h +++ b/arch/arm/mach-sti/smp.h @@ -14,4 +14,6 @@ extern struct smp_operations sti_smp_ops; +void sti_secondary_startup(void); + #endif diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5d1a318f1302..0fa4c5f8b1be 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -8,6 +8,7 @@ menuconfig ARCH_TEGRA select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select PM_OPP select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER select SOC_BUS diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 155807fa6fdd..9157546fe68c 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -24,6 +24,7 @@ #include <asm/cpuidle.h> #include <asm/smp_plat.h> #include <asm/suspend.h> +#include <asm/psci.h> #include "pm.h" #include "sleep.h" @@ -44,16 +45,12 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, tegra_set_cpu_in_lp2(); cpu_pm_enter(); - tick_broadcast_enter(); - call_firmware_op(prepare_idle); /* Do suspend by ourselves if the firmware does not implement it */ if (call_firmware_op(do_idle, 0) == -ENOSYS) cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - tick_broadcast_exit(); - cpu_pm_exit(); tegra_clear_cpu_in_lp2(); @@ -61,6 +58,13 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, return index; } + +static void tegra114_idle_enter_freeze(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + tegra114_idle_power_down(dev, drv, index); +} #endif static struct cpuidle_driver tegra_idle_driver = { @@ -72,8 +76,10 @@ static struct cpuidle_driver tegra_idle_driver = { #ifdef CONFIG_PM_SLEEP [1] = { .enter = tegra114_idle_power_down, + .enter_freeze = tegra114_idle_enter_freeze, .exit_latency = 500, .target_residency = 1000, + .flags = CPUIDLE_FLAG_TIMER_STOP, .power_usage = 0, .name = "powered-down", .desc = "CPU power gated", @@ -84,5 +90,8 @@ static struct cpuidle_driver tegra_idle_driver = { int __init tegra114_cpuidle_init(void) { - return cpuidle_register(&tegra_idle_driver, NULL); + if (!psci_smp_available()) + return cpuidle_register(&tegra_idle_driver, NULL); + + return 0; } diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 81dc950b4881..9e5b2f869fc8 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -82,9 +82,6 @@ #define TEGRA_EMC_BASE 0x7000F400 #define TEGRA_EMC_SIZE SZ_1K -#define TEGRA_FUSE_BASE 0x7000F800 -#define TEGRA_FUSE_SIZE SZ_1K - #define TEGRA_EMC0_BASE 0x7001A000 #define TEGRA_EMC0_SIZE SZ_2K diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c index 5943e1cb7fe1..4b784f721135 100644 --- a/arch/arm/mach-uniphier/platsmp.c +++ b/arch/arm/mach-uniphier/platsmp.c @@ -60,12 +60,6 @@ err: sbcm_regmap = NULL; } -static void __naked uniphier_secondary_startup(void) -{ - asm("bl v7_invalidate_l1\n" - "b secondary_startup\n"); -}; - static int uniphier_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -75,7 +69,7 @@ static int uniphier_boot_secondary(unsigned int cpu, return -ENODEV; ret = regmap_write(sbcm_regmap, 0x1208, - virt_to_phys(uniphier_secondary_startup)); + virt_to_phys(secondary_startup)); if (!ret) asm("sev"); /* wake up secondary CPU */ diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 4418a5078833..c8643ac5db71 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500-regulators.o \ board-mop500-audio.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 7557bede7ae6..780bd13cd7e3 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -8,6 +8,7 @@ #include <linux/of.h> #include <linux/of_address.h> +#include <asm/outercache.h> #include <asm/hardware/cache-l2x0.h> #include "db8500-regs.h" diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 16913800bbf9..f80560318c58 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -20,10 +20,10 @@ #include <linux/mfd/dbx500-prcmu.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/perf/arm_pmu.h> #include <linux/regulator/machine.h> #include <linux/random.h> -#include <asm/pmu.h> #include <asm/mach/map.h> #include "setup.h" @@ -154,7 +154,6 @@ static const char * stericsson_dt_platform_compat[] = { }; DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") - .smp = smp_ops(ux500_smp_ops), .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e31d3d61c998..41b81c4fbe63 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -56,7 +56,6 @@ void __init ux500_init_irq(void) struct device_node *np; struct resource r; - gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND); irqchip_init(); np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); of_address_to_resource(np, 0, &r); @@ -72,21 +71,12 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u8500_family()) { - u8500_of_clk_init(U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - } else if (cpu_is_u9540()) { - u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - } else if (cpu_is_u8540()) { - u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - } + if (cpu_is_u8500_family()) + u8500_clk_init(); + else if (cpu_is_u9540()) + u9540_clk_init(); + else if (cpu_is_u8540()) + u8540_clk_init(); } static const char * __init ux500_get_machine(void) diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S deleted file mode 100644 index 9cdea049485d..000000000000 --- a/arch/arm/mach-ux500/headsmp.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2009 ST-Ericsson - * This file is based ARM Realview platform - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - -/* - * U8500 specific entry point for secondary CPUs. - */ -ENTRY(u8500_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup -ENDPROC(u8500_secondary_startup) - - .align 2 -1: .long . - .long pen_release diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 62b1de922bd8..70766b963758 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -28,135 +28,81 @@ #include "db8500-regs.h" #include "id.h" -static void __iomem *scu_base; -static void __iomem *backupram; - -/* This is called from headsmp.S to wakeup the secondary core */ -extern void u8500_secondary_startup(void); - -/* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - sync_cache_w(&pen_release); -} - -static DEFINE_SPINLOCK(boot_lock); - -static void ux500_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} +/* Magic triggers in backup RAM */ +#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 +#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 -static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) +static void wakeup_secondary(void) { - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - */ - write_pen_release(cpu_logical_map(cpu)); - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + struct device_node *np; + static void __iomem *backupram; - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - if (pen_release == -1) - break; + np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); + if (!np) { + pr_err("No backupram base address\n"); + return; + } + backupram = of_iomap(np, 0); + of_node_put(np); + if (!backupram) { + pr_err("No backupram remap\n"); + return; } /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -static void __init wakeup_secondary(void) -{ - /* * write the address of secondary startup into the backup ram register * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the * backup ram register at offset 0x1FF0, which is what boot rom code - * is waiting for. This would wake up the secondary core from WFE + * is waiting for. This will wake up the secondary core from WFE. */ -#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 - __raw_writel(virt_to_phys(u8500_secondary_startup), - backupram + UX500_CPU1_JUMPADDR_OFFSET); - -#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 - __raw_writel(0xA1FEED01, - backupram + UX500_CPU1_WAKEMAGIC_OFFSET); + writel(virt_to_phys(secondary_startup), + backupram + UX500_CPU1_JUMPADDR_OFFSET); + writel(0xA1FEED01, + backupram + UX500_CPU1_WAKEMAGIC_OFFSET); /* make sure write buffer is drained */ mb(); + iounmap(backupram); } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init ux500_smp_init_cpus(void) +static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) { - unsigned int i, ncores; struct device_node *np; + static void __iomem *scu_base; + unsigned int ncores; + int i; np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!np) { + pr_err("No SCU base address\n"); + return; + } scu_base = of_iomap(np, 0); of_node_put(np); - if (!scu_base) + if (!scu_base) { + pr_err("No SCU remap\n"); return; - backupram = ioremap(U8500_BACKUPRAM0_BASE, SZ_8K); - ncores = scu_get_core_count(scu_base); - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; } + scu_enable(scu_base); + ncores = scu_get_core_count(scu_base); for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + iounmap(scu_base); } -static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) +static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) { - scu_enable(scu_base); wakeup_secondary(); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; } struct smp_operations ux500_smp_ops __initdata = { - .smp_init_cpus = ux500_smp_init_cpus, .smp_prepare_cpus = ux500_smp_prepare_cpus, - .smp_secondary_init = ux500_secondary_init, .smp_boot_secondary = ux500_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = ux500_cpu_die, #endif }; +CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops); diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index 1fb6ad2789f1..65876eac0761 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -26,7 +26,6 @@ extern struct device *ux500_soc_device_init(const char *soc_id); extern void ux500_timer_init(void); -extern struct smp_operations ux500_smp_ops; extern void ux500_cpu_die(unsigned int cpu); #endif /* __ASM_ARCH_SETUP_H */ diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index b3328cd46c33..1aa4ccece69f 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -80,7 +80,7 @@ static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) * to the CPU by disabling the GIC CPU IF to prevent wfi * from completing execution behind power controller back */ - gic_cpu_if_down(); + gic_cpu_if_down(0); } static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster) diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index d66d43ae8df5..491b317daffa 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -211,6 +211,6 @@ void __init nuc900_init_irq(void) for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { irq_set_chip_and_handler(irqno, &nuc900_irq_chip, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); + irq_clear_status_flags(irqno, IRQ_NOREQUEST); } } diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index 9230d3725599..cd1966ec9143 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c @@ -48,31 +48,32 @@ static unsigned int timer0_load; -static void nuc900_clockevent_setmode(enum clock_event_mode mode, - struct clock_event_device *clk) +static int nuc900_clockevent_shutdown(struct clock_event_device *evt) { - unsigned int val; + unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); - val = __raw_readl(REG_TCSR0); - val &= ~(0x03 << 27); + __raw_writel(val, REG_TCSR0); + return 0; +} + +static int nuc900_clockevent_set_oneshot(struct clock_event_device *evt) +{ + unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - __raw_writel(timer0_load, REG_TICR0); - val |= (PERIOD | COUNTEN | INTEN | PRESCALE); - break; + val |= (ONESHOT | COUNTEN | INTEN | PRESCALE); - case CLOCK_EVT_MODE_ONESHOT: - val |= (ONESHOT | COUNTEN | INTEN | PRESCALE); - break; + __raw_writel(val, REG_TCSR0); + return 0; +} - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - break; - } +static int nuc900_clockevent_set_periodic(struct clock_event_device *evt) +{ + unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27); + __raw_writel(timer0_load, REG_TICR0); + val |= (PERIOD | COUNTEN | INTEN | PRESCALE); __raw_writel(val, REG_TCSR0); + return 0; } static int nuc900_clockevent_setnextevent(unsigned long evt, @@ -90,11 +91,15 @@ static int nuc900_clockevent_setnextevent(unsigned long evt, } static struct clock_event_device nuc900_clockevent_device = { - .name = "nuc900-timer0", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = nuc900_clockevent_setmode, - .set_next_event = nuc900_clockevent_setnextevent, - .rating = 300, + .name = "nuc900-timer0", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = nuc900_clockevent_shutdown, + .set_state_periodic = nuc900_clockevent_set_periodic, + .set_state_oneshot = nuc900_clockevent_set_oneshot, + .tick_resume = nuc900_clockevent_shutdown, + .set_next_event = nuc900_clockevent_setnextevent, + .rating = 300, }; /*IRQ handler for the timer*/ diff --git a/arch/arm/mach-zx/Kconfig b/arch/arm/mach-zx/Kconfig index 2a910dc0d15e..7fdc5bf24f9b 100644 --- a/arch/arm/mach-zx/Kconfig +++ b/arch/arm/mach-zx/Kconfig @@ -13,6 +13,7 @@ config SOC_ZX296702 select ARM_GLOBAL_TIMER select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select PM_GENERIC_DOMAINS help Support for ZTE ZX296702 SoC which is a dual core CortexA9MP endif diff --git a/arch/arm/mach-zx/Makefile b/arch/arm/mach-zx/Makefile index 7c2edf6e5f8b..a4b486433209 100644 --- a/arch/arm/mach-zx/Makefile +++ b/arch/arm/mach-zx/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_SOC_ZX296702) += zx296702.o +obj-$(CONFIG_SOC_ZX296702) += zx296702.o zx296702-pm-domain.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-zx/zx296702-pm-domain.c b/arch/arm/mach-zx/zx296702-pm-domain.c new file mode 100644 index 000000000000..e08574d4e2ca --- /dev/null +++ b/arch/arm/mach-zx/zx296702-pm-domain.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2015 Linaro Ltd. + * + * Author: Jun Nie <jun.nie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_domain.h> +#include <linux/slab.h> + +#define PCU_DM_CLKEN 0x18 +#define PCU_DM_RSTEN 0x1C +#define PCU_DM_ISOEN 0x20 +#define PCU_DM_PWRDN 0x24 +#define PCU_DM_ACK_SYNC 0x28 + +enum { + PCU_DM_NEON0 = 0, + PCU_DM_NEON1, + PCU_DM_GPU, + PCU_DM_DECPPU, + PCU_DM_VOU, + PCU_DM_R2D, + PCU_DM_TOP, +}; + +static void __iomem *pcubase; + +struct zx_pm_domain { + struct generic_pm_domain dm; + unsigned int bit; +}; + +static int normal_power_off(struct generic_pm_domain *domain) +{ + struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain; + unsigned long loop = 1000; + u32 tmp; + + tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp, pcubase + PCU_DM_CLKEN); + udelay(5); + + tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN); + udelay(5); + + tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp, pcubase + PCU_DM_RSTEN); + udelay(5); + + tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN); + do { + tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); + } while (--loop && !tmp); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + return 0; +} + +static int normal_power_on(struct generic_pm_domain *domain) +{ + struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain; + unsigned long loop = 10000; + u32 tmp; + + tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp, pcubase + PCU_DM_PWRDN); + do { + tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); + } while (--loop && tmp); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN); + udelay(5); + + tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp, pcubase + PCU_DM_ISOEN); + udelay(5); + + tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); + tmp &= ~BIT(zpd->bit); + writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN); + udelay(5); + return 0; +} + +static struct zx_pm_domain gpu_domain = { + .dm = { + .name = "gpu_domain", + .power_off = normal_power_off, + .power_on = normal_power_on, + }, + .bit = PCU_DM_GPU, +}; + +static struct zx_pm_domain decppu_domain = { + .dm = { + .name = "decppu_domain", + .power_off = normal_power_off, + .power_on = normal_power_on, + }, + .bit = PCU_DM_DECPPU, +}; + +static struct zx_pm_domain vou_domain = { + .dm = { + .name = "vou_domain", + .power_off = normal_power_off, + .power_on = normal_power_on, + }, + .bit = PCU_DM_VOU, +}; + +static struct zx_pm_domain r2d_domain = { + .dm = { + .name = "r2d_domain", + .power_off = normal_power_off, + .power_on = normal_power_on, + }, + .bit = PCU_DM_R2D, +}; + +static struct generic_pm_domain *zx296702_pm_domains[] = { + &vou_domain.dm, + &gpu_domain.dm, + &decppu_domain.dm, + &r2d_domain.dm, +}; + +static int zx296702_pd_probe(struct platform_device *pdev) +{ + struct genpd_onecell_data *genpd_data; + struct resource *res; + int i; + + genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL); + if (!genpd_data) + return -ENOMEM; + + genpd_data->domains = zx296702_pm_domains; + genpd_data->num_domains = ARRAY_SIZE(zx296702_pm_domains); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no memory resource defined\n"); + return -ENODEV; + } + + pcubase = devm_ioremap_resource(&pdev->dev, res); + if (!pcubase) { + dev_err(&pdev->dev, "ioremap fail.\n"); + return -EIO; + } + + for (i = 0; i < ARRAY_SIZE(zx296702_pm_domains); ++i) + pm_genpd_init(zx296702_pm_domains[i], NULL, false); + + of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data); + return 0; +} + +static const struct of_device_id zx296702_pm_domain_matches[] __initconst = { + { .compatible = "zte,zx296702-pcu", }, + { }, +}; + +static struct platform_driver zx296702_pd_driver __initdata = { + .driver = { + .name = "zx-powerdomain", + .owner = THIS_MODULE, + .of_match_table = zx296702_pm_domain_matches, + }, + .probe = zx296702_pd_probe, +}; + +static int __init zx296702_pd_init(void) +{ + return platform_driver_register(&zx296702_pd_driver); +} +subsys_initcall(zx296702_pd_init); diff --git a/arch/arm/mach-zx/zx296702.c b/arch/arm/mach-zx/zx296702.c index 60bb1a8e1bf1..a041e13ab0ac 100644 --- a/arch/arm/mach-zx/zx296702.c +++ b/arch/arm/mach-zx/zx296702.c @@ -13,7 +13,7 @@ #include <linux/of_address.h> #include <linux/of_platform.h> -static const char *zx296702_dt_compat[] __initconst = { +static const char *const zx296702_dt_compat[] __initconst = { "zte,zx296702", NULL, }; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 616d5840fc2e..5a6e4e20ca0a 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -186,7 +186,6 @@ static void __init zynq_map_io(void) static void __init zynq_irq_init(void) { - gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND); irqchip_init(); } @@ -197,8 +196,8 @@ static const char * const zynq_dt_match[] = { DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") /* 64KB way size, 8-way associativity, parity disabled */ - .l2c_aux_val = 0x00000000, - .l2c_aux_mask = 0xffffffff, + .l2c_aux_val = 0x00400000, + .l2c_aux_mask = 0xffbfffff, .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, .init_irq = zynq_irq_init, diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index 045c72720a4d..f6d5de073e34 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -18,7 +18,7 @@ ARM_BE8(rev r0, r0) .globl zynq_secondary_trampoline_jump zynq_secondary_trampoline_jump: /* Space for jumping address */ - .word /* cpu 1 */ + .word 0 /* cpu 1 */ .globl zynq_secondary_trampoline_end zynq_secondary_trampoline_end: ENDPROC(zynq_secondary_trampoline) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7c6b976ab8d3..df7537f12469 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -883,6 +883,7 @@ config OUTER_CACHE config OUTER_CACHE_SYNC bool + select ARM_HEAVY_MB help The outer cache has a outer_cache_fns.sync function pointer that can be used to drain the write buffer of the outer cache. @@ -1031,6 +1032,9 @@ config ARCH_HAS_BARRIERS This option allows the use of custom mandatory barriers included via the mach/barriers.h file. +config ARM_HEAVY_MB + bool + config ARCH_SUPPORTS_BIG_ENDIAN bool help diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S index 54473cd4aba9..b3b31e30cadd 100644 --- a/arch/arm/mm/abort-ev4.S +++ b/arch/arm/mm/abort-ev4.S @@ -19,6 +19,7 @@ ENTRY(v4_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR ldr r3, [r4] @ read aborted ARM instruction + uaccess_disable ip @ disable userspace access bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR tst r3, #1 << 20 @ L = 1 -> write? orreq r1, r1, #1 << 11 @ yes. diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S index a0908d4653a3..a6a381a6caa5 100644 --- a/arch/arm/mm/abort-ev5t.S +++ b/arch/arm/mm/abort-ev5t.S @@ -21,8 +21,10 @@ ENTRY(v5t_early_abort) mrc p15, 0, r0, c6, c0, 0 @ get FAR do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 ldreq r3, [r4] @ read aborted ARM instruction + uaccess_disable ip @ disable user access bic r1, r1, #1 << 11 @ clear bits 11 of FSR - do_ldrd_abort tmp=ip, insn=r3 + teq_ldrd tmp=ip, insn=r3 @ insn was LDRD? + beq do_DataAbort @ yes tst r3, #1 << 20 @ check write orreq r1, r1, #1 << 11 b do_DataAbort diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S index 4006b7a61264..00ab011bef58 100644 --- a/arch/arm/mm/abort-ev5tj.S +++ b/arch/arm/mm/abort-ev5tj.S @@ -24,7 +24,9 @@ ENTRY(v5tj_early_abort) bne do_DataAbort do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 ldreq r3, [r4] @ read aborted ARM instruction - do_ldrd_abort tmp=ip, insn=r3 + uaccess_disable ip @ disable userspace access + teq_ldrd tmp=ip, insn=r3 @ insn was LDRD? + beq do_DataAbort @ yes tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. b do_DataAbort diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index 8c48c5c22a33..8801a15aa105 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -26,16 +26,18 @@ ENTRY(v6_early_abort) ldr ip, =0x4107b36 mrc p15, 0, r3, c0, c0, 0 @ get processor id teq ip, r3, lsr #4 @ r0 ARM1136? - bne do_DataAbort + bne 1f tst r5, #PSR_J_BIT @ Java? tsteq r5, #PSR_T_BIT @ Thumb? - bne do_DataAbort + bne 1f bic r1, r1, #1 << 11 @ clear bit 11 of FSR ldr r3, [r4] @ read aborted ARM instruction ARM_BE8(rev r3, r3) - do_ldrd_abort tmp=ip, insn=r3 + teq_ldrd tmp=ip, insn=r3 @ insn was LDRD? + beq 1f @ yes tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. #endif +1: uaccess_disable ip @ disable userspace access b do_DataAbort diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S index 4812ad054214..e8d0e08c227f 100644 --- a/arch/arm/mm/abort-ev7.S +++ b/arch/arm/mm/abort-ev7.S @@ -15,6 +15,7 @@ ENTRY(v7_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR + uaccess_disable ip @ disable userspace access /* * V6 code adjusts the returned DFSR. diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S index f3982580c273..6d8e8e3365d1 100644 --- a/arch/arm/mm/abort-lv4t.S +++ b/arch/arm/mm/abort-lv4t.S @@ -26,6 +26,7 @@ ENTRY(v4t_late_abort) #endif bne .data_thumb_abort ldr r8, [r4] @ read arm instruction + uaccess_disable ip @ disable userspace access tst r8, #1 << 20 @ L = 1 -> write? orreq r1, r1, #1 << 11 @ yes. and r7, r8, #15 << 24 @@ -155,6 +156,7 @@ ENTRY(v4t_late_abort) .data_thumb_abort: ldrh r8, [r4] @ read instruction + uaccess_disable ip @ disable userspace access tst r8, #1 << 11 @ L = 1 -> write? orreq r1, r1, #1 << 8 @ yes and r7, r8, #15 << 12 diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S index 2cbf68ef0e83..4509bee4e081 100644 --- a/arch/arm/mm/abort-macro.S +++ b/arch/arm/mm/abort-macro.S @@ -13,6 +13,7 @@ tst \psr, #PSR_T_BIT beq not_thumb ldrh \tmp, [\pc] @ Read aborted Thumb instruction + uaccess_disable ip @ disable userspace access and \tmp, \tmp, # 0xfe00 @ Mask opcode field cmp \tmp, # 0x5600 @ Is it ldrsb? orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes @@ -29,12 +30,9 @@ not_thumb: * [7:4] == 1101 * [20] == 0 */ - .macro do_ldrd_abort, tmp, insn - tst \insn, #0x0e100000 @ [27:25,20] == 0 - bne not_ldrd - and \tmp, \insn, #0x000000f0 @ [7:4] == 1101 - cmp \tmp, #0x000000d0 - beq do_DataAbort -not_ldrd: + .macro teq_ldrd, tmp, insn + mov \tmp, #0x0e100000 + orr \tmp, #0x000000f0 + and \tmp, \insn, \tmp + teq \tmp, #0x000000d0 .endm - diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 097181e08c25..5c1b7a7b9af6 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -368,7 +368,6 @@ int __init feroceon_of_init(void) struct device_node *node; void __iomem *base; bool l2_wt_override = false; - struct resource res; #if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) l2_wt_override = true; @@ -376,10 +375,7 @@ int __init feroceon_of_init(void) node = of_find_matching_node(NULL, feroceon_ids); if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { - if (of_address_to_resource(node, 0, &res)) - return -ENODEV; - - base = ioremap(res.start, resource_size(&res)); + base = of_iomap(node, 0); if (!base) return -ENOMEM; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 71b3d3309024..493692d838c6 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const struct device_node *np, } } + if (of_property_read_bool(np, "arm,shared-override")) { + *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE; + *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; + } + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index cba12f34ff77..e62604384945 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -39,6 +39,7 @@ #include <asm/system_info.h> #include <asm/dma-contiguous.h> +#include "dma.h" #include "mm.h" /* @@ -648,14 +649,18 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, size = PAGE_ALIGN(size); want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); - if (is_coherent || nommu()) + if (nommu()) + addr = __alloc_simple_buffer(dev, size, gfp, &page); + else if (dev_get_cma_area(dev) && (gfp & __GFP_WAIT)) + addr = __alloc_from_contiguous(dev, size, prot, &page, + caller, want_vaddr); + else if (is_coherent) addr = __alloc_simple_buffer(dev, size, gfp, &page); else if (!(gfp & __GFP_WAIT)) addr = __alloc_from_pool(size, &page); - else if (!dev_get_cma_area(dev)) - addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller, want_vaddr); else - addr = __alloc_from_contiguous(dev, size, prot, &page, caller, want_vaddr); + addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, + caller, want_vaddr); if (page) *handle = pfn_to_dma(dev, page_to_pfn(page)); @@ -671,10 +676,6 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); - void *memory; - - if (dma_alloc_from_coherent(dev, size, handle, &memory)) - return memory; return __dma_alloc(dev, size, handle, gfp, prot, false, attrs, __builtin_return_address(0)); @@ -683,13 +684,7 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, static void *arm_coherent_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { - pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); - void *memory; - - if (dma_alloc_from_coherent(dev, size, handle, &memory)) - return memory; - - return __dma_alloc(dev, size, handle, gfp, prot, true, + return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, attrs, __builtin_return_address(0)); } @@ -748,17 +743,14 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); - if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) - return; - size = PAGE_ALIGN(size); - if (is_coherent || nommu()) { + if (nommu()) { __dma_free_buffer(page, size); - } else if (__free_from_pool(cpu_addr, size)) { + } else if (!is_coherent && __free_from_pool(cpu_addr, size)) { return; } else if (!dev_get_cma_area(dev)) { - if (want_vaddr) + if (want_vaddr && !is_coherent) __dma_free_remap(cpu_addr, size); __dma_free_buffer(page, size); } else { @@ -1520,7 +1512,7 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, return -ENOMEM; for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { - phys_addr_t phys = page_to_phys(sg_page(s)); + phys_addr_t phys = sg_phys(s) & PAGE_MASK; unsigned int len = PAGE_ALIGN(s->offset + s->length); if (!is_coherent && diff --git a/arch/arm/mm/dma.h b/arch/arm/mm/dma.h new file mode 100644 index 000000000000..70ea6852f94e --- /dev/null +++ b/arch/arm/mm/dma.h @@ -0,0 +1,32 @@ +#ifndef DMA_H +#define DMA_H + +#include <asm/glue-cache.h> + +#ifndef MULTI_CACHE +#define dmac_map_area __glue(_CACHE,_dma_map_area) +#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) + +/* + * These are private to the dma-mapping API. Do not use directly. + * Their sole purpose is to ensure that data held in the cache + * is visible to DMA, or data written by DMA to system memory is + * visible to the CPU. + */ +extern void dmac_map_area(const void *, size_t, int); +extern void dmac_unmap_area(const void *, size_t, int); + +#else + +/* + * These are private to the dma-mapping API. Do not use directly. + * Their sole purpose is to ensure that data held in the cache + * is visible to DMA, or data written by DMA to system memory is + * visible to the CPU. + */ +#define dmac_map_area cpu_cache.dma_map_area +#define dmac_unmap_area cpu_cache.dma_unmap_area + +#endif + +#endif diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 34b66af516ea..1ec8e7590fc6 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -21,6 +21,21 @@ #include "mm.h" +#ifdef CONFIG_ARM_HEAVY_MB +void (*soc_mb)(void); + +void arm_heavy_mb(void) +{ +#ifdef CONFIG_OUTER_CACHE_SYNC + if (outer_cache.sync) + outer_cache.sync(); +#endif + if (soc_mb) + soc_mb(); +} +EXPORT_SYMBOL(arm_heavy_mb); +#endif + #ifdef CONFIG_CPU_CACHE_VIPT static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index ee8dfa793989..9df5f09585ca 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -79,7 +79,7 @@ void *kmap_atomic(struct page *page) type = kmap_atomic_idx_push(); - idx = type + KM_TYPE_NR * smp_processor_id(); + idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM /* @@ -106,7 +106,7 @@ void __kunmap_atomic(void *kvaddr) if (kvaddr >= (void *)FIXADDR_START) { type = kmap_atomic_idx(); - idx = type + KM_TYPE_NR * smp_processor_id(); + idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); if (cache_is_vivt()) __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); @@ -138,7 +138,7 @@ void *kmap_atomic_pfn(unsigned long pfn) return page_address(page); type = kmap_atomic_idx_push(); - idx = type + KM_TYPE_NR * smp_processor_id(); + idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(!pte_none(get_fixmap_pte(vaddr))); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 870838a46d52..7cd15143a507 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -291,13 +291,13 @@ static struct mem_type mem_types[] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_RDONLY, .prot_l1 = PMD_TYPE_TABLE, - .domain = DOMAIN_USER, + .domain = DOMAIN_VECTORS, }, [MT_HIGH_VECTORS] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_USER | L_PTE_RDONLY, .prot_l1 = PMD_TYPE_TABLE, - .domain = DOMAIN_USER, + .domain = DOMAIN_VECTORS, }, [MT_MEMORY_RWX] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, @@ -357,6 +357,47 @@ const struct mem_type *get_mem_type(unsigned int type) } EXPORT_SYMBOL(get_mem_type); +static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); + +static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] + __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; + +static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) +{ + return &bm_pte[pte_index(addr)]; +} + +static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) +{ + return pte_offset_kernel(dir, addr); +} + +static inline pmd_t * __init fixmap_pmd(unsigned long addr) +{ + pgd_t *pgd = pgd_offset_k(addr); + pud_t *pud = pud_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); + + return pmd; +} + +void __init early_fixmap_init(void) +{ + pmd_t *pmd; + + /* + * The early fixmap range spans multiple pmds, for which + * we are not prepared: + */ + BUILD_BUG_ON((__fix_to_virt(__end_of_permanent_fixed_addresses) >> PMD_SHIFT) + != FIXADDR_TOP >> PMD_SHIFT); + + pmd = fixmap_pmd(FIXADDR_TOP); + pmd_populate_kernel(&init_mm, pmd, bm_pte); + + pte_offset_fixmap = pte_offset_early_fixmap; +} + /* * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). * As a result, this can only be called with preemption disabled, as under @@ -365,7 +406,7 @@ EXPORT_SYMBOL(get_mem_type); void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) { unsigned long vaddr = __fix_to_virt(idx); - pte_t *pte = pte_offset_kernel(pmd_off_k(vaddr), vaddr); + pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); /* Make sure fixmap region does not exceed available allocation. */ BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > @@ -855,7 +896,7 @@ static void __init create_mapping(struct map_desc *md) } if ((md->type == MT_DEVICE || md->type == MT_ROM) && - md->virtual >= PAGE_OFFSET && + md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", (long long)__pfn_to_phys((u64)md->pfn), md->virtual); @@ -1219,10 +1260,10 @@ void __init arm_mm_memblock_reserve(void) /* * Set up the device mappings. Since we clear out the page tables for all - * mappings above VMALLOC_START, we will remove any debug device mappings. - * This means you have to be careful how you debug this function, or any - * called function. This means you can't use any function or debugging - * method which may touch any device, otherwise the kernel _will_ crash. + * mappings above VMALLOC_START, except early fixmap, we might remove debug + * device mappings. This means earlycon can be used to debug this function + * Any other function or debugging method which may touch any device _will_ + * crash the kernel. */ static void __init devicemaps_init(const struct machine_desc *mdesc) { @@ -1237,7 +1278,10 @@ static void __init devicemaps_init(const struct machine_desc *mdesc) early_trap_init(vectors); - for (addr = VMALLOC_START; addr; addr += PMD_SIZE) + /* + * Clear page table except top pmd used by early fixmaps + */ + for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); /* @@ -1489,6 +1533,35 @@ void __init early_paging_init(const struct machine_desc *mdesc) #endif +static void __init early_fixmap_shutdown(void) +{ + int i; + unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); + + pte_offset_fixmap = pte_offset_late_fixmap; + pmd_clear(fixmap_pmd(va)); + local_flush_tlb_kernel_page(va); + + for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { + pte_t *pte; + struct map_desc map; + + map.virtual = fix_to_virt(i); + pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); + + /* Only i/o device mappings are supported ATM */ + if (pte_none(*pte) || + (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) + continue; + + map.pfn = pte_pfn(*pte); + map.type = MT_DEVICE; + map.length = PAGE_SIZE; + + create_mapping(&map); + } +} + /* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. @@ -1502,6 +1575,7 @@ void __init paging_init(const struct machine_desc *mdesc) map_lowmem(); memblock_set_current_limit(arm_lowmem_limit); dma_contiguous_remap(); + early_fixmap_shutdown(); devicemaps_init(mdesc); kmap_init(); tcm_init(); diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index a3681f11dd9f..e683db1b90a3 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -84,6 +84,16 @@ pgd_t *pgd_alloc(struct mm_struct *mm) if (!new_pte) goto no_pte; +#ifndef CONFIG_ARM_LPAE + /* + * Modify the PTE pointer to have the correct domain. This + * needs to be the vectors domain to avoid the low vectors + * being unmapped. + */ + pmd_val(*new_pmd) &= ~PMD_DOMAIN_MASK; + pmd_val(*new_pmd) |= PMD_DOMAIN(DOMAIN_VECTORS); +#endif + init_pud = pud_offset(init_pgd, 0); init_pmd = pmd_offset(init_pud, 0); init_pte = pte_offset_map(init_pmd, 0); diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index c011e2296cb1..876060bcceeb 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -857,7 +857,9 @@ b_epilogue: emit(ARM_LDR_I(r_A, r_scratch, off), ctx); break; case BPF_ANC | SKF_AD_IFINDEX: + case BPF_ANC | SKF_AD_HATYPE: /* A = skb->dev->ifindex */ + /* A = skb->dev->type */ ctx->seen |= SEEN_SKB; off = offsetof(struct sk_buff, dev); emit(ARM_LDR_I(r_scratch, r_skb, off), ctx); @@ -867,8 +869,24 @@ b_epilogue: BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, ifindex) != 4); - off = offsetof(struct net_device, ifindex); - emit(ARM_LDR_I(r_A, r_scratch, off), ctx); + BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, + type) != 2); + + if (code == (BPF_ANC | SKF_AD_IFINDEX)) { + off = offsetof(struct net_device, ifindex); + emit(ARM_LDR_I(r_A, r_scratch, off), ctx); + } else { + /* + * offset of field "type" in "struct + * net_device" is above what can be + * used in the ldrh rd, [rn, #imm] + * instruction, so load the offset in + * a register and use ldrh rd, [rn, rm] + */ + off = offsetof(struct net_device, type); + emit_mov_i(ARM_R3, off, ctx); + emit(ARM_LDRH_R(r_A, r_scratch, ARM_R3), ctx); + } break; case BPF_ANC | SKF_AD_MARK: ctx->seen |= SEEN_SKB; @@ -895,6 +913,17 @@ b_epilogue: OP_IMM3(ARM_AND, r_A, r_A, 0x1, ctx); } break; + case BPF_ANC | SKF_AD_PKTTYPE: + ctx->seen |= SEEN_SKB; + BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, + __pkt_type_offset[0]) != 1); + off = PKT_TYPE_OFFSET(); + emit(ARM_LDRB_I(r_A, r_skb, off), ctx); + emit(ARM_AND_I(r_A, r_A, PKT_TYPE_MAX), ctx); +#ifdef __BIG_ENDIAN_BITFIELD + emit(ARM_LSR_I(r_A, r_A, 5), ctx); +#endif + break; case BPF_ANC | SKF_AD_QUEUE: ctx->seen |= SEEN_SKB; BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, @@ -904,6 +933,14 @@ b_epilogue: off = offsetof(struct sk_buff, queue_mapping); emit(ARM_LDRH_I(r_A, r_skb, off), ctx); break; + case BPF_ANC | SKF_AD_PAY_OFFSET: + ctx->seen |= SEEN_SKB | SEEN_CALL; + + emit(ARM_MOV_R(ARM_R0, r_skb), ctx); + emit_mov_i(ARM_R3, (unsigned int)skb_get_poff, ctx); + emit_blx_r(ARM_R3, ctx); + emit(ARM_MOV_R(r_A, ARM_R0), ctx); + break; case BPF_LDX | BPF_W | BPF_ABS: /* * load a 32bit word from struct seccomp_data. diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h index b2d7d92859d3..4b17d5ab652a 100644 --- a/arch/arm/net/bpf_jit_32.h +++ b/arch/arm/net/bpf_jit_32.h @@ -74,6 +74,7 @@ #define ARM_INST_LDRB_I 0x05d00000 #define ARM_INST_LDRB_R 0x07d00000 #define ARM_INST_LDRH_I 0x01d000b0 +#define ARM_INST_LDRH_R 0x019000b0 #define ARM_INST_LDR_I 0x05900000 #define ARM_INST_LDM 0x08900000 @@ -160,6 +161,8 @@ | (rm)) #define ARM_LDRH_I(rt, rn, off) (ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \ | (((off) & 0xf0) << 4) | ((off) & 0xf)) +#define ARM_LDRH_R(rt, rn, rm) (ARM_INST_LDRH_R | (rt) << 12 | (rn) << 16 \ + | (rm)) #define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs)) diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 6ad65d8ae237..101e8f2c7abe 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -77,41 +77,57 @@ static int iop_set_next_event(unsigned long delta, static unsigned long ticks_per_jiffy; -static void iop_set_mode(enum clock_event_mode mode, - struct clock_event_device *unused) +static int iop_set_periodic(struct clock_event_device *evt) { u32 tmr = read_tmr0(); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - write_tmr0(tmr & ~IOP_TMR_EN); - write_tcr0(ticks_per_jiffy - 1); - write_trr0(ticks_per_jiffy - 1); - tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* ->set_next_event sets period and enables timer */ - tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); - break; - case CLOCK_EVT_MODE_RESUME: - tmr |= IOP_TMR_EN; - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - default: - tmr &= ~IOP_TMR_EN; - break; - } + write_tmr0(tmr & ~IOP_TMR_EN); + write_tcr0(ticks_per_jiffy - 1); + write_trr0(ticks_per_jiffy - 1); + tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); write_tmr0(tmr); + return 0; +} + +static int iop_set_oneshot(struct clock_event_device *evt) +{ + u32 tmr = read_tmr0(); + + /* ->set_next_event sets period and enables timer */ + tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); + write_tmr0(tmr); + return 0; +} + +static int iop_shutdown(struct clock_event_device *evt) +{ + u32 tmr = read_tmr0(); + + tmr &= ~IOP_TMR_EN; + write_tmr0(tmr); + return 0; +} + +static int iop_resume(struct clock_event_device *evt) +{ + u32 tmr = read_tmr0(); + + tmr |= IOP_TMR_EN; + write_tmr0(tmr); + return 0; } static struct clock_event_device iop_clockevent = { - .name = "iop_timer0", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = iop_set_next_event, - .set_mode = iop_set_mode, + .name = "iop_timer0", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_next_event = iop_set_next_event, + .set_state_shutdown = iop_shutdown, + .set_state_periodic = iop_set_periodic, + .tick_resume = iop_resume, + .set_state_oneshot = iop_set_oneshot, }; static irqreturn_t diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 5168a52a17f9..79c33eca09a3 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -407,9 +407,9 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) return 0; } -static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void gpio_irq_handler(unsigned __irq, struct irq_desc *desc) { - struct orion_gpio_chip *ochip = irq_get_handler_data(irq); + struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc); u32 cause, type; int i; @@ -582,8 +582,9 @@ void __init orion_gpio_init(struct device_node *np, for (i = 0; i < 4; i++) { if (irqs[i]) { - irq_set_handler_data(irqs[i], ochip); - irq_set_chained_handler(irqs[i], gpio_irq_handler); + irq_set_chained_handler_and_data(irqs[i], + gpio_irq_handler, + ochip); } } diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 261258f717fc..8085a8aac812 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -106,60 +106,63 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) return 0; } -static void -orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +static int orion_clkevt_shutdown(struct clock_event_device *evt) { unsigned long flags; u32 u; local_irq_save(flags); - if (mode == CLOCK_EVT_MODE_PERIODIC) { - /* - * Setup timer to fire at 1/HZ intervals. - */ - writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); - writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); - - /* - * Enable timer interrupt. - */ - u = readl(bridge_base + BRIDGE_MASK_OFF); - writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); - - /* - * Enable timer. - */ - u = readl(timer_base + TIMER_CTRL_OFF); - writel(u | TIMER1_EN | TIMER1_RELOAD_EN, - timer_base + TIMER_CTRL_OFF); - } else { - /* - * Disable timer. - */ - u = readl(timer_base + TIMER_CTRL_OFF); - writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); - - /* - * Disable timer interrupt. - */ - u = readl(bridge_base + BRIDGE_MASK_OFF); - writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); - - /* - * ACK pending timer interrupt. - */ - writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); - - } + + /* Disable timer */ + u = readl(timer_base + TIMER_CTRL_OFF); + writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); + + /* Disable timer interrupt */ + u = readl(bridge_base + BRIDGE_MASK_OFF); + writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); + + /* ACK pending timer interrupt */ + writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); + + local_irq_restore(flags); + + return 0; +} + +static int orion_clkevt_set_periodic(struct clock_event_device *evt) +{ + unsigned long flags; + u32 u; + + local_irq_save(flags); + + /* Setup timer to fire at 1/HZ intervals */ + writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); + writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); + + /* Enable timer interrupt */ + u = readl(bridge_base + BRIDGE_MASK_OFF); + writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); + + /* Enable timer */ + u = readl(timer_base + TIMER_CTRL_OFF); + writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF); + local_irq_restore(flags); + + return 0; } static struct clock_event_device orion_clkevt = { - .name = "orion_tick", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .rating = 300, - .set_next_event = orion_clkevt_next_event, - .set_mode = orion_clkevt_mode, + .name = "orion_tick", + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, + .rating = 300, + .set_next_event = orion_clkevt_next_event, + .set_state_shutdown = orion_clkevt_shutdown, + .set_state_periodic = orion_clkevt_set_periodic, + .set_state_oneshot = orion_clkevt_shutdown, + .tick_resume = orion_clkevt_shutdown, }; static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index d92f07f6ecfb..de2b061889ec 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -289,7 +289,8 @@ int pxa_request_dma (char *name, pxa_dma_prio prio, /* try grabbing a DMA channel with the requested priority */ for (i = 0; i < num_dma_channels; i++) { if ((dma_channels[i].prio == prio) && - !dma_channels[i].name) { + !dma_channels[i].name && + !pxad_toggle_reserved_channel(i)) { found = 1; break; } @@ -326,13 +327,14 @@ void pxa_free_dma (int dma_ch) local_irq_save(flags); DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; dma_channels[dma_ch].name = NULL; + pxad_toggle_reserved_channel(dma_ch); local_irq_restore(flags); } EXPORT_SYMBOL(pxa_free_dma); static irqreturn_t dma_irq_handler(int irq, void *dev_id) { - int i, dint = DINT; + int i, dint = DINT, done = 0; struct dma_channel *channel; while (dint) { @@ -341,16 +343,13 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) channel = &dma_channels[i]; if (channel->name && channel->irq_handler) { channel->irq_handler(i, channel->data); - } else { - /* - * IRQ for an unregistered DMA channel: - * let's clear the interrupts and disable it. - */ - printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); - DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; + done++; } } - return IRQ_HANDLED; + if (done) + return IRQ_HANDLED; + else + return IRQ_NONE; } int __init pxa_init_dma(int irq, int num_ch) @@ -372,7 +371,8 @@ int __init pxa_init_dma(int irq, int num_ch) spin_lock_init(&dma_channels[i].lock); } - ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL); + ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA", + dma_channels); if (ret) { printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); kfree(dma_channels); diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h index a7b91dc06852..28848b344e2d 100644 --- a/arch/arm/plat-pxa/include/plat/dma.h +++ b/arch/arm/plat-pxa/include/plat/dma.h @@ -82,4 +82,19 @@ int pxa_request_dma (char *name, void pxa_free_dma (int dma_ch); +/* + * Cooperation with pxa_dma + dmaengine while there remains at least one pxa + * driver not converted to dmaengine. + */ +#if defined(CONFIG_PXA_DMA) +extern int pxad_toggle_reserved_channel(int legacy_channel); +#else +static inline int pxad_toggle_reserved_channel(int legacy_channel) +{ + return 0; +} +#endif + +extern void __init pxa2xx_set_dmac_info(int nb_channels); + #endif /* __PLAT_DMA_H */ diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index cb8e3d655d1a..57729b915003 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -217,12 +217,6 @@ config SAMSUNG_DEV_PWM help Compile in platform device definition for PWM Timer -config SAMSUNG_DEV_BACKLIGHT - bool - depends on SAMSUNG_DEV_PWM - help - Compile in platform device definition LCD backlight with PWM Timer - config S3C24XX_PWM bool "PWM device support" select PWM @@ -231,25 +225,14 @@ config S3C24XX_PWM Support for exporting the PWM timer blocks via the pwm device system -config S3C_SETUP_CAMIF - bool - help - Compile in common setup code for S3C CAMIF devices - config SAMSUNG_PM_GPIO bool default y if GPIO_SAMSUNG && PM help Include legacy GPIO power management code for platforms not using pinctrl-samsung driver. - endif -config S5P_DEV_MFC - bool - help - Compile in setup memory (init) code for MFC - comment "Power management" config SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 1a29ab1f446d..8c911760f55f 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -20,11 +20,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o -obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o - -obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o - -obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o # PM support diff --git a/arch/arm/plat-samsung/include/plat/keypad-core.h b/arch/arm/plat-samsung/include/plat/keypad-core.h deleted file mode 100644 index d513e1b3a31e..000000000000 --- a/arch/arm/plat-samsung/include/plat/keypad-core.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * linux/arch/arm/plat-samsung/include/plat/keypad-core.h - * - * Copyright (C) 2010 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * Samsung keypad controller core function - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __ASM_ARCH_KEYPAD_CORE_H -#define __ASM_ARCH_KEYPAD_CORE_H - -/* These function are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -/* re-define device name depending on support. */ -static inline void samsung_keypad_setname(char *name) -{ -#ifdef CONFIG_SAMSUNG_DEV_KEYPAD - samsung_device_keypad.name = name; -#endif -} - -#endif /* __ASM_ARCH_KEYPAD_CORE_H */ diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 6c09cc440a2b..eeeab074e154 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -45,46 +45,39 @@ static struct vcpu_info __percpu *xen_vcpu_info; unsigned long xen_released_pages; struct xen_memory_region xen_extra_mem[XEN_EXTRA_MEM_MAX_REGIONS] __initdata; -/* TODO: to be removed */ -__read_mostly int xen_have_vector_callback; -EXPORT_SYMBOL_GPL(xen_have_vector_callback); - -int xen_platform_pci_unplug = XEN_UNPLUG_ALL; -EXPORT_SYMBOL_GPL(xen_platform_pci_unplug); - static __read_mostly unsigned int xen_events_irq; static __initdata struct device_node *xen_node; -int xen_remap_domain_mfn_array(struct vm_area_struct *vma, +int xen_remap_domain_gfn_array(struct vm_area_struct *vma, unsigned long addr, - xen_pfn_t *mfn, int nr, + xen_pfn_t *gfn, int nr, int *err_ptr, pgprot_t prot, unsigned domid, struct page **pages) { - return xen_xlate_remap_gfn_array(vma, addr, mfn, nr, err_ptr, + return xen_xlate_remap_gfn_array(vma, addr, gfn, nr, err_ptr, prot, domid, pages); } -EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_array); +EXPORT_SYMBOL_GPL(xen_remap_domain_gfn_array); /* Not used by XENFEAT_auto_translated guests. */ -int xen_remap_domain_mfn_range(struct vm_area_struct *vma, +int xen_remap_domain_gfn_range(struct vm_area_struct *vma, unsigned long addr, - xen_pfn_t mfn, int nr, + xen_pfn_t gfn, int nr, pgprot_t prot, unsigned domid, struct page **pages) { return -ENOSYS; } -EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range); +EXPORT_SYMBOL_GPL(xen_remap_domain_gfn_range); -int xen_unmap_domain_mfn_range(struct vm_area_struct *vma, +int xen_unmap_domain_gfn_range(struct vm_area_struct *vma, int nr, struct page **pages) { return xen_xlate_unmap_gfn_range(vma, nr, pages); } -EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range); +EXPORT_SYMBOL_GPL(xen_unmap_domain_gfn_range); static void xen_percpu_init(void) { diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c index 03e75fef15b8..6dd911d1f0ac 100644 --- a/arch/arm/xen/mm.c +++ b/arch/arm/xen/mm.c @@ -139,9 +139,9 @@ void __xen_dma_sync_single_for_device(struct device *hwdev, bool xen_arch_need_swiotlb(struct device *dev, unsigned long pfn, - unsigned long mfn) + unsigned long bfn) { - return (!hypercall_cflush && (pfn != mfn) && !is_device_dma_coherent(dev)); + return (!hypercall_cflush && (pfn != bfn) && !is_device_dma_coherent(dev)); } int xen_create_contiguous_region(phys_addr_t pstart, unsigned int order, |