diff options
| author | Gayatri Kammela <gayatri.kammela@intel.com> | 2021-04-16 20:12:47 -0700 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2021-04-19 10:41:24 +0200 |
| commit | 29c2dd88ac9ed5780a762e49585e65e99c90d5a8 (patch) | |
| tree | f5220d7a37fb464551745c25089c34c79a5a701e /drivers/platform | |
| parent | 005125bfd70eb5532d284cc6e23396e161eb679e (diff) | |
platform/x86: intel_pmc_core: Show LPM residency in microseconds
Modify the low power mode (LPM or sub-state) residency counters to display
in microseconds just like the slp_s0_residency counter. The granularity of
the counter is approximately 30.5us per tick. Double this value then divide
by two to maintain accuracy.
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20210417031252.3020837-5-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.c | 14 | ||||
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 3 |
2 files changed, 15 insertions, 2 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index c02f63c00ecc..0e59a84b51bf 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -580,6 +580,7 @@ static const struct pmc_reg_map tgl_reg_map = { .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED, .lpm_num_maps = TGL_LPM_NUM_MAPS, + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, .lpm_en_offset = TGL_LPM_EN_OFFSET, .lpm_priority_offset = TGL_LPM_PRI_OFFSET, .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, @@ -1138,17 +1139,26 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); +static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset, + const int lpm_adj_x2) +{ + u64 lpm_res = pmc_core_reg_read(pmcdev, offset); + + return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res); +} + static int pmc_core_substate_res_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; + const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2; u32 offset = pmcdev->map->lpm_residency_offset; int i, mode; seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); pmc_for_each_mode(i, mode, pmcdev) { - seq_printf(s, "%-10s %-15u\n", pmc_lpm_modes[mode], - pmc_core_reg_read(pmcdev, offset + (4 * mode))); + seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode], + adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2)); } return 0; diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 2ffe0eba36e1..aa44fd5399cc 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -188,9 +188,11 @@ enum ppfear_regs { #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 #define LPM_MAX_NUM_MODES 8 +#define GET_X2_COUNTER(v) ((v) >> 1) #define TGL_NUM_IP_IGN_ALLOWED 22 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A +#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ /* * Tigerlake Power Management Controller register offsets @@ -268,6 +270,7 @@ struct pmc_reg_map { const u32 pm_vric1_offset; /* Low Power Mode registers */ const int lpm_num_maps; + const int lpm_res_counter_step_x2; const u32 lpm_en_offset; const u32 lpm_priority_offset; const u32 lpm_residency_offset; |