path: root/drivers/ntb
diff options
authorRoland Dreier <roland@purestorage.com>2014-02-21 08:07:21 -0800
committerJon Mason <jon.mason@intel.com>2014-04-07 10:58:14 -0700
commitc8eee3795d68d4b7448ce9e6752de379d9fe2c23 (patch)
treee92ecb2efea8499d51b57fbf9a9d952b53f9e58d /drivers/ntb
parente8bc2ebdceea3c0c6de16d899f0679654c308739 (diff)
NTB: Fix typo in setting one translation register
In the code for Xeon devices in back-to-back mode with xeon_errata_workaround disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL (SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR). This was spotted while reading code, since the typo has no practical effect, at least for now: the low 32 bits of both constants are actually identical anyway. However, it's clearer and safer to use the right name. Signed-off-by: Roland Dreier <roland@purestorage.com> Signed-off-by: Jon Mason <jon.mason@intel.com>
Diffstat (limited to 'drivers/ntb')
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c
index 170e8e60cdb7..2774d356b689 100644
--- a/drivers/ntb/ntb_hw.c
+++ b/drivers/ntb/ntb_hw.c
@@ -785,7 +785,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
/* B2B_XLAT_OFFSET is a 64bit register, but can
* only take 32bit writes
- writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
+ writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
writel(SNB_MBAR01_USD_ADDR >> 32,
ndev->reg_base + SNB_B2B_XLAT_OFFSETU);