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authorVladimir Oltean <vladimir.oltean@nxp.com>2022-05-22 00:37:42 +0300
committerDavid S. Miller <davem@davemloft.net>2022-05-23 10:39:54 +0100
commitc295f9831f1db12330d6a28a1cb2bd2562535e37 (patch)
tree7c63c40fbe883a321c0391499d91cb10ebe35824 /drivers/net/ethernet
parent8c166acb60f8284470db673b6dccd43e6fedfae2 (diff)
net: mscc: ocelot: switch from {,un}set to {,un}assign for tag_8021q CPU ports
There is a desire for the felix driver to gain support for multiple tag_8021q CPU ports, but the current model prevents it. This is because ocelot_apply_bridge_fwd_mask() only takes into consideration whether a port is a tag_8021q CPU port, but not whose CPU port it is. We need a model where we can have a direct affinity between an ocelot port and a tag_8021q CPU port. This serves as the basis for multiple CPU ports. Declare a "dsa_8021q_cpu" backpointer in struct ocelot_port which encodes that affinity. Repurpose the "ocelot_set_dsa_8021q_cpu" API to "ocelot_assign_dsa_8021q_cpu" to express the change of paradigm. Note that this change makes the first practical use of the new ocelot_port->index field in ocelot_port_unassign_dsa_8021q_cpu(), where we need to remove the old tag_8021q CPU port from the reserved VLAN range. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/mscc/ocelot.c120
1 files changed, 74 insertions, 46 deletions
diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index d208d57f4894..8da7e25a47c9 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -2046,57 +2046,68 @@ static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
return __ffs(bond_mask);
}
-u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
+static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
+ struct ocelot_port *cpu)
{
- struct ocelot_port *ocelot_port = ocelot->ports[src_port];
- const struct net_device *bridge;
u32 mask = 0;
int port;
- if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
- return 0;
-
- bridge = ocelot_port->bridge;
- if (!bridge)
- return 0;
-
for (port = 0; port < ocelot->num_phys_ports; port++) {
- ocelot_port = ocelot->ports[port];
+ struct ocelot_port *ocelot_port = ocelot->ports[port];
if (!ocelot_port)
continue;
- if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
- ocelot_port->bridge == bridge)
+ if (ocelot_port->dsa_8021q_cpu == cpu)
mask |= BIT(port);
}
return mask;
}
-EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
-u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
+u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
{
+ struct ocelot_port *ocelot_port = ocelot->ports[port];
+ struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
+
+ if (!cpu_port)
+ return 0;
+
+ return BIT(cpu_port->index);
+}
+EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
+
+u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
+{
+ struct ocelot_port *ocelot_port = ocelot->ports[src_port];
+ const struct net_device *bridge;
u32 mask = 0;
int port;
+ if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
+ return 0;
+
+ bridge = ocelot_port->bridge;
+ if (!bridge)
+ return 0;
+
for (port = 0; port < ocelot->num_phys_ports; port++) {
- struct ocelot_port *ocelot_port = ocelot->ports[port];
+ ocelot_port = ocelot->ports[port];
if (!ocelot_port)
continue;
- if (ocelot_port->is_dsa_8021q_cpu)
+ if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
+ ocelot_port->bridge == bridge)
mask |= BIT(port);
}
return mask;
}
-EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask);
+EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
{
- unsigned long cpu_fwd_mask;
int port;
lockdep_assert_held(&ocelot->fwd_domain_lock);
@@ -2108,15 +2119,6 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
if (joining && ocelot->ops->cut_through_fwd)
ocelot->ops->cut_through_fwd(ocelot);
- /* If a DSA tag_8021q CPU exists, it needs to be included in the
- * regular forwarding path of the front ports regardless of whether
- * those are bridged or standalone.
- * If DSA tag_8021q is not used, this returns 0, which is fine because
- * the hardware-based CPU port module can be a destination for packets
- * even if it isn't part of PGID_SRC.
- */
- cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
-
/* Apply FWD mask. The loop is needed to add/remove the current port as
* a source for the other ports.
*/
@@ -2129,17 +2131,19 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
mask = 0;
} else if (ocelot_port->is_dsa_8021q_cpu) {
/* The DSA tag_8021q CPU ports need to be able to
- * forward packets to all other ports except for
- * themselves
+ * forward packets to all ports assigned to them.
*/
- mask = GENMASK(ocelot->num_phys_ports - 1, 0);
- mask &= ~cpu_fwd_mask;
+ mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
+ ocelot_port);
} else if (ocelot_port->bridge) {
struct net_device *bond = ocelot_port->bond;
mask = ocelot_get_bridge_fwd_mask(ocelot, port);
- mask |= cpu_fwd_mask;
mask &= ~BIT(port);
+
+ mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
+ port);
+
if (bond)
mask &= ~ocelot_get_bond_mask(ocelot, bond);
} else {
@@ -2147,7 +2151,8 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
* ports (if those exist), or to the hardware CPU port
* module otherwise.
*/
- mask = cpu_fwd_mask;
+ mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
+ port);
}
ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
@@ -2191,43 +2196,66 @@ static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
}
-void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port)
+void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
+ int cpu)
{
+ struct ocelot_port *cpu_port = ocelot->ports[cpu];
u16 vid;
mutex_lock(&ocelot->fwd_domain_lock);
- ocelot->ports[port]->is_dsa_8021q_cpu = true;
+ ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
+
+ if (!cpu_port->is_dsa_8021q_cpu) {
+ cpu_port->is_dsa_8021q_cpu = true;
- for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
- ocelot_vlan_member_add(ocelot, port, vid, true);
+ for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
+ ocelot_vlan_member_add(ocelot, cpu, vid, true);
- ocelot_update_pgid_cpu(ocelot);
+ ocelot_update_pgid_cpu(ocelot);
+ }
ocelot_apply_bridge_fwd_mask(ocelot, true);
mutex_unlock(&ocelot->fwd_domain_lock);
}
-EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu);
+EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
-void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port)
+void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
{
+ struct ocelot_port *cpu_port = ocelot->ports[port]->dsa_8021q_cpu;
+ bool keep = false;
u16 vid;
+ int p;
mutex_lock(&ocelot->fwd_domain_lock);
- ocelot->ports[port]->is_dsa_8021q_cpu = false;
+ ocelot->ports[port]->dsa_8021q_cpu = NULL;
+
+ for (p = 0; p < ocelot->num_phys_ports; p++) {
+ if (!ocelot->ports[p])
+ continue;
+
+ if (ocelot->ports[p]->dsa_8021q_cpu == cpu_port) {
+ keep = true;
+ break;
+ }
+ }
+
+ if (!keep) {
+ cpu_port->is_dsa_8021q_cpu = false;
- for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
- ocelot_vlan_member_del(ocelot, port, vid);
+ for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
+ ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
- ocelot_update_pgid_cpu(ocelot);
+ ocelot_update_pgid_cpu(ocelot);
+ }
ocelot_apply_bridge_fwd_mask(ocelot, true);
mutex_unlock(&ocelot->fwd_domain_lock);
}
-EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu);
+EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
{