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authorLars-Peter Clausen <lars@metafoo.de>2020-04-03 15:27:14 +0200
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2020-04-19 17:50:01 +0100
commitf954b098fbac4d183219ce5b42d76d6df2aed50a (patch)
tree52ba4a35c8aea51cb2ab5755c60de104cfcf338d /drivers/iio/adc
parente44ec7794d88f918805d700240211a9ec05ed89d (diff)
downloadlinux-f954b098fbac4d183219ce5b42d76d6df2aed50a.tar.gz
iio: xilinx-xadc: Fix clearing interrupt when enabling trigger
When enabling the trigger and unmasking the end-of-sequence (EOS) interrupt the EOS interrupt should be cleared from the status register. Otherwise it is possible that it was still set from a previous capture. If that is the case the interrupt would fire immediately even though no conversion has been done yet and stale data is being read from the device. The old code only clears the interrupt if the interrupt was previously unmasked. Which does not make much sense since the interrupt is always masked at this point and in addition masking the interrupt does not clear the interrupt from the status register. So the clearing needs to be done unconditionally. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc')
-rw-r--r--drivers/iio/adc/xilinx-xadc-core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index f50e04a8b0ec..62ded9683a57 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -674,7 +674,7 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
spin_lock_irqsave(&xadc->lock, flags);
xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
- xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS);
+ xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
if (state)
val |= XADC_AXI_INT_EOS;
else