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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2014-03-07 20:08:14 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-19 16:39:41 +0100
commit7c8615d8f9faf7a33ad528a012e097631599207f (patch)
treeca5d15fed81e4f742eb4ead64e247f60f445e1b3 /drivers/gpu/drm/i915/intel_pm.c
parent6a932d88ae88ed8c601956802be8f8f39a06821d (diff)
drm/i915: remove dev_priv->pc8.enabled
It was just being used on debugfs and on a WARN inside hsw_set_power_well. But now that we PC8 is part of runtime PM and we get/put runtime PM when we get/put any power domain, we shouldn't need the WARN anymore. v2: - Rebase. v3: - Rebase. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 012867e85cda..ddd0368460ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5345,8 +5345,6 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
bool is_enabled, enable_requested;
uint32_t tmp;
- WARN_ON(dev_priv->pc8.enabled);
-
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
@@ -6161,7 +6159,6 @@ void intel_pm_setup(struct drm_device *dev)
mutex_init(&dev_priv->pc8.lock);
dev_priv->pc8.irqs_disabled = false;
- dev_priv->pc8.enabled = false;
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
intel_gen6_powersave_work);
}