diff options
| author | Imre Deak <imre.deak@intel.com> | 2017-07-11 23:42:32 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 09:38:50 +0200 |
| commit | fb9248e202df17cf731c76305f6015bf409179ca (patch) | |
| tree | 032dc527e33227a6c25ff315ef8596af8e8f06ad /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 120b56a2a7a262c0940299615c7bcf97d3982711 (diff) | |
drm/i915/hsw, bdw: Add an ID for the global display power well
Add an ID for the HSW/BDW global display power well for consistency. The
ID is selected so that it can be used to get at the HW request and
status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW
and GEN9+ versions of these macros and the power well ops using them
will be done in follow-up patches.
v2:
- Rebased on v2 of patch 2.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-3-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ef0c1a86a52f..23dc1b5328d0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1098,6 +1098,12 @@ enum i915_power_well_id { CHV_DISP_PW_PIPE_A, /* 13 */ /* + * HSW/BDW + * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + */ + HSW_DISP_PW_GLOBAL = 15, + + /* * GEN9+ * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) */ |