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authorIuliana Prodan <iuliana.prodan@nxp.com>2019-03-22 15:39:28 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2019-03-28 13:55:34 +0800
commit33d69455e402ad45f3c9f8df6af14866454655e7 (patch)
treebeae41e715430afb2a357e2b44549acb35eb8605 /drivers/crypto/cavium
parentc23116e48a9b8ffe2fa520add3ba5ba52049327a (diff)
crypto: caam - limit AXI pipeline to a depth of 1
Some i.MX6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6DQ) have an issue wherein AXI bus transactions may not occur in the correct order. This isn't a problem running single descriptors, but can be if running multiple concurrent descriptors. Reworking the CAAM driver to throttle to single requests is impractical, so this patch limits the AXI pipeline to a depth of one (from a default of 4) to preclude this situation from occurring. This patch applies to known affected platforms. Signed-off-by: Radu Solea <radu.solea@nxp.com> Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/cavium')
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