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authorLinus Torvalds <torvalds@linux-foundation.org>2014-05-21 18:55:17 +0900
committerLinus Torvalds <torvalds@linux-foundation.org>2014-05-21 18:55:17 +0900
commit026d68be45a217f65f1617d08271f6838bfc07d7 (patch)
tree8c85cbd8c0aeb7899473173fff41cd595a3401c6 /drivers/clk/socfpga/clk-pll.c
parentb2e3432af1546a9f44a8278a8a91abfbd439259e (diff)
parentd2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 (diff)
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework fixes from Mike Turquette: "Clock framework and driver fixes, all of which fix user-visible regressions. As usual most fixes are for platform-specific clock drivers, but there are also two fixes to the clk core after recent changes to the way that clock unregistration is handled" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: tegra: Fix wrong value written to PLLE_AUX clk: shmobile: clk-mstp: change to using clock-indices clk: Fix slab corruption in clk_unregister() clk: Fix double free due to devm_clk_register() clk: socfpga: fix clock driver for 3.15 clk: divider: Fix best div calculation for power-of-two and table dividers clk: bcm281xx: don't use unnamed structs or unions
Diffstat (limited to 'drivers/clk/socfpga/clk-pll.c')
-rw-r--r--drivers/clk/socfpga/clk-pll.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 88dafb5e9627..de6da957a09d 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -20,6 +20,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include "clk.h"
@@ -43,6 +44,8 @@
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
+void __iomem *clk_mgr_base_addr;
+
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
@@ -87,6 +90,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
+ struct device_node *clkmgr_np;
int rc;
int i = 0;
@@ -96,6 +100,9 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
if (WARN_ON(!pll_clk))
return NULL;
+ clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
+ clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
+ BUG_ON(!clk_mgr_base_addr);
pll_clk->hw.reg = clk_mgr_base_addr + reg;
of_property_read_string(node, "clock-output-names", &clk_name);