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authorSanchayan Maity <maitysanchayan@gmail.com>2015-09-07 13:51:35 +0530
committerShawn Guo <shawnguo@kernel.org>2015-09-22 18:02:40 -0700
commit0753f56e411a5e216c9899c21e54bd11dde17313 (patch)
tree8368e4b4bb79fbb1b764d6c614c7de1d30eee513 /drivers/clk/imx/clk-vf610.c
parent8efaf5ed4d442068a1b76f218c0a90e6a5989f11 (diff)
downloadlinux-0753f56e411a5e216c9899c21e54bd11dde17313.tar.gz
clk: clk-vf610: Add clock for Vybrid OCOTP controller
Add clock support for Vybrid On-Chip One Time Programmable (OCOTP) controller. While the OCOTP block does not require explicit clock gating, for programming the OCOTP timing register the clock rate of ipg clock is required for timing calculations related to fuse and shadow register read sequence. We explicitly specify the ipg clock for OCOTP as a result. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk-vf610.c')
-rw-r--r--drivers/clk/imx/clk-vf610.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index bff45ead7389..d1b1c95177bb 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -387,6 +387,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
+ clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
imx_check_clocks(clk, ARRAY_SIZE(clk));