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authorGreentime Hu <greentime.hu@sifive.com>2019-12-19 14:44:59 +0800
committerPaul Walmsley <paul.walmsley@sifive.com>2019-12-20 03:32:24 -0800
commitd411cf02ed0260dacc4b2fd61dd5040fc2aa97e7 (patch)
treed98782836429105d82651dcf854cbb42799a1132 /arch
parent0312a3d4b43c0045869379affc0e228e36411c78 (diff)
downloadlinux-d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7.tar.gz
riscv: fix scratch register clearing in M-mode.
This patch fixes that the sscratch register clearing in M-mode. It cleared sscratch register in M-mode, but it should clear mscratch register. That will cause kernel trap if the CPU core doesn't support S-mode when trying to access sscratch. Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/kernel/head.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 84a6f0a4b120..797802c73dee 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -246,7 +246,7 @@ ENTRY(reset_regs)
li t4, 0
li t5, 0
li t6, 0
- csrw sscratch, 0
+ csrw CSR_SCRATCH, 0
#ifdef CONFIG_FPU
csrr t0, CSR_MISA