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authorLinus Torvalds <torvalds@linux-foundation.org>2018-12-31 17:36:02 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2018-12-31 17:36:02 -0800
commitb7badd1d7aa61087010803affa19bb83fb5a0af1 (patch)
tree3b2a913060d952d93bc5a712dca10733a17e3c99 /arch
parentd36377c6eb071e3d0751e9e0e3c19198c58d9a5d (diff)
parent3f47de2c6b6068cf7d5221f8f307969e7e4f1fc5 (diff)
downloadlinux-b7badd1d7aa61087010803affa19bb83fb5a0af1.tar.gz
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson: "As usual, this is where the bulk of our changes end up landing each merge window. The individual updates are too many to enumerate, many many platforms have seen additions of device descriptions such that they are functionally more complete (in fact, this is often the bulk of updates we see). Instead I've mostly focused on highlighting the new platforms below as they are introduced. Sometimes the introduction is of mostly a fragment, that later gets filled in on later releases, and in some cases it's near-complete platform support. The latter is more common for derivative platforms that already has similar support in-tree. Two SoCs are slight outliers from the usual range of additions. Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping in the Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at infrastructure/networking. TI updates stick out in the diff stats too, in particular because they have moved the description of their L4 on-chip interconnect to devicetree, which opens up for removal of even more of their platform-specific 'hwmod' description tables over the next few releases. SoCs: - Qualcomm QCS404 (4x Cortex-A53) - Allwinner T3 (rebranded R40) and f1c100s (armv5) - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4) - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72) New platforms: - Rockchip: Gru Scarlet (RK3188 Tablet) - Amlogic: Phicomm N1 (S905D), Libretech S805-AC - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708) - Qualcomm: QCS404 base platform and EVB - Qualcomm: Remove of Arrow SD600 - PXA: First PXA3xx DT board: Raumfeld - Aspeed: Facebook Backpack-CMM BMC - Renesas iWave G20D-Q7 (RZ/G1N) - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s) - Allwinner Emlid Neutis N5, Mapleboard MP130 - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE) - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva - VF610: Liebherr's BK4 device, ZII SCU4 AIB board - i.MX7D PICO Hobbit baseboard - i.MX7ULP EVK board - NXP LX2160AQDS and LX2160ARDB boards Other: - Coresight binding updates across the board - CPU cooling maps updates across the board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits) ARM: dts: suniv: Fix improper bindings include patch ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node ARM: dts: suniv: Fix improper bindings include patch arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller arm64: dts: Remove unused properties from FSL QSPI driver nodes ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes ARM: dts: Remove unused properties from FSL QSPI driver nodes arm64: dts: ti: k3-am654: Enable main domain McSPI0 arm64: dts: ti: k3-am654: Add McSPI DT nodes arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM arm64: dts: ti: k3-am65-main: Add ECAP PWM node arm64: dts: ti: k3-am654-base-board: Add I2C nodes arm64: dts: ti: am654-base-board: Add pinmux for main uart0 arm64: dts: ti: k3-am65: Add pinctrl regions dt-bindings: pinctrl: k3: Introduce pinmux definitions ARM: dts: exynos: Specify I2S assigned clocks in proper node ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2 ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/Makefile26
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi2
-rw-r--r--arch/arm/boot/dts/am335x-boneblue.dts2
-rw-r--r--arch/arm/boot/dts/am335x-cm-t335.dts2
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts4
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts4
-rw-r--r--arch/arm/boot/dts/am335x-osd3358-sm-red.dts2
-rw-r--r--arch/arm/boot/dts/am335x-shc.dts4
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi110
-rw-r--r--arch/arm/boot/dts/am33xx-l4.dtsi2132
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi623
-rw-r--r--arch/arm/boot/dts/am3517-evm.dts4
-rw-r--r--arch/arm/boot/dts/am4372.dtsi876
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts127
-rw-r--r--arch/arm/boot/dts/am437x-l4.dtsi2505
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi74
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi2
-rw-r--r--arch/arm/boot/dts/arm-realview-pbx.dtsi5
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts2
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts368
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts2
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts3
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts39
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts24
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts9
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts2
-rw-r--r--arch/arm/boot/dts/at91-nattis-2-natte-2.dts8
-rw-r--r--arch/arm/boot/dts/at91-sama5d27_som1_ek.dts12
-rw-r--r--arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts2
-rw-r--r--arch/arm/boot/dts/at91-sama5d2_xplained.dts4
-rw-r--r--arch/arm/boot/dts/at91-sama5d4ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi308
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi287
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi315
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi23
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi239
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi326
-rw-r--r--arch/arm/boot/dts/at91sam9x5_can.dtsi18
-rw-r--r--arch/arm/boot/dts/at91sam9x5_isi.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9x5_lcd.dtsi19
-rw-r--r--arch/arm/boot/dts/at91sam9x5_macb0.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9x5_macb1.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9x5_usart3.dtsi11
-rw-r--r--arch/arm/boot/dts/axp81x.dtsi5
-rw-r--r--arch/arm/boot/dts/bcm-nsp.dtsi8
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-zero-w.dts8
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-zero.dts8
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2836-rpi-2-b.dts2
-rw-r--r--arch/arm/boot/dts/bcm2836-rpi.dtsi6
-rw-r--r--arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts2
-rw-r--r--arch/arm/boot/dts/bcm2837-rpi-3-b.dts2
-rw-r--r--arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi2
-rw-r--r--arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts45
-rw-r--r--arch/arm/boot/dts/bcm47081.dtsi13
-rw-r--r--arch/arm/boot/dts/bcm4709.dtsi3
-rw-r--r--arch/arm/boot/dts/bcm47094.dtsi3
-rw-r--r--arch/arm/boot/dts/bcm47189-tenda-ac9.dts3
-rw-r--r--arch/arm/boot/dts/bcm5301x.dtsi44
-rw-r--r--arch/arm/boot/dts/bcm53573.dtsi3
-rw-r--r--arch/arm/boot/dts/bcm63138.dtsi31
-rw-r--r--arch/arm/boot/dts/bcm958522er.dts4
-rw-r--r--arch/arm/boot/dts/bcm958525er.dts4
-rw-r--r--arch/arm/boot/dts/bcm958525xmc.dts4
-rw-r--r--arch/arm/boot/dts/bcm958622hr.dts4
-rw-r--r--arch/arm/boot/dts/bcm958623hr.dts4
-rw-r--r--arch/arm/boot/dts/bcm958625hr.dts4
-rw-r--r--arch/arm/boot/dts/bcm958625k.dts5
-rw-r--r--arch/arm/boot/dts/bcm963138dvt.dts8
-rw-r--r--arch/arm/boot/dts/bcm988312hr.dts4
-rw-r--r--arch/arm/boot/dts/dra7-evm-common.dtsi4
-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi4600
-rw-r--r--arch/arm/boot/dts/dra7.dtsi1434
-rw-r--r--arch/arm/boot/dts/dra72-evm-common.dtsi4
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi4
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi6
-rw-r--r--arch/arm/boot/dts/dra76x.dtsi2
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi159
-rw-r--r--arch/arm/boot/dts/emev2.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos3250-artik5.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos3250-monk.dts6
-rw-r--r--arch/arm/boot/dts/exynos3250-rinato.dts6
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts4
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos4412-midas.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidu3.dts18
-rw-r--r--arch/arm/boot/dts/exynos4412-prime.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts34
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts1
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts1
-rw-r--r--arch/arm/boot/dts/exynos5422-odroid-core.dtsi11
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidhc1.dts106
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi109
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu4.dts9
-rw-r--r--arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi42
-rw-r--r--arch/arm/boot/dts/gemini-dlink-dir-685.dts63
-rw-r--r--arch/arm/boot/dts/gemini-dlink-dns-313.dts2
-rw-r--r--arch/arm/boot/dts/gemini-nas4220b.dts12
-rw-r--r--arch/arm/boot/dts/gemini-rut1xx.dts22
-rw-r--r--arch/arm/boot/dts/gemini-sl93512r.dts8
-rw-r--r--arch/arm/boot/dts/gemini-sq201.dts78
-rw-r--r--arch/arm/boot/dts/gemini-wbd111.dts10
-rw-r--r--arch/arm/boot/dts/gemini-wbd222.dts10
-rw-r--r--arch/arm/boot/dts/gemini.dtsi32
-rw-r--r--arch/arm/boot/dts/imx1-ads.dts1
-rw-r--r--arch/arm/boot/dts/imx1-apf9328.dts1
-rw-r--r--arch/arm/boot/dts/imx1.dtsi2
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts1
-rw-r--r--arch/arm/boot/dts/imx23-sansa.dts1
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts1
-rw-r--r--arch/arm/boot/dts/imx23-xfi3.dts1
-rw-r--r--arch/arm/boot/dts/imx23.dtsi2
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi1
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts1
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts1
-rw-r--r--arch/arm/boot/dts/imx25.dtsi6
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts1
-rw-r--r--arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx27-pdk.dts1
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi1
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi1
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts1
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts1
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts1
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-485.dts1
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-enocean.dts1
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-spi.dts1
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2.dts1
-rw-r--r--arch/arm/boot/dts/imx28-duckbill.dts1
-rw-r--r--arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts1
-rw-r--r--arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts1
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx28-m28.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts1
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts1
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts1
-rw-r--r--arch/arm/boot/dts/imx28-ts4600.dts1
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts1
-rw-r--r--arch/arm/boot/dts/imx28.dtsi2
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts1
-rw-r--r--arch/arm/boot/dts/imx31-lite.dts1
-rw-r--r--arch/arm/boot/dts/imx31.dtsi2
-rw-r--r--arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi1
-rw-r--r--arch/arm/boot/dts/imx35-pdk.dts1
-rw-r--r--arch/arm/boot/dts/imx35.dtsi2
-rw-r--r--arch/arm/boot/dts/imx50-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi19
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts1
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts1
-rw-r--r--arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi1
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi1
-rw-r--r--arch/arm/boot/dts/imx51-ts4800.dts1
-rw-r--r--arch/arm/boot/dts/imx51-zii-rdu1.dts18
-rw-r--r--arch/arm/boot/dts/imx51-zii-scu2-mezz.dts1
-rw-r--r--arch/arm/boot/dts/imx51-zii-scu3-esb.dts1
-rw-r--r--arch/arm/boot/dts/imx51.dtsi12
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts1
-rw-r--r--arch/arm/boot/dts/imx53-cx9020.dts1
-rw-r--r--arch/arm/boot/dts/imx53-m53.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts1
-rw-r--r--arch/arm/boot/dts/imx53-tqma53.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-tx53.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-usbarmory.dts1
-rw-r--r--arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi8
-rw-r--r--arch/arm/boot/dts/imx53.dtsi27
-rw-r--r--arch/arm/boot/dts/imx6dl-apf6dev.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos2_4.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos2_7.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_4.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_7.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-emcon-avari.dts14
-rw-r--r--arch/arm/boot/dts/imx6dl-mamoj.dts6
-rw-r--r--arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6dl-rex-basic.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-riotboard.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-ts4900.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-ts7970.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard-revb1.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard-revd1.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard.dts1
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q-apf6dev.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-b450v3.dts7
-rw-r--r--arch/arm/boot/dts/imx6q-b650v3.dts7
-rw-r--r--arch/arm/boot/dts/imx6q-b850v3.dts16
-rw-r--r--arch/arm/boot/dts/imx6q-ba16.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6q-bx50v3.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6q-cm-fx6.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-dhcom-som.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6q-display5.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-emcon-avari.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-evi.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-gk802.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-h100.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-kp-tpc.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-marsboard.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-mccmon6.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-novena.dts1
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6q-pistachio.dts1
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-rw-r--r--arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts18
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts18
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi5
-rw-r--r--arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts153
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts20
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi30
-rw-r--r--arch/arm/boot/dts/sun8i-q8-common.dtsi8
-rw-r--r--arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts47
-rw-r--r--arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts2
-rw-r--r--arch/arm/boot/dts/sun8i-r16-parrot.dts42
-rw-r--r--arch/arm/boot/dts/sun8i-r40.dtsi18
-rw-r--r--arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi17
-rw-r--r--arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts226
-rw-r--r--arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts8
-rw-r--r--arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts4
-rw-r--r--arch/arm/boot/dts/sun8i-v3s.dtsi12
-rw-r--r--arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts26
-rw-r--r--arch/arm/boot/dts/suniv-f1c100s.dtsi144
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi56
-rw-r--r--arch/arm/boot/dts/sunxi-itead-core-common.dtsi2
-rw-r--r--arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi10
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/uniphier-ld4.dtsi14
-rw-r--r--arch/arm/boot/dts/uniphier-pro4.dtsi16
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2.dtsi6
-rw-r--r--arch/arm/boot/dts/uniphier-sld8.dtsi14
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi49
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi63
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts14
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts108
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts14
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts43
-rw-r--r--arch/arm/boot/dts/vf500-colibri.dtsi1
-rw-r--r--arch/arm/boot/dts/vf500.dtsi1
-rw-r--r--arch/arm/boot/dts/vf610-bk4.dts502
-rw-r--r--arch/arm/boot/dts/vf610-colibri.dtsi1
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts1
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts1
-rw-r--r--arch/arm/boot/dts/vf610-zii-cfu1.dts1
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev.dtsi1
-rw-r--r--arch/arm/boot/dts/vf610-zii-scu4-aib.dts851
-rw-r--r--arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts1
-rw-r--r--arch/arm/boot/dts/vf610m4-colibri.dts1
-rw-r--r--arch/arm/boot/dts/vf610m4.dtsi1
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi4
-rw-r--r--arch/arm/mach-mmp/mmp2-dt.c2
-rw-r--r--arch/arm64/boot/dts/allwinner/Makefile2
-rw-r--r--arch/arm64/boot/dts/allwinner/axp803.dtsi33
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts43
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts27
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts67
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts34
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi4
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi123
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts149
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi61
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi37
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts11
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts140
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi210
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts82
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi311
-rw-r--r--arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi3
-rw-r--r--arch/arm64/boot/dts/amlogic/Makefile2
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg-s400.dts36
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi178
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx.dtsi7
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts4
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts5
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi68
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts248
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts21
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts12
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts5
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl.dtsi70
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts23
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts23
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi37
-rw-r--r--arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts14
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi36
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi24
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile5
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts25
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi3
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts93
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts73
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi339
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts3
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi37
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts6
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi36
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi169
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi8
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi44
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts112
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts119
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi766
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts18
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660.dtsi16
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts338
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670.dtsi499
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts13
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts25
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi9
-rw-r--r--arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi244
-rw-r--r--arch/arm64/boot/dts/marvell/Makefile1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts22
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi10
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts22
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts29
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts333
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi346
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi10
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts6
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi4
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi45
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi30
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts157
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi538
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi4
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi2
-rw-r--r--arch/arm64/boot/dts/qcom/Makefile2
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi6
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi76
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi144
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996-pins.dtsi120
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi169
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi12
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998-pins.dtsi78
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998.dtsi25
-rw-r--r--arch/arm64/boot/dts/qcom/pm8998.dtsi5
-rw-r--r--arch/arm64/boot/dts/qcom/pms405.dtsi55
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts11
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts11
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404-evb.dtsi188
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404.dtsi490
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845.dtsi448
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774a1.dtsi606
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi284
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi321
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965.dtsi89
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi211
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980.dtsi221
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts314
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990.dtsi733
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995-draak.dts28
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995.dtsi45
-rw-r--r--arch/arm64/boot/dts/renesas/salvator-common.dtsi13
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb.dtsi8
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328-rock64.dts1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328.dtsi5
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi15
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-ficus.dts78
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi8
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts8
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts33
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts33
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi594
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi7
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-rock960.dts79
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts7
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts46
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi77
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi36
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi11
-rw-r--r--arch/arm64/boot/dts/sprd/sc9836.dtsi78
-rw-r--r--arch/arm64/boot/dts/sprd/sc9860.dtsi215
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi126
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi42
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi20
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65.dtsi7
-rw-r--r--arch/arm64/boot/dts/ti/k3-am654-base-board.dts124
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi4
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts6
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts12
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts4
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts4
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi16
664 files changed, 36664 insertions, 11685 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d625b9..78551c4375d5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
bcm4708-linksys-ea6300-v1.dtb \
+ bcm4708-linksys-ea6500-v2.dtb \
bcm4708-luxul-xap-1510.dtb \
bcm4708-luxul-xwc-1000.dtb \
bcm4708-netgear-r6250.dtb \
@@ -396,6 +397,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
+ imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
@@ -460,6 +462,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-dms-ba16.dtb \
+ imx6q-emcon-avari.dtb \
imx6q-evi.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
@@ -557,6 +560,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
+ imx6ul-pico-pi.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
@@ -569,18 +573,23 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
+ imx7d-pico-hobbit.dtb \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
+ imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
+ vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
vf610m4-colibri.dtb \
vf610-cosmic.dtb \
@@ -589,6 +598,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
vf610-zii-dev-rev-c.dtb \
+ vf610-zii-scu4-aib.dtb \
vf610-zii-ssmb-spu3.dtb
dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \
@@ -778,12 +788,18 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
+dtb-$(CONFIG_ARCH_PXA) += \
+ pxa300-raumfeld-connector.dtb \
+ pxa300-raumfeld-controller.dtb \
+ pxa300-raumfeld-speaker-l.dtb \
+ pxa300-raumfeld-speaker-m.dtb \
+ pxa300-raumfeld-speaker-one.dtb \
+ pxa300-raumfeld-speaker-s.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
- qcom-apq8064-arrow-sd-600eval.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
qcom-apq8064-sony-xperia-yuga.dtb \
@@ -829,6 +845,8 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7744-iwg20d-q7.dtb \
+ r8a7744-iwg20d-q7-dbcm-ca.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
@@ -854,6 +872,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
+ rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
@@ -1043,6 +1062,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-bananapi-m2-plus-v1.2.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
+ sun8i-h3-mapleboard-mp130.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
@@ -1060,12 +1080,15 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
+ sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+ suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
@@ -1212,6 +1235,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
+ aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-opp-lanyang.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 9e5e75ea87f5..456eef57ef89 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -419,6 +419,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 7bcd72691f06..ccb147e70d17 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -515,7 +515,7 @@
&rtc {
system-power-controller;
- clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index c4d3e1f1a95e..2c724bb60417 100644
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -393,7 +393,7 @@ status = "okay";
&epwmss0 {
status = "okay";
- ecap0: ecap@48300100 {
+ ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 98ec9c3e49ba..b67f5fee1469 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -519,7 +519,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap@48300100 {
+ ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
@@ -797,6 +797,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 245868f58fe3..172c0224e7f6 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -540,7 +540,7 @@
&epwmss2 {
status = "okay";
- ecap2: ecap@48304100 {
+ ecap2: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
@@ -738,6 +738,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
index 85cd1d0a73ca..95d54cf3849e 100644
--- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
+++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
@@ -456,6 +456,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index 1d925ed2b102..d0fd68873689 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -138,7 +138,7 @@
&epwmss1 {
status = "okay";
- ehrpwm1: pwm@48302200 {
+ ehrpwm1: pwm@200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
@@ -205,7 +205,7 @@
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
- cpsw_emac0: slave@4a100200 {
+ cpsw_emac0: slave@200 {
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 95d5c9d136c5..922182439048 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -334,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@@ -407,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@@ -477,7 +477,7 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
@@ -539,86 +539,140 @@
};
&prcm {
- l4_per_cm: l4_per_cm@0 {
+ per_cm: per-cm@0 {
compatible = "ti,omap4-cm";
- reg = <0x0 0x200>;
+ reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x0 0x200>;
+ ranges = <0 0x0 0x400>;
- l4_per_clkctrl: clk@14 {
+ l4ls_clkctrl: l4ls-clkctrl@38 {
compatible = "ti,clkctrl";
- reg = <0x14 0x13c>;
+ reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l3s_clkctrl: l3s-clkctrl@1c {
+ compatible = "ti,clkctrl";
+ reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l3_clkctrl: l3-clkctrl@24 {
+ compatible = "ti,clkctrl";
+ reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
+ #clock-cells = <2>;
+ };
+
+ l4hs_clkctrl: l4hs-clkctrl@120 {
+ compatible = "ti,clkctrl";
+ reg = <0x120 0x4>;
+ #clock-cells = <2>;
+ };
+
+ pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+ compatible = "ti,clkctrl";
+ reg = <0xe8 0x4>;
+ #clock-cells = <2>;
+ };
+
+ cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x18>;
+ #clock-cells = <2>;
+ };
+
+ lcdc_clkctrl: lcdc-clkctrl@18 {
+ compatible = "ti,clkctrl";
+ reg = <0x18 0x4>;
+ #clock-cells = <2>;
+ };
+
+ clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+ compatible = "ti,clkctrl";
+ reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
- l4_wkup_cm: l4_wkup_cm@400 {
+ wkup_cm: wkup-cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- l4_wkup_clkctrl: clk@4 {
+ l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x10>, <0xb4 0x24>;
+ #clock-cells = <2>;
+ };
+
+ l3_aon_clkctrl: l3-aon-clkctrl@14 {
+ compatible = "ti,clkctrl";
+ reg = <0x14 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
compatible = "ti,clkctrl";
- reg = <0x4 0xd4>;
+ reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu_cm@600 {
+ mpu_cm: mpu-cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- mpu_clkctrl: clk@4 {
+ mpu_clkctrl: mpu-clkctrl@0 {
compatible = "ti,clkctrl";
- reg = <0x4 0x4>;
+ reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4_rtc_cm@800 {
+ l4_rtc_cm: l4-rtc-cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
- l4_rtc_clkctrl: clk@0 {
+ l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx_l3_cm@900 {
+ gfx_l3_cm: gfx-l3-cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- gfx_l3_clkctrl: clk@4 {
+ gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
compatible = "ti,clkctrl";
- reg = <0x4 0x4>;
+ reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_cefuse_cm: l4_cefuse_cm@a00 {
+ l4_cefuse_cm: l4-cefuse-cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- l4_cefuse_clkctrl: clk@20 {
+ l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
+ reg = <0x0 0x24>;
#clock-cells = <2>;
};
};
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
new file mode 100644
index 000000000000..7b818d9d2eab
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -0,0 +1,2132 @@
+&l4_wkup { /* 0x44c00000 */
+ compatible = "ti,am33xx-l4-wkup", "simple-bus";
+ reg = <0x44c00000 0x800>,
+ <0x44c00800 0x800>,
+ <0x44c01000 0x400>,
+ <0x44c01400 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
+ <0x00100000 0x44d00000 0x100000>, /* segment 1 */
+ <0x00200000 0x44e00000 0x100000>; /* segment 2 */
+
+ segment@0 { /* 0x44c00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>; /* ap 3 */
+ };
+
+ segment@100000 { /* 0x44d00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
+ <0x00004000 0x00104000 0x001000>, /* ap 5 */
+ <0x00080000 0x00180000 0x002000>, /* ap 6 */
+ <0x00082000 0x00182000 0x001000>; /* ap 7 */
+
+ target-module@0 { /* 0x44d00000, ap 4 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x0 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x4000>;
+ status = "disabled";
+ };
+
+ target-module@80000 { /* 0x44d80000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x2000>;
+ };
+ };
+
+ segment@200000 { /* 0x44e00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
+ <0x00002000 0x00202000 0x001000>, /* ap 9 */
+ <0x00003000 0x00203000 0x001000>, /* ap 10 */
+ <0x00004000 0x00204000 0x001000>, /* ap 11 */
+ <0x00005000 0x00205000 0x001000>, /* ap 12 */
+ <0x00006000 0x00206000 0x001000>, /* ap 13 */
+ <0x00007000 0x00207000 0x001000>, /* ap 14 */
+ <0x00008000 0x00208000 0x001000>, /* ap 15 */
+ <0x00009000 0x00209000 0x001000>, /* ap 16 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
+ <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
+ <0x00010000 0x00210000 0x010000>, /* ap 22 */
+ <0x00020000 0x00220000 0x010000>, /* ap 23 */
+ <0x00030000 0x00230000 0x001000>, /* ap 24 */
+ <0x00031000 0x00231000 0x001000>, /* ap 25 */
+ <0x00032000 0x00232000 0x001000>, /* ap 26 */
+ <0x00033000 0x00233000 0x001000>, /* ap 27 */
+ <0x00034000 0x00234000 0x001000>, /* ap 28 */
+ <0x00035000 0x00235000 0x001000>, /* ap 29 */
+ <0x00036000 0x00236000 0x001000>, /* ap 30 */
+ <0x00037000 0x00237000 0x001000>, /* ap 31 */
+ <0x00038000 0x00238000 0x001000>, /* ap 32 */
+ <0x00039000 0x00239000 0x001000>, /* ap 33 */
+ <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
+ <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
+ <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
+ <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
+ <0x00040000 0x00240000 0x040000>, /* ap 38 */
+ <0x00080000 0x00280000 0x001000>; /* ap 39 */
+
+ target-module@0 { /* 0x44e00000, ap 8 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x2000>;
+
+ prcm: prcm@0 {
+ compatible = "ti,am3-prcm", "simple-bus";
+ reg = <0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3000 0x1000>;
+ };
+
+ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5000 0x1000>;
+ };
+
+ target-module@7000 { /* 0x44e07000, ap 14 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio1";
+ reg = <0x7000 0x4>,
+ <0x7010 0x4>,
+ <0x7114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x1000>;
+
+ gpio0: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <96>;
+ };
+ };
+
+ target-module@9000 { /* 0x44e09000, ap 16 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart1";
+ reg = <0x9050 0x4>,
+ <0x9054 0x4>,
+ <0x9058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9000 0x1000>;
+
+ uart0: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <72>;
+ status = "disabled";
+ dmas = <&edma 26 0>, <&edma 27 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c1";
+ reg = <0xb000 0x8>,
+ <0xb010 0x8>,
+ <0xb090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb000 0x1000>;
+
+ i2c0: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1000>;
+ interrupts = <70>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "adc_tsc";
+ reg = <0xd000 0x4>,
+ <0xd010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x0000d000 0x00001000>,
+ <0x00001000 0x0000e000 0x00001000>;
+
+ tscadc: tscadc@0 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x0 0x1000>;
+ interrupts = <16>;
+ status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
+
+ tsc {
+ compatible = "ti,am3359-tsc";
+ };
+ am335x_adc: adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+ };
+
+ target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x10000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x00010000>,
+ <0x00010000 0x00020000 0x00010000>;
+
+ scm: scm@0 {
+ compatible = "ti,am3-scm", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #pinctrl-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ phy_sel: cpsw-phy-sel@650 {
+ compatible = "ti,am3352-cpsw-phy-sel";
+ reg= <0x650 0x4>;
+ reg-names = "gmii-sel";
+ };
+
+ am33xx_pinmux: pinmux@800 {
+ compatible = "pinctrl-single";
+ reg = <0x800 0x238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x800>;
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ wkup_m3_ipc: wkup_m3_ipc@1324 {
+ compatible = "ti,am3352-wkup-m3-ipc";
+ reg = <0x1324 0x24>;
+ interrupts = <78>;
+ ti,rproc = <&wkup_m3>;
+ mboxes = <&mailbox &mbox_wkupm3>;
+ };
+
+ edma_xbar: dma-router@f90 {
+ compatible = "ti,am335x-edma-crossbar";
+ reg = <0xf90 0x40>;
+ #dma-cells = <3>;
+ dma-requests = <32>;
+ dma-masters = <&edma>;
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@31000 { /* 0x44e31000, ap 25 40.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x31000 0x4>,
+ <0x31010 0x4>,
+ <0x31014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x31000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x0 0x400>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@33000 { /* 0x44e33000, ap 27 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x33000 0x1000>;
+ };
+
+ target-module@35000 { /* 0x44e35000, ap 29 50.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "wd_timer2";
+ reg = <0x35000 0x4>,
+ <0x35010 0x4>,
+ <0x35014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x35000 0x1000>;
+
+ wdt2: wdt@0 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x0 0x1000>;
+ interrupts = <91>;
+ };
+ };
+
+ target-module@37000 { /* 0x44e37000, ap 31 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x37000 0x1000>;
+ };
+
+ target-module@39000 { /* 0x44e39000, ap 33 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x39000 0x1000>;
+ };
+
+ target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "rtc";
+ reg = <0x3e074 0x4>,
+ <0x3e078 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
+ clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ rtc: rtc@0 {
+ compatible = "ti,am3352-rtc", "ti,da830-rtc";
+ reg = <0x0 0x1000>;
+ interrupts = <75
+ 76>;
+ };
+ };
+
+ target-module@40000 { /* 0x44e40000, ap 38 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x40000>;
+ };
+ };
+};
+
+&l4_fw { /* 0x47c00000 */
+ compatible = "ti,am33xx-l4-fw", "simple-bus";
+ reg = <0x47c00000 0x800>,
+ <0x47c00800 0x800>,
+ <0x47c01000 0x400>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
+
+ segment@0 { /* 0x47c00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
+ <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
+ <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
+ <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
+ <0x00010000 0x00010000 0x001000>, /* ap 7 */
+ <0x00011000 0x00011000 0x001000>, /* ap 8 */
+ <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
+ <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
+ <0x00024000 0x00024000 0x001000>, /* ap 11 */
+ <0x00025000 0x00025000 0x001000>, /* ap 12 */
+ <0x00026000 0x00026000 0x001000>, /* ap 13 */
+ <0x00027000 0x00027000 0x001000>, /* ap 14 */
+ <0x00030000 0x00030000 0x001000>, /* ap 15 */
+ <0x00031000 0x00031000 0x001000>, /* ap 16 */
+ <0x00038000 0x00038000 0x001000>, /* ap 17 */
+ <0x00039000 0x00039000 0x001000>, /* ap 18 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
+ <0x00040000 0x00040000 0x001000>, /* ap 24 */
+ <0x00046000 0x00046000 0x001000>, /* ap 25 */
+ <0x00047000 0x00047000 0x001000>, /* ap 26 */
+ <0x00044000 0x00044000 0x001000>, /* ap 27 */
+ <0x00045000 0x00045000 0x001000>, /* ap 28 */
+ <0x00028000 0x00028000 0x001000>, /* ap 29 */
+ <0x00029000 0x00029000 0x001000>, /* ap 30 */
+ <0x00032000 0x00032000 0x001000>, /* ap 31 */
+ <0x00033000 0x00033000 0x001000>, /* ap 32 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
+ <0x00041000 0x00041000 0x001000>, /* ap 34 */
+ <0x00042000 0x00042000 0x001000>, /* ap 35 */
+ <0x00043000 0x00043000 0x001000>, /* ap 36 */
+ <0x00014000 0x00014000 0x001000>, /* ap 37 */
+ <0x00015000 0x00015000 0x001000>; /* ap 38 */
+
+ target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x47c10000, ap 7 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ target-module@24000 { /* 0x47c24000, ap 11 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x47c26000, ap 13 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@28000 { /* 0x47c28000, ap 29 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module@30000 { /* 0x47c30000, ap 15 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+ };
+
+ target-module@32000 { /* 0x47c32000, ap 31 06.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+ };
+
+ target-module@38000 { /* 0x47c38000, ap 17 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>;
+ };
+
+ target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>;
+ };
+
+ target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>;
+ };
+
+ target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+ };
+
+ target-module@40000 { /* 0x47c40000, ap 24 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+ };
+
+ target-module@42000 { /* 0x47c42000, ap 35 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x42000 0x1000>;
+ };
+
+ target-module@44000 { /* 0x47c44000, ap 27 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x44000 0x1000>;
+ };
+
+ target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x46000 0x1000>;
+ };
+ };
+};
+
+&l4_fast { /* 0x4a000000 */
+ compatible = "ti,am33xx-l4-fast", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x400>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00100000 0x00100000 0x008000>, /* ap 3 */
+ <0x00108000 0x00108000 0x001000>, /* ap 4 */
+ <0x00180000 0x00180000 0x020000>, /* ap 5 */
+ <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
+ <0x00200000 0x00200000 0x080000>, /* ap 7 */
+ <0x00280000 0x00280000 0x001000>, /* ap 8 */
+ <0x00300000 0x00300000 0x080000>, /* ap 9 */
+ <0x00380000 0x00380000 0x001000>; /* ap 10 */
+
+ target-module@100000 { /* 0x4a100000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "cpgmac0";
+ reg = <0x101200 0x4>,
+ <0x101208 0x4>,
+ <0x101204 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <0>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x100000 0x8000>;
+
+ mac: ethernet@0 {
+ compatible = "ti,am335x-cpsw","ti,cpsw";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+ clock-names = "fck", "cpts";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0x0 0x800
+ 0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * c0_rx_thresh_pend
+ * c0_rx_pend
+ * c0_tx_pend
+ * c0_misc_pend
+ */
+ interrupts = <40 41 42 43>;
+ ranges = <0 0 0x8000>;
+ syscon = <&scm_conf>;
+ cpsw-phy-sel = <&phy_sel>;
+ status = "disabled";
+
+ davinci_mdio: mdio@1000 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x1000 0x100>;
+ status = "disabled";
+ };
+
+ cpsw_emac0: slave@200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+ };
+
+ target-module@180000 { /* 0x4a180000, ap 5 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x180000 0x20000>;
+ };
+
+ target-module@200000 { /* 0x4a200000, ap 7 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x200000 0x80000>;
+ };
+
+ target-module@300000 { /* 0x4a300000, ap 9 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x300000 0x80000>;
+ };
+ };
+};
+
+&l4_mpuss { /* 0x4b140000 */
+ compatible = "ti,am33xx-l4-mpuss", "simple-bus";
+ reg = <0x4b144400 0x100>,
+ <0x4b144800 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
+
+ segment@0 { /* 0x4b140000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00002000 0x00002000 0x001000>, /* ap 2 */
+ <0x00004000 0x00004000 0x000400>, /* ap 3 */
+ <0x00005000 0x00005000 0x000400>, /* ap 4 */
+ <0x00000000 0x00000000 0x001000>, /* ap 5 */
+ <0x00003000 0x00003000 0x001000>, /* ap 6 */
+ <0x00000800 0x00000800 0x000800>; /* ap 7 */
+
+ target-module@0 { /* 0x4b140000, ap 5 02.2 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00001000>,
+ <0x00001000 0x00001000 0x00001000>,
+ <0x00002000 0x00002000 0x00001000>;
+ };
+
+ target-module@3000 { /* 0x4b143000, ap 6 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3000 0x1000>;
+ };
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,am33xx-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
+ <0x00100000 0x48100000 0x100000>, /* segment 1 */
+ <0x00200000 0x48200000 0x100000>, /* segment 2 */
+ <0x00300000 0x48300000 0x100000>, /* segment 3 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>, /* ap 3 */
+ <0x00001800 0x00001800 0x000400>, /* ap 4 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
+ <0x00008000 0x00008000 0x001000>, /* ap 6 */
+ <0x00009000 0x00009000 0x001000>, /* ap 7 */
+ <0x00016000 0x00016000 0x001000>, /* ap 8 */
+ <0x00017000 0x00017000 0x001000>, /* ap 9 */
+ <0x00022000 0x00022000 0x001000>, /* ap 10 */
+ <0x00023000 0x00023000 0x001000>, /* ap 11 */
+ <0x00024000 0x00024000 0x001000>, /* ap 12 */
+ <0x00025000 0x00025000 0x001000>, /* ap 13 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
+ <0x00038000 0x00038000 0x002000>, /* ap 16 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
+ <0x00014000 0x00014000 0x001000>, /* ap 18 */
+ <0x00015000 0x00015000 0x001000>, /* ap 19 */
+ <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
+ <0x00040000 0x00040000 0x001000>, /* ap 22 */
+ <0x00041000 0x00041000 0x001000>, /* ap 23 */
+ <0x00042000 0x00042000 0x001000>, /* ap 24 */
+ <0x00043000 0x00043000 0x001000>, /* ap 25 */
+ <0x00044000 0x00044000 0x001000>, /* ap 26 */
+ <0x00045000 0x00045000 0x001000>, /* ap 27 */
+ <0x00046000 0x00046000 0x001000>, /* ap 28 */
+ <0x00047000 0x00047000 0x001000>, /* ap 29 */
+ <0x00048000 0x00048000 0x001000>, /* ap 30 */
+ <0x00049000 0x00049000 0x001000>, /* ap 31 */
+ <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
+ <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
+ <0x00050000 0x00050000 0x002000>, /* ap 34 */
+ <0x00052000 0x00052000 0x001000>, /* ap 35 */
+ <0x00060000 0x00060000 0x001000>, /* ap 36 */
+ <0x00061000 0x00061000 0x001000>, /* ap 37 */
+ <0x00080000 0x00080000 0x010000>, /* ap 38 */
+ <0x00090000 0x00090000 0x001000>, /* ap 39 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
+ <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
+ <0x00030000 0x00030000 0x001000>, /* ap 77 */
+ <0x00031000 0x00031000 0x001000>, /* ap 78 */
+ <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
+ <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
+ <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
+ <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
+ <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
+ <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
+ <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
+ <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ target-module@8000 { /* 0x48008000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x48014000, ap 18 58.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@16000 { /* 0x48016000, ap 8 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module@22000 { /* 0x48022000, ap 10 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart2";
+ reg = <0x22050 0x4>,
+ <0x22054 0x4>,
+ <0x22058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <73>;
+ status = "disabled";
+ dmas = <&edma 28 0>, <&edma 29 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@24000 { /* 0x48024000, ap 12 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart3";
+ reg = <0x24050 0x4>,
+ <0x24054 0x4>,
+ <0x24058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <74>;
+ status = "disabled";
+ dmas = <&edma 30 0>, <&edma 31 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c2";
+ reg = <0x2a000 0x8>,
+ <0x2a010 0x8>,
+ <0x2a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1000>;
+ interrupts = <71>;
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x48030000, ap 77 08.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi0";
+ reg = <0x30000 0x4>,
+ <0x30110 0x4>,
+ <0x30114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+
+ spi0: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x400>;
+ interrupts = <65>;
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 16 0
+ &edma 17 0
+ &edma 18 0
+ &edma 19 0>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+ };
+
+ target-module@38000 { /* 0x48038000, ap 16 02.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "mcasp0";
+ reg = <0x38000 0x4>,
+ <0x38004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x2000>,
+ <0x46000000 0x46000000 0x400000>;
+
+ mcasp0: mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46000000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <80>, <81>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 8 2>,
+ <&edma 9 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "mcasp1";
+ reg = <0x3c000 0x4>,
+ <0x3c004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x2000>,
+ <0x46400000 0x46400000 0x400000>;
+
+ mcasp1: mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46400000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <82>, <83>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 10 2>,
+ <&edma 11 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@40000 { /* 0x48040000, ap 22 1e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer2";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>,
+ <0x40014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <68>;
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@42000 { /* 0x48042000, ap 24 1c.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer3";
+ reg = <0x42000 0x4>,
+ <0x42010 0x4>,
+ <0x42014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x42000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <69>;
+ };
+ };
+
+ target-module@44000 { /* 0x48044000, ap 26 26.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer4";
+ reg = <0x44000 0x4>,
+ <0x44010 0x4>,
+ <0x44014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x44000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <92>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@46000 { /* 0x48046000, ap 28 28.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer5";
+ reg = <0x46000 0x4>,
+ <0x46010 0x4>,
+ <0x46014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x46000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <93>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@48000 { /* 0x48048000, ap 30 22.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer6";
+ reg = <0x48000 0x4>,
+ <0x48010 0x4>,
+ <0x48014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <94>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer7";
+ reg = <0x4a000 0x4>,
+ <0x4a010 0x4>,
+ <0x4a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4a000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <95>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio2";
+ reg = <0x4c000 0x4>,
+ <0x4c010 0x4>,
+ <0x4c114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <98>;
+ };
+ };
+
+ target-module@50000 { /* 0x48050000, ap 34 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x50000 0x2000>;
+ };
+
+ target-module@60000 { /* 0x48060000, ap 36 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "mmc1";
+ reg = <0x602fc 0x4>,
+ <0x60110 0x4>,
+ <0x60114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ ti,needs-special-hs-handling;
+ dmas = <&edma_xbar 24 0 0
+ &edma_xbar 25 0 0>;
+ dma-names = "tx", "rx";
+ interrupts = <64>;
+ reg = <0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ target-module@80000 { /* 0x48080000, ap 38 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "elm";
+ reg = <0x80000 0x4>,
+ <0x80010 0x4>,
+ <0x80014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>;
+
+ elm: elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0x2000>;
+ interrupts = <4>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>;
+ };
+
+ target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mailbox";
+ reg = <0xc8000 0x4>,
+ <0xc8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc8000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <77>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-send-noirq;
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
+ };
+ };
+
+ target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spinlock";
+ reg = <0xca000 0x4>,
+ <0xca010 0x4>,
+ <0xca014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xca000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+
+ target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xcc000 0x1000>;
+ };
+ };
+
+ segment@100000 { /* 0x48100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
+ <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
+ <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
+ <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
+ <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
+ <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
+ <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
+ <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
+ <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
+ <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
+ <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
+ <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
+ <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
+ <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
+ <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
+ <0x000af000 0x001af000 0x001000>, /* ap 57 */
+ <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
+ <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
+ <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
+ <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
+ <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
+ <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
+ <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
+ <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
+ <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
+ <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
+ <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
+ <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
+ <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
+ <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
+
+ target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8c000 0x1000>;
+ };
+
+ target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8e000 0x1000>;
+ };
+
+ target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c3";
+ reg = <0x9c000 0x8>,
+ <0x9c010 0x8>,
+ <0x9c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1000>;
+ interrupts = <30>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi1";
+ reg = <0xa0000 0x4>,
+ <0xa0110 0x4>,
+ <0xa0114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x1000>;
+
+ spi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x400>;
+ interrupts = <125>;
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 42 0
+ &edma 43 0
+ &edma 44 0
+ &edma 45 0>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+ };
+
+ target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa4000 0x1000>;
+ };
+
+ target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart4";
+ reg = <0xa6050 0x4>,
+ <0xa6054 0x4>,
+ <0xa6058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa6000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <44>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart5";
+ reg = <0xa8050 0x4>,
+ <0xa8054 0x4>,
+ <0xa8058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <45>;
+ status = "disabled";
+ };
+ };
+
+ target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart6";
+ reg = <0xaa050 0x4>,
+ <0xaa054 0x4>,
+ <0xaa058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xaa000 0x1000>;
+
+ uart5: serial@0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x2000>;
+ interrupts = <46>;
+ status = "disabled";
+ };
+ };
+
+ target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio3";
+ reg = <0xac000 0x4>,
+ <0xac010 0x4>,
+ <0xac114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xac000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <32>;
+ };
+ };
+
+ target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio4";
+ reg = <0xae000 0x4>,
+ <0xae010 0x4>,
+ <0xae114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xae000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x1000>;
+ interrupts = <62>;
+ };
+ };
+
+ target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb0000 0x10000>;
+ };
+
+ target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "d_can0";
+ reg = <0xcc000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_D_CAN0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xcc000 0x2000>;
+
+ dcan0: can@0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ clocks = <&dcan0_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 0>;
+ interrupts = <52>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "d_can1";
+ reg = <0xd0000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_D_CAN1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd0000 0x2000>;
+
+ dcan1: can@0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ clocks = <&dcan1_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 1>;
+ interrupts = <55>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "mmc2";
+ reg = <0xd82fc 0x4>,
+ <0xd8110 0x4>,
+ <0xd8114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd8000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ ti,needs-special-reset;
+ dmas = <&edma 2 0
+ &edma 3 0>;
+ dma-names = "tx", "rx";
+ interrupts = <28>;
+ reg = <0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@300000 { /* 0x48300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
+ <0x00001000 0x00301000 0x001000>, /* ap 67 */
+ <0x00002000 0x00302000 0x001000>, /* ap 68 */
+ <0x00003000 0x00303000 0x001000>, /* ap 69 */
+ <0x00004000 0x00304000 0x001000>, /* ap 70 */
+ <0x00005000 0x00305000 0x001000>, /* ap 71 */
+ <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
+ <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
+ <0x00018000 0x00318000 0x004000>, /* ap 74 */
+ <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
+ <0x00010000 0x00310000 0x002000>, /* ap 76 */
+ <0x00012000 0x00312000 0x001000>, /* ap 93 */
+ <0x00015000 0x00315000 0x001000>, /* ap 94 */
+ <0x00016000 0x00316000 0x001000>, /* ap 95 */
+ <0x00017000 0x00317000 0x001000>, /* ap 96 */
+ <0x00013000 0x00313000 0x001000>, /* ap 97 */
+ <0x00014000 0x00314000 0x001000>, /* ap 98 */
+ <0x00020000 0x00320000 0x001000>, /* ap 99 */
+ <0x00021000 0x00321000 0x001000>, /* ap 100 */
+ <0x00022000 0x00322000 0x001000>, /* ap 101 */
+ <0x00023000 0x00323000 0x001000>, /* ap 102 */
+ <0x00024000 0x00324000 0x001000>, /* ap 103 */
+ <0x00025000 0x00325000 0x001000>; /* ap 104 */
+
+ target-module@0 { /* 0x48300000, ap 66 48.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss0";
+ reg = <0x0 0x4>,
+ <0x4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ epwmss0: epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap0: ecap@100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <31>;
+ interrupt-names = "ecap0";
+ status = "disabled";
+ };
+
+ ehrpwm0: pwm@200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@2000 { /* 0x48302000, ap 68 52.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss1";
+ reg = <0x2000 0x4>,
+ <0x2004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ epwmss1: epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap1: ecap@100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <47>;
+ interrupt-names = "ecap1";
+ status = "disabled";
+ };
+
+ ehrpwm1: pwm@200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x48304000, ap 70 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss2";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ epwmss2: epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap2: ecap@100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <61>;
+ interrupt-names = "ecap2";
+ status = "disabled";
+ };
+
+ ehrpwm2: pwm@200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "lcdc";
+ reg = <0xe000 0x4>,
+ <0xe054 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle ;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, lcdc_clkdm */
+ clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+
+ lcdc: lcdc@0 {
+ compatible = "ti,am33xx-tilcdc";
+ reg = <0x0 0x1000>;
+ interrupts = <36>;
+ status = "disabled";
+ };
+ };
+
+ target-module@10000 { /* 0x48310000, ap 76 4e.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "rng";
+ reg = <0x11fe0 0x4>,
+ <0x11fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <111>;
+ };
+ };
+
+ target-module@13000 { /* 0x48313000, ap 97 62.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x13000 0x1000>;
+ };
+
+ target-module@15000 { /* 0x48315000, ap 94 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00015000 0x00001000>,
+ <0x00001000 0x00016000 0x00001000>;
+ };
+
+ target-module@18000 { /* 0x48318000, ap 74 4c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x4000>;
+ };
+
+ target-module@20000 { /* 0x48320000, ap 99 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@22000 { /* 0x48322000, ap 101 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+ };
+
+ target-module@24000 { /* 0x48324000, ap 103 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+ };
+};
+
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index d3dd6a16e70a..e5c2f71a7c77 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
@@ -166,87 +167,23 @@
ranges;
ti,hwmods = "l3_main";
- l4_wkup: l4_wkup@44c00000 {
- compatible = "ti,am3-l4-wkup", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x44c00000 0x280000>;
-
+ l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
- <0x180000 0x2000>;
+ <0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
-
- prcm: prcm@200000 {
- compatible = "ti,am3-prcm", "simple-bus";
- reg = <0x200000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x200000 0x4000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@210000 {
- compatible = "ti,am3-scm", "simple-bus";
- reg = <0x210000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x210000 0x2000>;
-
- am33xx_pinmux: pinmux@800 {
- compatible = "pinctrl-single";
- reg = <0x800 0x238>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7f>;
- };
-
- scm_conf: scm_conf@0 {
- compatible = "syscon", "simple-bus";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x800>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- wkup_m3_ipc: wkup_m3_ipc@1324 {
- compatible = "ti,am3352-wkup-m3-ipc";
- reg = <0x1324 0x24>;
- interrupts = <78>;
- ti,rproc = <&wkup_m3>;
- mboxes = <&mailbox &mbox_wkupm3>;
- };
-
- edma_xbar: dma-router@f90 {
- compatible = "ti,am335x-edma-crossbar";
- reg = <0xf90 0x40>;
- #dma-cells = <3>;
- dma-requests = <32>;
- dma-masters = <&edma>;
- };
-
- scm_clockdomains: clockdomains {
- };
- };
+ };
+ l4_per: interconnect@48000000 {
+ };
+ l4_fw: interconnect@47c00000 {
+ };
+ l4_fast: interconnect@4a000000 {
+ };
+ l4_mpuss: interconnect@4b140000 {
};
intc: interrupt-controller@48200000 {
@@ -297,166 +234,6 @@
interrupt-names = "edma3_tcerrint";
};
- gpio0: gpio@44e07000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio1";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x44e07000 0x1000>;
- interrupts = <96>;
- };
-
- gpio1: gpio@4804c000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio2";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4804c000 0x1000>;
- interrupts = <98>;
- };
-
- gpio2: gpio@481ac000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio3";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x481ac000 0x1000>;
- interrupts = <32>;
- };
-
- gpio3: gpio@481ae000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio4";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x481ae000 0x1000>;
- interrupts = <62>;
- };
-
- uart0: serial@44e09000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart1";
- clock-frequency = <48000000>;
- reg = <0x44e09000 0x2000>;
- interrupts = <72>;
- status = "disabled";
- dmas = <&edma 26 0>, <&edma 27 0>;
- dma-names = "tx", "rx";
- };
-
- uart1: serial@48022000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart2";
- clock-frequency = <48000000>;
- reg = <0x48022000 0x2000>;
- interrupts = <73>;
- status = "disabled";
- dmas = <&edma 28 0>, <&edma 29 0>;
- dma-names = "tx", "rx";
- };
-
- uart2: serial@48024000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart3";
- clock-frequency = <48000000>;
- reg = <0x48024000 0x2000>;
- interrupts = <74>;
- status = "disabled";
- dmas = <&edma 30 0>, <&edma 31 0>;
- dma-names = "tx", "rx";
- };
-
- uart3: serial@481a6000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- reg = <0x481a6000 0x2000>;
- interrupts = <44>;
- status = "disabled";
- };
-
- uart4: serial@481a8000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart5";
- clock-frequency = <48000000>;
- reg = <0x481a8000 0x2000>;
- interrupts = <45>;
- status = "disabled";
- };
-
- uart5: serial@481aa000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart6";
- clock-frequency = <48000000>;
- reg = <0x481aa000 0x2000>;
- interrupts = <46>;
- status = "disabled";
- };
-
- i2c0: i2c@44e0b000 {
- compatible = "ti,omap4-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c1";
- reg = <0x44e0b000 0x1000>;
- interrupts = <70>;
- status = "disabled";
- };
-
- i2c1: i2c@4802a000 {
- compatible = "ti,omap4-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c2";
- reg = <0x4802a000 0x1000>;
- interrupts = <71>;
- status = "disabled";
- };
-
- i2c2: i2c@4819c000 {
- compatible = "ti,omap4-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c3";
- reg = <0x4819c000 0x1000>;
- interrupts = <30>;
- status = "disabled";
- };
-
- mmc1: mmc@48060000 {
- compatible = "ti,omap4-hsmmc";
- ti,hwmods = "mmc1";
- ti,dual-volt;
- ti,needs-special-reset;
- ti,needs-special-hs-handling;
- dmas = <&edma_xbar 24 0 0
- &edma_xbar 25 0 0>;
- dma-names = "tx", "rx";
- interrupts = <64>;
- reg = <0x48060000 0x1000>;
- status = "disabled";
- };
-
- mmc2: mmc@481d8000 {
- compatible = "ti,omap4-hsmmc";
- ti,hwmods = "mmc2";
- ti,needs-special-reset;
- dmas = <&edma 2 0
- &edma 3 0>;
- dma-names = "tx", "rx";
- interrupts = <28>;
- reg = <0x481d8000 0x1000>;
- status = "disabled";
- };
-
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc3";
@@ -466,157 +243,6 @@
status = "disabled";
};
- hwspinlock: spinlock@480ca000 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x480ca000 0x1000>;
- ti,hwmods = "spinlock";
- #hwlock-cells = <1>;
- };
-
- wdt2: wdt@44e35000 {
- compatible = "ti,omap3-wdt";
- ti,hwmods = "wd_timer2";
- reg = <0x44e35000 0x1000>;
- interrupts = <91>;
- };
-
- dcan0: can@481cc000 {
- compatible = "ti,am3352-d_can";
- ti,hwmods = "d_can0";
- reg = <0x481cc000 0x2000>;
- clocks = <&dcan0_fck>;
- clock-names = "fck";
- syscon-raminit = <&scm_conf 0x644 0>;
- interrupts = <52>;
- status = "disabled";
- };
-
- dcan1: can@481d0000 {
- compatible = "ti,am3352-d_can";
- ti,hwmods = "d_can1";
- reg = <0x481d0000 0x2000>;
- clocks = <&dcan1_fck>;
- clock-names = "fck";
- syscon-raminit = <&scm_conf 0x644 1>;
- interrupts = <55>;
- status = "disabled";
- };
-
- mailbox: mailbox@480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480C8000 0x200>;
- interrupts = <77>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
- ti,mbox-send-noirq;
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <0 0 3>;
- };
- };
-
- timer1: timer@44e31000 {
- compatible = "ti,am335x-timer-1ms";
- reg = <0x44e31000 0x400>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- clocks = <&timer1_fck>;
- clock-names = "fck";
- };
-
- timer2: timer@48040000 {
- compatible = "ti,am335x-timer";
- reg = <0x48040000 0x400>;
- interrupts = <68>;
- ti,hwmods = "timer2";
- clocks = <&timer2_fck>;
- clock-names = "fck";
- };
-
- timer3: timer@48042000 {
- compatible = "ti,am335x-timer";
- reg = <0x48042000 0x400>;
- interrupts = <69>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@48044000 {
- compatible = "ti,am335x-timer";
- reg = <0x48044000 0x400>;
- interrupts = <92>;
- ti,hwmods = "timer4";
- ti,timer-pwm;
- };
-
- timer5: timer@48046000 {
- compatible = "ti,am335x-timer";
- reg = <0x48046000 0x400>;
- interrupts = <93>;
- ti,hwmods = "timer5";
- ti,timer-pwm;
- };
-
- timer6: timer@48048000 {
- compatible = "ti,am335x-timer";
- reg = <0x48048000 0x400>;
- interrupts = <94>;
- ti,hwmods = "timer6";
- ti,timer-pwm;
- };
-
- timer7: timer@4804a000 {
- compatible = "ti,am335x-timer";
- reg = <0x4804a000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer7";
- ti,timer-pwm;
- };
-
- rtc: rtc@44e3e000 {
- compatible = "ti,am3352-rtc", "ti,da830-rtc";
- reg = <0x44e3e000 0x1000>;
- interrupts = <75
- 76>;
- ti,hwmods = "rtc";
- clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
- clock-names = "int-clk";
- };
-
- spi0: spi@48030000 {
- compatible = "ti,omap4-mcspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x48030000 0x400>;
- interrupts = <65>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi0";
- dmas = <&edma 16 0
- &edma 17 0
- &edma 18 0
- &edma 19 0>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
- spi1: spi@481a0000 {
- compatible = "ti,omap4-mcspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x481a0000 0x400>;
- interrupts = <125>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi1";
- dmas = <&edma 42 0
- &edma 43 0
- &edma 44 0
- &edma 45 0>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
usb: usb@47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
@@ -747,163 +373,6 @@
};
};
- epwmss0: epwmss@48300000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48300000 0x10>;
- ti,hwmods = "epwmss0";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48300100 0x48300100 0x80 /* ECAP */
- 0x48300180 0x48300180 0x80 /* EQEP */
- 0x48300200 0x48300200 0x80>; /* EHRPWM */
-
- ecap0: ecap@48300100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48300100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <31>;
- interrupt-names = "ecap0";
- status = "disabled";
- };
-
- ehrpwm0: pwm@48300200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48300200 0x80>;
- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss1: epwmss@48302000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48302000 0x10>;
- ti,hwmods = "epwmss1";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48302100 0x48302100 0x80 /* ECAP */
- 0x48302180 0x48302180 0x80 /* EQEP */
- 0x48302200 0x48302200 0x80>; /* EHRPWM */
-
- ecap1: ecap@48302100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48302100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <47>;
- interrupt-names = "ecap1";
- status = "disabled";
- };
-
- ehrpwm1: pwm@48302200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48302200 0x80>;
- clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss2: epwmss@48304000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48304000 0x10>;
- ti,hwmods = "epwmss2";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48304100 0x48304100 0x80 /* ECAP */
- 0x48304180 0x48304180 0x80 /* EQEP */
- 0x48304200 0x48304200 0x80>; /* EHRPWM */
-
- ecap2: ecap@48304100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48304100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <61>;
- interrupt-names = "ecap2";
- status = "disabled";
- };
-
- ehrpwm2: pwm@48304200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48304200 0x80>;
- clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- mac: ethernet@4a100000 {
- compatible = "ti,am335x-cpsw","ti,cpsw";
- ti,hwmods = "cpgmac0";
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
- clock-names = "fck", "cpts";
- cpdma_channels = <8>;
- ale_entries = <1024>;
- bd_ram_size = <0x2000>;
- mac_control = <0x20>;
- slaves = <2>;
- active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
- cpts_clock_shift = <29>;
- reg = <0x4a100000 0x800
- 0x4a101200 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- /*
- * c0_rx_thresh_pend
- * c0_rx_pend
- * c0_tx_pend
- * c0_misc_pend
- */
- interrupts = <40 41 42 43>;
- ranges;
- syscon = <&scm_conf>;
- status = "disabled";
-
- davinci_mdio: mdio@4a101000 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "davinci_mdio";
- bus_freq = <1000000>;
- reg = <0x4a101000 0x100>;
- status = "disabled";
- };
-
- cpsw_emac0: slave@4a100200 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- };
-
- cpsw_emac1: slave@4a100300 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- };
-
- phy_sel: cpsw-phy-sel@44e10650 {
- compatible = "ti,am3352-cpsw-phy-sel";
- reg= <0x44e10650 0x4>;
- reg-names = "gmii-sel";
- };
- };
-
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
@@ -924,40 +393,6 @@
};
};
- elm: elm@48080000 {
- compatible = "ti,am3352-elm";
- reg = <0x48080000 0x2000>;
- interrupts = <4>;
- ti,hwmods = "elm";
- status = "disabled";
- };
-
- lcdc: lcdc@4830e000 {
- compatible = "ti,am33xx-tilcdc";
- reg = <0x4830e000 0x1000>;
- interrupts = <36>;
- ti,hwmods = "lcdc";
- status = "disabled";
- };
-
- tscadc: tscadc@44e0d000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x44e0d000 0x1000>;
- interrupts = <16>;
- ti,hwmods = "adc_tsc";
- status = "disabled";
- dmas = <&edma 53 0>, <&edma 57 0>;
- dma-names = "fifo0", "fifo1";
-
- tsc {
- compatible = "ti,am3359-tsc";
- };
- am335x_adc: adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
@@ -1005,42 +440,8 @@
<&edma 5 0>;
dma-names = "tx", "rx";
};
-
- mcasp0: mcasp@48038000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp0";
- reg = <0x48038000 0x2000>,
- <0x46000000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <80>, <81>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 8 2>,
- <&edma 9 2>;
- dma-names = "tx", "rx";
- };
-
- mcasp1: mcasp@4803c000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp1";
- reg = <0x4803C000 0x2000>,
- <0x46400000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <82>, <83>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 10 2>,
- <&edma 11 2>;
- dma-names = "tx", "rx";
- };
-
- rng: rng@48310000 {
- compatible = "ti,omap4-rng";
- ti,hwmods = "rng";
- reg = <0x48310000 0x2000>;
- interrupts = <111>;
- };
};
};
+#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 1e2bb68231ad..3527c0f2dfff 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -20,6 +20,10 @@
display0 = &lcd0;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index a68e89dae7a1..55aff4db9c7c 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
@@ -159,12 +160,7 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- l4_wkup: l4_wkup@44c00000 {
- compatible = "ti,am4-l4-wkup", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x44c00000 0x287000>;
-
+ l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
@@ -173,75 +169,10 @@
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
-
- prcm: prcm@1f0000 {
- compatible = "ti,am4-prcm", "simple-bus";
- reg = <0x1f0000 0x11000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1f0000 0x11000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm@210000 {
- compatible = "ti,am4-scm", "simple-bus";
- reg = <0x210000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x210000 0x4000>;
-
- am43xx_pinmux: pinmux@800 {
- compatible = "ti,am437-padconf",
- "pinctrl-single";
- reg = <0x800 0x31c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- scm_conf: scm_conf@0 {
- compatible = "syscon";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- wkup_m3_ipc: wkup_m3_ipc@1324 {
- compatible = "ti,am4372-wkup-m3-ipc";
- reg = <0x1324 0x44>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- ti,rproc = <&wkup_m3>;
- mboxes = <&mailbox &mbox_wkupm3>;
- };
-
- edma_xbar: dma-router@f90 {
- compatible = "ti,am335x-edma-crossbar";
- reg = <0xf90 0x40>;
- #dma-cells = <3>;
- dma-requests = <64>;
- dma-masters = <&edma>;
- };
-
- scm_clockdomains: clockdomains {
- };
- };
+ };
+ l4_per: interconnect@48000000 {
+ };
+ l4_fast: interconnect@4a000000 {
};
emif: emif@4c000000 {
@@ -297,333 +228,6 @@
interrupt-names = "edma3_tcerrint";
};
- uart0: serial@44e09000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x44e09000 0x2000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart1";
- };
-
- uart1: serial@48022000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x48022000 0x2000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart2";
- status = "disabled";
- };
-
- uart2: serial@48024000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x48024000 0x2000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart3";
- status = "disabled";
- };
-
- uart3: serial@481a6000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x481a6000 0x2000>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart4";
- status = "disabled";
- };
-
- uart4: serial@481a8000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x481a8000 0x2000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart5";
- status = "disabled";
- };
-
- uart5: serial@481aa000 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
- reg = <0x481aa000 0x2000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "uart6";
- status = "disabled";
- };
-
- mailbox: mailbox@480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480C8000 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
- ti,mbox-send-noirq;
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <0 0 3>;
- };
- };
-
- timer1: timer@44e31000 {
- compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
- reg = <0x44e31000 0x400>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-alwon;
- ti,hwmods = "timer1";
- clocks = <&timer1_fck>;
- clock-names = "fck";
- };
-
- timer2: timer@48040000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48040000 0x400>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer2";
- clocks = <&timer2_fck>;
- clock-names = "fck";
- };
-
- timer3: timer@48042000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48042000 0x400>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer3";
- status = "disabled";
- };
-
- timer4: timer@48044000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48044000 0x400>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- ti,hwmods = "timer4";
- status = "disabled";
- };
-
- timer5: timer@48046000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48046000 0x400>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- ti,hwmods = "timer5";
- status = "disabled";
- };
-
- timer6: timer@48048000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48048000 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- ti,hwmods = "timer6";
- status = "disabled";
- };
-
- timer7: timer@4804a000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x4804a000 0x400>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- ti,hwmods = "timer7";
- status = "disabled";
- };
-
- timer8: timer@481c1000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x481c1000 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer8";
- status = "disabled";
- };
-
- timer9: timer@4833d000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x4833d000 0x400>;
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer9";
- status = "disabled";
- };
-
- timer10: timer@4833f000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x4833f000 0x400>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer10";
- status = "disabled";
- };
-
- timer11: timer@48341000 {
- compatible = "ti,am4372-timer","ti,am335x-timer";
- reg = <0x48341000 0x400>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "timer11";
- status = "disabled";
- };
-
- counter32k: counter@44e86000 {
- compatible = "ti,am4372-counter32k","ti,omap-counter32k";
- reg = <0x44e86000 0x40>;
- ti,hwmods = "counter_32k";
- };
-
- rtc: rtc@44e3e000 {
- compatible = "ti,am4372-rtc", "ti,am3352-rtc",
- "ti,da830-rtc";
- reg = <0x44e3e000 0x1000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "rtc";
- clocks = <&clk_32768_ck>;
- clock-names = "int-clk";
- system-power-controller;
- status = "disabled";
- };
-
- wdt: wdt@44e35000 {
- compatible = "ti,am4372-wdt","ti,omap3-wdt";
- reg = <0x44e35000 0x1000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "wd_timer2";
- };
-
- gpio0: gpio@44e07000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x44e07000 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio1";
- status = "disabled";
- };
-
- gpio1: gpio@4804c000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x4804c000 0x1000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio2";
- status = "disabled";
- };
-
- gpio2: gpio@481ac000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x481ac000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio3";
- status = "disabled";
- };
-
- gpio3: gpio@481ae000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x481ae000 0x1000>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio4";
- status = "disabled";
- };
-
- gpio4: gpio@48320000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x48320000 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio5";
- status = "disabled";
- };
-
- gpio5: gpio@48322000 {
- compatible = "ti,am4372-gpio","ti,omap4-gpio";
- reg = <0x48322000 0x1000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,hwmods = "gpio6";
- status = "disabled";
- };
-
- hwspinlock: spinlock@480ca000 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x480ca000 0x1000>;
- ti,hwmods = "spinlock";
- #hwlock-cells = <1>;
- };
-
- i2c0: i2c@44e0b000 {
- compatible = "ti,am4372-i2c","ti,omap4-i2c";
- reg = <0x44e0b000 0x1000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "i2c1";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@4802a000 {
- compatible = "ti,am4372-i2c","ti,omap4-i2c";
- reg = <0x4802a000 0x1000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "i2c2";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@4819c000 {
- compatible = "ti,am4372-i2c","ti,omap4-i2c";
- reg = <0x4819c000 0x1000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "i2c3";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@48030000 {
- compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
- reg = <0x48030000 0x400>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "spi0";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmc1: mmc@48060000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x48060000 0x1000>;
- ti,hwmods = "mmc1";
- ti,dual-volt;
- ti,needs-special-reset;
- dmas = <&edma 24 0>,
- <&edma 25 0>;
- dma-names = "tx", "rx";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- mmc2: mmc@481d8000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x481d8000 0x1000>;
- ti,hwmods = "mmc2";
- ti,needs-special-reset;
- dmas = <&edma 2 0>,
- <&edma 3 0>;
- dma-names = "tx", "rx";
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
reg = <0x47810000 0x1000>;
@@ -633,282 +237,6 @@
status = "disabled";
};
- spi1: spi@481a0000 {
- compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
- reg = <0x481a0000 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "spi1";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@481a2000 {
- compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
- reg = <0x481a2000 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "spi2";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@481a4000 {
- compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
- reg = <0x481a4000 0x400>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "spi3";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi4: spi@48345000 {
- compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
- reg = <0x48345000 0x400>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "spi4";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mac: ethernet@4a100000 {
- compatible = "ti,am4372-cpsw","ti,cpsw";
- reg = <0x4a100000 0x800
- 0x4a101200 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- ti,hwmods = "cpgmac0";
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
- <&dpll_clksel_mac_clk>;
- clock-names = "fck", "cpts", "50mclk";
- assigned-clocks = <&dpll_clksel_mac_clk>;
- assigned-clock-rates = <50000000>;
- status = "disabled";
- cpdma_channels = <8>;
- ale_entries = <1024>;
- bd_ram_size = <0x2000>;
- mac_control = <0x20>;
- slaves = <2>;
- active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
- cpts_clock_shift = <29>;
- ranges;
- syscon = <&scm_conf>;
-
- davinci_mdio: mdio@4a101000 {
- compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x4a101000 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "davinci_mdio";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpsw_emac0: slave@4a100200 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- };
-
- cpsw_emac1: slave@4a100300 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- };
-
- phy_sel: cpsw-phy-sel@44e10650 {
- compatible = "ti,am43xx-cpsw-phy-sel";
- reg= <0x44e10650 0x4>;
- reg-names = "gmii-sel";
- };
- };
-
- epwmss0: epwmss@48300000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x48300000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss0";
- status = "disabled";
-
- ecap0: ecap@48300100 {
- compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48300100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ehrpwm0: pwm@48300200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48300200 0x80>;
- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss1: epwmss@48302000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x48302000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss1";
- status = "disabled";
-
- ecap1: ecap@48302100 {
- compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48302100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ehrpwm1: pwm@48302200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48302200 0x80>;
- clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss2: epwmss@48304000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x48304000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss2";
- status = "disabled";
-
- ecap2: ecap@48304100 {
- compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48304100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ehrpwm2: pwm@48304200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48304200 0x80>;
- clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss3: epwmss@48306000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x48306000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss3";
- status = "disabled";
-
- ehrpwm3: pwm@48306200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48306200 0x80>;
- clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss4: epwmss@48308000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x48308000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss4";
- status = "disabled";
-
- ehrpwm4: pwm@48308200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48308200 0x80>;
- clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss5: epwmss@4830a000 {
- compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
- reg = <0x4830a000 0x10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "epwmss5";
- status = "disabled";
-
- ehrpwm5: pwm@4830a200 {
- compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x4830a200 0x80>;
- clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- tscadc: tscadc@44e0d000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x44e0d000 0x1000>;
- ti,hwmods = "adc_tsc";
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&adc_tsc_fck>;
- clock-names = "fck";
- status = "disabled";
- dmas = <&edma 53 0>, <&edma 57 0>;
- dma-names = "fifo0", "fifo1";
-
- tsc {
- compatible = "ti,am3359-tsc";
- };
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
-
- };
-
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
@@ -938,53 +266,6 @@
dma-names = "tx", "rx";
};
- rng: rng@48310000 {
- compatible = "ti,omap4-rng";
- ti,hwmods = "rng";
- reg = <0x48310000 0x2000>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- mcasp0: mcasp@48038000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp0";
- reg = <0x48038000 0x2000>,
- <0x46000000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 8 2>,
- <&edma 9 2>;
- dma-names = "tx", "rx";
- };
-
- mcasp1: mcasp@4803c000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp1";
- reg = <0x4803C000 0x2000>,
- <0x46400000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 10 2>,
- <&edma 11 2>;
- dma-names = "tx", "rx";
- };
-
- elm: elm@48080000 {
- compatible = "ti,am3352-elm";
- reg = <0x48080000 0x2000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "elm";
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- status = "disabled";
- };
-
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
@@ -1005,102 +286,6 @@
status = "disabled";
};
- ocp2scp0: ocp2scp@483a8000 {
- compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "ocp2scp0";
-
- usb2_phy1: phy@483a8000 {
- compatible = "ti,am437x-usb2";
- reg = <0x483a8000 0x8000>;
- syscon-phy-power = <&scm_conf 0x620>;
- clocks = <&usb_phy0_always_on_clk32k>,
- <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- ocp2scp1: ocp2scp@483e8000 {
- compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "ocp2scp1";
-
- usb2_phy2: phy@483e8000 {
- compatible = "ti,am437x-usb2";
- reg = <0x483e8000 0x8000>;
- syscon-phy-power = <&scm_conf 0x628>;
- clocks = <&usb_phy1_always_on_clk32k>,
- <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- dwc3_1: omap_dwc3@48380000 {
- compatible = "ti,am437x-dwc3";
- ti,hwmods = "usb_otg_ss0";
- reg = <0x48380000 0x10000>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <1>;
- ranges;
-
- usb1: usb@48390000 {
- compatible = "synopsys,dwc3";
- reg = <0x48390000 0x10000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- status = "disabled";
- snps,dis_u3_susphy_quirk;
- snps,dis_u2_susphy_quirk;
- };
- };
-
- dwc3_2: omap_dwc3@483c0000 {
- compatible = "ti,am437x-dwc3";
- ti,hwmods = "usb_otg_ss1";
- reg = <0x483c0000 0x10000>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <1>;
- ranges;
-
- usb2: usb@483d0000 {
- compatible = "synopsys,dwc3";
- reg = <0x483d0000 0x10000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- phys = <&usb2_phy2>;
- phy-names = "usb2-phy";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- status = "disabled";
- snps,dis_u3_susphy_quirk;
- snps,dis_u2_susphy_quirk;
- };
- };
-
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
@@ -1114,16 +299,6 @@
status = "disabled";
};
- hdq: hdq@48347000 {
- compatible = "ti,am4372-hdq";
- reg = <0x48347000 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&func_12m_clk>;
- clock-names = "fck";
- ti,hwmods = "hdq1w";
- status = "disabled";
- };
-
dss: dss@4832a000 {
compatible = "ti,omap3-dss";
reg = <0x4832a000 0x200>;
@@ -1173,45 +348,8 @@
pool;
};
};
-
- dcan0: can@481cc000 {
- compatible = "ti,am4372-d_can", "ti,am3352-d_can";
- ti,hwmods = "d_can0";
- clocks = <&dcan0_fck>;
- clock-names = "fck";
- reg = <0x481cc000 0x2000>;
- syscon-raminit = <&scm_conf 0x644 0>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- dcan1: can@481d0000 {
- compatible = "ti,am4372-d_can", "ti,am3352-d_can";
- ti,hwmods = "d_can1";
- clocks = <&dcan1_fck>;
- clock-names = "fck";
- reg = <0x481d0000 0x2000>;
- syscon-raminit = <&scm_conf 0x644 1>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- vpfe0: vpfe@48326000 {
- compatible = "ti,am437x-vpfe";
- reg = <0x48326000 0x2000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "vpfe0";
- status = "disabled";
- };
-
- vpfe1: vpfe@48328000 {
- compatible = "ti,am437x-vpfe";
- reg = <0x48328000 0x2000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "vpfe1";
- status = "disabled";
- };
};
};
+#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 601bf4daaeb7..f4a20cade808 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -67,7 +67,13 @@
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
- row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&matrix_keypad_default>;
+ pinctrl-1 = <&matrix_keypad_sleep>;
+
+ linux,wakeup;
+
+ row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
@@ -155,16 +161,23 @@
beeper: beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
- pinctrl-0 = <&beeper_pins>;
+ pinctrl-0 = <&beeper_pins_default>;
+ pinctrl-1 = <&beeper_pins_sleep>;
gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
};
};
&am43xx_pinmux {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&wlan_pins_default>;
+ pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
pinctrl-1 = <&wlan_pins_sleep>;
+ ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
+ pinctrl-single,pins = <
+ 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
+ >;
+ };
+
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
@@ -511,27 +524,121 @@
>;
};
+ beeper_pins_default: beeper_pins_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
+ >;
+ };
+
+ beeper_pins_sleep: beeper_pins_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */
+ >;
+ };
+
+ unused_pins: unused_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
+ AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
+ AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
+ AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
+ AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ debugss_pins: pinmux_debugss_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
+ AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
+ >;
+ };
+
uart0_pins_default: uart0_pins_default {
pinctrl-single,pins = <
- AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
- AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
- AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
- AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
+ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
+ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
- beeper_pins: beeper_pins {
+ uart0_pins_sleep: uart0_pins_sleep {
pinctrl-single,pins = <
- AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
+ AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
+ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
+ AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ matrix_keypad_default: matrix_keypad_default {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
+ AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
+ AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
+ AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
+ matrix_keypad_sleep: matrix_keypad_sleep {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
+ AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
+ AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
+ AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
+ >;
+ };
};
&uart0 {
status = "okay";
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_default>;
+ pinctrl-1 = <&uart0_pins_sleep>;
};
&i2c0 {
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
new file mode 100644
index 000000000000..ca0896f80248
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -0,0 +1,2505 @@
+&l4_wkup { /* 0x44c00000 */
+ compatible = "ti,am4-l4-wkup", "simple-bus";
+ reg = <0x44c00000 0x800>,
+ <0x44c00800 0x800>,
+ <0x44c01000 0x400>,
+ <0x44c01400 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
+ <0x00100000 0x44d00000 0x100000>, /* segment 1 */
+ <0x00200000 0x44e00000 0x100000>; /* segment 2 */
+
+ segment@0 { /* 0x44c00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>; /* ap 3 */
+ };
+
+ segment@100000 { /* 0x44d00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
+ <0x00004000 0x00104000 0x001000>, /* ap 5 */
+ <0x00080000 0x00180000 0x002000>, /* ap 6 */
+ <0x00082000 0x00182000 0x001000>, /* ap 7 */
+ <0x000f0000 0x001f0000 0x010000>; /* ap 8 */
+
+ target-module@0 { /* 0x44d00000, ap 4 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x4000>;
+ };
+
+ target-module@80000 { /* 0x44d80000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x2000>;
+ };
+
+ target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf0000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0000 0x10000>;
+
+ prcm: prcm@0 {
+ compatible = "ti,am4-prcm", "simple-bus";
+ reg = <0x0 0x11000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+ };
+ };
+
+ segment@200000 { /* 0x44e00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
+ <0x00003000 0x00203000 0x001000>, /* ap 10 */
+ <0x00004000 0x00204000 0x001000>, /* ap 11 */
+ <0x00005000 0x00205000 0x001000>, /* ap 12 */
+ <0x00006000 0x00206000 0x001000>, /* ap 13 */
+ <0x00007000 0x00207000 0x001000>, /* ap 14 */
+ <0x00008000 0x00208000 0x001000>, /* ap 15 */
+ <0x00009000 0x00209000 0x001000>, /* ap 16 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
+ <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
+ <0x00010000 0x00210000 0x010000>, /* ap 22 */
+ <0x00030000 0x00230000 0x001000>, /* ap 23 */
+ <0x00031000 0x00231000 0x001000>, /* ap 24 */
+ <0x00032000 0x00232000 0x001000>, /* ap 25 */
+ <0x00033000 0x00233000 0x001000>, /* ap 26 */
+ <0x00034000 0x00234000 0x001000>, /* ap 27 */
+ <0x00035000 0x00235000 0x001000>, /* ap 28 */
+ <0x00036000 0x00236000 0x001000>, /* ap 29 */
+ <0x00037000 0x00237000 0x001000>, /* ap 30 */
+ <0x00038000 0x00238000 0x001000>, /* ap 31 */
+ <0x00039000 0x00239000 0x001000>, /* ap 32 */
+ <0x0003a000 0x0023a000 0x001000>, /* ap 33 */
+ <0x0003e000 0x0023e000 0x001000>, /* ap 34 */
+ <0x0003f000 0x0023f000 0x001000>, /* ap 35 */
+ <0x00040000 0x00240000 0x040000>, /* ap 36 */
+ <0x00080000 0x00280000 0x001000>, /* ap 37 */
+ <0x00088000 0x00288000 0x008000>, /* ap 38 */
+ <0x00092000 0x00292000 0x001000>, /* ap 39 */
+ <0x00086000 0x00286000 0x001000>, /* ap 40 */
+ <0x00087000 0x00287000 0x001000>, /* ap 41 */
+ <0x00090000 0x00290000 0x001000>, /* ap 42 */
+ <0x00091000 0x00291000 0x001000>; /* ap 43 */
+
+ target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3000 0x1000>;
+ };
+
+ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5000 0x1000>;
+ };
+
+ target-module@7000 { /* 0x44e07000, ap 14 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio1";
+ reg = <0x7000 0x4>,
+ <0x7010 0x4>,
+ <0x7114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x1000>;
+
+ gpio0: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@9000 { /* 0x44e09000, ap 16 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart1";
+ reg = <0x9050 0x4>,
+ <0x9054 0x4>,
+ <0x9058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9000 0x1000>;
+
+ uart0: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c1";
+ reg = <0xb000 0x8>,
+ <0xb010 0x8>,
+ <0xb090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb000 0x1000>;
+
+ i2c0: i2c@0 {
+ compatible = "ti,am4372-i2c","ti,omap4-i2c";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "adc_tsc";
+ reg = <0xd000 0x4>,
+ <0xd010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */
+ clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd000 0x1000>;
+
+ tscadc: tscadc@0 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&adc_tsc_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
+
+ tsc {
+ compatible = "ti,am3359-tsc";
+ };
+
+ adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+
+ };
+ };
+
+ target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x10000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x10000>;
+
+ scm: scm@0 {
+ compatible = "ti,am4-scm", "simple-bus";
+ reg = <0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x4000>;
+
+ phy_sel: cpsw-phy-sel@650 {
+ compatible = "ti,am43xx-cpsw-phy-sel";
+ reg= <0x650 0x4>;
+ reg-names = "gmii-sel";
+ };
+
+ am43xx_pinmux: pinmux@800 {
+ compatible = "ti,am437-padconf",
+ "pinctrl-single";
+ reg = <0x800 0x31c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ wkup_m3_ipc: wkup_m3_ipc@1324 {
+ compatible = "ti,am4372-wkup-m3-ipc";
+ reg = <0x1324 0x44>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ ti,rproc = <&wkup_m3>;
+ mboxes = <&mailbox &mbox_wkupm3>;
+ };
+
+ edma_xbar: dma-router@f90 {
+ compatible = "ti,am335x-edma-crossbar";
+ reg = <0xf90 0x40>;
+ #dma-cells = <3>;
+ dma-requests = <64>;
+ dma-masters = <&edma>;
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@31000 { /* 0x44e31000, ap 24 40.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ ti,hwmods = "timer1";
+ reg = <0x31000 0x4>,
+ <0x31010 0x4>,
+ <0x31014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x31000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@33000 { /* 0x44e33000, ap 26 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x33000 0x1000>;
+ };
+
+ target-module@35000 { /* 0x44e35000, ap 28 50.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "wd_timer2";
+ reg = <0x35000 0x4>,
+ <0x35010 0x4>,
+ <0x35014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x35000 0x1000>;
+
+ wdt: wdt@0 {
+ compatible = "ti,am4372-wdt","ti,omap3-wdt";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@37000 { /* 0x44e37000, ap 30 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x37000 0x1000>;
+ };
+
+ target-module@39000 { /* 0x44e39000, ap 32 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x39000 0x1000>;
+ };
+
+ target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "rtc";
+ reg = <0x3e074 0x4>,
+ <0x3e078 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
+ clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ rtc: rtc@0 {
+ compatible = "ti,am4372-rtc", "ti,am3352-rtc",
+ "ti,da830-rtc";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_32768_ck>;
+ clock-names = "int-clk";
+ system-power-controller;
+ status = "disabled";
+ };
+ };
+
+ target-module@40000 { /* 0x44e40000, ap 36 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x40000>;
+ };
+
+ target-module@86000 { /* 0x44e86000, ap 40 70.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "counter_32k";
+ reg = <0x86000 0x4>,
+ <0x86004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */
+ clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+ reg = <0x0 0x40>;
+ };
+ };
+
+ target-module@88000 { /* 0x44e88000, ap 38 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00088000 0x00008000>,
+ <0x00008000 0x00090000 0x00001000>,
+ <0x00009000 0x00091000 0x00001000>;
+ };
+ };
+};
+
+&l4_fast { /* 0x4a000000 */
+ compatible = "ti,am4-l4-fast", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x400>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00100000 0x00100000 0x008000>, /* ap 3 */
+ <0x00108000 0x00108000 0x001000>, /* ap 4 */
+ <0x00400000 0x00400000 0x002000>, /* ap 5 */
+ <0x00402000 0x00402000 0x001000>, /* ap 6 */
+ <0x00200000 0x00200000 0x080000>, /* ap 7 */
+ <0x00280000 0x00280000 0x001000>; /* ap 8 */
+
+ target-module@100000 { /* 0x4a100000, ap 3 04.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "cpgmac0";
+ reg = <0x101200 0x4>,
+ <0x101208 0x4>,
+ <0x101204 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <0>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x100000 0x8000>;
+
+ mac: ethernet@0 {
+ compatible = "ti,am4372-cpsw","ti,cpsw";
+ reg = <0x0 0x800
+ 0x1200 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
+ <&dpll_clksel_mac_clk>;
+ clock-names = "fck", "cpts", "50mclk";
+ assigned-clocks = <&dpll_clksel_mac_clk>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ ranges = <0 0 0x8000>;
+ syscon = <&scm_conf>;
+ cpsw-phy-sel = <&phy_sel>;
+
+ davinci_mdio: mdio@1000 {
+ compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpsw_emac0: slave@200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+ };
+
+ target-module@200000 { /* 0x4a200000, ap 7 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x200000 0x80000>;
+ };
+
+ target-module@400000 { /* 0x4a400000, ap 5 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x400000 0x2000>;
+ };
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,am4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
+ <0x00100000 0x48100000 0x100000>, /* segment 1 */
+ <0x00200000 0x48200000 0x100000>, /* segment 2 */
+ <0x00300000 0x48300000 0x100000>, /* segment 3 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>, /* ap 3 */
+ <0x00001800 0x00001800 0x000400>, /* ap 4 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
+ <0x00008000 0x00008000 0x001000>, /* ap 6 */
+ <0x00009000 0x00009000 0x001000>, /* ap 7 */
+ <0x00022000 0x00022000 0x001000>, /* ap 8 */
+ <0x00023000 0x00023000 0x001000>, /* ap 9 */
+ <0x00024000 0x00024000 0x001000>, /* ap 10 */
+ <0x00025000 0x00025000 0x001000>, /* ap 11 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 12 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 13 */
+ <0x00038000 0x00038000 0x002000>, /* ap 14 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 15 */
+ <0x0003c000 0x0003c000 0x002000>, /* ap 16 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 17 */
+ <0x00040000 0x00040000 0x001000>, /* ap 18 */
+ <0x00041000 0x00041000 0x001000>, /* ap 19 */
+ <0x00042000 0x00042000 0x001000>, /* ap 20 */
+ <0x00043000 0x00043000 0x001000>, /* ap 21 */
+ <0x00044000 0x00044000 0x001000>, /* ap 22 */
+ <0x00045000 0x00045000 0x001000>, /* ap 23 */
+ <0x00046000 0x00046000 0x001000>, /* ap 24 */
+ <0x00047000 0x00047000 0x001000>, /* ap 25 */
+ <0x00048000 0x00048000 0x001000>, /* ap 26 */
+ <0x00049000 0x00049000 0x001000>, /* ap 27 */
+ <0x0004c000 0x0004c000 0x001000>, /* ap 28 */
+ <0x0004d000 0x0004d000 0x001000>, /* ap 29 */
+ <0x00060000 0x00060000 0x001000>, /* ap 30 */
+ <0x00061000 0x00061000 0x001000>, /* ap 31 */
+ <0x00080000 0x00080000 0x010000>, /* ap 32 */
+ <0x00090000 0x00090000 0x001000>, /* ap 33 */
+ <0x00030000 0x00030000 0x001000>, /* ap 65 */
+ <0x00031000 0x00031000 0x001000>, /* ap 66 */
+ <0x0004a000 0x0004a000 0x001000>, /* ap 71 */
+ <0x0004b000 0x0004b000 0x001000>, /* ap 72 */
+ <0x000c8000 0x000c8000 0x001000>, /* ap 73 */
+ <0x000c9000 0x000c9000 0x001000>, /* ap 74 */
+ <0x000ca000 0x000ca000 0x001000>, /* ap 77 */
+ <0x000cb000 0x000cb000 0x001000>, /* ap 78 */
+ <0x00034000 0x00034000 0x001000>, /* ap 80 */
+ <0x00035000 0x00035000 0x001000>, /* ap 81 */
+ <0x00036000 0x00036000 0x001000>, /* ap 84 */
+ <0x00037000 0x00037000 0x001000>, /* ap 85 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ target-module@8000 { /* 0x48008000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@22000 { /* 0x48022000, ap 8 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart2";
+ reg = <0x22050 0x4>,
+ <0x22054 0x4>,
+ <0x22058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@24000 { /* 0x48024000, ap 10 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart3";
+ reg = <0x24050 0x4>,
+ <0x24054 0x4>,
+ <0x24058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c2";
+ reg = <0x2a000 0x8>,
+ <0x2a010 0x8>,
+ <0x2a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,am4372-i2c","ti,omap4-i2c";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@30000 { /* 0x48030000, ap 65 08.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi0";
+ reg = <0x30000 0x4>,
+ <0x30110 0x4>,
+ <0x30114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+
+ spi0: spi@0 {
+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 80 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+ };
+
+ target-module@36000 { /* 0x48036000, ap 84 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+
+ target-module@38000 { /* 0x48038000, ap 14 04.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "mcasp0";
+ reg = <0x38000 0x4>,
+ <0x38004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x2000>,
+ <0x46000000 0x46000000 0x400000>;
+
+ mcasp0: mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46000000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 8 2>,
+ <&edma 9 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ ti,hwmods = "mcasp1";
+ reg = <0x3c000 0x4>,
+ <0x3c004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x2000>,
+ <0x46400000 0x46400000 0x400000>;
+
+ mcasp1: mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46400000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 10 2>,
+ <&edma 11 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@40000 { /* 0x48040000, ap 18 1e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer2";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>,
+ <0x40014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@42000 { /* 0x48042000, ap 20 24.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer3";
+ reg = <0x42000 0x4>,
+ <0x42010 0x4>,
+ <0x42014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x42000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@44000 { /* 0x48044000, ap 22 26.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer4";
+ reg = <0x44000 0x4>,
+ <0x44010 0x4>,
+ <0x44014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x44000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ status = "disabled";
+ };
+ };
+
+ target-module@46000 { /* 0x48046000, ap 24 28.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer5";
+ reg = <0x46000 0x4>,
+ <0x46010 0x4>,
+ <0x46014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x46000 0x1000>;
+
+ timer5: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ status = "disabled";
+ };
+ };
+
+ target-module@48000 { /* 0x48048000, ap 26 1a.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer6";
+ reg = <0x48000 0x4>,
+ <0x48010 0x4>,
+ <0x48014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48000 0x1000>;
+
+ timer6: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ status = "disabled";
+ };
+ };
+
+ target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer7";
+ reg = <0x4a000 0x4>,
+ <0x4a010 0x4>,
+ <0x4a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4a000 0x1000>;
+
+ timer7: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ ti,timer-pwm;
+ status = "disabled";
+ };
+ };
+
+ target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio2";
+ reg = <0x4c000 0x4>,
+ <0x4c010 0x4>,
+ <0x4c114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000 0x1000>;
+
+ gpio1: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 30 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "mmc1";
+ reg = <0x602fc 0x4>,
+ <0x60110 0x4>,
+ <0x60114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x1000>;
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&edma 24 0>,
+ <&edma 25 0>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@80000 { /* 0x48080000, ap 32 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "elm";
+ reg = <0x80000 0x4>,
+ <0x80010 0x4>,
+ <0x80014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>;
+
+ elm: elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mailbox";
+ reg = <0xc8000 0x4>,
+ <0xc8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc8000 0x1000>;
+
+ mailbox: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-send-noirq;
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
+ };
+ };
+
+ target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spinlock";
+ reg = <0xca000 0x4>,
+ <0xca010 0x4>,
+ <0xca014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xca000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x48100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
+ <0x0008d000 0x0018d000 0x001000>, /* ap 35 */
+ <0x0008e000 0x0018e000 0x001000>, /* ap 36 */
+ <0x0008f000 0x0018f000 0x001000>, /* ap 37 */
+ <0x0009c000 0x0019c000 0x001000>, /* ap 38 */
+ <0x0009d000 0x0019d000 0x001000>, /* ap 39 */
+ <0x000a6000 0x001a6000 0x001000>, /* ap 40 */
+ <0x000a7000 0x001a7000 0x001000>, /* ap 41 */
+ <0x000a8000 0x001a8000 0x001000>, /* ap 42 */
+ <0x000a9000 0x001a9000 0x001000>, /* ap 43 */
+ <0x000aa000 0x001aa000 0x001000>, /* ap 44 */
+ <0x000ab000 0x001ab000 0x001000>, /* ap 45 */
+ <0x000ac000 0x001ac000 0x001000>, /* ap 46 */
+ <0x000ad000 0x001ad000 0x001000>, /* ap 47 */
+ <0x000ae000 0x001ae000 0x001000>, /* ap 48 */
+ <0x000af000 0x001af000 0x001000>, /* ap 49 */
+ <0x000cc000 0x001cc000 0x002000>, /* ap 50 */
+ <0x000ce000 0x001ce000 0x002000>, /* ap 51 */
+ <0x000d0000 0x001d0000 0x002000>, /* ap 52 */
+ <0x000d2000 0x001d2000 0x002000>, /* ap 53 */
+ <0x000d8000 0x001d8000 0x001000>, /* ap 54 */
+ <0x000d9000 0x001d9000 0x001000>, /* ap 55 */
+ <0x000a0000 0x001a0000 0x001000>, /* ap 67 */
+ <0x000a1000 0x001a1000 0x001000>, /* ap 68 */
+ <0x000a2000 0x001a2000 0x001000>, /* ap 69 */
+ <0x000a3000 0x001a3000 0x001000>, /* ap 70 */
+ <0x000a4000 0x001a4000 0x001000>, /* ap 92 */
+ <0x000a5000 0x001a5000 0x001000>, /* ap 93 */
+ <0x000c1000 0x001c1000 0x001000>, /* ap 94 */
+ <0x000c2000 0x001c2000 0x001000>; /* ap 95 */
+
+ target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8c000 0x1000>;
+ };
+
+ target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8e000 0x1000>;
+ };
+
+ target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c3";
+ reg = <0x9c000 0x8>,
+ <0x9c010 0x8>,
+ <0x9c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,am4372-i2c","ti,omap4-i2c";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi1";
+ reg = <0xa0000 0x4>,
+ <0xa0110 0x4>,
+ <0xa0114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x1000>;
+
+ spi1: spi@0 {
+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi2";
+ reg = <0xa2000 0x4>,
+ <0xa2110 0x4>,
+ <0xa2114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+
+ spi2: spi@0 {
+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi3";
+ reg = <0xa4000 0x4>,
+ <0xa4110 0x4>,
+ <0xa4114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa4000 0x1000>;
+
+ spi3: spi@0 {
+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart4";
+ reg = <0xa6050 0x4>,
+ <0xa6054 0x4>,
+ <0xa6058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa6000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart5";
+ reg = <0xa8050 0x4>,
+ <0xa8054 0x4>,
+ <0xa8058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart6";
+ reg = <0xaa050 0x4>,
+ <0xaa054 0x4>,
+ <0xaa058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xaa000 0x1000>;
+
+ uart5: serial@0 {
+ compatible = "ti,am4372-uart","ti,omap2-uart";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio3";
+ reg = <0xac000 0x4>,
+ <0xac010 0x4>,
+ <0xac114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xac000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio4";
+ reg = <0xae000 0x4>,
+ <0xae010 0x4>,
+ <0xae114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xae000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer8";
+ reg = <0xc1000 0x4>,
+ <0xc1010 0x4>,
+ <0xc1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc1000 0x1000>;
+
+ timer8: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "d_can0";
+ reg = <0xcc000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xcc000 0x2000>;
+
+ dcan0: can@0 {
+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ syscon-raminit = <&scm_conf 0x644 0>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "d_can1";
+ reg = <0xd0000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd0000 0x2000>;
+
+ dcan1: can@0 {
+ compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ syscon-raminit = <&scm_conf 0x644 1>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "mmc2";
+ reg = <0xd82fc 0x4>,
+ <0xd8110 0x4>,
+ <0xd8114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd8000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x0 0x1000>;
+ ti,needs-special-reset;
+ dmas = <&edma 2 0>,
+ <&edma 3 0>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+ };
+
+ segment@200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment@300000 { /* 0x48300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */
+ <0x00001000 0x00301000 0x001000>, /* ap 57 */
+ <0x00002000 0x00302000 0x001000>, /* ap 58 */
+ <0x00003000 0x00303000 0x001000>, /* ap 59 */
+ <0x00004000 0x00304000 0x001000>, /* ap 60 */
+ <0x00005000 0x00305000 0x001000>, /* ap 61 */
+ <0x00018000 0x00318000 0x004000>, /* ap 62 */
+ <0x0001c000 0x0031c000 0x001000>, /* ap 63 */
+ <0x00010000 0x00310000 0x002000>, /* ap 64 */
+ <0x00028000 0x00328000 0x001000>, /* ap 75 */
+ <0x00029000 0x00329000 0x001000>, /* ap 76 */
+ <0x00012000 0x00312000 0x001000>, /* ap 79 */
+ <0x00020000 0x00320000 0x001000>, /* ap 82 */
+ <0x00021000 0x00321000 0x001000>, /* ap 83 */
+ <0x00026000 0x00326000 0x001000>, /* ap 86 */
+ <0x00027000 0x00327000 0x001000>, /* ap 87 */
+ <0x0002a000 0x0032a000 0x000400>, /* ap 88 */
+ <0x0002c000 0x0032c000 0x001000>, /* ap 89 */
+ <0x00013000 0x00313000 0x001000>, /* ap 90 */
+ <0x00014000 0x00314000 0x001000>, /* ap 91 */
+ <0x00006000 0x00306000 0x001000>, /* ap 96 */
+ <0x00007000 0x00307000 0x001000>, /* ap 97 */
+ <0x00008000 0x00308000 0x001000>, /* ap 98 */
+ <0x00009000 0x00309000 0x001000>, /* ap 99 */
+ <0x0000a000 0x0030a000 0x001000>, /* ap 100 */
+ <0x0000b000 0x0030b000 0x001000>, /* ap 101 */
+ <0x0003d000 0x0033d000 0x001000>, /* ap 102 */
+ <0x0003e000 0x0033e000 0x001000>, /* ap 103 */
+ <0x0003f000 0x0033f000 0x001000>, /* ap 104 */
+ <0x00040000 0x00340000 0x001000>, /* ap 105 */
+ <0x00041000 0x00341000 0x001000>, /* ap 106 */
+ <0x00042000 0x00342000 0x001000>, /* ap 107 */
+ <0x00045000 0x00345000 0x001000>, /* ap 108 */
+ <0x00046000 0x00346000 0x001000>, /* ap 109 */
+ <0x00047000 0x00347000 0x001000>, /* ap 110 */
+ <0x00048000 0x00348000 0x001000>, /* ap 111 */
+ <0x000f2000 0x003f2000 0x002000>, /* ap 112 */
+ <0x000f4000 0x003f4000 0x001000>, /* ap 113 */
+ <0x0004c000 0x0034c000 0x002000>, /* ap 114 */
+ <0x0004e000 0x0034e000 0x001000>, /* ap 115 */
+ <0x00022000 0x00322000 0x001000>, /* ap 116 */
+ <0x00023000 0x00323000 0x001000>, /* ap 117 */
+ <0x000f0000 0x003f0000 0x001000>, /* ap 118 */
+ <0x0002a400 0x0032a400 0x000400>, /* ap 119 */
+ <0x0002a800 0x0032a800 0x000400>, /* ap 120 */
+ <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */
+ <0x0002b000 0x0032b000 0x001000>, /* ap 122 */
+ <0x00080000 0x00380000 0x020000>, /* ap 123 */
+ <0x000a0000 0x003a0000 0x001000>, /* ap 124 */
+ <0x000a8000 0x003a8000 0x008000>, /* ap 125 */
+ <0x000b0000 0x003b0000 0x001000>, /* ap 126 */
+ <0x000c0000 0x003c0000 0x020000>, /* ap 127 */
+ <0x000e0000 0x003e0000 0x001000>, /* ap 128 */
+ <0x000e8000 0x003e8000 0x008000>; /* ap 129 */
+
+ target-module@0 { /* 0x48300000, ap 56 40.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss0";
+ reg = <0x0 0x4>,
+ <0x4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ epwmss0: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ecap0: ecap@100 {
+ compatible = "ti,am4372-ecap",
+ "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ehrpwm0: pwm@200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@2000 { /* 0x48302000, ap 58 4a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss1";
+ reg = <0x2000 0x4>,
+ <0x2004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ epwmss1: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ecap1: ecap@100 {
+ compatible = "ti,am4372-ecap",
+ "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ehrpwm1: pwm@200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@4000 { /* 0x48304000, ap 60 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss2";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ epwmss2: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ecap2: ecap@100 {
+ compatible = "ti,am4372-ecap",
+ "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ehrpwm2: pwm@200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@6000 { /* 0x48306000, ap 96 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss3";
+ reg = <0x6000 0x4>,
+ <0x6004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x1000>;
+
+ epwmss3: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ehrpwm3: pwm@200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x48308000, ap 98 54.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss4";
+ reg = <0x8000 0x4>,
+ <0x8004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+
+ epwmss4: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ehrpwm4: pwm@48308200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@a000 { /* 0x4830a000, ap 100 60.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "epwmss5";
+ reg = <0xa000 0x4>,
+ <0xa004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+
+ epwmss5: epwmss@0 {
+ compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000>;
+ status = "disabled";
+
+ ehrpwm5: pwm@200 {
+ compatible = "ti,am4372-ehrpwm",
+ "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@10000 { /* 0x48310000, ap 64 4e.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "rng";
+ reg = <0x11fe0 0x4>,
+ <0x11fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@13000 { /* 0x48313000, ap 90 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x13000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x48318000, ap 62 4c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x4000>;
+ };
+
+ target-module@20000 { /* 0x48320000, ap 82 34.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio5";
+ reg = <0x20000 0x4>,
+ <0x20010 0x4>,
+ <0x20114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@22000 { /* 0x48322000, ap 116 64.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio6";
+ reg = <0x22000 0x4>,
+ <0x22010 0x4>,
+ <0x22114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,am4372-gpio","ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ target-module@26000 { /* 0x48326000, ap 86 66.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "vpfe0";
+ reg = <0x26000 0x4>,
+ <0x26104 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+
+ vpfe0: vpfe@0 {
+ compatible = "ti,am437x-vpfe";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@28000 { /* 0x48328000, ap 75 0e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "vpfe1";
+ reg = <0x28000 0x4>,
+ <0x28104 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+
+ vpfe1: vpfe@0 {
+ compatible = "ti,am437x-vpfe";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "dss_core";
+ reg = <0x2a000 0x4>,
+ <0x2a010 0x4>,
+ <0x2a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, dss_clkdm */
+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x0002a000 0x00000400>,
+ <0x00000400 0x0002a400 0x00000400>,
+ <0x00000800 0x0002a800 0x00000400>,
+ <0x00000c00 0x0002ac00 0x00000400>,
+ <0x00001000 0x0002b000 0x00001000>;
+ };
+
+ target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer9";
+ reg = <0x3d000 0x4>,
+ <0x3d010 0x4>,
+ <0x3d014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3d000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer10";
+ reg = <0x3f000 0x4>,
+ <0x3f010 0x4>,
+ <0x3f014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3f000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@41000 { /* 0x48341000, ap 106 76.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer11";
+ reg = <0x41000 0x4>,
+ <0x41010 0x4>,
+ <0x41014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x41000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,am4372-timer","ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@45000 { /* 0x48345000, ap 108 6a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spi4";
+ reg = <0x45000 0x4>,
+ <0x45110 0x4>,
+ <0x45114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x45000 0x1000>;
+
+ spi4: spi@0 {
+ compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@47000 { /* 0x48347000, ap 110 70.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "hdq1w";
+ reg = <0x47000 0x4>,
+ <0x47014 0x4>,
+ <0x47018 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x47000 0x1000>;
+
+ hdq: hdq@0 {
+ compatible = "ti,am4372-hdq";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&func_12m_clk>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000 0x2000>;
+ };
+
+ target-module@80000 { /* 0x48380000, ap 123 42.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_otg_ss0";
+ reg = <0x80000 0x4>,
+ <0x80010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x20000>;
+
+ dwc3_1: omap_dwc3@0 {
+ compatible = "ti,am437x-dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <1>;
+ ranges = <0 0 0x20000>;
+
+ usb1: usb@10000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ status = "disabled";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+ };
+
+ target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ocp2scp0";
+ reg = <0xa8000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x8000>;
+
+ ocp2scp0: ocp2scp@0 {
+ compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x8000>;
+
+ usb2_phy1: phy@8000 {
+ compatible = "ti,am437x-usb2";
+ reg = <0x0 0x8000>;
+ syscon-phy-power = <&scm_conf 0x620>;
+ clocks = <&usb_phy0_always_on_clk32k>,
+ <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "usb_otg_ss1";
+ reg = <0xc0000 0x4>,
+ <0xc0010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000 0x20000>;
+
+ dwc3_2: omap_dwc3@0 {
+ compatible = "ti,am437x-dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <1>;
+ ranges = <0 0 0x20000>;
+
+ usb2: usb@10000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ phys = <&usb2_phy2>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ status = "disabled";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+ };
+
+ target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "ocp2scp1";
+ reg = <0xe8000 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe8000 0x8000>;
+
+ ocp2scp1: ocp2scp@0 {
+ compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x8000>;
+
+ usb2_phy2: phy@8000 {
+ compatible = "ti,am437x-usb2";
+ reg = <0x0 0x8000>;
+ syscon-phy-power = <&scm_conf 0x628>;
+ clocks = <&usb_phy1_always_on_clk32k>,
+ <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>;
+ clock-names = "wkupclk", "refclk";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf2000 0x2000>;
+ };
+ };
+};
+
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index a7037a4b4fd4..e3f420793c12 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -710,73 +710,123 @@
};
&prcm {
- l4_wkup_cm: l4_wkup_cm@2800 {
+ wkup_cm: wkup-cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
- l4_wkup_clkctrl: clk@20 {
+ l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
compatible = "ti,clkctrl";
- reg = <0x20 0x34c>;
+ reg = <0x120 0x4>;
#clock-cells = <2>;
};
+
+ l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
+ compatible = "ti,clkctrl";
+ reg = <0x228 0xc>;
+ #clock-cells = <2>;
+ };
+
+ l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
+ compatible = "ti,clkctrl";
+ reg = <0x220 0x4>, <0x328 0x44>;
+ #clock-cells = <2>;
+ };
+
};
- mpu_cm: mpu_cm@8300 {
+ mpu_cm: mpu-cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
- mpu_clkctrl: clk@20 {
+ mpu_clkctrl: mpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx_l3_cm@8400 {
+ gfx_l3_cm: gfx-l3-cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
- gfx_l3_clkctrl: clk@20 {
+ gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4_rtc_cm@8500 {
+ l4_rtc_cm: l4-rtc-cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
- l4_rtc_clkctrl: clk@20 {
+ l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l4_per_cm: l4_per_cm@8800 {
+ per_cm: per-cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
- l4_per_clkctrl: clk@20 {
+ l3_clkctrl: l3-clkctrl@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x3c>, <0x78 0x2c>;
+ #clock-cells = <2>;
+ };
+
+ l3s_clkctrl: l3s-clkctrl@68 {
+ compatible = "ti,clkctrl";
+ reg = <0x68 0xc>, <0x220 0x4c>;
+ #clock-cells = <2>;
+ };
+
+ pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
compatible = "ti,clkctrl";
- reg = <0x20 0xb04>;
+ reg = <0x320 0x4>;
#clock-cells = <2>;
};
+
+ l4ls_clkctrl: l4ls-clkctrl@420 {
+ compatible = "ti,clkctrl";
+ reg = <0x420 0x1a4>;
+ #clock-cells = <2>;
+ };
+
+ emif_clkctrl: emif-clkctrl@720 {
+ compatible = "ti,clkctrl";
+ reg = <0x720 0x4>;
+ #clock-cells = <2>;
+ };
+
+ dss_clkctrl: dss-clkctrl@a20 {
+ compatible = "ti,clkctrl";
+ reg = <0xa20 0x4>;
+ #clock-cells = <2>;
+ };
+
+ cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
+ compatible = "ti,clkctrl";
+ reg = <0xb20 0x4>;
+ #clock-cells = <2>;
+ };
+
};
};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index ad953113cefb..1e6620f139dd 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -555,7 +555,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
+ assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index a5676697ff3b..916a97734f84 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -44,7 +44,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@@ -52,7 +52,7 @@
regulator-boot-on;
};
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
@@ -567,4 +567,3 @@
};
};
};
-
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
index df1227613d48..c2ece0b91885 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
@@ -13,7 +13,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
new file mode 100644
index 000000000000..9f194b5eeba4
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2018 Facebook Inc.
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ model = "Facebook Backpack CMM BMC";
+ compatible = "facebook,cmm-bmc", "aspeed,ast2500";
+
+ aliases {
+ /*
+ * Override the default uart aliases to avoid breaking
+ * the legacy applications.
+ */
+ serial0 = &uart5;
+ serial1 = &uart1;
+ serial2 = &uart3;
+ serial3 = &uart4;
+
+ /*
+ * Hardcode the bus number of i2c switches' channels to
+ * avoid breaking the legacy applications.
+ */
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
+ i2c38 = &imux38;
+ i2c39 = &imux39;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+/*
+ * Update reset type to "system" (full chip) to fix warm reboot hang issue
+ * when reset type is set to default ("soc", gated by reset mask registers).
+ */
+&wdt1 {
+ status = "okay";
+ aspeed,reset-type = "system";
+};
+
+/*
+ * wdt2 is not used by Backpack CMM.
+ */
+&wdt2 {
+ status = "disabled";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+#include "facebook-bmc-flash-layout.dtsi"
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_nrts1_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default
+ &pinctrl_ncts3_default
+ &pinctrl_ndcd3_default
+ &pinctrl_nri3_default>;
+};
+
+&uart4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default
+ &pinctrl_rxd4_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac1 {
+ status = "okay";
+ no-hw-checksum;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+/*
+ * I2C bus reserved for communication with COM-E.
+ */
+&i2c0 {
+ status = "okay";
+};
+
+/*
+ * I2C bus to Line Cards and Fabric Cards.
+ */
+&i2c1 {
+ status = "okay";
+
+ i2c-switch@77 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+
+ imux16: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux17: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux18: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux19: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux20: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux21: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux22: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux23: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/*
+ * I2C bus to Power Distribution Board.
+ */
+&i2c2 {
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ imux24: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux25: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux26: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux27: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux28: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux29: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux30: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux31: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/*
+ * I2c bus connected with temperature sensors on CMM.
+ */
+&i2c3 {
+ status = "okay";
+};
+
+/*
+ * I2C bus reserved for communication with COM-E.
+ */
+&i2c4 {
+ status = "okay";
+};
+
+/*
+ * I2c bus connected with ADM1278.
+ */
+&i2c5 {
+ status = "okay";
+};
+
+/*
+ * I2c bus connected with I/O Expander.
+ */
+&i2c6 {
+ status = "okay";
+};
+
+/*
+ * I2c bus connected with I/O Expander and EPROMs.
+ */
+&i2c7 {
+ status = "okay";
+};
+
+/*
+ * I2C bus to Fan Control Board.
+ */
+&i2c8 {
+ status = "okay";
+
+ i2c-switch@77 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x77>;
+
+ imux32: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux33: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux34: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux35: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux36: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux37: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux38: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux39: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/*
+ * I2C bus to CMM CPLD.
+ */
+&i2c13 {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
index 7a291de02543..22dade6393d0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
@@ -13,7 +13,7 @@
bootargs = "earlyprintk";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
index d598b6391362..024e52a6cd0f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
@@ -14,7 +14,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@@ -322,4 +322,3 @@
&adc {
status = "okay";
};
-
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index c7084a819dc6..9aa1d4467453 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -26,6 +26,16 @@
no-map;
reg = <0x5f000000 0x01000000>; /* 16M */
};
+
+ coldfire_memory: codefire_memory@5ee00000 {
+ reg = <0x5ee00000 0x00200000>;
+ no-map;
+ };
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x01000000>; /* 16MB */
+ };
};
leds {
@@ -44,6 +54,22 @@
};
};
+ fsi: gpio-fsi {
+ compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ memory-region = <&coldfire_memory>;
+ aspeed,sram = <&sram>;
+ aspeed,cvic = <&cvic>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -169,6 +195,12 @@
status = "okay";
};
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+};
+
&gpio {
pin_func_mode0 {
gpio-hog;
@@ -303,13 +335,6 @@
line-name = "SYS_PWROK_BMC";
};
- pin_gpio_h6 {
- gpio-hog;
- gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "SCM1_FSI0_DATA_EN";
- };
-
pin_gpio_h7 {
gpio-hog;
gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 7d28c03a9e0b..76fe994f2ba4 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -30,6 +30,11 @@
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
+
+ coldfire_memory: codefire_memory@9ef00000 {
+ reg = <0x9ef00000 0x00100000>;
+ no-map;
+ };
};
leds {
@@ -49,11 +54,15 @@
};
fsi: gpio-fsi {
- compatible = "fsi-master-gpio", "fsi-master";
+ compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
no-gpio-delays;
+ memory-region = <&coldfire_memory>;
+ aspeed,sram = <&sram>;
+ aspeed,cvic = <&cvic>;
+
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
@@ -76,6 +85,11 @@
linux,code = <ASPEED_GPIO(Q, 7)>;
};
};
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
};
&fmc {
@@ -274,3 +288,11 @@
&ibt {
status = "okay";
};
+
+&vhub {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 656036106001..ad54117c075e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -56,6 +56,11 @@
};
};
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@@ -583,3 +588,7 @@
&ibt {
status = "okay";
};
+
+&adc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
index 43ed13963d35..33d704541de6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
@@ -17,7 +17,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index 911d2c7c1500..0f6d335125e2 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -60,6 +60,8 @@
power-supply = <&bl_reg>;
enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_blon>;
};
panel: panel {
@@ -164,6 +166,12 @@
(AT91_PINCTRL_OUTPUT |
AT91_PINCTRL_OUTPUT_VAL(0))>;
};
+
+ pinctrl_blon: blon {
+ atmel,pins = <AT91_PIOA 20 AT91_PERIPH_GPIO
+ (AT91_PINCTRL_OUTPUT |
+ AT91_PINCTRL_OUTPUT_VAL(0))>;
+ };
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 363a43d77424..4a258867ddf1 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -165,7 +165,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
atmel,fifo-size = <16>;
@@ -211,7 +211,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@@ -223,7 +223,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@@ -240,7 +240,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
@@ -252,7 +252,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
@@ -268,7 +268,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 2214bfe7aa20..ba7f3e646c26 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -197,7 +197,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 518e2b095ccf..fa54e8866f1e 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -258,7 +258,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&flx0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
@@ -313,7 +313,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&flx4_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 0702a2f2b336..12d5af938aa3 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -115,7 +115,7 @@
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck2>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 10>;
clock-names = "mclk";
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 9118e29b6d6a..7cd9c3bc4dfb 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -113,276 +113,28 @@
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9260-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc>, <&slow_xtal>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
- <150000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 105000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- reg = <11>;
- #clock-cells = <0>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- tc3_clk: tc3_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- tc4_clk: tc4_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- tc5_clk: tc5_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fffa0000 {
@@ -393,7 +145,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -405,7 +157,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -746,7 +498,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -757,7 +509,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -768,7 +520,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -778,7 +530,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -791,7 +543,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -804,7 +556,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -817,7 +569,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -830,7 +582,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
status = "disabled";
};
@@ -843,7 +595,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "usart";
status = "disabled";
};
@@ -856,7 +608,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "usart";
status = "disabled";
};
@@ -867,7 +619,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -876,7 +628,7 @@
compatible = "atmel,at91sam9260-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -887,7 +639,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -898,7 +650,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -909,7 +661,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@@ -922,7 +674,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -935,7 +687,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -946,7 +698,7 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
@@ -981,7 +733,7 @@
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
status = "disabled";
};
@@ -989,7 +741,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&clk32k>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1007,7 +759,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1027,7 +779,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 33f09d5ea020..01d700b63b45 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -75,7 +75,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -86,7 +86,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&hclk1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@@ -106,7 +106,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -132,7 +132,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -140,7 +140,7 @@
compatible = "atmel,at91sam9261-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
atmel,matrix = <&matrix>;
status = "disabled";
@@ -154,7 +154,7 @@
pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -167,7 +167,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -179,7 +179,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -192,7 +192,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -205,7 +205,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -216,7 +216,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@@ -227,7 +227,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "pclk";
status = "disabled";
};
@@ -238,7 +238,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
- clocks = <&ssc2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -252,7 +252,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -265,7 +265,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -299,7 +299,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -563,7 +563,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -574,7 +574,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -585,7 +585,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -593,250 +593,9 @@
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 94000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
-
- prog3: prog3 {
- #clock-cells = <0>;
- reg = <3>;
- interrupts = <AT91_PMC_PCKRDY(3)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- pck3: pck3 {
- #clock-cells = <0>;
- reg = <11>;
- clocks = <&prog3>;
- };
-
- hclk0: hclk0 {
- #clock-cells = <0>;
- reg = <16>;
- clocks = <&mck>;
- };
-
- hclk1: hclk1 {
- #clock-cells = <0>;
- reg = <17>;
- clocks = <&mck>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- reg = <11>;
- #clock-cells = <0>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc2_clk: ssc2_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
@@ -855,7 +614,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
rtc@fffffd20 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index af68a86c9973..c5766da4e54e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -96,264 +96,9 @@
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
- <190000000 240000000 2 1>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 120000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 4 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
-
- prog3: prog3 {
- #clock-cells = <0>;
- reg = <3>;
- interrupts = <AT91_PMC_PCKRDY(3)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- pck3: pck3 {
- #clock-cells = <0>;
- reg = <11>;
- clocks = <&prog3>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioCDE_clk: pioCDE_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- can_clk: can_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- twi0_clk: twi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- ac97_clk: ac97_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tcb_clk: tcb_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- g2de_clk: g2de_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- dma_clk: dma_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
ramc0: ramc@ffffe200 {
@@ -385,7 +130,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fff7c000 {
@@ -394,7 +139,7 @@
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
@@ -736,7 +481,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff400 {
@@ -747,7 +492,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff600 {
@@ -758,7 +503,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffff800 {
@@ -769,7 +514,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioE: gpio@fffffa00 {
@@ -780,7 +525,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@@ -790,7 +535,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -803,7 +548,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -816,7 +561,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -829,7 +574,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -840,7 +585,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -851,7 +596,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "pclk";
status = "disabled";
};
@@ -862,7 +607,7 @@
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ac97>;
- clocks = <&ac97_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
clock-names = "ac97_clk";
status = "disabled";
};
@@ -873,7 +618,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -882,7 +627,7 @@
compatible = "atmel,at91sam9263-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -893,7 +638,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
status = "disabled";
};
@@ -904,7 +649,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -916,7 +661,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -940,7 +685,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -953,7 +698,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -963,7 +708,7 @@
reg = <0xfffb8000 0x300>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "pwm_clk";
status = "disabled";
};
@@ -974,7 +719,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_rx_tx>;
- clocks = <&can_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "can_clk";
};
@@ -1007,7 +752,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&lcd_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@@ -1016,7 +761,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1034,7 +779,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller0: nand-controller {
@@ -1055,7 +800,7 @@
reg = <0x80000000 0x20000000>;
ranges = <0x0 0x0 0x80000000 0x10000000
0x1 0x0 0x90000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller1: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index 27de7dc0f0e0..b34a6c65bd44 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -24,6 +24,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 90705ee6008b..e976fd6bc6fd 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -40,28 +40,7 @@
};
pmc: pmc@fffffc00 {
- plla: pllack {
- atmel,clk-input-range = <2000000 32000000>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
- <695000000 750000000 1 0>,
- <645000000 700000000 2 0>,
- <595000000 650000000 3 0>,
- <545000000 600000000 0 1>,
- <495000000 550000000 1 1>,
- <445000000 500000000 2 1>,
- <400000000 450000000 3 1>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91sam9g20-clk-pllb";
- atmel,clk-input-range = <2000000 32000000>;
- atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
- };
-
- mck: masterck {
- atmel,clk-output-range = <0 133000000>;
- atmel,clk-divisors = <1 2 4 6>;
- };
+ compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 0898213f3bb2..d8bb56253e64 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 31fecc2cdaf9..ac730812a81d 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,9 +32,9 @@
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
- clocks = <&pck0>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "xvclk";
- assigned-clocks = <&pck0>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <25000000>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index ff4115886f97..333e158feb61 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -25,6 +25,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 8fb22030f00b..3862ff2f26e0 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -88,7 +88,7 @@
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&lcd_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "lcdc_clk";
status = "disabled";
};
@@ -106,7 +106,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -132,7 +132,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -143,7 +143,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -154,7 +154,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -175,7 +175,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -188,7 +188,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -201,7 +201,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -214,7 +214,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -242,7 +242,7 @@
reg = <0xfffc8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "pwm_clk";
status = "disabled";
};
@@ -255,7 +255,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -266,7 +266,7 @@
compatible = "atmel,at91sam9rl-adc";
reg = <0xfffd0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0x3f>;
@@ -304,7 +304,7 @@
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
@@ -366,7 +366,7 @@
reg = <0xffffe600 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@@ -399,7 +399,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -794,7 +794,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -805,7 +805,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -816,7 +816,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
@@ -827,7 +827,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
};
@@ -835,202 +835,9 @@
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <3>;
- atmel,pll-clk-output-ranges = <80000000 200000000 0>,
- <190000000 240000000 2>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
- atmel,clk-output-range = <0 94000000>;
- atmel,clk-divisors = <1 2 4 0>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- pioD_clk: pioD_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi0_clk: twi0_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
@@ -1049,7 +856,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
watchdog@fffffd40 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 3c5fa3388997..a99703a262c9 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -27,6 +27,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index d9054e8167b7..bca274d33f68 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 11c0ef102ab1..07443a387a8f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -111,7 +111,7 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&ddrck>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
@@ -124,269 +124,9 @@
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <50000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc>, <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0
- 695000000 750000000 1 0
- 645000000 700000000 2 0
- 595000000 650000000 3 0
- 545000000 600000000 0 1
- 495000000 555000000 1 1
- 445000000 500000000 2 1
- 400000000 450000000 3 1>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <0 133333333>;
- atmel,clk-divisors = <1 2 4 3>;
- atmel,master-clk-have-div3-pres;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- smd: smdclk {
- compatible = "atmel,at91sam9x5-clk-smd";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- smdck: smdck {
- #clock-cells = <0>;
- reg = <4>;
- clocks = <&smd>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioAB_clk: pioAB_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioCD_clk: pioCD_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- smd_clk: smd_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- twi0_clk: twi0_clk {
- reg = <9>;
- #clock-cells = <0>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- twi2_clk: twi2_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- dma1_clk: dma1_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
@@ -405,7 +145,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
sckc@fffffe50 {
@@ -438,7 +178,7 @@
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -448,7 +188,7 @@
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -457,7 +197,7 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "dma_clk";
};
@@ -466,7 +206,7 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@@ -864,7 +604,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -876,7 +616,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioC: gpio@fffff800 {
@@ -887,7 +627,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioD: gpio@fffffa00 {
@@ -899,7 +639,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
};
@@ -912,7 +652,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "pclk";
status = "disabled";
};
@@ -924,7 +664,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@@ -938,7 +678,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@@ -954,7 +694,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -968,7 +708,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "usart";
status = "disabled";
};
@@ -982,7 +722,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -996,7 +736,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -1012,7 +752,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
status = "disabled";
};
@@ -1027,7 +767,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
status = "disabled";
};
@@ -1042,7 +782,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&twi2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@@ -1052,7 +792,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "usart";
status = "disabled";
};
@@ -1063,7 +803,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
@@ -1074,7 +814,7 @@
compatible = "atmel,at91sam9x5-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>,
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
@@ -1121,7 +861,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1137,7 +877,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1149,7 +889,7 @@
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&utmi>, <&udphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "pclk";
status = "disabled";
@@ -1229,7 +969,7 @@
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -1239,7 +979,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1248,7 +988,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -1266,7 +1006,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index 8eb2f9c1b978..125f9e3b49ad 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -13,27 +13,13 @@
/ {
ahb {
apb {
- pmc: pmc@fffffc00 {
- periphck {
- can0_clk: can0_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
- };
- };
-
can0: can@f8000000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
- clocks = <&can0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "can_clk";
status = "disabled";
};
@@ -44,7 +30,7 @@
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
- clocks = <&can1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "can_clk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
index 8fc45ca4dcb5..c3e45b57b6a2 100644
--- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -44,22 +44,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
- };
- };
-
isi: isi@f8048000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
- clocks = <&isi_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "isi_clk";
status = "disabled";
port {
diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
index 1629db9dd563..12595fb11691 100644
--- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
@@ -17,7 +17,7 @@
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@@ -143,23 +143,6 @@
};
};
};
-
- pmc: pmc@fffffc00 {
- periphck {
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
- };
-
- systemck {
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
index 73d7e30965ba..57c2e5a4fb53 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -43,22 +43,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
- };
- };
-
macb0: ethernet@f802c000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
index d81980c40c7d..59b8da87d3c1 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -31,22 +31,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- macb1_clk: macb1_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
- };
- };
-
macb1: ethernet@f8030000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
- clocks = <&macb1_clk>, <&macb1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index a32d12b406a3..9102dfbed5d8 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -42,15 +42,6 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
- };
- };
-
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
@@ -60,7 +51,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index 043c717dcef1..bd83962d3627 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -48,6 +48,11 @@
interrupt-controller;
#interrupt-cells = <1>;
+ ac_power_supply: ac-power-supply {
+ compatible = "x-powers,axp813-ac-power-supply";
+ status = "disabled";
+ };
+
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 2fd111d9d59c..0d2538b46139 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -41,6 +41,14 @@
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = &amac0;
+ ethernet1 = &amac1;
+ ethernet2 = &amac2;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index b7f79f1c431a..644d907bafbb 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 70362405c595..00323ba8f7de 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Stefan Wahren <stefan.wahren@i2se.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index cb2d6d78a7fb..29f970f864dc 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -30,9 +30,9 @@
#power-domain-cells = <1>;
};
- mailbox@7e00b840 {
+ vchiq: mailbox@7e00b840 {
compatible = "brcm,bcm2835-vchiq";
- reg = <0x7e00b840 0xf>;
+ reg = <0x7e00b840 0x3c>;
interrupts = <0 2>;
};
};
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index 2fef70a09953..ac4408b34b58 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2836.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/bcm2836-rpi.dtsi
new file mode 100644
index 000000000000..c4c858b984c6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2836-rpi.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm2835-rpi.dtsi"
+
+&vchiq {
+ compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq";
+};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index 93762244be7f..42bb09044cc7 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 89e6fd547c75..0c155dd4f396 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
index 7b7ab6aea988..4a89a1885a3d 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2836-rpi.dtsi"
/ {
memory {
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
new file mode 100644
index 000000000000..babcfec50dde
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
+ * Copyright (C) 2018 Rene Kjellerup <rk.katana.steel@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "linksys,ea6500-v2", "brcm,bcm4708";
+ model = "Linksys EA6500 V2";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&usb3_phy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi
index 9829d044aaf4..ed13af028528 100644
--- a/arch/arm/boot/dts/bcm47081.dtsi
+++ b/arch/arm/boot/dts/bcm47081.dtsi
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for BCM47081 SoC.
*
* Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
*/
#include "bcm5301x.dtsi"
diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi
index c645fea2b7f7..e1bb8661955f 100644
--- a/arch/arm/boot/dts/bcm4709.dtsi
+++ b/arch/arm/boot/dts/bcm4709.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
- *
- * Licensed under the ISC license.
*/
#include "bcm4708.dtsi"
diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
index f7c3e274b354..cdc5ff593adb 100644
--- a/arch/arm/boot/dts/bcm47094.dtsi
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
- *
- * Licensed under the ISC license.
*/
#include "bcm4708.dtsi"
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index 19e61b5b066c..e15e2a1e9d8c 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
- *
- * Licensed under the ISC license.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 7a5c188c2676..fd7af943fb0b 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -37,6 +37,8 @@
reg = <0x0400 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_uart1>;
status = "disabled";
};
};
@@ -391,6 +393,48 @@
status = "disabled";
};
+ dmu@1800c000 {
+ compatible = "simple-bus";
+ ranges = <0 0x1800c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cru@100 {
+ compatible = "simple-bus";
+ reg = <0x100 0x1a4>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pin-controller@1c0 {
+ compatible = "brcm,bcm4708-pinmux";
+ reg = <0x1c0 0x24>;
+ reg-names = "cru_gpio_control";
+
+ spi-pins {
+ groups = "spi_grp";
+ function = "spi";
+ };
+
+ i2c {
+ groups = "i2c_grp";
+ function = "i2c";
+ };
+
+ pwm {
+ groups = "pwm0_grp", "pwm1_grp",
+ "pwm2_grp", "pwm3_grp";
+ function = "pwm";
+ };
+
+ pinmux_uart1: uart1 {
+ groups = "uart1_grp";
+ function = "uart1";
+ };
+ };
+ };
+ };
+
lcpll0: lcpll0@1800c100 {
#clock-cells = <1>;
compatible = "brcm,nsp-lcpll0";
diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
index 453a2a37dabd..5054fa9eb0d0 100644
--- a/arch/arm/boot/dts/bcm53573.dtsi
+++ b/arch/arm/boot/dts/bcm53573.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
- *
- * Licensed under the ISC license.
*/
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 6df61518776f..f59764008b9c 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -143,6 +143,37 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
+
+ ahci: sata@8000 {
+ compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0xa000 0x9ac>, <0x8040 0x24>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&pmb0 3 1>;
+ reset-names = "ahci";
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy0>;
+ };
+ };
+
+ sata_phy: sata-phy@8100 {
+ compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
+ reg = <0x8100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
/* Legacy UBUS base */
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index f9dd342cc2ae..21479b4ce823 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958522ER)";
compatible = "brcm,bcm58522", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index 374508a9cfbf..cda3d790965b 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958525ER)";
compatible = "brcm,bcm58525", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 403250c5ad8e..f86649812b59 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus XMC (BCM958525xmc)";
compatible = "brcm,bcm58525", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index ecd05e26c262..df60602b054d 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958622HR)";
compatible = "brcm,bcm58622", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index f5e85b301497..3893e7af343a 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958623HR)";
compatible = "brcm,bcm58623", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index a53a2f629d74..cf226b02141f 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958625HR)";
compatible = "brcm,bcm58625", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 3ea5f739e90b..10b3d512bb33 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -38,11 +38,6 @@
model = "NorthStar Plus SVK (BCM958625K)";
compatible = "brcm,bcm58625", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
index c61673638fa8..8dca97eeaf57 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -41,3 +41,11 @@
brcm,nand-oob-sectors-size = <16>;
};
};
+
+&ahci {
+ status = "okay";
+};
+
+&sata_phy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index ea9a0806b446..e39db14d805e 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM988312HR)";
compatible = "brcm,bcm88312", "brcm,nsp";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
index 7e18147dc563..0d6f8647cc91 100644
--- a/arch/arm/boot/dts/dra7-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -214,7 +214,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
+ <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@@ -232,7 +232,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
+ assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
new file mode 100644
index 000000000000..bb45cb7fc3b6
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -0,0 +1,4600 @@
+&l4_cfg { /* 0x4a000000 */
+ compatible = "ti,dra7-l4-cfg", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x1000>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
+ <0x00100000 0x4a100000 0x100000>, /* segment 1 */
+ <0x00200000 0x4a200000 0x100000>; /* segment 2 */
+
+ segment@0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x001000>, /* ap 2 */
+ <0x00002000 0x00002000 0x002000>, /* ap 3 */
+ <0x00004000 0x00004000 0x001000>, /* ap 4 */
+ <0x00005000 0x00005000 0x001000>, /* ap 5 */
+ <0x00006000 0x00006000 0x001000>, /* ap 6 */
+ <0x00008000 0x00008000 0x002000>, /* ap 7 */
+ <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
+ <0x00056000 0x00056000 0x001000>, /* ap 9 */
+ <0x00057000 0x00057000 0x001000>, /* ap 10 */
+ <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
+ <0x00060000 0x00060000 0x001000>, /* ap 12 */
+ <0x00080000 0x00080000 0x008000>, /* ap 13 */
+ <0x00088000 0x00088000 0x001000>, /* ap 14 */
+ <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
+ <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
+ <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
+ <0x000da000 0x000da000 0x001000>, /* ap 18 */
+ <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
+ <0x000de000 0x000de000 0x001000>, /* ap 20 */
+ <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
+ <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
+ <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
+ <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
+ <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
+ <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
+ <0x00090000 0x00090000 0x008000>, /* ap 59 */
+ <0x00098000 0x00098000 0x001000>; /* ap 60 */
+
+ target-module@2000 { /* 0x4a002000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x2000>;
+
+ scm: scm@0 {
+ compatible = "ti,dra7-scm-core", "simple-bus";
+ reg = <0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x1400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x1400>;
+
+ pbias_regulator: pbias_regulator@e00 {
+ compatible = "ti,pbias-dra7", "ti,pbias-omap";
+ reg = <0xe00 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ scm_conf_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ phy_sel: cpsw-phy-sel@554 {
+ compatible = "ti,dra7xx-cpsw-phy-sel";
+ reg= <0x554 0x4>;
+ reg-names = "gmii-sel";
+ };
+
+ dra7_pmx_core: pinmux@1400 {
+ compatible = "ti,dra7-padconf",
+ "pinctrl-single";
+ reg = <0x1400 0x0468>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ scm_conf1: scm_conf@1c04 {
+ compatible = "syscon";
+ reg = <0x1c04 0x0020>;
+ #syscon-cells = <2>;
+ };
+
+ scm_conf_pcie: scm_conf@1c24 {
+ compatible = "syscon";
+ reg = <0x1c24 0x0024>;
+ };
+
+ sdma_xbar: dma-router@b78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xb78 0xfc>;
+ #dma-cells = <1>;
+ dma-requests = <205>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&sdma>;
+ };
+
+ edma_xbar: dma-router@c78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xc78 0x7c>;
+ #dma-cells = <2>;
+ dma-requests = <204>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&edma>;
+ };
+ };
+ };
+
+ target-module@5000 { /* 0x4a005000, ap 5 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5000 0x1000>;
+
+ cm_core_aon: cm_core_aon@0 {
+ compatible = "ti,dra7-cm-core-aon",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2000>;
+ ranges = <0 0 0x2000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x8000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x2000>;
+
+ cm_core: cm_core@0 {
+ compatible = "ti,dra7-cm-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x3000>;
+ ranges = <0 0 0x3000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module@56000 { /* 0x4a056000, ap 9 02.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "dma_system";
+ reg = <0x56000 0x4>,
+ <0x5602c 0x4>,
+ <0x56028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): core_pwrdm, dma_clkdm */
+ clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x56000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+ };
+
+ target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5e000 0x2000>;
+ };
+
+ target-module@80000 { /* 0x4a080000, ap 13 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "ocp2scp1";
+ reg = <0x80000 0x4>,
+ <0x80010 0x4>,
+ <0x80014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x8000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x8000>;
+ reg = <0x0 0x20>;
+
+ usb2_phy1: phy@4000 {
+ compatible = "ti,dra7x-usb2", "ti,omap-usb2";
+ reg = <0x4000 0x400>;
+ syscon-phy-power = <&scm_conf 0x300>;
+ clocks = <&usb_phy1_always_on_clk32k>,
+ <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy2: phy@5000 {
+ compatible = "ti,dra7x-usb2-phy2",
+ "ti,omap-usb2";
+ reg = <0x5000 0x400>;
+ syscon-phy-power = <&scm_conf 0xe74>;
+ clocks = <&usb_phy2_always_on_clk32k>,
+ <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy1: phy@4400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4400 0x80>,
+ <0x4800 0x64>,
+ <0x4c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x370>;
+ clocks = <&usb_phy3_always_on_clk32k>,
+ <&sys_clkin1>,
+ <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ target-module@90000 { /* 0x4a090000, ap 59 42.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "ocp2scp3";
+ reg = <0x90000 0x4>,
+ <0x90010 0x4>,
+ <0x90014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x8000>;
+
+ ocp2scp@0 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x8000>;
+ reg = <0x0 0x20>;
+
+ pcie1_phy: pciephy@4000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4000 0x80>, /* phy_rx */
+ <0x4400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ syscon-phy-power = <&scm_conf_pcie 0x1c>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div", "sysclk";
+ #phy-cells = <0>;
+ };
+
+ pcie2_phy: pciephy@5000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x5000 0x80>, /* phy_rx */
+ <0x5400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ syscon-phy-power = <&scm_conf_pcie 0x20>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div", "sysclk";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ sata_phy: phy@6000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x6000 0x80>, /* phy_rx */
+ <0x6400 0x64>, /* phy_tx */
+ <0x6800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ syscon-phy-power = <&scm_conf 0x374>;
+ clocks = <&sys_clkin1>,
+ <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
+ clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x8000>;
+ };
+
+ target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ ti,hwmods = "smartreflex_mpu";
+ reg = <0xd9038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
+ clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd9000 0x1000>;
+
+ /* SmartReflex child device marked reserved in TRM */
+ };
+
+ target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
+ compatible = "ti,sysc-omap4-sr", "ti,sysc";
+ ti,hwmods = "smartreflex_core";
+ reg = <0xdd038 0x4>;
+ reg-names = "sysc";
+ ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
+ clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xdd000 0x1000>;
+
+ /* SmartReflex child device marked reserved in TRM */
+ };
+
+ target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0000 0x1000>;
+ };
+
+ target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mailbox1";
+ reg = <0xf4000 0x4>,
+ <0xf4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf4000 0x1000>;
+
+ mailbox1: mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ status = "disabled";
+ };
+ };
+
+ target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "spinlock";
+ reg = <0xf6000 0x4>,
+ <0xf6010 0x4>,
+ <0xf6014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
+ clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf6000 0x1000>;
+
+ hwspinlock: spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+
+ segment@100000 { /* 0x4a100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
+ <0x00003000 0x00103000 0x001000>, /* ap 28 */
+ <0x00008000 0x00108000 0x001000>, /* ap 29 */
+ <0x00009000 0x00109000 0x001000>, /* ap 30 */
+ <0x00040000 0x00140000 0x010000>, /* ap 31 */
+ <0x00050000 0x00150000 0x001000>, /* ap 32 */
+ <0x00051000 0x00151000 0x001000>, /* ap 33 */
+ <0x00052000 0x00152000 0x001000>, /* ap 34 */
+ <0x00053000 0x00153000 0x001000>, /* ap 35 */
+ <0x00054000 0x00154000 0x001000>, /* ap 36 */
+ <0x00055000 0x00155000 0x001000>, /* ap 37 */
+ <0x00056000 0x00156000 0x001000>, /* ap 38 */
+ <0x00057000 0x00157000 0x001000>, /* ap 39 */
+ <0x00058000 0x00158000 0x001000>, /* ap 40 */
+ <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
+ <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
+ <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
+ <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
+ <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
+ <0x00060000 0x00160000 0x001000>, /* ap 48 */
+ <0x00061000 0x00161000 0x001000>, /* ap 49 */
+ <0x00062000 0x00162000 0x001000>, /* ap 50 */
+ <0x00063000 0x00163000 0x001000>, /* ap 51 */
+ <0x00064000 0x00164000 0x001000>, /* ap 52 */
+ <0x00065000 0x00165000 0x001000>, /* ap 53 */
+ <0x00066000 0x00166000 0x001000>, /* ap 54 */
+ <0x00067000 0x00167000 0x001000>, /* ap 55 */
+ <0x00068000 0x00168000 0x001000>, /* ap 56 */
+ <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
+ <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
+ <0x00071000 0x00171000 0x001000>, /* ap 61 */
+ <0x00072000 0x00172000 0x001000>, /* ap 62 */
+ <0x00073000 0x00173000 0x001000>, /* ap 63 */
+ <0x00074000 0x00174000 0x001000>, /* ap 64 */
+ <0x00075000 0x00175000 0x001000>, /* ap 65 */
+ <0x00076000 0x00176000 0x001000>, /* ap 66 */
+ <0x00077000 0x00177000 0x001000>, /* ap 67 */
+ <0x00078000 0x00178000 0x001000>, /* ap 68 */
+ <0x00081000 0x00181000 0x001000>, /* ap 69 */
+ <0x00082000 0x00182000 0x001000>, /* ap 70 */
+ <0x00083000 0x00183000 0x001000>, /* ap 71 */
+ <0x00084000 0x00184000 0x001000>, /* ap 72 */
+ <0x00085000 0x00185000 0x001000>, /* ap 73 */
+ <0x00086000 0x00186000 0x001000>, /* ap 74 */
+ <0x00087000 0x00187000 0x001000>, /* ap 75 */
+ <0x00088000 0x00188000 0x001000>, /* ap 76 */
+ <0x00069000 0x00169000 0x001000>, /* ap 103 */
+ <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
+ <0x00079000 0x00179000 0x001000>, /* ap 105 */
+ <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
+ <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
+ <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
+ <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
+ <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
+ <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
+ <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
+ <0x00059000 0x00159000 0x001000>, /* ap 125 */
+ <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
+
+ target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+ };
+
+ target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module@40000 { /* 0x4a140000, ap 31 06.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x10000>;
+ };
+
+ target-module@51000 { /* 0x4a151000, ap 33 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x51000 0x1000>;
+ };
+
+ target-module@53000 { /* 0x4a153000, ap 35 54.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53000 0x1000>;
+ };
+
+ target-module@55000 { /* 0x4a155000, ap 37 46.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+ };
+
+ target-module@57000 { /* 0x4a157000, ap 39 58.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+ };
+
+ target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+ };
+
+ target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+ };
+
+ target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+ };
+
+ target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5f000 0x1000>;
+ };
+
+ target-module@61000 { /* 0x4a161000, ap 49 32.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x61000 0x1000>;
+ };
+
+ target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x63000 0x1000>;
+ };
+
+ target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x65000 0x1000>;
+ };
+
+ target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x67000 0x1000>;
+ };
+
+ target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x69000 0x1000>;
+ };
+
+ target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6b000 0x1000>;
+ };
+
+ target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6d000 0x1000>;
+ };
+
+ target-module@71000 { /* 0x4a171000, ap 61 48.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x71000 0x1000>;
+ };
+
+ target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x73000 0x1000>;
+ };
+
+ target-module@75000 { /* 0x4a175000, ap 65 64.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x75000 0x1000>;
+ };
+
+ target-module@77000 { /* 0x4a177000, ap 67 66.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x77000 0x1000>;
+ };
+
+ target-module@79000 { /* 0x4a179000, ap 105 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x79000 0x1000>;
+ };
+
+ target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7b000 0x1000>;
+ };
+
+ target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7d000 0x1000>;
+ };
+
+ target-module@81000 { /* 0x4a181000, ap 69 26.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x81000 0x1000>;
+ };
+
+ target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x83000 0x1000>;
+ };
+
+ target-module@85000 { /* 0x4a185000, ap 73 36.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x85000 0x1000>;
+ };
+
+ target-module@87000 { /* 0x4a187000, ap 75 74.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x87000 0x1000>;
+ };
+ };
+
+ segment@200000 { /* 0x4a200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
+ <0x00019000 0x00219000 0x001000>, /* ap 44 */
+ <0x00000000 0x00200000 0x001000>, /* ap 77 */
+ <0x00001000 0x00201000 0x001000>, /* ap 78 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
+ <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
+ <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
+ <0x00010000 0x00210000 0x001000>, /* ap 85 */
+ <0x00011000 0x00211000 0x001000>, /* ap 86 */
+ <0x00012000 0x00212000 0x001000>, /* ap 87 */
+ <0x00013000 0x00213000 0x001000>, /* ap 88 */
+ <0x00014000 0x00214000 0x001000>, /* ap 89 */
+ <0x00015000 0x00215000 0x001000>, /* ap 90 */
+ <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
+ <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
+ <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
+ <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
+ <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
+ <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
+ <0x00020000 0x00220000 0x001000>, /* ap 97 */
+ <0x00021000 0x00221000 0x001000>, /* ap 98 */
+ <0x00024000 0x00224000 0x001000>, /* ap 99 */
+ <0x00025000 0x00225000 0x001000>, /* ap 100 */
+ <0x00026000 0x00226000 0x001000>, /* ap 101 */
+ <0x00027000 0x00227000 0x001000>, /* ap 102 */
+ <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
+ <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
+ <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
+ <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
+ <0x00030000 0x00230000 0x001000>, /* ap 113 */
+ <0x00031000 0x00231000 0x001000>, /* ap 114 */
+ <0x00032000 0x00232000 0x001000>, /* ap 115 */
+ <0x00033000 0x00233000 0x001000>, /* ap 116 */
+ <0x00034000 0x00234000 0x001000>, /* ap 117 */
+ <0x00035000 0x00235000 0x001000>, /* ap 118 */
+ <0x00036000 0x00236000 0x001000>, /* ap 119 */
+ <0x00037000 0x00237000 0x001000>, /* ap 120 */
+ <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
+ <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
+
+ target-module@0 { /* 0x4a200000, ap 77 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa000 0x1000>;
+ };
+
+ target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+ };
+
+ target-module@10000 { /* 0x4a210000, ap 85 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module@12000 { /* 0x4a212000, ap 87 16.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x12000 0x1000>;
+ };
+
+ target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module@18000 { /* 0x4a218000, ap 43 12.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x1000>;
+ };
+
+ target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1c000 0x1000>;
+ };
+
+ target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e000 0x1000>;
+ };
+
+ target-module@20000 { /* 0x4a220000, ap 97 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module@24000 { /* 0x4a224000, ap 99 44.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+
+ target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+
+ target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2c000 0x1000>;
+ };
+
+ target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>;
+ };
+
+ target-module@30000 { /* 0x4a230000, ap 113 70.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+ };
+
+ target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+ };
+
+ target-module@34000 { /* 0x4a234000, ap 117 76.1 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+ };
+
+ target-module@36000 { /* 0x4a236000, ap 119 62.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+ };
+ };
+};
+
+&l4_per1 { /* 0x48000000 */
+ compatible = "ti,dra7-l4-per1", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
+ <0x00200000 0x48200000 0x200000>; /* segment 1 */
+
+ segment@0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00001000 0x00001000 0x000400>, /* ap 1 */
+ <0x00000800 0x00000800 0x000800>, /* ap 2 */
+ <0x00020000 0x00020000 0x001000>, /* ap 3 */
+ <0x00021000 0x00021000 0x001000>, /* ap 4 */
+ <0x00032000 0x00032000 0x001000>, /* ap 5 */
+ <0x00033000 0x00033000 0x001000>, /* ap 6 */
+ <0x00034000 0x00034000 0x001000>, /* ap 7 */
+ <0x00035000 0x00035000 0x001000>, /* ap 8 */
+ <0x00036000 0x00036000 0x001000>, /* ap 9 */
+ <0x00037000 0x00037000 0x001000>, /* ap 10 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
+ <0x00055000 0x00055000 0x001000>, /* ap 13 */
+ <0x00056000 0x00056000 0x001000>, /* ap 14 */
+ <0x00057000 0x00057000 0x001000>, /* ap 15 */
+ <0x00058000 0x00058000 0x001000>, /* ap 16 */
+ <0x00059000 0x00059000 0x001000>, /* ap 17 */
+ <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
+ <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
+ <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
+ <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
+ <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
+ <0x00060000 0x00060000 0x001000>, /* ap 23 */
+ <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
+ <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
+ <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
+ <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
+ <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
+ <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
+ <0x00070000 0x00070000 0x001000>, /* ap 30 */
+ <0x00071000 0x00071000 0x001000>, /* ap 31 */
+ <0x00072000 0x00072000 0x001000>, /* ap 32 */
+ <0x00073000 0x00073000 0x001000>, /* ap 33 */
+ <0x00061000 0x00061000 0x001000>, /* ap 34 */
+ <0x00053000 0x00053000 0x001000>, /* ap 35 */
+ <0x00054000 0x00054000 0x001000>, /* ap 36 */
+ <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
+ <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
+ <0x00078000 0x00078000 0x001000>, /* ap 39 */
+ <0x00079000 0x00079000 0x001000>, /* ap 40 */
+ <0x00086000 0x00086000 0x001000>, /* ap 41 */
+ <0x00087000 0x00087000 0x001000>, /* ap 42 */
+ <0x00088000 0x00088000 0x001000>, /* ap 43 */
+ <0x00089000 0x00089000 0x001000>, /* ap 44 */
+ <0x00051000 0x00051000 0x001000>, /* ap 45 */
+ <0x00052000 0x00052000 0x001000>, /* ap 46 */
+ <0x00098000 0x00098000 0x001000>, /* ap 47 */
+ <0x00099000 0x00099000 0x001000>, /* ap 48 */
+ <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
+ <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
+ <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
+ <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
+ <0x00068000 0x00068000 0x001000>, /* ap 53 */
+ <0x00069000 0x00069000 0x001000>, /* ap 54 */
+ <0x00090000 0x00090000 0x002000>, /* ap 55 */
+ <0x00092000 0x00092000 0x001000>, /* ap 56 */
+ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
+ <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
+ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
+ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
+ <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
+ <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
+ <0x00066000 0x00066000 0x001000>, /* ap 63 */
+ <0x00067000 0x00067000 0x001000>, /* ap 64 */
+ <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
+ <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
+ <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
+ <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
+ <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
+ <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
+ <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
+ <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
+ <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
+ <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
+ <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
+ <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
+ <0x00001400 0x00001400 0x000400>, /* ap 77 */
+ <0x00001800 0x00001800 0x000400>, /* ap 78 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
+ <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
+ <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
+ <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
+ <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
+ <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
+
+ target-module@20000 { /* 0x48020000, ap 3 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart3";
+ reg = <0x20050 0x4>,
+ <0x20054 0x4>,
+ <0x20058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ uart3: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@32000 { /* 0x48032000, ap 5 3e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer2";
+ reg = <0x32000 0x4>,
+ <0x32010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@34000 { /* 0x48034000, ap 7 46.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer3";
+ reg = <0x34000 0x4>,
+ <0x34010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x1000>;
+
+ timer3: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@36000 { /* 0x48036000, ap 9 4e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer4";
+ reg = <0x36000 0x4>,
+ <0x36010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x36000 0x1000>;
+
+ timer4: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer9";
+ reg = <0x3e000 0x4>,
+ <0x3e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ timer9: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@51000 { /* 0x48051000, ap 45 2e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio7";
+ reg = <0x51000 0x4>,
+ <0x51010 0x4>,
+ <0x51114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x51000 0x1000>;
+
+ gpio7: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@53000 { /* 0x48053000, ap 35 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio8";
+ reg = <0x53000 0x4>,
+ <0x53010 0x4>,
+ <0x53114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53000 0x1000>;
+
+ gpio8: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@55000 { /* 0x48055000, ap 13 0e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio2";
+ reg = <0x55000 0x4>,
+ <0x55010 0x4>,
+ <0x55114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55000 0x1000>;
+
+ gpio2: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@57000 { /* 0x48057000, ap 15 06.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio3";
+ reg = <0x57000 0x4>,
+ <0x57010 0x4>,
+ <0x57114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x57000 0x1000>;
+
+ gpio3: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@59000 { /* 0x48059000, ap 17 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio4";
+ reg = <0x59000 0x4>,
+ <0x59010 0x4>,
+ <0x59114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x59000 0x1000>;
+
+ gpio4: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio5";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>,
+ <0x5b114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ gpio5: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "gpio6";
+ reg = <0x5d000 0x4>,
+ <0x5d010 0x4>,
+ <0x5d114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
+ <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5d000 0x1000>;
+
+ gpio6: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ target-module@60000 { /* 0x48060000, ap 23 32.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c3";
+ reg = <0x60000 0x8>,
+ <0x60010 0x8>,
+ <0x60090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+
+ i2c3: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@66000 { /* 0x48066000, ap 63 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart5";
+ reg = <0x66050 0x4>,
+ <0x66054 0x4>,
+ <0x66058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x1000>;
+
+ uart5: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@68000 { /* 0x48068000, ap 53 1c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart6";
+ reg = <0x68050 0x4>,
+ <0x68054 0x4>,
+ <0x68058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
+ clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x68000 0x1000>;
+
+ uart6: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart1";
+ reg = <0x6a050 0x4>,
+ <0x6a054 0x4>,
+ <0x6a058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6a000 0x1000>;
+
+ uart1: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart2";
+ reg = <0x6c050 0x4>,
+ <0x6c054 0x4>,
+ <0x6c058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6c000 0x1000>;
+
+ uart2: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "uart4";
+ reg = <0x6e050 0x4>,
+ <0x6e054 0x4>,
+ <0x6e058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6e000 0x1000>;
+
+ uart4: serial@0 {
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@70000 { /* 0x48070000, ap 30 22.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c1";
+ reg = <0x70000 0x8>,
+ <0x70010 0x8>,
+ <0x70090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x70000 0x1000>;
+
+ i2c1: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@72000 { /* 0x48072000, ap 32 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c2";
+ reg = <0x72000 0x8>,
+ <0x72010 0x8>,
+ <0x72090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x72000 0x1000>;
+
+ i2c2: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@78000 { /* 0x48078000, ap 39 0a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "elm";
+ reg = <0x78000 0x4>,
+ <0x78010 0x4>,
+ <0x78014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x78000 0x1000>;
+
+ elm: elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0xfc0>; /* device IO registers */
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c4";
+ reg = <0x7a000 0x8>,
+ <0x7a010 0x8>,
+ <0x7a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7a000 0x1000>;
+
+ i2c4: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "i2c5";
+ reg = <0x7c000 0x8>,
+ <0x7c010 0x8>,
+ <0x7c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
+ clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7c000 0x1000>;
+
+ i2c5: i2c@0 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ target-module@86000 { /* 0x48086000, ap 41 5e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer10";
+ reg = <0x86000 0x4>,
+ <0x86010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x86000 0x1000>;
+
+ timer10: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@88000 { /* 0x48088000, ap 43 66.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ ti,hwmods = "timer11";
+ reg = <0x88000 0x4>,
+ <0x88010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x88000 0x1000>;
+
+ timer11: timer@0 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
+ clock-names = "fck";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@90000 { /* 0x48090000, ap 55 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "rng";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@98000 { /* 0x48098000, ap 47 08.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mcspi1";
+ reg = <0x98000 0x4>,
+ <0x98010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x98000 0x1000>;
+
+ mcspi1: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma_xbar 35>,
+ <&sdma_xbar 36>,
+ <&sdma_xbar 37>,
+ <&sdma_xbar 38>,
+ <&sdma_xbar 39>,
+ <&sdma_xbar 40>,
+ <&sdma_xbar 41>,
+ <&sdma_xbar 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ status = "disabled";
+ };
+ };
+
+ target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mcspi2";
+ reg = <0x9a000 0x4>,
+ <0x9a010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9a000 0x1000>;
+
+ mcspi2: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma_xbar 43>,
+ <&sdma_xbar 44>,
+ <&sdma_xbar 45>,
+ <&sdma_xbar 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+ };
+
+ target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mmc1";
+ reg = <0x9c000 0x4>,
+ <0x9c010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+
+ mmc1: mmc@0 {
+ compatible = "ti,dra7-sdhci";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ pbias-supply = <&pbias_mmc_reg>;
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-ddr-3_3v;
+ };
+ };
+
+ target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x000a4000 0x00001000>,
+ <0x00001000 0x000a5000 0x00001000>;
+ };
+
+ target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x4000>;
+ };
+
+ target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mmc3";
+ reg = <0xad000 0x4>,
+ <0xad010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xad000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,dra7-sdhci";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
+ max-frequency = <64000000>;
+ /* SDMA is not supported */
+ sdhci-caps-mask = <0x0 0x400000>;
+ };
+ };
+
+ target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ ti,hwmods = "hdq1w";
+ reg = <0xb2000 0x4>,
+ <0xb2014 0x4>,
+ <0xb2018 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb2000 0x1000>;
+
+ hdqw1w: 1w@0 {
+ compatible = "ti,omap3-1w";
+ reg = <0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mmc2";
+ reg = <0xb4000 0x4>,
+ <0xb4010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb4000 0x1000>;
+
+ mmc2: mmc@0 {
+ compatible = "ti,dra7-sdhci";
+ reg = <0x0 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ max-frequency = <192000000>;
+ /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
+ sdhci-caps-mask = <0x7 0x0>;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ mmc-ddr-3_3v;
+ };
+ };
+
+ target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ ti,hwmods = "mcspi3";
+ reg = <0xb8000 0x4>,
+ <0xb8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
+ clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb8000 0x1000>;
+
+ mcspi3: spi@0 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x0 0x200>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
+