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authorJim Mattson <jmattson@google.com>2022-03-07 17:24:52 -0800
committerPaolo Bonzini <pbonzini@redhat.com>2022-04-02 05:34:40 -0400
commit95b065bf5c431c06c68056a03a5853b660640ecc (patch)
tree9a74f619c8d4754dcc022591265018c7a68f7f09 /arch/x86/kvm/svm/pmu.c
parentdf06dae3f2a8bfb83683abf88d3dcde23fc8093d (diff)
downloadlinux-95b065bf5c431c06c68056a03a5853b660640ecc.tar.gz
KVM: x86/pmu: Use different raw event masks for AMD and Intel
The third nybble of AMD's event select overlaps with Intel's IN_TX and IN_TXCP bits. Therefore, we can't use AMD64_RAW_EVENT_MASK on Intel platforms that support TSX. Declare a raw_event_mask in the kvm_pmu structure, initialize it in the vendor-specific pmu_refresh() functions, and use that mask for PERF_TYPE_RAW configurations in reprogram_gp_counter(). Fixes: 710c47651431 ("KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for PERF_TYPE_RAW") Signed-off-by: Jim Mattson <jmattson@google.com> Message-Id: <20220308012452.3468611-1-jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/svm/pmu.c')
-rw-r--r--arch/x86/kvm/svm/pmu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index d4de52409335..e4163f75c11b 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -284,6 +284,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
pmu->reserved_bits = 0xfffffff000280000ull;
+ pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;
pmu->version = 1;
/* not applicable to AMD; but clean them to prevent any fall out */
pmu->counter_bitmask[KVM_PMC_FIXED] = 0;