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authorKan Liang <kan.liang@linux.intel.com>2020-01-28 10:31:19 -0800
committerIngo Molnar <mingo@kernel.org>2020-02-11 13:17:50 +0100
commit0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 (patch)
treef20e489f58d062ea1a8c7b8e7484639fa961f07c /arch/x86/events
parentecf71fbccb9ac5cb964eb7de59bb9da3755b7885 (diff)
downloadlinux-0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832.tar.gz
perf/x86/msr: Add Tremont support
Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also supported. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
-rw-r--r--arch/x86/events/msr.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 6f86650b3f77..a949f6f55991 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ATOM_GOLDMONT:
case INTEL_FAM6_ATOM_GOLDMONT_D:
-
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
+ case INTEL_FAM6_ATOM_TREMONT_D:
+ case INTEL_FAM6_ATOM_TREMONT:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM: