aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv
diff options
context:
space:
mode:
authorZihao Yu <yuzihao@ict.ac.cn>2021-03-17 16:17:25 +0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2021-04-01 21:37:05 -0700
commitac8d0b901f0033b783156ab2dc1a0e73ec42409b (patch)
treec30bba6025078108ef26dadf653ac8083b0941af /arch/riscv
parent285a76bb2cf51b0c74c634f2aaccdb93e1f2a359 (diff)
downloadlinux-ac8d0b901f0033b783156ab2dc1a0e73ec42409b.tar.gz
riscv,entry: fix misaligned base for excp_vect_table
In RV64, the size of each entry in excp_vect_table is 8 bytes. If the base of the table is not 8-byte aligned, loading an entry in the table will raise a misaligned exception. Although such exception will be handled by opensbi/bbl, this still causes performance degradation. Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/kernel/entry.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 744f3209c48d..76274a4a1d8e 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -447,6 +447,7 @@ ENDPROC(__switch_to)
#endif
.section ".rodata"
+ .align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned