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authorBin Meng <bmeng.cn@gmail.com>2019-09-05 05:45:53 -0700
committerPaul Walmsley <paul.walmsley@sifive.com>2019-09-20 08:37:24 -0700
commitc81007116bd23e9e2103c267184dc38d3acc1099 (patch)
tree299b24335c779a6ce3880cd39dfdad2eff76eb3d /arch/riscv/boot
parent3bcca2a5a933e05db628ba731567de86ba7ed372 (diff)
downloadlinux-c81007116bd23e9e2103c267184dc38d3acc1099.tar.gz
riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes
The "clock-frequency" property of cpu nodes isn't required. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/boot')
-rw-r--r--arch/riscv/boot/dts/sifive/fu540-c000.dtsi3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index ae5c42d6943a..afa43c7ea369 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -61,7 +61,6 @@
};
};
cpu2: cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -85,7 +84,6 @@
};
};
cpu3: cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -109,7 +107,6 @@
};
};
cpu4: cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;