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authorJuri Lelli <juri.lelli@arm.com>2016-10-17 16:46:46 +0100
committerSudeep Holla <sudeep.holla@arm.com>2016-10-17 17:43:21 +0100
commit4d6815b453c60c75c9a910756858a421c0d79a1a (patch)
tree916643db5e67363956b6051677cff3eca4db0dbc /arch/arm64
parent2ac15068f3468d439c19865fbc04597fc6d98832 (diff)
downloadlinux-4d6815b453c60c75c9a910756858a421c0d79a1a.tar.gz
arm64: dts: juno: add cpu capacity-dmips-mhz information to R0 boards
This patch adds cpu capacity-dmips-mhz information to Juno R0 boards. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <tixy@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index a7270eff6939..6b4135e9cfe5 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -90,6 +90,7 @@
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
};
A57_1: cpu@1 {
@@ -100,6 +101,7 @@
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
};
A53_0: cpu@100 {
@@ -110,6 +112,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <578>;
};
A53_1: cpu@101 {
@@ -120,6 +123,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <578>;
};
A53_2: cpu@102 {
@@ -130,6 +134,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <578>;
};
A53_3: cpu@103 {
@@ -140,6 +145,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <578>;
};
A57_L2: l2-cache0 {