diff options
| author | Daniel Thompson <daniel.thompson@linaro.org> | 2017-01-27 16:07:13 +0000 |
|---|---|---|
| committer | Daniel Thompson <daniel.thompson@linaro.org> | 2017-03-29 17:02:10 +0100 |
| commit | e6daa5a0ef457ecdc187d078eebd3f425744eab5 (patch) | |
| tree | 177814479264ac34731811fcc47ec7017a87cfcc /arch/arm64/kernel/entry.S | |
| parent | 660f38b6a61ab655d65bf3370fe909c8ed0f6d2c (diff) | |
WIP: Migrating PMR interrupt locking away from kernel_entrydev/arm64_nmi-v4.10
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Diffstat (limited to 'arch/arm64/kernel/entry.S')
| -rw-r--r-- | arch/arm64/kernel/entry.S | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 96a36b849980..3acc5cf9b308 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -125,8 +125,6 @@ alternative_endif lsl x20, x20, #PSR_G_PMR_G_SHIFT // Shift to a PSTATE RES0 bit eor x20, x20, #PSR_G_BIT // Invert bit orr x23, x20, x23 // Store PMR within PSTATE - mov x20, #ICC_PMR_EL1_MASKED - msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR 1: #endif @@ -370,6 +368,8 @@ tsk .req x28 // current thread_info * Interrupt handling. */ .macro irq_handler + mov x20, #ICC_PMR_EL1_MASKED + msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR ldr_l x1, handle_arch_irq mov x0, sp irq_stack_entry @@ -419,6 +419,8 @@ END(vectors) */ .macro inv_entry, el, reason, regsize = 64 kernel_entry \el, \regsize + mov x20, #ICC_PMR_EL1_MASKED + msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR mov x0, sp mov x1, #\reason mrs x2, esr_el1 @@ -473,6 +475,8 @@ ENDPROC(el1_error_invalid) .align 6 el1_sync: kernel_entry 1 + mov x20, #ICC_PMR_EL1_MASKED + msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR mrs x1, esr_el1 // read the syndrome register lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 @@ -605,6 +609,8 @@ el1_preempt: .align 6 el0_sync: kernel_entry 0 + mov x20, #ICC_PMR_EL1_MASKED + msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR mrs x25, esr_el1 // read the syndrome register lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state @@ -633,6 +639,8 @@ el0_sync: .align 6 el0_sync_compat: kernel_entry 0, 32 + mov x20, #ICC_PMR_EL1_MASKED + msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR mrs x25, esr_el1 // read the syndrome register lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state |