diff options
| author | Xiaogang Cui <xiaogang@codeaurora.org> | 2015-11-19 13:24:05 +0800 |
|---|---|---|
| committer | Xiaogang Cui <xiaogang@codeaurora.org> | 2015-12-17 19:46:37 +0800 |
| commit | 300ab09dc2b199c589800f93cf8aff2ddda0ce1c (patch) | |
| tree | 546a0fb2030c3b8ae6096acbcadcabaaa09b37d8 /arch/arm64/include/asm | |
| parent | 5d82f29d1b91946106ccc49fe7a6051e1eb83450 (diff) | |
coresight: add system instruction access to etm for AArch32
According to the ETMV4 spec. ETMV4 support two type of access
operations, memeory mapped access and system instruction access.
In some specified chipsets. The memory-mapped access may result
in secure watchdog bite accross power collapse.
Add system instruction access to ETMv4 for AArch32 to fix the
compiling errors.
Change-Id: I1ec69e70bf83359374700e579191fac755a3a64e
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Diffstat (limited to 'arch/arm64/include/asm')
| -rw-r--r-- | arch/arm64/include/asm/etmv4x.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/etmv4x.h b/arch/arm64/include/asm/etmv4x.h index 1faccbe1f867..014aa5572543 100644 --- a/arch/arm64/include/asm/etmv4x.h +++ b/arch/arm64/include/asm/etmv4x.h @@ -41,6 +41,10 @@ val; \ asm volatile("msr S"#op0"_"#op1"_"#crn"_"#crm"_"#op2", %0" : : "r" (val)); \ }) +/* Clock and Power Management Register */ +#define RSYSL_CPMR_EL1() MRSL(3, 7, c15, c0, 5) +#define WSYS_CPMR_EL1(val) MSR(val, 3, 7, c15, c0, 5) + /* * ETMv4 Registers * |