diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2014-11-14 15:54:10 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-11-25 15:56:21 +0000 |
| commit | 301bcfac42897dbd1b0b3c1be49f24654a1bc49e (patch) | |
| tree | bd42ce2fcf06bc99fb2b553969cdc2dba3cb1c0b /arch/arm64/include/asm/alternative-asm.h | |
| parent | e116a375423393cdb94714e90a96857005d58428 (diff) | |
arm64: add Cortex-A53 cache errata workaround
The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/alternative-asm.h')
| -rw-r--r-- | arch/arm64/include/asm/alternative-asm.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/alternative-asm.h b/arch/arm64/include/asm/alternative-asm.h index 5ee9340459b8..919a67855b63 100644 --- a/arch/arm64/include/asm/alternative-asm.h +++ b/arch/arm64/include/asm/alternative-asm.h @@ -11,6 +11,19 @@ .byte \alt_len .endm +.macro alternative_insn insn1 insn2 cap +661: \insn1 +662: .pushsection .altinstructions, "a" + altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f + .popsection + .pushsection .altinstr_replacement, "ax" +663: \insn2 +664: .popsection + .if ((664b-663b) != (662b-661b)) + .error "Alternatives instruction length mismatch" + .endif +.endm + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ALTERNATIVE_ASM_H */ |