diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-02-21 15:04:28 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-02-25 10:37:55 +0100 |
| commit | c21cd4ae82e169b394139243684aaacf31bfcdf8 (patch) | |
| tree | 7877fa44db2abb462f67a6c5a955c7d0cc3a909a /arch/arm64/boot | |
| parent | e20119f7eaaaf6aad5b44f35155ce500429e17f6 (diff) | |
arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels
Correct the DMA channels for SCIF5 from 16..47 to 0..15, as was done for
R-Car E3.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 2660a6af690ebbb4 ("arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f2e390f7f1d5..6590b63268b0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the RZ/G2E (R8A774C0) SoC * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> @@ -990,9 +990,8 @@ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; |