diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2017-02-14 17:40:21 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-21 13:52:49 +0200 |
| commit | 3c220bf420908319cc1dc0715eb822e6a7c663e3 (patch) | |
| tree | 8f0fc6f0f66d891592960dd6b50b6a538446360f /arch/arm/boot/dts/zynq-7000.dtsi | |
| parent | e5e6f6872c7a6e2b15295574ecab8391c03808cd (diff) | |
arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index f3ac9bfe580e..0f79fe1ccd9d 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -42,6 +42,14 @@ }; }; + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&devcfg>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; |