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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-12-09 16:59:17 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-12-20 12:41:45 -0800
commitfbd1cec57064aa1380726ec899c49fcd84e702b9 (patch)
tree17a239d70f4f03ca2121d88f16d0c9c4941be511 /arch/arc/plat-axs10x
parent7bde846d0957fb81ac0bf8c4e2cab284a1da34e0 (diff)
downloadlinux-fbd1cec57064aa1380726ec899c49fcd84e702b9.tar.gz
ARC: [plat-axs103]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/plat-axs10x')
-rw-r--r--arch/arc/plat-axs10x/axs10x.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index f1ac6790da5f..ac1a712f6f1f 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -320,22 +320,18 @@ static void __init axs103_early_init(void)
unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
if (num_cores > 2) {
u32 freq = 50, orig;
- /*
- * TODO: use cpu node "cpu-freq" param instead of platform-specific
- * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
- */
int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
const struct fdt_property *prop;
prop = fdt_get_property(initial_boot_params, off,
- "clock-frequency", NULL);
+ "assigned-clock-rates", NULL);
orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
/* Patching .dtb in-place with new core clock value */
if (freq != orig ) {
freq = cpu_to_be32(freq * 1000000);
fdt_setprop_inplace(initial_boot_params, off,
- "clock-frequency", &freq, sizeof(freq));
+ "assigned-clock-rates", &freq, sizeof(freq));
}
}
#endif