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authorVineet Gupta <vgupta@synopsys.com>2015-08-03 18:27:56 +0530
committerVineet Gupta <vgupta@synopsys.com>2015-08-04 09:26:30 +0530
commit6de7abfbad1c6a45893a47a17c2ac91b551aa90d (patch)
tree11d53df8337ba1f498dcfb4d08a10c41d5e638ed /arch/arc/plat-axs10x
parente13c42ecbe580509451e021ba2586871e5b47640 (diff)
downloadlinux-6de7abfbad1c6a45893a47a17c2ac91b551aa90d.tar.gz
ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/plat-axs10x')
-rw-r--r--arch/arc/plat-axs10x/axs10x.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 99f7da513a48..e7769c3ab5f2 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -389,6 +389,21 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
static void __init axs103_early_init(void)
{
+ /*
+ * AXS103 configurations for SMP/QUAD configurations share device tree
+ * which defaults to 90 MHz. However recent failures of Quad config
+ * revealed P&R timing violations so clamp it down to safe 50 MHz
+ * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
+ *
+ * This hack is really hacky as of now. Fix it properly by getting the
+ * number of cores as return value of platform's early SMP callback
+ */
+#ifdef CONFIG_ARC_MCIP
+ unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
+ if (num_cores > 2)
+ arc_set_core_freq(50 * 1000000);
+#endif
+
switch (arc_get_core_freq()/1000000) {
case 33:
axs103_set_freq(1, 1, 1);