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authorVineet Gupta <vgupta@synopsys.com>2019-02-21 13:44:49 -0800
committerVineet Gupta <vgupta@synopsys.com>2019-02-21 14:53:36 -0800
commit7b2e932f633bcb7b190fc7031ce6dac75f8c3472 (patch)
tree4102321338daed2d80932fe7951bba20b78858b7 /arch/arc/include
parentb6835ea77729e7faf4656ca637ba53f42b8ee3fd (diff)
downloadlinux-7b2e932f633bcb7b190fc7031ce6dac75f8c3472.tar.gz
ARCv2: don't assume core 0x54 has dual issue
The first release of core4 (0x54) was dual issue only (HS4x). Newer releases allow hardware to be configured as single issue (HS3x) or dual issue. Prevent accessing a HS4x only aux register in HS3x, which otherwise leads to illegal instruction exceptions Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
-rw-r--r--arch/arc/include/asm/arcregs.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f1b86cef0905..a27eafdc8260 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -151,6 +151,14 @@ struct bcr_isa_arcv2 {
#endif
};
+struct bcr_uarch_build_arcv2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad:8, prod:8, maj:8, min:8;
+#else
+ unsigned int min:8, maj:8, prod:8, pad:8;
+#endif
+};
+
struct bcr_mpy {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;