diff options
| author | Lilin <lin.li@archermind.com> | 2016-10-17 09:39:49 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-10-17 09:39:49 +0800 |
| commit | 4a8efe0fd083d28ca89bb7ea0e49240ef37be01d (patch) | |
| tree | 102cf37b9d50067b0e6d12df79497015df9af939 | |
| parent | 94d44eb5c3d7dd6183f530dedd534c3a2bea4c59 (diff) | |
| parent | 3fe4fffc22db0b147251487f9dccae6e3e2a5a1f (diff) | |
Merge pull request #2 from n005056/helio-x20
Helio x20
74 files changed, 3912 insertions, 1278 deletions
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c index ec8991d2fca8..7bc8c0e59d22 100644..100755 --- a/arch/arm/kernel/hibernate.c +++ b/arch/arm/kernel/hibernate.c @@ -22,7 +22,6 @@ #include <asm/suspend.h> #include <asm/memory.h> #include <asm/sections.h> -#include <mtk_hibernate_core.h> #include "reboot.h" #ifdef CONFIG_MTK_HIBERNATION diff --git a/arch/arm64/boot/dts/amt6797_64_open.dts b/arch/arm64/boot/dts/amt6797_64_open.dts index 14734e83a759..71a6bc50973e 100755 --- a/arch/arm64/boot/dts/amt6797_64_open.dts +++ b/arch/arm64/boot/dts/amt6797_64_open.dts @@ -991,14 +991,14 @@ }; camera_pins_cam_ldo_vcama_0: cam0@vcama0 { pins_cmd_dat { - pins = <PINMUX_GPIO63__FUNC_GPIO63>; + pins = <PINMUX_GPIO253__FUNC_GPIO253>; slew-rate = <1>; output-low; }; }; camera_pins_cam_ldo_vcama_1: cam1@vcama1 { pins_cmd_dat { - pins = <PINMUX_GPIO63__FUNC_GPIO63>; + pins = <PINMUX_GPIO253__FUNC_GPIO253>; slew-rate = <1>; output-high; }; @@ -1007,7 +1007,7 @@ pins_cmd_dat { pins = <PINMUX_GPIO63__FUNC_GPIO63>; slew-rate = <1>; - output-low; + output-high; }; }; camera_pins_cam_ldo_vcamd_1: cam1@vcamd1 { @@ -1019,14 +1019,14 @@ }; camera_pins_cam_ldo_e2_vcamd_0: cam0@vcamd2 { pins_cmd_dat { - pins = <PINMUX_GPIO140__FUNC_GPIO140>; + pins = <PINMUX_GPIO63__FUNC_GPIO63>; slew-rate = <1>; output-low; }; }; camera_pins_cam_ldo_e2_vcamd_1: cam1@vcamd3 { pins_cmd_dat { - pins = <PINMUX_GPIO140__FUNC_GPIO140>; + pins = <PINMUX_GPIO63__FUNC_GPIO63>; slew-rate = <1>; output-high; }; diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c index b81c77d5389a..7da6803dc37c 100644..100755 --- a/arch/arm64/kernel/psci.c +++ b/arch/arm64/kernel/psci.c @@ -32,7 +32,6 @@ #include <asm/smp_plat.h> #include <asm/suspend.h> #include <asm/system_misc.h> -#include <mtk_hibernate_core.h> #ifdef CONFIG_ARCH_MT6797 #include <mt6797/da9214.h> #include <mach/mt_freqhopping.h> diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile index 2d68ed2590b4..eaaad5933d12 100644..100755 --- a/arch/arm64/lib/Makefile +++ b/arch/arm64/lib/Makefile @@ -4,5 +4,4 @@ lib-y := bitops.o clear_user.o delay.o copy_from_user.o \ copy_to_user.o copy_in_user.o copy_page.o \ clear_page.o memchr.o memcpy.o memmove.o memset.o \ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ - strchr.o strrchr.o \ - call_with_stack.o + strchr.o strrchr.o diff --git a/arch/arm64/mm/mt_cache_v8.S b/arch/arm64/mm/mt_cache_v8.S index ef3606df9bb2..86c386ac18e1 100644..100755 --- a/arch/arm64/mm/mt_cache_v8.S +++ b/arch/arm64/mm/mt_cache_v8.S @@ -1,3 +1,16 @@ +/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> diff --git a/block/Makefile b/block/Makefile index 9392a9f22c1e..a3bb40daf862 100644..100755 --- a/block/Makefile +++ b/block/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_BLOCK) := bio.o elevator.o blk-core.o blk-tag.o blk-sysfs.o \ blk-exec.o blk-merge.o blk-softirq.o blk-timeout.o \ blk-iopoll.o blk-lib.o blk-mq.o blk-mq-tag.o \ blk-mq-sysfs.o blk-mq-cpu.o blk-mq-cpumap.o ioctl.o \ - uuid.o genhd.o scsi_ioctl.o partition-generic.o ioprio.o \ + genhd.o scsi_ioctl.o partition-generic.o ioprio.o \ partitions/ obj-$(CONFIG_BOUNCE) += bounce.o diff --git a/block/genhd.c b/block/genhd.c index 897cea082660..c675ad1ad69b 100644..100755 --- a/block/genhd.c +++ b/block/genhd.c @@ -17,8 +17,6 @@ #include <linux/kobj_map.h> #include <linux/mutex.h> #include <linux/idr.h> -#include <linux/ctype.h> -#include <linux/fs_uuid.h> #include <linux/log2.h> #include <linux/pm_runtime.h> @@ -1403,88 +1401,6 @@ int invalidate_partition(struct gendisk *disk, int partno) EXPORT_SYMBOL(invalidate_partition); -dev_t blk_lookup_fs_info(struct fs_info *seek) -{ - dev_t devt = MKDEV(0, 0); - struct class_dev_iter iter; - struct device *dev; - int best_score = 0; - - class_dev_iter_init(&iter, &block_class, NULL, &disk_type); - while (best_score < 3 && (dev = class_dev_iter_next(&iter))) { - struct gendisk *disk = dev_to_disk(dev); - struct disk_part_iter piter; - struct hd_struct *part; - - disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); - - while (best_score < 3 && (part = disk_part_iter_next(&piter))) { - int score = part_matches_fs_info(part, seek); - - if (score > best_score) { - devt = part_devt(part); - best_score = score; - } - } - disk_part_iter_exit(&piter); - } - class_dev_iter_exit(&iter); - return devt; -} -EXPORT_SYMBOL_GPL(blk_lookup_fs_info); - -/* Caller uses NULL, key to start. For each match found, we return a bdev on - * which we have done blkdev_get, and we do the blkdev_put on block devices - * that are passed to us. When no more matches are found, we return NULL. - */ -struct block_device *next_bdev_of_type(struct block_device *last, - const char *key) -{ - dev_t devt = MKDEV(0, 0); - struct class_dev_iter iter; - struct device *dev; - struct block_device *next = NULL, *bdev; - int got_last = 0; - - if (!key) - goto out; - - class_dev_iter_init(&iter, &block_class, NULL, &disk_type); - while (!devt && (dev = class_dev_iter_next(&iter))) { - struct gendisk *disk = dev_to_disk(dev); - struct disk_part_iter piter; - struct hd_struct *part; - - disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); - - while ((part = disk_part_iter_next(&piter))) { - bdev = bdget(part_devt(part)); - if (last && !got_last) { - if (last == bdev) - got_last = 1; - continue; - } - - if (blkdev_get(bdev, FMODE_READ, 0)) - continue; - - if (bdev_matches_key(bdev, key)) { - next = bdev; - break; - } - - blkdev_put(bdev, FMODE_READ); - } - disk_part_iter_exit(&piter); - } - class_dev_iter_exit(&iter); -out: - if (last) - blkdev_put(last, FMODE_READ); - return next; -} -EXPORT_SYMBOL_GPL(next_bdev_of_type); - /* * Disk events - monitor disk events like media change and eject request. */ diff --git a/drivers/misc/mediatek/Kconfig b/drivers/misc/mediatek/Kconfig index 44a836d49855..3d61c7c22029 100644..100755 --- a/drivers/misc/mediatek/Kconfig +++ b/drivers/misc/mediatek/Kconfig @@ -114,17 +114,6 @@ config MTK_PASR This can help system reduce power consumption. It is based on MTK_MEMORY_LOWPOWER technology. -config MTK_HIBERNATION - bool "MTK Hibernation support (IPOH)" - depends on TOI - default y - help - MTK Hibernation is the improved hibernation driver in kernel for IPOH. - This depends on TuxOnIce implementation of kernel hibernation - architecture to improve mediatek platform hibernation flow. - This option is required when IPOH is enabled. - - source "drivers/misc/mediatek/base/power/Kconfig" source "drivers/misc/mediatek/freqhopping/Kconfig" source "drivers/misc/mediatek/pmic/Kconfig" diff --git a/drivers/misc/mediatek/Makefile b/drivers/misc/mediatek/Makefile index 69efcfd2f41e..23ad56c4d596 100755 --- a/drivers/misc/mediatek/Makefile +++ b/drivers/misc/mediatek/Makefile @@ -14,7 +14,6 @@ #$(call all-subdir-src-or-makefile) MTK_PLATFORM := $(subst ",,$(CONFIG_MTK_PLATFORM)) subdir-ccflags-y += -Werror -subdir-ccflags-y += -I$(srctree)/drivers/misc/mediatek/hibcore subdir-ccflags-y += -I$(srctree)/drivers/misc/mediatek/include subdir-ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat/$(MTK_PLATFORM)/include subdir-ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat @@ -131,8 +130,6 @@ obj-$(CONFIG_MTK_CCCI_EXT) += dual_ccci/ obj-$(CONFIG_MTK_C2K_SUPPORT) += c2k_ccci/ obj-$(CONFIG_MTK_ECCCI_DRIVER) += eccci/ -obj-$(CONFIG_MTK_HIBERNATION) += hibcore/ - ifdef CONFIG_CUSTOM_KERNEL_SSW ifneq ($(strip $(CONFIG_CUSTOM_KERNEL_SSW)),"") obj-y += ssw/ diff --git a/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant-v7.S b/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant-v7.S index 7d91cfbe91f1..05a5376a1031 100644..100755 --- a/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant-v7.S +++ b/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant-v7.S @@ -1,3 +1,16 @@ +/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + .global write_cntpctl write_cntpctl: .func diff --git a/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant.S b/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant.S index 335d44c8995c..0f91fe511aad 100644..100755 --- a/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant.S +++ b/drivers/misc/mediatek/base/power/cpuidle_v1/cpu_dormant.S @@ -1,3 +1,16 @@ +/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + .global write_cntpctl write_cntpctl: .func diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq.c b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq.c index 90eb1cc19884..9428f5d25d20 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq.c +++ b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq.c @@ -174,6 +174,10 @@ static u32 enable_hw_gov = 1; ktime_t now[NR_SET_V_F]; ktime_t delta[NR_SET_V_F]; ktime_t max[NR_SET_V_F]; +ktime_t start_ktime_dvfs; +ktime_t start_ktime_dvfs_cb; +ktime_t dvfs_step_delta[16]; +ktime_t dvfs_cb_step_delta[16]; /* used @ set_cur_volt_extBuck() */ /* #define MIN_DIFF_VSRAM_PROC 1000 */ @@ -207,7 +211,7 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ2_LL_FY (1287000) /* KHz */ #define CPU_DVFS_FREQ3_LL_FY (1222000) /* KHz */ #define CPU_DVFS_FREQ4_LL_FY (1118000) /* KHz */ -#define CPU_DVFS_FREQ5_LL_FY (1066000) /* KHz */ +#define CPU_DVFS_FREQ5_LL_FY (1092000) /* KHz */ #define CPU_DVFS_FREQ6_LL_FY (949000) /* KHz */ #define CPU_DVFS_FREQ7_LL_FY (897000) /* KHz */ #define CPU_DVFS_FREQ8_LL_FY (806000) /* KHz */ @@ -228,8 +232,8 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ5_L_FY (1417000) /* KHz */ #define CPU_DVFS_FREQ6_L_FY (1274000) /* KHz */ #define CPU_DVFS_FREQ7_L_FY (1209000) /* KHz */ -#define CPU_DVFS_FREQ8_L_FY (1079000) /* KHz */ -#define CPU_DVFS_FREQ9_L_FY (962000) /* KHz */ +#define CPU_DVFS_FREQ8_L_FY (1092000) /* KHz */ +#define CPU_DVFS_FREQ9_L_FY (949000) /* KHz */ #define CPU_DVFS_FREQ10_L_FY (832000) /* KHz */ #define CPU_DVFS_FREQ11_L_FY (741000) /* KHz */ #define CPU_DVFS_FREQ12_L_FY (650000) /* KHz */ @@ -256,39 +260,75 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ15_CCI_FY (169000) /* KHz */ /* for DVFS OPP table B/FY */ -#define CPU_DVFS_FREQ0_B_FY (2249000) /* KHz */ -#define CPU_DVFS_FREQ1_B_FY (2197000) /* KHz */ -#define CPU_DVFS_FREQ2_B_FY (2171000) /* KHz */ -#define CPU_DVFS_FREQ3_B_FY (2119000) /* KHz */ -#define CPU_DVFS_FREQ4_B_FY (2093000) /* KHz */ -#define CPU_DVFS_FREQ5_B_FY (1989000) /* KHz */ -#define CPU_DVFS_FREQ6_B_FY (1781000) /* KHz */ -#define CPU_DVFS_FREQ7_B_FY (1677000) /* KHz */ -#define CPU_DVFS_FREQ8_B_FY (1495000) /* KHz */ -#define CPU_DVFS_FREQ9_B_FY (1378000) /* KHz */ -#define CPU_DVFS_FREQ10_B_FY (1248000) /* KHz */ -#define CPU_DVFS_FREQ11_B_FY (1131000) /* KHz */ -#define CPU_DVFS_FREQ12_B_FY (1001000) /* KHz */ -#define CPU_DVFS_FREQ13_B_FY (845000) /* KHz */ -#define CPU_DVFS_FREQ14_B_FY (676000) /* KHz */ -#define CPU_DVFS_FREQ15_B_FY (338000) /* KHz */ - -#define CPU_IDVFS_FREQ0_B_FY (8996) /* Perc */ -#define CPU_IDVFS_FREQ1_B_FY (8788) /* Perc */ -#define CPU_IDVFS_FREQ2_B_FY (8684) /* Perc */ -#define CPU_IDVFS_FREQ3_B_FY (8476) /* Perc */ -#define CPU_IDVFS_FREQ4_B_FY (8372) /* Perc */ -#define CPU_IDVFS_FREQ5_B_FY (7956) /* Perc */ -#define CPU_IDVFS_FREQ6_B_FY (7124) /* Perc */ -#define CPU_IDVFS_FREQ7_B_FY (6708) /* Perc */ -#define CPU_IDVFS_FREQ8_B_FY (5980) /* Perc */ -#define CPU_IDVFS_FREQ9_B_FY (5512) /* Perc */ -#define CPU_IDVFS_FREQ10_B_FY (4992) /* Perc */ -#define CPU_IDVFS_FREQ11_B_FY (4524) /* Perc */ -#define CPU_IDVFS_FREQ12_B_FY (4004) /* Perc */ -#define CPU_IDVFS_FREQ13_B_FY (3380) /* Perc */ -#define CPU_IDVFS_FREQ14_B_FY (2704) /* Perc */ -#define CPU_IDVFS_FREQ15_B_FY (1352) /* Perc */ +/* 1221 */ +#define CPU_DVFS_FREQ0_B_FY1221 (2145000) /* KHz */ +#define CPU_DVFS_FREQ1_B_FY1221 (2093000) /* KHz */ +#define CPU_DVFS_FREQ2_B_FY1221 (2054000) /* KHz */ +#define CPU_DVFS_FREQ3_B_FY1221 (1989000) /* KHz */ +#define CPU_DVFS_FREQ4_B_FY1221 (1963000) /* KHz */ +#define CPU_DVFS_FREQ5_B_FY1221 (1872000) /* KHz */ +#define CPU_DVFS_FREQ6_B_FY1221 (1690000) /* KHz */ +#define CPU_DVFS_FREQ7_B_FY1221 (1599000) /* KHz */ +#define CPU_DVFS_FREQ8_B_FY1221 (1404000) /* KHz */ +#define CPU_DVFS_FREQ9_B_FY1221 (1287000) /* KHz */ +#define CPU_DVFS_FREQ10_B_FY1221 (1170000) /* KHz */ +#define CPU_DVFS_FREQ11_B_FY1221 (1053000) /* KHz */ +#define CPU_DVFS_FREQ12_B_FY1221 (936000) /* KHz */ +#define CPU_DVFS_FREQ13_B_FY1221 (793000) /* KHz */ +#define CPU_DVFS_FREQ14_B_FY1221 (650000) /* KHz */ +#define CPU_DVFS_FREQ15_B_FY1221 (338000) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_FY1221 (8580) /* Perc */ +#define CPU_IDVFS_FREQ1_B_FY1221 (8372) /* Perc */ +#define CPU_IDVFS_FREQ2_B_FY1221 (8216) /* Perc */ +#define CPU_IDVFS_FREQ3_B_FY1221 (7956) /* Perc */ +#define CPU_IDVFS_FREQ4_B_FY1221 (7852) /* Perc */ +#define CPU_IDVFS_FREQ5_B_FY1221 (7488) /* Perc */ +#define CPU_IDVFS_FREQ6_B_FY1221 (6760) /* Perc */ +#define CPU_IDVFS_FREQ7_B_FY1221 (6396) /* Perc */ +#define CPU_IDVFS_FREQ8_B_FY1221 (5616) /* Perc */ +#define CPU_IDVFS_FREQ9_B_FY1221 (5148) /* Perc */ +#define CPU_IDVFS_FREQ10_B_FY1221 (4680) /* Perc */ +#define CPU_IDVFS_FREQ11_B_FY1221 (4212) /* Perc */ +#define CPU_IDVFS_FREQ12_B_FY1221 (3744) /* Perc */ +#define CPU_IDVFS_FREQ13_B_FY1221 (3172) /* Perc */ +#define CPU_IDVFS_FREQ14_B_FY1221 (2600) /* Perc */ +#define CPU_IDVFS_FREQ15_B_FY1221 (1352) /* Perc */ + +/* 0119 */ +#define CPU_DVFS_FREQ0_B_FY0119 (2314000) /* KHz */ +#define CPU_DVFS_FREQ1_B_FY0119 (2197000) /* KHz */ +#define CPU_DVFS_FREQ2_B_FY0119 (2171000) /* KHz */ +#define CPU_DVFS_FREQ3_B_FY0119 (2119000) /* KHz */ +#define CPU_DVFS_FREQ4_B_FY0119 (2093000) /* KHz */ +#define CPU_DVFS_FREQ5_B_FY0119 (1989000) /* KHz */ +#define CPU_DVFS_FREQ6_B_FY0119 (1781000) /* KHz */ +#define CPU_DVFS_FREQ7_B_FY0119 (1677000) /* KHz */ +#define CPU_DVFS_FREQ8_B_FY0119 (1495000) /* KHz */ +#define CPU_DVFS_FREQ9_B_FY0119 (1378000) /* KHz */ +#define CPU_DVFS_FREQ10_B_FY0119 (1248000) /* KHz */ +#define CPU_DVFS_FREQ11_B_FY0119 (1131000) /* KHz */ +#define CPU_DVFS_FREQ12_B_FY0119 (1001000) /* KHz */ +#define CPU_DVFS_FREQ13_B_FY0119 (845000) /* KHz */ +#define CPU_DVFS_FREQ14_B_FY0119 (676000) /* KHz */ +#define CPU_DVFS_FREQ15_B_FY0119 (338000) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_FY0119 (9256) /* Perc */ +#define CPU_IDVFS_FREQ1_B_FY0119 (8788) /* Perc */ +#define CPU_IDVFS_FREQ2_B_FY0119 (8684) /* Perc */ +#define CPU_IDVFS_FREQ3_B_FY0119 (8476) /* Perc */ +#define CPU_IDVFS_FREQ4_B_FY0119 (8372) /* Perc */ +#define CPU_IDVFS_FREQ5_B_FY0119 (7956) /* Perc */ +#define CPU_IDVFS_FREQ6_B_FY0119 (7124) /* Perc */ +#define CPU_IDVFS_FREQ7_B_FY0119 (6708) /* Perc */ +#define CPU_IDVFS_FREQ8_B_FY0119 (5980) /* Perc */ +#define CPU_IDVFS_FREQ9_B_FY0119 (5512) /* Perc */ +#define CPU_IDVFS_FREQ10_B_FY0119 (4992) /* Perc */ +#define CPU_IDVFS_FREQ11_B_FY0119 (4524) /* Perc */ +#define CPU_IDVFS_FREQ12_B_FY0119 (4004) /* Perc */ +#define CPU_IDVFS_FREQ13_B_FY0119 (3380) /* Perc */ +#define CPU_IDVFS_FREQ14_B_FY0119 (2704) /* Perc */ +#define CPU_IDVFS_FREQ15_B_FY0119 (1352) /* Perc */ /* for DVFS OPP table LL|L|CCI */ #define CPU_DVFS_VOLT0_VPROC1_FY (120000) /* 10MV */ @@ -309,22 +349,41 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_VOLT15_VPROC1_FY (78000) /* 10MV */ /* for DVFS OPP table B */ -#define CPU_DVFS_VOLT0_VPROC2_FY (118000) /* 10MV */ -#define CPU_DVFS_VOLT1_VPROC2_FY (117000) /* 10MV */ -#define CPU_DVFS_VOLT2_VPROC2_FY (116000) /* 10MV */ -#define CPU_DVFS_VOLT3_VPROC2_FY (114000) /* 10MV */ -#define CPU_DVFS_VOLT4_VPROC2_FY (113000) /* 10MV */ -#define CPU_DVFS_VOLT5_VPROC2_FY (111000) /* 10MV */ -#define CPU_DVFS_VOLT6_VPROC2_FY (107000) /* 10MV */ -#define CPU_DVFS_VOLT7_VPROC2_FY (105000) /* 10MV */ -#define CPU_DVFS_VOLT8_VPROC2_FY (100000) /* 10MV */ -#define CPU_DVFS_VOLT9_VPROC2_FY (98000) /* 10MV */ -#define CPU_DVFS_VOLT10_VPROC2_FY (95000) /* 10MV */ -#define CPU_DVFS_VOLT11_VPROC2_FY (93000) /* 10MV */ -#define CPU_DVFS_VOLT12_VPROC2_FY (90000) /* 10MV */ -#define CPU_DVFS_VOLT13_VPROC2_FY (88000) /* 10MV */ -#define CPU_DVFS_VOLT14_VPROC2_FY (85000) /* 10MV */ -#define CPU_DVFS_VOLT15_VPROC2_FY (80000) /* 10MV */ +/* 1221 */ +#define CPU_DVFS_VOLT0_VPROC2_FY1221 (118000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_FY1221 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_FY1221 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_FY1221 (114000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_FY1221 (113000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_FY1221 (111000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_FY1221 (107000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_FY1221 (105000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_FY1221 (100000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_FY1221 (98000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_FY1221 (95000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_FY1221 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_FY1221 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_FY1221 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_FY1221 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_FY1221 (80000) /* 10MV */ + +/* 0119 */ +#define CPU_DVFS_VOLT0_VPROC2_FY0119 (120000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_FY0119 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_FY0119 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_FY0119 (114000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_FY0119 (113000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_FY0119 (111000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_FY0119 (107000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_FY0119 (105000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_FY0119 (100000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_FY0119 (98000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_FY0119 (95000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_FY0119 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_FY0119 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_FY0119 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_FY0119 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_FY0119 (80000) /* 10MV */ /* for DVFS OPP table LL/SB */ #define CPU_DVFS_FREQ0_LL_SB (1547000) /* KHz */ @@ -355,7 +414,7 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ7_L_SB (1495000) /* KHz */ #define CPU_DVFS_FREQ8_L_SB (1352000) /* KHz */ #define CPU_DVFS_FREQ9_L_SB (1209000) /* KHz */ -#define CPU_DVFS_FREQ10_L_SB (1079000) /* KHz */ +#define CPU_DVFS_FREQ10_L_SB (1092000) /* KHz */ #define CPU_DVFS_FREQ11_L_SB (962000) /* KHz */ #define CPU_DVFS_FREQ12_L_SB (832000) /* KHz */ #define CPU_DVFS_FREQ13_L_SB (650000) /* KHz */ @@ -381,39 +440,75 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ15_CCI_SB (169000) /* KHz */ /* for DVFS OPP table B/SB */ -#define CPU_DVFS_FREQ0_B_SB (2457000) /* KHz */ -#define CPU_DVFS_FREQ1_B_SB (2392000) /* KHz */ -#define CPU_DVFS_FREQ2_B_SB (2327000) /* KHz */ -#define CPU_DVFS_FREQ3_B_SB (2262000) /* KHz */ -#define CPU_DVFS_FREQ4_B_SB (2223000) /* KHz */ -#define CPU_DVFS_FREQ5_B_SB (2158000) /* KHz */ -#define CPU_DVFS_FREQ6_B_SB (2093000) /* KHz */ -#define CPU_DVFS_FREQ7_B_SB (1885000) /* KHz */ -#define CPU_DVFS_FREQ8_B_SB (1677000) /* KHz */ -#define CPU_DVFS_FREQ9_B_SB (1495000) /* KHz */ -#define CPU_DVFS_FREQ10_B_SB (1378000) /* KHz */ -#define CPU_DVFS_FREQ11_B_SB (1131000) /* KHz */ -#define CPU_DVFS_FREQ12_B_SB (1001000) /* KHz */ -#define CPU_DVFS_FREQ13_B_SB (845000) /* KHz */ -#define CPU_DVFS_FREQ14_B_SB (676000) /* KHz */ -#define CPU_DVFS_FREQ15_B_SB (338000) /* KHz */ - -#define CPU_IDVFS_FREQ0_B_SB (9828) /* Perc */ -#define CPU_IDVFS_FREQ1_B_SB (9568) /* Perc */ -#define CPU_IDVFS_FREQ2_B_SB (9308) /* Perc */ -#define CPU_IDVFS_FREQ3_B_SB (9048) /* Perc */ -#define CPU_IDVFS_FREQ4_B_SB (8892) /* Perc */ -#define CPU_IDVFS_FREQ5_B_SB (8632) /* Perc */ -#define CPU_IDVFS_FREQ6_B_SB (8372) /* Perc */ -#define CPU_IDVFS_FREQ7_B_SB (7540) /* Perc */ -#define CPU_IDVFS_FREQ8_B_SB (6708) /* Perc */ -#define CPU_IDVFS_FREQ9_B_SB (5980) /* Perc */ -#define CPU_IDVFS_FREQ10_B_SB (5512) /* Perc */ -#define CPU_IDVFS_FREQ11_B_SB (4524) /* Perc */ -#define CPU_IDVFS_FREQ12_B_SB (4004) /* Perc */ -#define CPU_IDVFS_FREQ13_B_SB (3380) /* Perc */ -#define CPU_IDVFS_FREQ14_B_SB (2704) /* Perc */ -#define CPU_IDVFS_FREQ15_B_SB (1352) /* Perc */ +/* 1221 */ +#define CPU_DVFS_FREQ0_B_SB1221 (2340000) /* KHz */ +#define CPU_DVFS_FREQ1_B_SB1221 (2288000) /* KHz */ +#define CPU_DVFS_FREQ2_B_SB1221 (2223000) /* KHz */ +#define CPU_DVFS_FREQ3_B_SB1221 (2145000) /* KHz */ +#define CPU_DVFS_FREQ4_B_SB1221 (2093000) /* KHz */ +#define CPU_DVFS_FREQ5_B_SB1221 (2028000) /* KHz */ +#define CPU_DVFS_FREQ6_B_SB1221 (1963000) /* KHz */ +#define CPU_DVFS_FREQ7_B_SB1221 (1781000) /* KHz */ +#define CPU_DVFS_FREQ8_B_SB1221 (1599000) /* KHz */ +#define CPU_DVFS_FREQ9_B_SB1221 (1404000) /* KHz */ +#define CPU_DVFS_FREQ10_B_SB1221 (1287000) /* KHz */ +#define CPU_DVFS_FREQ11_B_SB1221 (1053000) /* KHz */ +#define CPU_DVFS_FREQ12_B_SB1221 (936000) /* KHz */ +#define CPU_DVFS_FREQ13_B_SB1221 (793000) /* KHz */ +#define CPU_DVFS_FREQ14_B_SB1221 (650000) /* KHz */ +#define CPU_DVFS_FREQ15_B_SB1221 (338000) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_SB1221 (9360) /* Perc */ +#define CPU_IDVFS_FREQ1_B_SB1221 (9152) /* Perc */ +#define CPU_IDVFS_FREQ2_B_SB1221 (8892) /* Perc */ +#define CPU_IDVFS_FREQ3_B_SB1221 (8580) /* Perc */ +#define CPU_IDVFS_FREQ4_B_SB1221 (8372) /* Perc */ +#define CPU_IDVFS_FREQ5_B_SB1221 (8112) /* Perc */ +#define CPU_IDVFS_FREQ6_B_SB1221 (7852) /* Perc */ +#define CPU_IDVFS_FREQ7_B_SB1221 (7124) /* Perc */ +#define CPU_IDVFS_FREQ8_B_SB1221 (6396) /* Perc */ +#define CPU_IDVFS_FREQ9_B_SB1221 (5616) /* Perc */ +#define CPU_IDVFS_FREQ10_B_SB1221 (5148) /* Perc */ +#define CPU_IDVFS_FREQ11_B_SB1221 (4212) /* Perc */ +#define CPU_IDVFS_FREQ12_B_SB1221 (3744) /* Perc */ +#define CPU_IDVFS_FREQ13_B_SB1221 (3172) /* Perc */ +#define CPU_IDVFS_FREQ14_B_SB1221 (2600) /* Perc */ +#define CPU_IDVFS_FREQ15_B_SB1221 (1352) /* Perc */ + +/* 0119*/ +#define CPU_DVFS_FREQ0_B_SB0119 (2522000) /* KHz */ +#define CPU_DVFS_FREQ1_B_SB0119 (2392000) /* KHz */ +#define CPU_DVFS_FREQ2_B_SB0119 (2327000) /* KHz */ +#define CPU_DVFS_FREQ3_B_SB0119 (2262000) /* KHz */ +#define CPU_DVFS_FREQ4_B_SB0119 (2223000) /* KHz */ +#define CPU_DVFS_FREQ5_B_SB0119 (2158000) /* KHz */ +#define CPU_DVFS_FREQ6_B_SB0119 (2093000) /* KHz */ +#define CPU_DVFS_FREQ7_B_SB0119 (1885000) /* KHz */ +#define CPU_DVFS_FREQ8_B_SB0119 (1677000) /* KHz */ +#define CPU_DVFS_FREQ9_B_SB0119 (1495000) /* KHz */ +#define CPU_DVFS_FREQ10_B_SB0119 (1378000) /* KHz */ +#define CPU_DVFS_FREQ11_B_SB0119 (1131000) /* KHz */ +#define CPU_DVFS_FREQ12_B_SB0119 (1001000) /* KHz */ +#define CPU_DVFS_FREQ13_B_SB0119 (845000) /* KHz */ +#define CPU_DVFS_FREQ14_B_SB0119 (676000) /* KHz */ +#define CPU_DVFS_FREQ15_B_SB0119 (338000) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_SB0119 (10088) /* Perc */ +#define CPU_IDVFS_FREQ1_B_SB0119 (9568) /* Perc */ +#define CPU_IDVFS_FREQ2_B_SB0119 (9308) /* Perc */ +#define CPU_IDVFS_FREQ3_B_SB0119 (9048) /* Perc */ +#define CPU_IDVFS_FREQ4_B_SB0119 (8892) /* Perc */ +#define CPU_IDVFS_FREQ5_B_SB0119 (8632) /* Perc */ +#define CPU_IDVFS_FREQ6_B_SB0119 (8372) /* Perc */ +#define CPU_IDVFS_FREQ7_B_SB0119 (7540) /* Perc */ +#define CPU_IDVFS_FREQ8_B_SB0119 (6708) /* Perc */ +#define CPU_IDVFS_FREQ9_B_SB0119 (5980) /* Perc */ +#define CPU_IDVFS_FREQ10_B_SB0119 (5512) /* Perc */ +#define CPU_IDVFS_FREQ11_B_SB0119 (4524) /* Perc */ +#define CPU_IDVFS_FREQ12_B_SB0119 (4004) /* Perc */ +#define CPU_IDVFS_FREQ13_B_SB0119 (3380) /* Perc */ +#define CPU_IDVFS_FREQ14_B_SB0119 (2704) /* Perc */ +#define CPU_IDVFS_FREQ15_B_SB0119 (1352) /* Perc */ /* for DVFS OPP table LL|L|CCI */ #define CPU_DVFS_VOLT0_VPROC1_SB (120000) /* 10MV */ @@ -434,22 +529,41 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_VOLT15_VPROC1_SB (77000) /* 10MV */ /* for DVFS OPP table B */ -#define CPU_DVFS_VOLT0_VPROC2_SB (118000) /* 10MV */ -#define CPU_DVFS_VOLT1_VPROC2_SB (117000) /* 10MV */ -#define CPU_DVFS_VOLT2_VPROC2_SB (116000) /* 10MV */ -#define CPU_DVFS_VOLT3_VPROC2_SB (115000) /* 10MV */ -#define CPU_DVFS_VOLT4_VPROC2_SB (114000) /* 10MV */ -#define CPU_DVFS_VOLT5_VPROC2_SB (113000) /* 10MV */ -#define CPU_DVFS_VOLT6_VPROC2_SB (111000) /* 10MV */ -#define CPU_DVFS_VOLT7_VPROC2_SB (108000) /* 10MV */ -#define CPU_DVFS_VOLT8_VPROC2_SB (104000) /* 10MV */ -#define CPU_DVFS_VOLT9_VPROC2_SB (100000) /* 10MV */ -#define CPU_DVFS_VOLT10_VPROC2_SB (98000) /* 10MV */ -#define CPU_DVFS_VOLT11_VPROC2_SB (93000) /* 10MV */ -#define CPU_DVFS_VOLT12_VPROC2_SB (90000) /* 10MV */ -#define CPU_DVFS_VOLT13_VPROC2_SB (88000) /* 10MV */ -#define CPU_DVFS_VOLT14_VPROC2_SB (85000) /* 10MV */ -#define CPU_DVFS_VOLT15_VPROC2_SB (80000) /* 10MV */ +/* 1221 */ +#define CPU_DVFS_VOLT0_VPROC2_SB1221 (118000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_SB1221 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_SB1221 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_SB1221 (115000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_SB1221 (114000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_SB1221 (113000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_SB1221 (111000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_SB1221 (108000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_SB1221 (104000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_SB1221 (100000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_SB1221 (98000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_SB1221 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_SB1221 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_SB1221 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_SB1221 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_SB1221 (80000) /* 10MV */ + +/* 0119 */ +#define CPU_DVFS_VOLT0_VPROC2_SB0119 (120000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_SB0119 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_SB0119 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_SB0119 (115000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_SB0119 (114000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_SB0119 (113000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_SB0119 (111000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_SB0119 (108000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_SB0119 (104000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_SB0119 (100000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_SB0119 (98000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_SB0119 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_SB0119 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_SB0119 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_SB0119 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_SB0119 (80000) /* 10MV */ /* for DVFS OPP table LL/M */ #define CPU_DVFS_FREQ0_LL_M (1391000) /* KHz */ @@ -457,7 +571,7 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ2_LL_M (1287000) /* KHz */ #define CPU_DVFS_FREQ3_LL_M (1222000) /* KHz */ #define CPU_DVFS_FREQ4_LL_M (1118000) /* KHz */ -#define CPU_DVFS_FREQ5_LL_M (1066000) /* KHz */ +#define CPU_DVFS_FREQ5_LL_M (1092000) /* KHz */ #define CPU_DVFS_FREQ6_LL_M (949000) /* KHz */ #define CPU_DVFS_FREQ7_LL_M (897000) /* KHz */ #define CPU_DVFS_FREQ8_LL_M (806000) /* KHz */ @@ -478,7 +592,7 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ5_L_M (1417000) /* KHz */ #define CPU_DVFS_FREQ6_L_M (1274000) /* KHz */ #define CPU_DVFS_FREQ7_L_M (1209000) /* KHz */ -#define CPU_DVFS_FREQ8_L_M (1079000) /* KHz */ +#define CPU_DVFS_FREQ8_L_M (1092000) /* KHz */ #define CPU_DVFS_FREQ9_L_M (949000) /* KHz */ #define CPU_DVFS_FREQ10_L_M (832000) /* KHz */ #define CPU_DVFS_FREQ11_L_M (741000) /* KHz */ @@ -506,39 +620,75 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_FREQ15_CCI_M (169000) /* KHz */ /* for DVFS OPP table B/M */ -#define CPU_DVFS_FREQ0_B_M (2041000) /* KHz */ -#define CPU_DVFS_FREQ1_B_M (1989000) /* KHz */ -#define CPU_DVFS_FREQ2_B_M (1963000) /* KHz */ -#define CPU_DVFS_FREQ3_B_M (1898000) /* KHz */ -#define CPU_DVFS_FREQ4_B_M (1859000) /* KHz */ -#define CPU_DVFS_FREQ5_B_M (1768000) /* KHz */ -#define CPU_DVFS_FREQ6_B_M (1586000) /* KHz */ -#define CPU_DVFS_FREQ7_B_M (1495000) /* KHz */ -#define CPU_DVFS_FREQ8_B_M (1339000) /* KHz */ -#define CPU_DVFS_FREQ9_B_M (1222000) /* KHz */ -#define CPU_DVFS_FREQ10_B_M (1118000) /* KHz */ -#define CPU_DVFS_FREQ11_B_M (1001000) /* KHz */ -#define CPU_DVFS_FREQ12_B_M (897000) /* KHz */ -#define CPU_DVFS_FREQ13_B_M (741000) /* KHz */ -#define CPU_DVFS_FREQ14_B_M (598000) /* KHz */ -#define CPU_DVFS_FREQ15_B_M (304200) /* KHz */ - -#define CPU_IDVFS_FREQ0_B_M (8164) /* Perc */ -#define CPU_IDVFS_FREQ1_B_M (7956) /* Perc */ -#define CPU_IDVFS_FREQ2_B_M (7852) /* Perc */ -#define CPU_IDVFS_FREQ3_B_M (7592) /* Perc */ -#define CPU_IDVFS_FREQ4_B_M (7436) /* Perc */ -#define CPU_IDVFS_FREQ5_B_M (7072) /* Perc */ -#define CPU_IDVFS_FREQ6_B_M (6344) /* Perc */ -#define CPU_IDVFS_FREQ7_B_M (5980) /* Perc */ -#define CPU_IDVFS_FREQ8_B_M (5356) /* Perc */ -#define CPU_IDVFS_FREQ9_B_M (4888) /* Perc */ -#define CPU_IDVFS_FREQ10_B_M (4472) /* Perc */ -#define CPU_IDVFS_FREQ11_B_M (4004) /* Perc */ -#define CPU_IDVFS_FREQ12_B_M (3588) /* Perc */ -#define CPU_IDVFS_FREQ13_B_M (2964) /* Perc */ -#define CPU_IDVFS_FREQ14_B_M (2392) /* Perc */ -#define CPU_IDVFS_FREQ15_B_M (1216) /* Perc */ +/* 1221 */ +#define CPU_DVFS_FREQ0_B_M1221 (1950000) /* KHz */ +#define CPU_DVFS_FREQ1_B_M1221 (1898000) /* KHz */ +#define CPU_DVFS_FREQ2_B_M1221 (1859000) /* KHz */ +#define CPU_DVFS_FREQ3_B_M1221 (1807000) /* KHz */ +#define CPU_DVFS_FREQ4_B_M1221 (1768000) /* KHz */ +#define CPU_DVFS_FREQ5_B_M1221 (1677000) /* KHz */ +#define CPU_DVFS_FREQ6_B_M1221 (1495000) /* KHz */ +#define CPU_DVFS_FREQ7_B_M1221 (1404000) /* KHz */ +#define CPU_DVFS_FREQ8_B_M1221 (1274000) /* KHz */ +#define CPU_DVFS_FREQ9_B_M1221 (1170000) /* KHz */ +#define CPU_DVFS_FREQ10_B_M1221 (1066000) /* KHz */ +#define CPU_DVFS_FREQ11_B_M1221 (962000) /* KHz */ +#define CPU_DVFS_FREQ12_B_M1221 (858000) /* KHz */ +#define CPU_DVFS_FREQ13_B_M1221 (715000) /* KHz */ +#define CPU_DVFS_FREQ14_B_M1221 (572000) /* KHz */ +#define CPU_DVFS_FREQ15_B_M1221 (304200) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_M1221 (7800) /* Perc */ +#define CPU_IDVFS_FREQ1_B_M1221 (7592) /* Perc */ +#define CPU_IDVFS_FREQ2_B_M1221 (7436) /* Perc */ +#define CPU_IDVFS_FREQ3_B_M1221 (7228) /* Perc */ +#define CPU_IDVFS_FREQ4_B_M1221 (7072) /* Perc */ +#define CPU_IDVFS_FREQ5_B_M1221 (6708) /* Perc */ +#define CPU_IDVFS_FREQ6_B_M1221 (5980) /* Perc */ +#define CPU_IDVFS_FREQ7_B_M1221 (5616) /* Perc */ +#define CPU_IDVFS_FREQ8_B_M1221 (5096) /* Perc */ +#define CPU_IDVFS_FREQ9_B_M1221 (4680) /* Perc */ +#define CPU_IDVFS_FREQ10_B_M1221 (4264) /* Perc */ +#define CPU_IDVFS_FREQ11_B_M1221 (3848) /* Perc */ +#define CPU_IDVFS_FREQ12_B_M1221 (3432) /* Perc */ +#define CPU_IDVFS_FREQ13_B_M1221 (2860) /* Perc */ +#define CPU_IDVFS_FREQ14_B_M1221 (2288) /* Perc */ +#define CPU_IDVFS_FREQ15_B_M1221 (1216) /* Perc */ + +/* 0119 */ +#define CPU_DVFS_FREQ0_B_M0119 (2106000) /* KHz */ +#define CPU_DVFS_FREQ1_B_M0119 (1989000) /* KHz */ +#define CPU_DVFS_FREQ2_B_M0119 (1963000) /* KHz */ +#define CPU_DVFS_FREQ3_B_M0119 (1898000) /* KHz */ +#define CPU_DVFS_FREQ4_B_M0119 (1859000) /* KHz */ +#define CPU_DVFS_FREQ5_B_M0119 (1768000) /* KHz */ +#define CPU_DVFS_FREQ6_B_M0119 (1586000) /* KHz */ +#define CPU_DVFS_FREQ7_B_M0119 (1495000) /* KHz */ +#define CPU_DVFS_FREQ8_B_M0119 (1339000) /* KHz */ +#define CPU_DVFS_FREQ9_B_M0119 (1222000) /* KHz */ +#define CPU_DVFS_FREQ10_B_M0119 (1118000) /* KHz */ +#define CPU_DVFS_FREQ11_B_M0119 (1001000) /* KHz */ +#define CPU_DVFS_FREQ12_B_M0119 (897000) /* KHz */ +#define CPU_DVFS_FREQ13_B_M0119 (741000) /* KHz */ +#define CPU_DVFS_FREQ14_B_M0119 (598000) /* KHz */ +#define CPU_DVFS_FREQ15_B_M0119 (304200) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_M0119 (8424) /* Perc */ +#define CPU_IDVFS_FREQ1_B_M0119 (7956) /* Perc */ +#define CPU_IDVFS_FREQ2_B_M0119 (7852) /* Perc */ +#define CPU_IDVFS_FREQ3_B_M0119 (7592) /* Perc */ +#define CPU_IDVFS_FREQ4_B_M0119 (7436) /* Perc */ +#define CPU_IDVFS_FREQ5_B_M0119 (7072) /* Perc */ +#define CPU_IDVFS_FREQ6_B_M0119 (6344) /* Perc */ +#define CPU_IDVFS_FREQ7_B_M0119 (5980) /* Perc */ +#define CPU_IDVFS_FREQ8_B_M0119 (5356) /* Perc */ +#define CPU_IDVFS_FREQ9_B_M0119 (4888) /* Perc */ +#define CPU_IDVFS_FREQ10_B_M0119 (4472) /* Perc */ +#define CPU_IDVFS_FREQ11_B_M0119 (4004) /* Perc */ +#define CPU_IDVFS_FREQ12_B_M0119 (3588) /* Perc */ +#define CPU_IDVFS_FREQ13_B_M0119 (2964) /* Perc */ +#define CPU_IDVFS_FREQ14_B_M0119 (2392) /* Perc */ +#define CPU_IDVFS_FREQ15_B_M0119 (1216) /* Perc */ /* for DVFS OPP table LL|L|CCI */ #define CPU_DVFS_VOLT0_VPROC1_M (120000) /* 10MV */ @@ -550,7 +700,7 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_VOLT6_VPROC1_M (102000) /* 10MV */ #define CPU_DVFS_VOLT7_VPROC1_M (100000) /* 10MV */ #define CPU_DVFS_VOLT8_VPROC1_M (97000) /* 10MV */ -#define CPU_DVFS_VOLT9_VPROC1_M (93000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC1_M (94000) /* 10MV */ #define CPU_DVFS_VOLT10_VPROC1_M (90000) /* 10MV */ #define CPU_DVFS_VOLT11_VPROC1_M (88000) /* 10MV */ #define CPU_DVFS_VOLT12_VPROC1_M (85000) /* 10MV */ @@ -559,22 +709,164 @@ ktime_t max[NR_SET_V_F]; #define CPU_DVFS_VOLT15_VPROC1_M (78000) /* 10MV */ /* for DVFS OPP table B */ -#define CPU_DVFS_VOLT0_VPROC2_M (118000) /* 10MV */ -#define CPU_DVFS_VOLT1_VPROC2_M (117000) /* 10MV */ -#define CPU_DVFS_VOLT2_VPROC2_M (116000) /* 10MV */ -#define CPU_DVFS_VOLT3_VPROC2_M (114000) /* 10MV */ -#define CPU_DVFS_VOLT4_VPROC2_M (113000) /* 10MV */ -#define CPU_DVFS_VOLT5_VPROC2_M (111000) /* 10MV */ -#define CPU_DVFS_VOLT6_VPROC2_M (107000) /* 10MV */ -#define CPU_DVFS_VOLT7_VPROC2_M (104000) /* 10MV */ -#define CPU_DVFS_VOLT8_VPROC2_M (100000) /* 10MV */ -#define CPU_DVFS_VOLT9_VPROC2_M (98000) /* 10MV */ -#define CPU_DVFS_VOLT10_VPROC2_M (95000) /* 10MV */ -#define CPU_DVFS_VOLT11_VPROC2_M (93000) /* 10MV */ -#define CPU_DVFS_VOLT12_VPROC2_M (90000) /* 10MV */ -#define CPU_DVFS_VOLT13_VPROC2_M (88000) /* 10MV */ -#define CPU_DVFS_VOLT14_VPROC2_M (85000) /* 10MV */ -#define CPU_DVFS_VOLT15_VPROC2_M (80000) /* 10MV */ +/* 1221 */ +#define CPU_DVFS_VOLT0_VPROC2_M1221 (118000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_M1221 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_M1221 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_M1221 (114000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_M1221 (113000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_M1221 (111000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_M1221 (107000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_M1221 (104000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_M1221 (100000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_M1221 (98000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_M1221 (95000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_M1221 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_M1221 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_M1221 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_M1221 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_M1221 (80000) /* 10MV */ + +/* 0119 */ +#define CPU_DVFS_VOLT0_VPROC2_M0119 (120000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_M0119 (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_M0119 (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_M0119 (114000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_M0119 (113000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_M0119 (111000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_M0119 (107000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_M0119 (105000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_M0119 (100000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_M0119 (98000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_M0119 (95000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_M0119 (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_M0119 (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_M0119 (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_M0119 (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_M0119 (80000) /* 10MV */ + +/* for DVFS OPP table LL/L */ +#define CPU_DVFS_FREQ0_LL_L (1391000) /* KHz */ +#define CPU_DVFS_FREQ1_LL_L (1339000) /* KHz */ +#define CPU_DVFS_FREQ2_LL_L (1287000) /* KHz */ +#define CPU_DVFS_FREQ3_LL_L (1222000) /* KHz */ +#define CPU_DVFS_FREQ4_LL_L (1118000) /* KHz */ +#define CPU_DVFS_FREQ5_LL_L (1092000) /* KHz */ +#define CPU_DVFS_FREQ6_LL_L (949000) /* KHz */ +#define CPU_DVFS_FREQ7_LL_L (897000) /* KHz */ +#define CPU_DVFS_FREQ8_LL_L (806000) /* KHz */ +#define CPU_DVFS_FREQ9_LL_L (715000) /* KHz */ +#define CPU_DVFS_FREQ10_LL_L (624000) /* KHz */ +#define CPU_DVFS_FREQ11_LL_L (559000) /* KHz */ +#define CPU_DVFS_FREQ12_LL_L (481000) /* KHz */ +#define CPU_DVFS_FREQ13_LL_L (416000) /* KHz */ +#define CPU_DVFS_FREQ14_LL_L (338000) /* KHz */ +#define CPU_DVFS_FREQ15_LL_L (221000) /* KHz */ + +/* for DVFS OPP table L/M */ +#define CPU_DVFS_FREQ0_L_L (1599000) /* KHz */ +#define CPU_DVFS_FREQ1_L_L (1534000) /* KHz */ +#define CPU_DVFS_FREQ2_L_L (1456000) /* KHz */ +#define CPU_DVFS_FREQ3_L_L (1378000) /* KHz */ +#define CPU_DVFS_FREQ4_L_L (1274000) /* KHz */ +#define CPU_DVFS_FREQ5_L_L (1209000) /* KHz */ +#define CPU_DVFS_FREQ6_L_L (1092000) /* KHz */ +#define CPU_DVFS_FREQ7_L_L (1092000) /* KHz */ +#define CPU_DVFS_FREQ8_L_L (936000) /* KHz */ +#define CPU_DVFS_FREQ9_L_L (845000) /* KHz */ +#define CPU_DVFS_FREQ10_L_L (754000) /* KHz */ +#define CPU_DVFS_FREQ11_L_L (689000) /* KHz */ +#define CPU_DVFS_FREQ12_L_L (611000) /* KHz */ +#define CPU_DVFS_FREQ13_L_L (546000) /* KHz */ +#define CPU_DVFS_FREQ14_L_L (468000) /* KHz */ +#define CPU_DVFS_FREQ15_L_L (325000) /* KHz */ + +/* for DVFS OPP table CCI/M */ +#define CPU_DVFS_FREQ0_CCI_L (806000) /* KHz */ +#define CPU_DVFS_FREQ1_CCI_L (767000) /* KHz */ +#define CPU_DVFS_FREQ2_CCI_L (728000) /* KHz */ +#define CPU_DVFS_FREQ3_CCI_L (689000) /* KHz */ +#define CPU_DVFS_FREQ4_CCI_L (637000) /* KHz */ +#define CPU_DVFS_FREQ5_CCI_L (611000) /* KHz */ +#define CPU_DVFS_FREQ6_CCI_L (546000) /* KHz */ +#define CPU_DVFS_FREQ7_CCI_L (520000) /* KHz */ +#define CPU_DVFS_FREQ8_CCI_L (468000) /* KHz */ +#define CPU_DVFS_FREQ9_CCI_L (429000) /* KHz */ +#define CPU_DVFS_FREQ10_CCI_L (377000) /* KHz */ +#define CPU_DVFS_FREQ11_CCI_L (338000) /* KHz */ +#define CPU_DVFS_FREQ12_CCI_L (312000) /* KHz */ +#define CPU_DVFS_FREQ13_CCI_L (273000) /* KHz */ +#define CPU_DVFS_FREQ14_CCI_L (234000) /* KHz */ +#define CPU_DVFS_FREQ15_CCI_L (169000) /* KHz */ + +#define CPU_DVFS_FREQ0_B_L (1794000) /* KHz */ +#define CPU_DVFS_FREQ1_B_L (1729000) /* KHz */ +#define CPU_DVFS_FREQ2_B_L (1690000) /* KHz */ +#define CPU_DVFS_FREQ3_B_L (1625000) /* KHz */ +#define CPU_DVFS_FREQ4_B_L (1573000) /* KHz */ +#define CPU_DVFS_FREQ5_B_L (1495000) /* KHz */ +#define CPU_DVFS_FREQ6_B_L (1339000) /* KHz */ +#define CPU_DVFS_FREQ7_B_L (1261000) /* KHz */ +#define CPU_DVFS_FREQ8_B_L (1092000) /* KHz */ +#define CPU_DVFS_FREQ9_B_L (949000) /* KHz */ +#define CPU_DVFS_FREQ10_B_L (897000) /* KHz */ +#define CPU_DVFS_FREQ11_B_L (793000) /* KHz */ +#define CPU_DVFS_FREQ12_B_L (702000) /* KHz */ +#define CPU_DVFS_FREQ13_B_L (598000) /* KHz */ +#define CPU_DVFS_FREQ14_B_L (507000) /* KHz */ +#define CPU_DVFS_FREQ15_B_L (304200) /* KHz */ + +#define CPU_IDVFS_FREQ0_B_L (7176) /* Perc */ +#define CPU_IDVFS_FREQ1_B_L (6916) /* Perc */ +#define CPU_IDVFS_FREQ2_B_L (6760) /* Perc */ +#define CPU_IDVFS_FREQ3_B_L (6500) /* Perc */ +#define CPU_IDVFS_FREQ4_B_L (6292) /* Perc */ +#define CPU_IDVFS_FREQ5_B_L (5980) /* Perc */ +#define CPU_IDVFS_FREQ6_B_L (5356) /* Perc */ +#define CPU_IDVFS_FREQ7_B_L (5044) /* Perc */ +#define CPU_IDVFS_FREQ8_B_L (4368) /* Perc */ +#define CPU_IDVFS_FREQ9_B_L (3796) /* Perc */ +#define CPU_IDVFS_FREQ10_B_L (3588) /* Perc */ +#define CPU_IDVFS_FREQ11_B_L (3172) /* Perc */ +#define CPU_IDVFS_FREQ12_B_L (2808) /* Perc */ +#define CPU_IDVFS_FREQ13_B_L (2392) /* Perc */ +#define CPU_IDVFS_FREQ14_B_L (2028) /* Perc */ +#define CPU_IDVFS_FREQ15_B_L (1216) /* Perc */ + +#define CPU_DVFS_VOLT0_VPROC1_L (120000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC1_L (118000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC1_L (115000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC1_L (113000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC1_L (109000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC1_L (107000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC1_L (102000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC1_L (100000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC1_L (97000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC1_L (94000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC1_L (90000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC1_L (88000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC1_L (85000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC1_L (83000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC1_L (80000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC1_L (78000) /* 10MV */ + +/* for DVFS OPP table B */ +#define CPU_DVFS_VOLT0_VPROC2_L (120000) /* 10MV */ +#define CPU_DVFS_VOLT1_VPROC2_L (117000) /* 10MV */ +#define CPU_DVFS_VOLT2_VPROC2_L (116000) /* 10MV */ +#define CPU_DVFS_VOLT3_VPROC2_L (114000) /* 10MV */ +#define CPU_DVFS_VOLT4_VPROC2_L (113000) /* 10MV */ +#define CPU_DVFS_VOLT5_VPROC2_L (111000) /* 10MV */ +#define CPU_DVFS_VOLT6_VPROC2_L (107000) /* 10MV */ +#define CPU_DVFS_VOLT7_VPROC2_L (105000) /* 10MV */ +#define CPU_DVFS_VOLT8_VPROC2_L (100000) /* 10MV */ +#define CPU_DVFS_VOLT9_VPROC2_L (98000) /* 10MV */ +#define CPU_DVFS_VOLT10_VPROC2_L (95000) /* 10MV */ +#define CPU_DVFS_VOLT11_VPROC2_L (93000) /* 10MV */ +#define CPU_DVFS_VOLT12_VPROC2_L (90000) /* 10MV */ +#define CPU_DVFS_VOLT13_VPROC2_L (88000) /* 10MV */ +#define CPU_DVFS_VOLT14_VPROC2_L (85000) /* 10MV */ +#define CPU_DVFS_VOLT15_VPROC2_L (80000) /* 10MV */ #define CPUFREQ_LAST_FREQ_LEVEL (CPU_DVFS_FREQ15_CCI_FY) @@ -704,7 +996,21 @@ int thres_b = 0; #define CPU_LEVEL_3 (0x3) #define CPU_LV_TO_OPP_IDX(lv) ((lv)) /* cpu_level to opp_idx */ +#define DATE_CODE_EFUSE_INDEX (61) +#define DATE_CODE_1221 (0x0) +#define DATE_CODE_0119 (0x1) + #ifdef __KERNEL__ +static unsigned int _mt_cpufreq_get_cpu_date_code(void) +{ + unsigned int date_code_0 = _GET_BITS_VAL_(7:4, get_devinfo_with_index(DATE_CODE_EFUSE_INDEX)); + + if (date_code_0 < 7) + return DATE_CODE_1221; + else + return DATE_CODE_0119; +} +int is_tt_segment = 0; static unsigned int _mt_cpufreq_get_cpu_level(void) { unsigned int lv = 0; @@ -720,6 +1026,12 @@ static unsigned int _mt_cpufreq_get_cpu_level(void) lv = CPU_LEVEL_1; else if ((func_code_1 == 2) || (func_code_1 == 7)) lv = CPU_LEVEL_2; + else if (func_code_1 == 0x0F) + lv = CPU_LEVEL_3; + else if (func_code_1 == 4) { + lv = CPU_LEVEL_1; + is_tt_segment = 1; + } else lv = CPU_LEVEL_0; @@ -811,10 +1123,10 @@ EXPORT_SYMBOL(mt_cpufreq_setvolt_registerCB); .clk_div = clk, \ } struct mt_cpu_freq_method { - const unsigned int target_f; - const unsigned int vco_dds; - const unsigned int pos_div; - const unsigned int clk_div; + unsigned int target_f; + unsigned int vco_dds; + unsigned int pos_div; + unsigned int clk_div; }; struct opp_idx_tbl { @@ -837,9 +1149,9 @@ struct opp_idx_tbl opp_tbl_m[NR_OPP_IDX]; } struct mt_cpu_freq_info { - const unsigned int cpufreq_khz; + unsigned int cpufreq_khz; unsigned int cpufreq_volt; - const unsigned int cpufreq_volt_org; + unsigned int cpufreq_volt_org; }; struct mt_cpu_dvfs { @@ -1128,10 +1440,37 @@ static void aee_record_cpu_dvfs_out(enum mt_cpu_dvfs_id id) static void aee_record_cpu_dvfs_step(unsigned int step) { #ifdef CONFIG_CPU_DVFS_AEE_RR_REC - if (step == 0) + int i; + + if (step == 0) { aee_rr_rec_cpu_dvfs_step(aee_rr_curr_cpu_dvfs_step() & 0xF0); - else + dvfs_step_delta[step] = ktime_sub(ktime_get(), start_ktime_dvfs); + start_ktime_dvfs.tv64 = 0; + } else if (step == 1) { + aee_rr_rec_cpu_dvfs_step((aee_rr_curr_cpu_dvfs_step() & 0xF0) | (step)); + /* Clean dvfs_step_delta[16] to 0 */ + for (i = 0; i < 16; i++) + dvfs_step_delta[i].tv64 = 0; + start_ktime_dvfs = ktime_get(); + dvfs_step_delta[step] = ktime_get(); + } else { aee_rr_rec_cpu_dvfs_step((aee_rr_curr_cpu_dvfs_step() & 0xF0) | (step)); + dvfs_step_delta[step] = ktime_sub(ktime_get(), start_ktime_dvfs); + } +#endif +} + +#define LOG_BUF_SIZE 256 +static void aee_record_cpu_dvfs_step_dump(void) +{ +#ifdef CONFIG_CPU_DVFS_AEE_RR_REC + int i; + char buf[LOG_BUF_SIZE]; + char *ptr = buf; + + for (i = 0; i < 16; i++) + ptr += snprintf(ptr, LOG_BUF_SIZE, "[%d]:%lld->", i, ktime_to_us(dvfs_step_delta[i])); + cpufreq_err("dvfs_step = %s\n", buf); #endif } @@ -1148,10 +1487,35 @@ static void aee_record_cci_dvfs_step(unsigned int step) static void aee_record_cpu_dvfs_cb(unsigned int step) { #ifdef CONFIG_CPU_DVFS_AEE_RR_REC - if (step == 0) + int i; + + if (step == 0) { aee_rr_rec_cpu_dvfs_cb(aee_rr_curr_cpu_dvfs_cb() & 0x0); - else + dvfs_cb_step_delta[step] = ktime_sub(ktime_get(), start_ktime_dvfs_cb); + start_ktime_dvfs_cb.tv64 = 0; + } else if (step == 1) { aee_rr_rec_cpu_dvfs_cb((aee_rr_curr_cpu_dvfs_cb() & 0x0) | (step)); + for (i = 0; i < 16; i++) + dvfs_cb_step_delta[i].tv64 = 0; + start_ktime_dvfs_cb = ktime_get(); + dvfs_cb_step_delta[step] = ktime_get(); + } else { + aee_rr_rec_cpu_dvfs_cb((aee_rr_curr_cpu_dvfs_cb() & 0x0) | (step)); + dvfs_cb_step_delta[step] = ktime_sub(ktime_get(), start_ktime_dvfs_cb); + } +#endif +} + +static void aee_record_cpu_dvfs_cb_dump(void) +{ +#ifdef CONFIG_CPU_DVFS_AEE_RR_REC + int i; + char buf[LOG_BUF_SIZE]; + char *ptr = buf; + + for (i = 0; i < 16; i++) + ptr += snprintf(ptr, LOG_BUF_SIZE, "[%d]:%lld->", i, ktime_to_us(dvfs_cb_step_delta[i])); + cpufreq_err("cb_step = %s\n", buf); #endif } @@ -1229,74 +1593,176 @@ static struct mt_cpu_freq_info opp_tbl_##cluster##_e##lv##_0[] = { \ OPP_TBL(LL, FY, 1, 1); OPP_TBL(L, FY, 1, 1); OPP_TBL(CCI, FY, 1, 1); -OPP_TBL(B, FY, 1, 2); +OPP_TBL(B, FY1221, 1, 2); +OPP_TBL(B, FY0119, 4, 2); OPP_TBL(LL, SB, 2, 1); OPP_TBL(L, SB, 2, 1); OPP_TBL(CCI, SB, 2, 1); -OPP_TBL(B, SB, 2, 2); +OPP_TBL(B, SB1221, 2, 2); +OPP_TBL(B, SB0119, 5, 2); OPP_TBL(LL, M, 3, 1); OPP_TBL(L, M, 3, 1); OPP_TBL(CCI, M, 3, 1); -OPP_TBL(B, M, 3, 2); +OPP_TBL(B, M1221, 3, 2); +OPP_TBL(B, M0119, 6, 2); +OPP_TBL(LL, L, 7, 1); +OPP_TBL(L, L, 7, 1); +OPP_TBL(CCI, L, 7, 1); +OPP_TBL(B, L, 8, 2); + #ifdef ENABLE_IDVFS -#define IDVFS_OPP_MAP_FY(idx) CPU_IDVFS_FREQ##idx##_B_FY -#define IDVFS_OPP_MAP_SB(idx) CPU_IDVFS_FREQ##idx##_B_SB -#define IDVFS_OPP_MAP_M(idx) CPU_IDVFS_FREQ##idx##_B_M -static unsigned int idvfs_opp_tbls[3][16] = { +#define IDVFS_OPP_MAP_FY(idx, date) CPU_IDVFS_FREQ##idx##_B_FY##date +#define IDVFS_OPP_MAP_SB(idx, date) CPU_IDVFS_FREQ##idx##_B_SB##date +#define IDVFS_OPP_MAP_M(idx, date) CPU_IDVFS_FREQ##idx##_B_M##date +#define IDVFS_OPP_MAP_L(idx) CPU_IDVFS_FREQ##idx##_B_L +static unsigned int idvfs_opp_tbls_1221[4][16] = { + { + IDVFS_OPP_MAP_FY(0, 1221), + IDVFS_OPP_MAP_FY(1, 1221), + IDVFS_OPP_MAP_FY(2, 1221), + IDVFS_OPP_MAP_FY(3, 1221), + IDVFS_OPP_MAP_FY(4, 1221), + IDVFS_OPP_MAP_FY(5, 1221), + IDVFS_OPP_MAP_FY(6, 1221), + IDVFS_OPP_MAP_FY(7, 1221), + IDVFS_OPP_MAP_FY(8, 1221), + IDVFS_OPP_MAP_FY(9, 1221), + IDVFS_OPP_MAP_FY(10, 1221), + IDVFS_OPP_MAP_FY(11, 1221), + IDVFS_OPP_MAP_FY(12, 1221), + IDVFS_OPP_MAP_FY(13, 1221), + IDVFS_OPP_MAP_FY(14, 1221), + IDVFS_OPP_MAP_FY(15, 1221), + }, { - IDVFS_OPP_MAP_FY(0), - IDVFS_OPP_MAP_FY(1), - IDVFS_OPP_MAP_FY(2), - IDVFS_OPP_MAP_FY(3), - IDVFS_OPP_MAP_FY(4), - IDVFS_OPP_MAP_FY(5), - IDVFS_OPP_MAP_FY(6), - IDVFS_OPP_MAP_FY(7), - IDVFS_OPP_MAP_FY(8), - IDVFS_OPP_MAP_FY(9), - IDVFS_OPP_MAP_FY(10), - IDVFS_OPP_MAP_FY(11), - IDVFS_OPP_MAP_FY(12), - IDVFS_OPP_MAP_FY(13), - IDVFS_OPP_MAP_FY(14), - IDVFS_OPP_MAP_FY(15), + IDVFS_OPP_MAP_SB(0, 1221), + IDVFS_OPP_MAP_SB(1, 1221), + IDVFS_OPP_MAP_SB(2, 1221), + IDVFS_OPP_MAP_SB(3, 1221), + IDVFS_OPP_MAP_SB(4, 1221), + IDVFS_OPP_MAP_SB(5, 1221), + IDVFS_OPP_MAP_SB(6, 1221), + IDVFS_OPP_MAP_SB(7, 1221), + IDVFS_OPP_MAP_SB(8, 1221), + IDVFS_OPP_MAP_SB(9, 1221), + IDVFS_OPP_MAP_SB(10, 1221), + IDVFS_OPP_MAP_SB(11, 1221), + IDVFS_OPP_MAP_SB(12, 1221), + IDVFS_OPP_MAP_SB(13, 1221), + IDVFS_OPP_MAP_SB(14, 1221), + IDVFS_OPP_MAP_SB(15, 1221), }, { - IDVFS_OPP_MAP_SB(0), - IDVFS_OPP_MAP_SB(1), - IDVFS_OPP_MAP_SB(2), - IDVFS_OPP_MAP_SB(3), - IDVFS_OPP_MAP_SB(4), - IDVFS_OPP_MAP_SB(5), - IDVFS_OPP_MAP_SB(6), - IDVFS_OPP_MAP_SB(7), - IDVFS_OPP_MAP_SB(8), - IDVFS_OPP_MAP_SB(9), - IDVFS_OPP_MAP_SB(10), - IDVFS_OPP_MAP_SB(11), - IDVFS_OPP_MAP_SB(12), - IDVFS_OPP_MAP_SB(13), - IDVFS_OPP_MAP_SB(14), - IDVFS_OPP_MAP_SB(15), + IDVFS_OPP_MAP_M(0, 1221), + IDVFS_OPP_MAP_M(1, 1221), + IDVFS_OPP_MAP_M(2, 1221), + IDVFS_OPP_MAP_M(3, 1221), + IDVFS_OPP_MAP_M(4, 1221), + IDVFS_OPP_MAP_M(5, 1221), + IDVFS_OPP_MAP_M(6, 1221), + IDVFS_OPP_MAP_M(7, 1221), + IDVFS_OPP_MAP_M(8, 1221), + IDVFS_OPP_MAP_M(9, 1221), + IDVFS_OPP_MAP_M(10, 1221), + IDVFS_OPP_MAP_M(11, 1221), + IDVFS_OPP_MAP_M(12, 1221), + IDVFS_OPP_MAP_M(13, 1221), + IDVFS_OPP_MAP_M(14, 1221), + IDVFS_OPP_MAP_M(15, 1221), }, { - IDVFS_OPP_MAP_M(0), - IDVFS_OPP_MAP_M(1), - IDVFS_OPP_MAP_M(2), - IDVFS_OPP_MAP_M(3), - IDVFS_OPP_MAP_M(4), - IDVFS_OPP_MAP_M(5), - IDVFS_OPP_MAP_M(6), - IDVFS_OPP_MAP_M(7), - IDVFS_OPP_MAP_M(8), - IDVFS_OPP_MAP_M(9), - IDVFS_OPP_MAP_M(10), - IDVFS_OPP_MAP_M(11), - IDVFS_OPP_MAP_M(12), - IDVFS_OPP_MAP_M(13), - IDVFS_OPP_MAP_M(14), - IDVFS_OPP_MAP_M(15), + IDVFS_OPP_MAP_L(0), + IDVFS_OPP_MAP_L(1), + IDVFS_OPP_MAP_L(2), + IDVFS_OPP_MAP_L(3), + IDVFS_OPP_MAP_L(4), + IDVFS_OPP_MAP_L(5), + IDVFS_OPP_MAP_L(6), + IDVFS_OPP_MAP_L(7), + IDVFS_OPP_MAP_L(8), + IDVFS_OPP_MAP_L(9), + IDVFS_OPP_MAP_L(10), + IDVFS_OPP_MAP_L(11), + IDVFS_OPP_MAP_L(12), + IDVFS_OPP_MAP_L(13), + IDVFS_OPP_MAP_L(14), + IDVFS_OPP_MAP_L(15), + }, +}; + +static unsigned int idvfs_opp_tbls_0119[4][16] = { + { + IDVFS_OPP_MAP_FY(0, 0119), + IDVFS_OPP_MAP_FY(1, 0119), + IDVFS_OPP_MAP_FY(2, 0119), + IDVFS_OPP_MAP_FY(3, 0119), + IDVFS_OPP_MAP_FY(4, 0119), + IDVFS_OPP_MAP_FY(5, 0119), + IDVFS_OPP_MAP_FY(6, 0119), + IDVFS_OPP_MAP_FY(7, 0119), + IDVFS_OPP_MAP_FY(8, 0119), + IDVFS_OPP_MAP_FY(9, 0119), + IDVFS_OPP_MAP_FY(10, 0119), + IDVFS_OPP_MAP_FY(11, 0119), + IDVFS_OPP_MAP_FY(12, 0119), + IDVFS_OPP_MAP_FY(13, 0119), + IDVFS_OPP_MAP_FY(14, 0119), + IDVFS_OPP_MAP_FY(15, 0119), + }, + { + IDVFS_OPP_MAP_SB(0, 0119), + IDVFS_OPP_MAP_SB(1, 0119), + IDVFS_OPP_MAP_SB(2, 0119), + IDVFS_OPP_MAP_SB(3, 0119), + IDVFS_OPP_MAP_SB(4, 0119), + IDVFS_OPP_MAP_SB(5, 0119), + IDVFS_OPP_MAP_SB(6, 0119), + IDVFS_OPP_MAP_SB(7, 0119), + IDVFS_OPP_MAP_SB(8, 0119), + IDVFS_OPP_MAP_SB(9, 0119), + IDVFS_OPP_MAP_SB(10, 0119), + IDVFS_OPP_MAP_SB(11, 0119), + IDVFS_OPP_MAP_SB(12, 0119), + IDVFS_OPP_MAP_SB(13, 0119), + IDVFS_OPP_MAP_SB(14, 0119), + IDVFS_OPP_MAP_SB(15, 0119), + }, + { + IDVFS_OPP_MAP_M(0, 0119), + IDVFS_OPP_MAP_M(1, 0119), + IDVFS_OPP_MAP_M(2, 0119), + IDVFS_OPP_MAP_M(3, 0119), + IDVFS_OPP_MAP_M(4, 0119), + IDVFS_OPP_MAP_M(5, 0119), + IDVFS_OPP_MAP_M(6, 0119), + IDVFS_OPP_MAP_M(7, 0119), + IDVFS_OPP_MAP_M(8, 0119), + IDVFS_OPP_MAP_M(9, 0119), + IDVFS_OPP_MAP_M(10, 0119), + IDVFS_OPP_MAP_M(11, 0119), + IDVFS_OPP_MAP_M(12, 0119), + IDVFS_OPP_MAP_M(13, 0119), + IDVFS_OPP_MAP_M(14, 0119), + IDVFS_OPP_MAP_M(15, 0119), + }, + { + IDVFS_OPP_MAP_L(0), + IDVFS_OPP_MAP_L(1), + IDVFS_OPP_MAP_L(2), + IDVFS_OPP_MAP_L(3), + IDVFS_OPP_MAP_L(4), + IDVFS_OPP_MAP_L(5), + IDVFS_OPP_MAP_L(6), + IDVFS_OPP_MAP_L(7), + IDVFS_OPP_MAP_L(8), + IDVFS_OPP_MAP_L(9), + IDVFS_OPP_MAP_L(10), + IDVFS_OPP_MAP_L(11), + IDVFS_OPP_MAP_L(12), + IDVFS_OPP_MAP_L(13), + IDVFS_OPP_MAP_L(14), + IDVFS_OPP_MAP_L(15), }, }; #endif @@ -1308,8 +1774,8 @@ static struct mt_cpu_freq_method opp_tbl_method_LL_e1[] = { FP(CPU_DVFS_FREQ1_LL_FY, 1, 1), FP(CPU_DVFS_FREQ2_LL_FY, 1, 1), FP(CPU_DVFS_FREQ3_LL_FY, 1, 1), - FP(CPU_DVFS_FREQ4_LL_FY, 2, 1), - FP(CPU_DVFS_FREQ5_LL_FY, 2, 1), + FP(CPU_DVFS_FREQ4_LL_FY, 1, 1), + FP(CPU_DVFS_FREQ5_LL_FY, 1, 1), FP(CPU_DVFS_FREQ6_LL_FY, 2, 1), FP(CPU_DVFS_FREQ7_LL_FY, 2, 1), FP(CPU_DVFS_FREQ8_LL_FY, 2, 1), @@ -1332,7 +1798,7 @@ static struct mt_cpu_freq_method opp_tbl_method_L_e1[] = { FP(CPU_DVFS_FREQ5_L_FY, 1, 1), FP(CPU_DVFS_FREQ6_L_FY, 1, 1), FP(CPU_DVFS_FREQ7_L_FY, 1, 1), - FP(CPU_DVFS_FREQ8_L_FY, 2, 1), + FP(CPU_DVFS_FREQ8_L_FY, 1, 1), FP(CPU_DVFS_FREQ9_L_FY, 2, 1), FP(CPU_DVFS_FREQ10_L_FY, 2, 1), FP(CPU_DVFS_FREQ11_L_FY, 2, 1), @@ -1364,22 +1830,42 @@ static struct mt_cpu_freq_method opp_tbl_method_CCI_e1[] = { static struct mt_cpu_freq_method opp_tbl_method_B_e1[] = { /* Target Frequency, POS, CLK */ - FP(CPU_DVFS_FREQ0_B_FY, 1, 1), - FP(CPU_DVFS_FREQ1_B_FY, 1, 1), - FP(CPU_DVFS_FREQ2_B_FY, 1, 1), - FP(CPU_DVFS_FREQ3_B_FY, 1, 1), - FP(CPU_DVFS_FREQ4_B_FY, 1, 1), - FP(CPU_DVFS_FREQ5_B_FY, 1, 1), - FP(CPU_DVFS_FREQ6_B_FY, 1, 1), - FP(CPU_DVFS_FREQ7_B_FY, 1, 1), - FP(CPU_DVFS_FREQ8_B_FY, 1, 1), - FP(CPU_DVFS_FREQ9_B_FY, 1, 1), - FP(CPU_DVFS_FREQ10_B_FY, 1, 1), - FP(CPU_DVFS_FREQ11_B_FY, 2, 1), - FP(CPU_DVFS_FREQ12_B_FY, 2, 1), - FP(CPU_DVFS_FREQ13_B_FY, 2, 1), - FP(CPU_DVFS_FREQ14_B_FY, 2, 1), - FP(CPU_DVFS_FREQ15_B_FY, 2, 2), + FP(CPU_DVFS_FREQ0_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ1_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ2_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ3_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ4_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ5_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ6_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ7_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ8_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ9_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ10_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ11_B_FY1221, 1, 1), + FP(CPU_DVFS_FREQ12_B_FY1221, 2, 1), + FP(CPU_DVFS_FREQ13_B_FY1221, 2, 1), + FP(CPU_DVFS_FREQ14_B_FY1221, 2, 1), + FP(CPU_DVFS_FREQ15_B_FY1221, 2, 2), +}; + +static struct mt_cpu_freq_method opp_tbl_method_B_e4[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ1_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ2_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ3_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ4_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ5_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ6_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ7_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ8_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ9_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ10_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ11_B_FY0119, 1, 1), + FP(CPU_DVFS_FREQ12_B_FY0119, 2, 1), + FP(CPU_DVFS_FREQ13_B_FY0119, 2, 1), + FP(CPU_DVFS_FREQ14_B_FY0119, 2, 1), + FP(CPU_DVFS_FREQ15_B_FY0119, 2, 2), }; static struct mt_cpu_freq_method opp_tbl_method_LL_e2[] = { @@ -1391,7 +1877,7 @@ static struct mt_cpu_freq_method opp_tbl_method_LL_e2[] = { FP(CPU_DVFS_FREQ4_LL_SB, 1, 1), FP(CPU_DVFS_FREQ5_LL_SB, 1, 1), FP(CPU_DVFS_FREQ6_LL_SB, 1, 1), - FP(CPU_DVFS_FREQ7_LL_SB, 2, 1), + FP(CPU_DVFS_FREQ7_LL_SB, 1, 1), FP(CPU_DVFS_FREQ8_LL_SB, 2, 1), FP(CPU_DVFS_FREQ9_LL_SB, 2, 1), FP(CPU_DVFS_FREQ10_LL_SB, 2, 1), @@ -1414,7 +1900,7 @@ static struct mt_cpu_freq_method opp_tbl_method_L_e2[] = { FP(CPU_DVFS_FREQ7_L_SB, 1, 1), FP(CPU_DVFS_FREQ8_L_SB, 1, 1), FP(CPU_DVFS_FREQ9_L_SB, 1, 1), - FP(CPU_DVFS_FREQ10_L_SB, 2, 1), + FP(CPU_DVFS_FREQ10_L_SB, 1, 1), FP(CPU_DVFS_FREQ11_L_SB, 2, 1), FP(CPU_DVFS_FREQ12_L_SB, 2, 1), FP(CPU_DVFS_FREQ13_L_SB, 2, 1), @@ -1444,22 +1930,42 @@ static struct mt_cpu_freq_method opp_tbl_method_CCI_e2[] = { static struct mt_cpu_freq_method opp_tbl_method_B_e2[] = { /* Target Frequency, POS, CLK */ - FP(CPU_DVFS_FREQ0_B_SB, 1, 1), - FP(CPU_DVFS_FREQ1_B_SB, 1, 1), - FP(CPU_DVFS_FREQ2_B_SB, 1, 1), - FP(CPU_DVFS_FREQ3_B_SB, 1, 1), - FP(CPU_DVFS_FREQ4_B_SB, 1, 1), - FP(CPU_DVFS_FREQ5_B_SB, 1, 1), - FP(CPU_DVFS_FREQ6_B_SB, 1, 1), - FP(CPU_DVFS_FREQ7_B_SB, 1, 1), - FP(CPU_DVFS_FREQ8_B_SB, 1, 1), - FP(CPU_DVFS_FREQ9_B_SB, 1, 1), - FP(CPU_DVFS_FREQ10_B_SB, 1, 1), - FP(CPU_DVFS_FREQ11_B_SB, 2, 1), - FP(CPU_DVFS_FREQ12_B_SB, 2, 1), - FP(CPU_DVFS_FREQ13_B_SB, 2, 1), - FP(CPU_DVFS_FREQ14_B_SB, 2, 1), - FP(CPU_DVFS_FREQ15_B_SB, 2, 2), + FP(CPU_DVFS_FREQ0_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ1_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ2_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ3_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ4_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ5_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ6_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ7_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ8_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ9_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ10_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ11_B_SB1221, 1, 1), + FP(CPU_DVFS_FREQ12_B_SB1221, 2, 1), + FP(CPU_DVFS_FREQ13_B_SB1221, 2, 1), + FP(CPU_DVFS_FREQ14_B_SB1221, 2, 1), + FP(CPU_DVFS_FREQ15_B_SB1221, 2, 2), +}; + +static struct mt_cpu_freq_method opp_tbl_method_B_e5[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ1_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ2_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ3_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ4_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ5_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ6_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ7_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ8_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ9_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ10_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ11_B_SB0119, 1, 1), + FP(CPU_DVFS_FREQ12_B_SB0119, 2, 1), + FP(CPU_DVFS_FREQ13_B_SB0119, 2, 1), + FP(CPU_DVFS_FREQ14_B_SB0119, 2, 1), + FP(CPU_DVFS_FREQ15_B_SB0119, 2, 2), }; static struct mt_cpu_freq_method opp_tbl_method_LL_e3[] = { @@ -1468,8 +1974,8 @@ static struct mt_cpu_freq_method opp_tbl_method_LL_e3[] = { FP(CPU_DVFS_FREQ1_LL_M, 1, 1), FP(CPU_DVFS_FREQ2_LL_M, 1, 1), FP(CPU_DVFS_FREQ3_LL_M, 1, 1), - FP(CPU_DVFS_FREQ4_LL_M, 2, 1), - FP(CPU_DVFS_FREQ5_LL_M, 2, 1), + FP(CPU_DVFS_FREQ4_LL_M, 1, 1), + FP(CPU_DVFS_FREQ5_LL_M, 1, 1), FP(CPU_DVFS_FREQ6_LL_M, 2, 1), FP(CPU_DVFS_FREQ7_LL_M, 2, 1), FP(CPU_DVFS_FREQ8_LL_M, 2, 1), @@ -1492,7 +1998,7 @@ static struct mt_cpu_freq_method opp_tbl_method_L_e3[] = { FP(CPU_DVFS_FREQ5_L_M, 1, 1), FP(CPU_DVFS_FREQ6_L_M, 1, 1), FP(CPU_DVFS_FREQ7_L_M, 1, 1), - FP(CPU_DVFS_FREQ8_L_M, 2, 1), + FP(CPU_DVFS_FREQ8_L_M, 1, 1), FP(CPU_DVFS_FREQ9_L_M, 2, 1), FP(CPU_DVFS_FREQ10_L_M, 2, 1), FP(CPU_DVFS_FREQ11_L_M, 2, 1), @@ -1524,85 +2030,255 @@ static struct mt_cpu_freq_method opp_tbl_method_CCI_e3[] = { static struct mt_cpu_freq_method opp_tbl_method_B_e3[] = { /* Target Frequency, POS, CLK */ - FP(CPU_DVFS_FREQ0_B_M, 1, 1), - FP(CPU_DVFS_FREQ1_B_M, 1, 1), - FP(CPU_DVFS_FREQ2_B_M, 1, 1), - FP(CPU_DVFS_FREQ3_B_M, 1, 1), - FP(CPU_DVFS_FREQ4_B_M, 1, 1), - FP(CPU_DVFS_FREQ5_B_M, 1, 1), - FP(CPU_DVFS_FREQ6_B_M, 1, 1), - FP(CPU_DVFS_FREQ7_B_M, 1, 1), - FP(CPU_DVFS_FREQ8_B_M, 1, 1), - FP(CPU_DVFS_FREQ9_B_M, 1, 1), - FP(CPU_DVFS_FREQ10_B_M, 2, 1), - FP(CPU_DVFS_FREQ11_B_M, 2, 1), - FP(CPU_DVFS_FREQ12_B_M, 2, 1), - FP(CPU_DVFS_FREQ13_B_M, 2, 1), - FP(CPU_DVFS_FREQ14_B_M, 2, 1), - FP(CPU_DVFS_FREQ15_B_M, 2, 2), /* should be 1.7 with legacy */ + FP(CPU_DVFS_FREQ0_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ1_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ2_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ3_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ4_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ5_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ6_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ7_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ8_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ9_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ10_B_M1221, 1, 1), + FP(CPU_DVFS_FREQ11_B_M1221, 2, 1), + FP(CPU_DVFS_FREQ12_B_M1221, 2, 1), + FP(CPU_DVFS_FREQ13_B_M1221, 2, 1), + FP(CPU_DVFS_FREQ14_B_M1221, 2, 1), + FP(CPU_DVFS_FREQ15_B_M1221, 2, 2), /* should be 1.7 with legacy */ +}; + +static struct mt_cpu_freq_method opp_tbl_method_B_e6[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ1_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ2_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ3_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ4_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ5_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ6_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ7_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ8_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ9_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ10_B_M0119, 1, 1), + FP(CPU_DVFS_FREQ11_B_M0119, 2, 1), + FP(CPU_DVFS_FREQ12_B_M0119, 2, 1), + FP(CPU_DVFS_FREQ13_B_M0119, 2, 1), + FP(CPU_DVFS_FREQ14_B_M0119, 2, 1), + FP(CPU_DVFS_FREQ15_B_M0119, 2, 2), /* should be 1.7 with legacy */ +}; + +static struct mt_cpu_freq_method opp_tbl_method_LL_e7[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_LL_L, 1, 1), + FP(CPU_DVFS_FREQ1_LL_L, 1, 1), + FP(CPU_DVFS_FREQ2_LL_L, 1, 1), + FP(CPU_DVFS_FREQ3_LL_L, 1, 1), + FP(CPU_DVFS_FREQ4_LL_L, 1, 1), + FP(CPU_DVFS_FREQ5_LL_L, 1, 1), + FP(CPU_DVFS_FREQ6_LL_L, 2, 1), + FP(CPU_DVFS_FREQ7_LL_L, 2, 1), + FP(CPU_DVFS_FREQ8_LL_L, 2, 1), + FP(CPU_DVFS_FREQ9_LL_L, 2, 1), + FP(CPU_DVFS_FREQ10_LL_L, 2, 1), + FP(CPU_DVFS_FREQ11_LL_L, 2, 1), + FP(CPU_DVFS_FREQ12_LL_L, 2, 2), + FP(CPU_DVFS_FREQ13_LL_L, 2, 2), + FP(CPU_DVFS_FREQ14_LL_L, 2, 2), + FP(CPU_DVFS_FREQ15_LL_L, 2, 4), +}; + +static struct mt_cpu_freq_method opp_tbl_method_L_e7[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_L_L, 1, 1), + FP(CPU_DVFS_FREQ1_L_L, 1, 1), + FP(CPU_DVFS_FREQ2_L_L, 1, 1), + FP(CPU_DVFS_FREQ3_L_L, 1, 1), + FP(CPU_DVFS_FREQ4_L_L, 1, 1), + FP(CPU_DVFS_FREQ5_L_L, 1, 1), + FP(CPU_DVFS_FREQ6_L_L, 1, 1), + FP(CPU_DVFS_FREQ7_L_L, 1, 1), + FP(CPU_DVFS_FREQ8_L_L, 2, 1), + FP(CPU_DVFS_FREQ9_L_L, 2, 1), + FP(CPU_DVFS_FREQ10_L_L, 2, 1), + FP(CPU_DVFS_FREQ11_L_L, 2, 1), + FP(CPU_DVFS_FREQ12_L_L, 2, 1), + FP(CPU_DVFS_FREQ13_L_L, 2, 1), + FP(CPU_DVFS_FREQ14_L_L, 2, 2), + FP(CPU_DVFS_FREQ15_L_L, 2, 2), +}; + +static struct mt_cpu_freq_method opp_tbl_method_CCI_e7[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ1_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ2_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ3_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ4_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ5_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ6_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ7_CCI_L, 2, 1), + FP(CPU_DVFS_FREQ8_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ9_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ10_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ11_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ12_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ13_CCI_L, 2, 2), + FP(CPU_DVFS_FREQ14_CCI_L, 2, 4), + FP(CPU_DVFS_FREQ15_CCI_L, 2, 4), +}; + +static struct mt_cpu_freq_method opp_tbl_method_B_e8[] = { + /* Target Frequency, POS, CLK */ + FP(CPU_DVFS_FREQ0_B_L, 1, 1), + FP(CPU_DVFS_FREQ1_B_L, 1, 1), + FP(CPU_DVFS_FREQ2_B_L, 1, 1), + FP(CPU_DVFS_FREQ3_B_L, 1, 1), + FP(CPU_DVFS_FREQ4_B_L, 1, 1), + FP(CPU_DVFS_FREQ5_B_L, 1, 1), + FP(CPU_DVFS_FREQ6_B_L, 1, 1), + FP(CPU_DVFS_FREQ7_B_L, 1, 1), + FP(CPU_DVFS_FREQ8_B_L, 1, 1), + FP(CPU_DVFS_FREQ9_B_L, 2, 1), + FP(CPU_DVFS_FREQ10_B_L, 2, 1), + FP(CPU_DVFS_FREQ11_B_L, 2, 1), + FP(CPU_DVFS_FREQ12_B_L, 2, 1), + FP(CPU_DVFS_FREQ13_B_L, 2, 1), + FP(CPU_DVFS_FREQ14_B_L, 2, 1), + FP(CPU_DVFS_FREQ15_B_L, 2, 2), /* should be 1.7 with legacy */ }; struct opp_tbl_info { - struct mt_cpu_freq_info *const opp_tbl; + struct mt_cpu_freq_info *opp_tbl; const int size; }; -static struct opp_tbl_info opp_tbls[NR_MT_CPU_DVFS][3] = { +static struct opp_tbl_info opp_tbls_1221[NR_MT_CPU_DVFS][4] = { /* LL */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_LL_e1_0, ARRAY_SIZE(opp_tbl_LL_e1_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_LL_e2_0, ARRAY_SIZE(opp_tbl_LL_e2_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_LL_e3_0, ARRAY_SIZE(opp_tbl_LL_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_LL_e7_0, ARRAY_SIZE(opp_tbl_LL_e7_0),}, }, /* L */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_L_e1_0, ARRAY_SIZE(opp_tbl_L_e1_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_L_e2_0, ARRAY_SIZE(opp_tbl_L_e2_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_L_e3_0, ARRAY_SIZE(opp_tbl_L_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_L_e7_0, ARRAY_SIZE(opp_tbl_L_e7_0),}, }, /* B */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_B_e1_0, ARRAY_SIZE(opp_tbl_B_e1_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_B_e2_0, ARRAY_SIZE(opp_tbl_B_e2_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_B_e3_0, ARRAY_SIZE(opp_tbl_B_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_B_e8_0, ARRAY_SIZE(opp_tbl_B_e8_0),}, + }, + /* CCI */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_CCI_e1_0, ARRAY_SIZE(opp_tbl_CCI_e1_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_CCI_e2_0, ARRAY_SIZE(opp_tbl_CCI_e2_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_CCI_e3_0, ARRAY_SIZE(opp_tbl_CCI_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_CCI_e7_0, ARRAY_SIZE(opp_tbl_CCI_e7_0),}, + }, +}; + +static struct opp_tbl_info opp_tbls_0119[NR_MT_CPU_DVFS][4] = { + /* LL */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_LL_e1_0, ARRAY_SIZE(opp_tbl_LL_e1_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_LL_e2_0, ARRAY_SIZE(opp_tbl_LL_e2_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_LL_e3_0, ARRAY_SIZE(opp_tbl_LL_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_LL_e7_0, ARRAY_SIZE(opp_tbl_LL_e7_0),}, + }, + /* L */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_L_e1_0, ARRAY_SIZE(opp_tbl_L_e1_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_L_e2_0, ARRAY_SIZE(opp_tbl_L_e2_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_L_e3_0, ARRAY_SIZE(opp_tbl_L_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_L_e7_0, ARRAY_SIZE(opp_tbl_L_e7_0),}, + }, + /* B */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_B_e4_0, ARRAY_SIZE(opp_tbl_B_e4_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_B_e5_0, ARRAY_SIZE(opp_tbl_B_e5_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_B_e6_0, ARRAY_SIZE(opp_tbl_B_e6_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_B_e8_0, ARRAY_SIZE(opp_tbl_B_e8_0),}, }, /* CCI */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_CCI_e1_0, ARRAY_SIZE(opp_tbl_CCI_e1_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_CCI_e2_0, ARRAY_SIZE(opp_tbl_CCI_e2_0),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_CCI_e3_0, ARRAY_SIZE(opp_tbl_CCI_e3_0),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_CCI_e7_0, ARRAY_SIZE(opp_tbl_CCI_e7_0),}, }, }; struct opp_tbl_m_info { - struct mt_cpu_freq_method *const opp_tbl_m; + struct mt_cpu_freq_method *opp_tbl_m; const int size; }; -static struct opp_tbl_m_info opp_tbls_m[NR_MT_CPU_DVFS][3] = { +static struct opp_tbl_m_info opp_tbls_m_1221[NR_MT_CPU_DVFS][4] = { /* LL */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_LL_e1, ARRAY_SIZE(opp_tbl_method_LL_e1),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_LL_e2, ARRAY_SIZE(opp_tbl_method_LL_e2),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_LL_e3, ARRAY_SIZE(opp_tbl_method_LL_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_LL_e7, ARRAY_SIZE(opp_tbl_method_LL_e7),}, }, /* L */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_L_e1, ARRAY_SIZE(opp_tbl_method_L_e1),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_L_e2, ARRAY_SIZE(opp_tbl_method_L_e2),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_L_e3, ARRAY_SIZE(opp_tbl_method_L_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_L_e7, ARRAY_SIZE(opp_tbl_method_L_e7),}, }, /* B */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_B_e1, ARRAY_SIZE(opp_tbl_method_B_e1),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_B_e2, ARRAY_SIZE(opp_tbl_method_B_e2),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_B_e3, ARRAY_SIZE(opp_tbl_method_B_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_B_e8, ARRAY_SIZE(opp_tbl_method_B_e8),}, }, /* CCI */ { [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_CCI_e1, ARRAY_SIZE(opp_tbl_method_CCI_e1),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_CCI_e2, ARRAY_SIZE(opp_tbl_method_CCI_e2),}, [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_CCI_e3, ARRAY_SIZE(opp_tbl_method_CCI_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_CCI_e7, ARRAY_SIZE(opp_tbl_method_CCI_e7),}, + }, +}; + +static struct opp_tbl_m_info opp_tbls_m_0119[NR_MT_CPU_DVFS][4] = { + /* LL */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_LL_e1, ARRAY_SIZE(opp_tbl_method_LL_e1),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_LL_e2, ARRAY_SIZE(opp_tbl_method_LL_e2),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_LL_e3, ARRAY_SIZE(opp_tbl_method_LL_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_LL_e7, ARRAY_SIZE(opp_tbl_method_LL_e7),}, + }, + /* L */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_L_e1, ARRAY_SIZE(opp_tbl_method_L_e1),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_L_e2, ARRAY_SIZE(opp_tbl_method_L_e2),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_L_e3, ARRAY_SIZE(opp_tbl_method_L_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_L_e7, ARRAY_SIZE(opp_tbl_method_L_e7),}, + }, + /* B */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_B_e4, ARRAY_SIZE(opp_tbl_method_B_e4),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_B_e5, ARRAY_SIZE(opp_tbl_method_B_e5),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_B_e6, ARRAY_SIZE(opp_tbl_method_B_e6),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_B_e8, ARRAY_SIZE(opp_tbl_method_B_e8),}, + }, + /* CCI */ + { + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_0)] = {opp_tbl_method_CCI_e1, ARRAY_SIZE(opp_tbl_method_CCI_e1),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_1)] = {opp_tbl_method_CCI_e2, ARRAY_SIZE(opp_tbl_method_CCI_e2),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_2)] = {opp_tbl_method_CCI_e3, ARRAY_SIZE(opp_tbl_method_CCI_e3),}, + [CPU_LV_TO_OPP_IDX(CPU_LEVEL_3)] = {opp_tbl_method_CCI_e7, ARRAY_SIZE(opp_tbl_method_CCI_e7),}, }, }; @@ -1825,12 +2501,15 @@ int mt_cpufreq_update_volt_b(enum mt_cpu_dvfs_id id, unsigned int *volt_tbl, int BUG_ON(NULL == p); - if (!cpu_dvfs_is_available(p)) { + if (!cpu_dvfs_is_available(p) || p->nr_opp_tbl == 0) { FUNC_EXIT(FUNC_LV_API); return 0; } - BUG_ON(nr_volt_tbl > p->nr_opp_tbl); + if (nr_volt_tbl > p->nr_opp_tbl) { + cpufreq_err("nr_volt_tbl = %d, nr_opp_tbl = %d\n", nr_volt_tbl, p->nr_opp_tbl); + BUG(); + } cpufreq_lock(flags); @@ -1877,12 +2556,16 @@ int mt_cpufreq_update_volt(enum mt_cpu_dvfs_id id, unsigned int *volt_tbl, int n p_l = id_to_cpu_dvfs(MT_CPU_DVFS_L); p_cci = id_to_cpu_dvfs(MT_CPU_DVFS_CCI); - if (!cpu_dvfs_is_available(p_ll) || !cpu_dvfs_is_available(p_l) || !cpu_dvfs_is_available(p_cci)) { + if (!cpu_dvfs_is_available(p_ll) || !cpu_dvfs_is_available(p_l) || !cpu_dvfs_is_available(p_cci) || + p->nr_opp_tbl == 0) { FUNC_EXIT(FUNC_LV_HELP); return 0; } - BUG_ON(nr_volt_tbl > p->nr_opp_tbl); + if (nr_volt_tbl > p->nr_opp_tbl) { + cpufreq_err("nr_volt_tbl = %d, nr_opp_tbl = %d\n", nr_volt_tbl, p->nr_opp_tbl); + BUG(); + } cpufreq_lock(flags); @@ -2002,11 +2685,15 @@ static void _kick_PBM_by_cpu(struct mt_cpu_dvfs *p) #ifdef ENABLE_IDVFS if (!disable_idvfs_flag && cpu_dvfs_is(p, MT_CPU_DVFS_B) && p->armpll_is_available) { - aee_record_cpu_dvfs_cb(14); idvfs_avg = (BigiDVFSSWAvgStatus() / (10000 / IDVFS_FMAX)); + + if (idvfs_avg == 0) + ppm_data[i].freq_idx = -1; + else { ppm_data[i].freq_idx = _search_available_freq_idx(p, idvfs_avg * 1000, CPUFREQ_RELATION_L); cpufreq_ver("iDVFS average freq = %d, idx map to %d\n", idvfs_avg, _search_available_freq_idx(p, idvfs_avg * 1000, CPUFREQ_RELATION_L)); + } } else ppm_data[i].freq_idx = p_dvfs[i]->idx_opp_tbl; #else @@ -2018,11 +2705,7 @@ static void _kick_PBM_by_cpu(struct mt_cpu_dvfs *p) i, ppm_data[i].core_num, ppm_data[i].freq_idx, ppm_data[i].volt); } - aee_record_cpu_dvfs_cb(15); - mt_ppm_dlpt_kick_PBM(ppm_data, (unsigned int)arch_get_nr_clusters()); - - aee_record_cpu_dvfs_cb(0); #endif } #endif @@ -2475,7 +3158,19 @@ static void idvfs_set_cur_freq(struct mt_cpu_dvfs *p, unsigned int cur_khz, unsi if (idx < 0) idx = 0; - ret = BigIDVFSFreq(idvfs_opp_tbls[p->cpu_level][idx]); + if (_mt_cpufreq_get_cpu_date_code() == DATE_CODE_1221) + ret = BigIDVFSFreq(idvfs_opp_tbls_1221[p->cpu_level][idx]); + else { + if (is_tt_segment) { + if (idx == 0) + ret = BigIDVFSFreq(10348); + else if (idx == 1) + ret = BigIDVFSFreq(9724); + else + ret = BigIDVFSFreq(idvfs_opp_tbls_0119[p->cpu_level][idx]); + } else + ret = BigIDVFSFreq(idvfs_opp_tbls_0119[p->cpu_level][idx]); + } } #endif @@ -3325,7 +4020,7 @@ static unsigned int _calc_new_opp_idx(struct mt_cpu_dvfs *p, int new_opp_idx); static unsigned int _calc_new_cci_opp_idx(struct mt_cpu_dvfs *p, int new_opp_idx, unsigned int *target_cci_volt); -static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id id, int new_opp_idx) +static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id id, int new_opp_idx, int lock) { unsigned long flags; struct mt_cpu_dvfs *p = id_to_cpu_dvfs(id); @@ -3342,6 +4037,7 @@ static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id i int ret = -1; unsigned int target_volt_vpro1 = 0; int log = 1; + int ignore_new_opp_idx = 0; FUNC_ENTER(FUNC_LV_LOCAL); @@ -3357,10 +4053,12 @@ static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id i id_cci = MT_CPU_DVFS_CCI; p_cci = id_to_cpu_dvfs(id_cci); - cpufreq_lock(flags); + if (lock) + cpufreq_lock(flags); if (p->dvfs_disable_by_suspend || p->armpll_is_available != 1) { - cpufreq_unlock(flags); + if (lock) + cpufreq_unlock(flags); return; } @@ -3371,6 +4069,16 @@ static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id i log = 0; } + if (new_opp_idx == -2) { + policy = p->mt_policy; + if (cpu_dvfs_is(p, MT_CPU_DVFS_B)) + new_opp_idx = 13; + else + new_opp_idx = 12; + ignore_new_opp_idx = 1; + log = 1; + } + if (do_dvfs_stress_test) { new_opp_idx = jiffies & 0xF; @@ -3389,8 +4097,10 @@ static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id i if (cpu_dvfs_is(p, MT_CPU_DVFS_B)) if (new_opp_idx < p_b->idx_opp_ppm_limit) new_opp_idx = p_b->idx_opp_ppm_limit; - } else - new_opp_idx = _calc_new_opp_idx(id_to_cpu_dvfs(id), new_opp_idx); + } else { + if (ignore_new_opp_idx == 0) + new_opp_idx = _calc_new_opp_idx(id_to_cpu_dvfs(id), new_opp_idx); + } if (abs(new_opp_idx - p->idx_opp_tbl) < 5 && new_opp_idx != 0 && new_opp_idx != p->nr_opp_tbl - 1) @@ -3430,13 +4140,14 @@ static void _mt_cpufreq_set(struct cpufreq_policy *policy, enum mt_cpu_dvfs_id i aee_record_freq_idx(p_cci, p_cci->idx_opp_tbl); #endif + if (lock) + cpufreq_unlock(flags); + #ifndef DISABLE_PBM_FEATURE - if (!ret && !p->dvfs_disable_by_suspend) + if (!ret && !p->dvfs_disable_by_suspend && lock) _kick_PBM_by_cpu(p); #endif - cpufreq_unlock(flags); - FUNC_EXIT(FUNC_LV_LOCAL); } @@ -3841,14 +4552,11 @@ UNLOCK_DD: if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN || action == CPU_DEAD || action == CPU_DEAD_FROZEN) { - cpufreq_lock(flags); - aee_record_cpu_dvfs_cb(13); if (!p->dvfs_disable_by_suspend) _kick_PBM_by_cpu(p); - cpufreq_unlock(flags); } #endif } @@ -4075,6 +4783,41 @@ static unsigned int _calc_new_cci_opp_idx(struct mt_cpu_dvfs *p, int new_opp_idx return new_cci_opp_idx; } +#define PPM_DVFS_LATENCY_DEBUG 1 + +#ifdef PPM_DVFS_LATENCY_DEBUG +#include <linux/time.h> +#include <linux/hrtimer.h> + +#define DVFS_LATENCY_TIMEOUT (500) +#define MS_TO_NS(x) (x * 1E6L) + +static struct hrtimer ppm_hrtimer; + +static void ppm_main_start_hrtimer(void) +{ + ktime_t ktime = ktime_set(0, MS_TO_NS(DVFS_LATENCY_TIMEOUT)); + + hrtimer_start(&ppm_hrtimer, ktime, HRTIMER_MODE_REL); +} + +static void ppm_main_cancel_hrtimer(void) +{ + hrtimer_cancel(&ppm_hrtimer); +} + +static enum hrtimer_restart ppm_hrtimer_cb(struct hrtimer *timer) +{ + cpufreq_dbg("PPM callback over %d ms(cur:%lld), cpu_dvfs_step = 0x%x, cpu_dvfs_cb = 0x%x\n", + DVFS_LATENCY_TIMEOUT, ktime_to_us(ktime_get()), aee_rr_curr_cpu_dvfs_step(), + aee_rr_curr_cpu_dvfs_cb()); + aee_record_cpu_dvfs_step_dump(); + aee_record_cpu_dvfs_cb_dump(); + /* BUG(); */ + + return HRTIMER_NORESTART; +} +#endif #if 1 static void ppm_limit_callback(struct ppm_client_req req) @@ -4085,12 +4828,15 @@ static void ppm_limit_callback(struct ppm_client_req req) struct mt_cpu_dvfs *p; int ignore_ppm[NR_MT_CPU_DVFS] = {0}; unsigned int i; + int kick = 0; if (dvfs_disable_flag) return; cpufreq_ver("get feedback from PPM module\n"); + ppm_main_start_hrtimer(); + cpufreq_lock(flags); for (i = 0; i < ppm->cluster_num; i++) { cpufreq_ver("[%d]:cluster_id = %d, cpu_id = %d, min_cpufreq_idx = %d, max_cpufreq_idx = %d\n", @@ -4130,7 +4876,7 @@ static void ppm_limit_callback(struct ppm_client_req req) } for_each_cpu_dvfs_only(i, p) { - if (p->armpll_is_available) { + if (p->armpll_is_available && p->mt_policy->governor) { if (p->idx_opp_ppm_limit == -1) p->mt_policy->max = cpu_dvfs_get_max_freq(p); else @@ -4139,15 +4885,19 @@ static void ppm_limit_callback(struct ppm_client_req req) p->mt_policy->min = cpu_dvfs_get_min_freq(p); else p->mt_policy->min = cpu_dvfs_get_freq_by_idx(p, p->idx_opp_ppm_base); + + if (!ignore_ppm[i]) { + _mt_cpufreq_set(p->mt_policy, i, -1, 0); + kick = 1; + } } } - cpufreq_unlock(flags); - for_each_cpu_dvfs_only(i, p) - if (!ignore_ppm[i]) - _mt_cpufreq_set(p->mt_policy, i, -1); + ppm_main_cancel_hrtimer(); + if (!p->dvfs_disable_by_suspend && kick) + _kick_PBM_by_cpu(p); } #endif @@ -4196,7 +4946,7 @@ static int _mt_cpufreq_target(struct cpufreq_policy *policy, unsigned int target ) return -EINVAL; - _mt_cpufreq_set(policy, id, new_opp_idx); + _mt_cpufreq_set(policy, id, new_opp_idx, 1); FUNC_EXIT(FUNC_LV_MODULE); @@ -4241,7 +4991,17 @@ static int _mt_cpufreq_init(struct cpufreq_policy *policy) cpufreq_ver("DVFS: _mt_cpufreq_init: %s(cpu_id = %d)\n", cpu_dvfs_get_name(p), p->cpu_id); - opp_tbl_info = &opp_tbls[id][CPU_LV_TO_OPP_IDX(lv)]; + if (_mt_cpufreq_get_cpu_date_code() == DATE_CODE_1221) + opp_tbl_info = &opp_tbls_1221[id][CPU_LV_TO_OPP_IDX(lv)]; + else { + opp_tbl_info = &opp_tbls_0119[id][CPU_LV_TO_OPP_IDX(lv)]; + if (id == MT_CPU_DVFS_B && is_tt_segment && lv == CPU_LEVEL_1) { + opp_tbl_info->opp_tbl[0].cpufreq_khz = 2587000; + opp_tbl_info->opp_tbl[1].cpufreq_khz = 2431000; + opp_tbl_info->opp_tbl[1].cpufreq_volt = 118000; + opp_tbl_info->opp_tbl[1].cpufreq_volt_org = 118000; + } + } BUG_ON(NULL == p); BUG_ON(! @@ -4283,7 +5043,19 @@ static int _mt_cpufreq_init(struct cpufreq_policy *policy) p->idx_normal_max_opp = p->idx_opp_tbl; aee_record_cpufreq_cb(9); - opp_tbl_m_info = &opp_tbls_m[id][CPU_LV_TO_OPP_IDX(lv)]; + + if (_mt_cpufreq_get_cpu_date_code() == DATE_CODE_1221) + opp_tbl_m_info = &opp_tbls_m_1221[id][CPU_LV_TO_OPP_IDX(lv)]; + else { + opp_tbl_m_info = &opp_tbls_m_0119[id][CPU_LV_TO_OPP_IDX(lv)]; + if (id == MT_CPU_DVFS_B && is_tt_segment && lv == CPU_LEVEL_1) { + opp_tbl_m_info->opp_tbl_m[0].target_f = 2587000; + opp_tbl_m_info->opp_tbl_m[1].target_f = 2431000; + opp_tbl_m_info->opp_tbl_m[0].vco_dds = 2587000; + opp_tbl_m_info->opp_tbl_m[1].vco_dds = 2431000; + } + } + p->freq_tbl = opp_tbl_m_info->opp_tbl_m; cpufreq_lock(flags); @@ -4314,7 +5086,11 @@ static int _mt_cpufreq_init(struct cpufreq_policy *policy) if (p_cci->idx_normal_max_opp == -1) p_cci->idx_normal_max_opp = p_cci->idx_opp_tbl; - opp_tbl_m_cci_info = &opp_tbls_m[id_cci][CPU_LV_TO_OPP_IDX(lv)]; + if (_mt_cpufreq_get_cpu_date_code() == DATE_CODE_1221) + opp_tbl_m_cci_info = &opp_tbls_m_1221[id_cci][CPU_LV_TO_OPP_IDX(lv)]; + else + opp_tbl_m_cci_info = &opp_tbls_m_0119[id_cci][CPU_LV_TO_OPP_IDX(lv)]; + p_cci->freq_tbl = opp_tbl_m_cci_info->opp_tbl_m; p_cci->mt_policy = NULL; p_cci->armpll_is_available = 1; @@ -4443,7 +5219,6 @@ static void notify_cpuhvfs_change_cb(struct dvfs_log *log_box, int num_log) cpufreq_freq_transition_end(p->mt_policy, &freqs, 0); } - cpufreq_unlock(flags); } #endif @@ -4522,6 +5297,7 @@ _mt_cpufreq_pm_callback(struct notifier_block *nb, for_each_cpu_dvfs(i, p) { if (!cpu_dvfs_is_available(p)) continue; + _mt_cpufreq_set(p->mt_policy, i, -2, 0); p->dvfs_disable_by_suspend = true; } cpufreq_unlock(flags); @@ -4618,6 +5394,12 @@ static int _mt_cpufreq_pdrv_probe(struct platform_device *pdev) #ifdef CONFIG_CPU_DVFS_AEE_RR_REC _mt_cpufreq_aee_init(); + start_ktime_dvfs.tv64 = 0; + start_ktime_dvfs_cb.tv64 = 0; + for (i = 0; i < 16; i++) { + dvfs_step_delta[i].tv64 = 0; + dvfs_cb_step_delta[i].tv64 = 0; + } #endif /* Prepare OPP table for PPM in probe to avoid nested lock */ @@ -4626,7 +5408,10 @@ static int _mt_cpufreq_pdrv_probe(struct platform_device *pdev) cpu_dvfs_is(p, MT_CPU_DVFS_L) ? (unsigned int *)ARMCAXPLL1_CON1 : cpu_dvfs_is(p, MT_CPU_DVFS_B) ? NULL : (unsigned int *)ARMCAXPLL2_CON1); - opp_tbl_info = &opp_tbls[j][CPU_LV_TO_OPP_IDX(lv)]; + if (_mt_cpufreq_get_cpu_date_code() == DATE_CODE_1221) + opp_tbl_info = &opp_tbls_1221[j][CPU_LV_TO_OPP_IDX(lv)]; + else + opp_tbl_info = &opp_tbls_0119[j][CPU_LV_TO_OPP_IDX(lv)]; if (NULL == p->freq_tbl_for_cpufreq) { table = kzalloc((opp_tbl_info->size + 1) * sizeof(*table), GFP_KERNEL); @@ -4685,6 +5470,12 @@ static int _mt_cpufreq_pdrv_probe(struct platform_device *pdev) #endif register_hotcpu_notifier(&_mt_cpufreq_cpu_notifier); mt_ppm_register_client(PPM_CLIENT_DVFS, &ppm_limit_callback); + +#ifdef PPM_DVFS_LATENCY_DEBUG + hrtimer_init(&ppm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + ppm_hrtimer.function = ppm_hrtimer_cb; +#endif + pm_notifier(_mt_cpufreq_pm_callback, 0); FUNC_EXIT(FUNC_LV_MODULE); @@ -4695,6 +5486,10 @@ static int _mt_cpufreq_pdrv_remove(struct platform_device *pdev) { FUNC_ENTER(FUNC_LV_MODULE); +#ifdef PPM_DVFS_LATENCY_DEBUG + hrtimer_cancel(&ppm_hrtimer); +#endif + unregister_hotcpu_notifier(&_mt_cpufreq_cpu_notifier); #ifdef CONFIG_CPU_FREQ cpufreq_unregister_driver(&_mt_cpufreq_driver); diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid.c b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid.c index 2b3ba8ab2b69..50830fa2edd1 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid.c +++ b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid.c @@ -57,6 +57,8 @@ #define OFFS_FW_RSV2 0x02c8 #define OFFS_TIMER_OUT1 0x02d0 #define OFFS_TIMER_OUT2 0x02d4 +#define OFFS_PCM_PC1 0x02d8 +#define OFFS_PCM_PC2 0x02dc #define OFFS_INIT_OPP 0x02e0 #define OFFS_INIT_FREQ 0x02f0 #define OFFS_INIT_VOLT 0x0300 @@ -68,12 +70,14 @@ #define OFFS_DVFS_WAIT 0x0334 #define OFFS_FUNC_ENTER 0x0338 #define OFFS_NXLOG_OFFS 0x033c +#define OFFS_PAUSE_TIME 0x0350 +#define OFFS_UNPAUSE_TIME 0x0354 #define OFFS_LOG_S 0x03d0 #define OFFS_LOG_E 0x2ff8 -#define DVFS_TIMEOUT 3000 /* us */ -#define SEMA_GET_TIMEOUT 1500 /* us */ -#define PAUSE_TIMEOUT 1500 /* us */ +#define DVFS_TIMEOUT 6000 /* us */ +#define SEMA_GET_TIMEOUT 2000 /* us */ +#define PAUSE_TIMEOUT 2000 /* us */ #define DVFS_NOTIFY_INTV 20 /* ms */ #define MAX_LOG_FETCH 20 @@ -730,6 +734,7 @@ do { \ } while (0) #define cspm_get_timestamp() cspm_read(CSPM_PCM_TIMER_OUT) +#define cspm_get_pcmpc() cspm_read(CSPM_PCM_REG15_DATA) #define cspm_min_freq(reg) ((cspm_read(reg) & SW_F_MIN_MASK) >> 0) #define cspm_max_freq(reg) ((cspm_read(reg) & SW_F_MAX_MASK) >> 4) @@ -765,19 +770,21 @@ do { \ #define wait_complete_us(condition, delay, timeout) \ ({ \ - int i = 0; \ - int n = DIV_ROUND_UP(timeout, delay); \ + int _i = 0; \ + int _n = DIV_ROUND_UP(timeout, delay); \ + csram_write(OFFS_PCM_PC1, cspm_get_pcmpc()); \ csram_write(OFFS_TIMER_OUT1, cspm_get_timestamp()); \ while (!(condition)) { \ - if (i >= n) { \ - i = -EBUSY; \ + if (_i >= _n) { \ + _i = -_i; \ break; \ } \ udelay(delay); \ - i++; \ + _i++; \ } \ csram_write(OFFS_TIMER_OUT2, cspm_get_timestamp()); \ - i; \ + csram_write(OFFS_PCM_PC2, cspm_get_pcmpc()); \ + _i; \ }) static inline u32 base_va_to_pa(const u32 *base) @@ -1174,9 +1181,28 @@ static void __cspm_clean_after_pause(void) static void cspm_dump_debug_info(struct cpuhvfs_dvfsp *dvfsp, const char *fmt, ...) { + u32 timer, reg15, sema3_m0, sema3_m1, sema3_m2, sema1_m0, sema1_m1, sema1_m2; + u32 rsv0, rsv1, rsv2, rsv3, rsv4, rsv5, rsv6; char msg[320]; va_list args; + timer = cspm_read(CSPM_PCM_TIMER_OUT); + reg15 = cspm_read(CSPM_PCM_REG15_DATA); + sema3_m0 = cspm_read(CSPM_SEMA3_M0); + sema3_m1 = cspm_read(CSPM_SEMA3_M1); + sema3_m2 = cspm_read(CSPM_SEMA3_M2); + sema1_m0 = cspm_read(CSPM_SEMA1_M0); + sema1_m1 = cspm_read(CSPM_SEMA1_M1); + sema1_m2 = cspm_read(CSPM_SEMA1_M2); + + rsv3 = cspm_read(CSPM_SW_RSV3); + rsv4 = cspm_read(CSPM_SW_RSV4); + rsv5 = cspm_read(CSPM_SW_RSV5); + rsv6 = cspm_read(CSPM_SW_RSV6); + rsv0 = cspm_read(CSPM_SW_RSV0); + rsv1 = cspm_read(CSPM_SW_RSV1); + rsv2 = cspm_read(CSPM_SW_RSV2); + va_start(args, fmt); vsnprintf(msg, sizeof(msg), fmt, args); va_end(args); @@ -1184,19 +1210,18 @@ static void cspm_dump_debug_info(struct cpuhvfs_dvfsp *dvfsp, const char *fmt, . cspm_err("(%u) %s\n" , dvfsp->hw_gov_en, msg); cspm_err("FW_VER: %s\n", dvfsp->pcmdesc->version); - cspm_err("PCM_TIMER: %08x\n", cspm_read(CSPM_PCM_TIMER_OUT)); - cspm_err("PCM_REG15: %u, SEMA3: 0x(%x %x %x)\n", cspm_read(CSPM_PCM_REG15_DATA), - cspm_read(CSPM_SEMA3_M0), - cspm_read(CSPM_SEMA3_M1), - cspm_read(CSPM_SEMA3_M2)); + cspm_err("PCM_TIMER: %08x\n", timer); + cspm_err("PCM_REG15: %u, SEMA3: 0x(%x %x %x), SEMA1: 0x(%x %x %x)\n", + reg15, sema3_m0, sema3_m1, sema3_m2, + sema1_m0, sema1_m1, sema1_m2); - cspm_err("SW_RSV0: 0x%x\n", cspm_read(CSPM_SW_RSV0)); - cspm_err("SW_RSV1: 0x%x\n", cspm_read(CSPM_SW_RSV1)); - cspm_err("SW_RSV2: 0x%x\n", cspm_read(CSPM_SW_RSV2)); - cspm_err("SW_RSV3: 0x%x\n", cspm_read(CSPM_SW_RSV3)); - cspm_err("SW_RSV4: 0x%x\n", cspm_read(CSPM_SW_RSV4)); - cspm_err("SW_RSV5: 0x%x\n", cspm_read(CSPM_SW_RSV5)); - cspm_err("SW_RSV6: 0x%x\n", cspm_read(CSPM_SW_RSV6)); + cspm_err("SW_RSV0: 0x%x\n", rsv0); + cspm_err("SW_RSV1: 0x%x\n", rsv1); + cspm_err("SW_RSV2: 0x%x\n", rsv2); + cspm_err("SW_RSV3: 0x%x\n", rsv3); + cspm_err("SW_RSV4: 0x%x\n", rsv4); + cspm_err("SW_RSV5: 0x%x\n", rsv5); + cspm_err("SW_RSV6: 0x%x\n", rsv6); cspm_err("M3_RECx: 0x(%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x)\n", cspm_read(CSPM_M3_REC1), @@ -1245,6 +1270,7 @@ static int __cspm_pause_pcm_running(struct cpuhvfs_dvfsp *dvfsp, u32 psf) cspm_write(swctrl_reg[i], cspm_read(swctrl_reg[i]) | SW_PAUSE); csram_write(swctrl_offs[i], cspm_read(swctrl_reg[i])); } + csram_write(OFFS_PAUSE_TIME, cspm_get_timestamp()); udelay(10); /* skip FW_DONE 1->0 transition */ @@ -1302,6 +1328,7 @@ static void __cspm_unpause_pcm_to_run(struct cpuhvfs_dvfsp *dvfsp, u32 psf) csram_write(swctrl_offs[i], cspm_read(swctrl_reg[i])); all_pause = 0; } + csram_write(OFFS_UNPAUSE_TIME, cspm_get_timestamp()); BUG_ON(all_pause); /* no cluster on!? */ @@ -1470,7 +1497,7 @@ static int cspm_set_target_opp(struct cpuhvfs_dvfsp *dvfsp, unsigned int cluster spin_lock(&dvfs_lock); csram_write(OFFS_FUNC_ENTER, (cluster << 24) | (index << 16) | FEF_DVFS); - cspm_dbgx(DVFS, "(%u) cluster%u dvfs, opp = (%u, %u), pause = 0x%x\n", + cspm_dbgx(DVFS, "(%u) cluster%u dvfs, opp = %u <%u>, pause = 0x%x\n", dvfsp->hw_gov_en, cluster, index, f_des, pause_src_map); while (pause_src_map != 0) { @@ -1499,7 +1526,7 @@ static int cspm_set_target_opp(struct cpuhvfs_dvfsp *dvfsp, unsigned int cluster if (ret_volt) *ret_volt = cspm_curr_volt(hwsta_reg[cluster]); } else { - cspm_dump_debug_info(dvfsp, "CLUSTER%u DVFS TIMEOUT, opp = (%u, %u)", + cspm_dump_debug_info(dvfsp, "CLUSTER%u DVFS TIMEOUT, opp = %u <%u>", cluster, index, f_des); BUG_ON(dvfs_fail_ke); } @@ -2334,4 +2361,4 @@ fs_initcall(cpuhvfs_pre_module_init); #endif /* CONFIG_HYBRID_CPU_DVFS */ -MODULE_DESCRIPTION("Hybrid CPU DVFS Driver v0.6"); +MODULE_DESCRIPTION("Hybrid CPU DVFS Driver v0.6.1"); diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid_fw.h b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid_fw.h index cd22addbf893..ef204503c9fe 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid_fw.h +++ b/drivers/misc/mediatek/base/power/mt6797/mt_cpufreq_hybrid_fw.h @@ -36,6 +36,7 @@ struct pcm_desc { }; +#ifdef CPUHVFS_HW_GOVERNOR static const u32 dvfs_binary[] = { 0x1ad0001f, 0x11015614, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015614, 0xb8400161, 0xfffffff0, 0x18c0001f, 0x11015614, @@ -95,87 +96,430 @@ static const u32 dvfs_binary[] = { 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x11015604, 0x1850001f, 0x11015604, 0xa052040b, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x11015604, 0x1850001f, 0x11015604, 0xa054040b, 0xe0c00001, 0xf0000000, 0x17c07c1f, - 0x1a10001f, 0x10220744, 0x1850001f, 0x11015320, 0x82200408, 0x18c0001f, - 0x10220744, 0xe0c00008, 0xa2000408, 0x100aac1f, 0x88000000, 0x0000001f, + 0x1a10001f, 0x10220744, 0x1850001f, 0x11015320, 0x1052841f, 0x82200408, + 0x18c0001f, 0x10220744, 0xe0c00008, 0x100aac1f, 0x88000000, 0x0000001f, 0x1850001f, 0x11015324, 0x82000408, 0x1a50001f, 0x1101531c, 0x80501809, 0xd8202e21, 0x17c07c1f, 0xa2148008, 0x80509809, 0xd8202ea1, 0x17c07c1f, 0xa2188008, 0x80511809, 0xd8202f21, 0x17c07c1f, 0xa2108008, 0xe0c00008, - 0xf0000000, 0x17c07c1f, 0x1003ac1f, 0x88000000, 0x0000001f, 0x18c0001f, - 0x1001a274, 0xe8208000, 0x11015444, 0x00000001, 0x1a10001f, 0x11015444, - 0xd8203028, 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a300003, 0x17c07c1f, - 0x1a50001f, 0x1101531c, 0x80501809, 0xd8203281, 0x17c07c1f, 0x8a000008, - 0xfffffc1f, 0xa2128008, 0x80509809, 0xd8203341, 0x17c07c1f, 0x8a000008, - 0xffff83ff, 0xa2150008, 0x80519809, 0xd8203401, 0x17c07c1f, 0x8a000008, - 0xffffffe0, 0xa2100008, 0x80511809, 0xd82034c1, 0x17c07c1f, 0x8a000008, - 0xfff07fff, 0xa2178008, 0xe0c00008, 0x1b80001f, 0x20000006, 0xe8208000, - 0x11015444, 0x00000001, 0x1b80001f, 0x20000104, 0xf0000000, 0x17c07c1f, - 0x18c0001f, 0x0012a08c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, - 0x17c07c1f, 0x18c0001f, 0x0012a11c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, - 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x0012a23c, 0x00f1ac03, 0x1af00003, - 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x1800001f, 0x1001a270, 0xe8208000, - 0x11015444, 0x00000001, 0x18d0001f, 0x11015444, 0xd82038e3, 0x17c07c1f, - 0x1b80001f, 0x20000006, 0x18d0001f, 0x1001a270, 0x1850001f, 0x11015330, - 0x80c00403, 0x1850001f, 0x1101532c, 0xa0c00403, 0xe0000003, 0x1b80001f, - 0x20000006, 0x1002101f, 0x88000000, 0x00000007, 0x101c001f, 0x18d0001f, - 0x11015318, 0x1b80001f, 0x20000006, 0x18700003, 0x17c07c1f, 0x88400001, - 0xf8ffffff, 0xa8400001, 0x80000000, 0xa0400001, 0xe0c00001, 0x1b80001f, - 0x20000104, 0x1800001f, 0x1001a270, 0x1b80001f, 0x20000006, 0x18d0001f, - 0x1001a270, 0x1850001f, 0x11015330, 0x80c00403, 0x1850001f, 0x11015328, - 0xa0c00403, 0xe0000003, 0x1b80001f, 0x20000006, 0xe8208000, 0x11015444, - 0x00000001, 0xf0000000, 0x17c07c1f, 0x1810001f, 0x1101530c, 0x1850001f, - 0x11015318, 0xe8208000, 0x11015444, 0x00000001, 0x18d0001f, 0x11015444, - 0xd82040a3, 0x17c07c1f, 0x1b80001f, 0x20000006, 0x18f00001, 0x17c07c1f, - 0x88c00003, 0x001fffff, 0xa8c00003, 0x80000000, 0xe0000003, 0x1b80001f, - 0x20000006, 0x1810001f, 0x11015304, 0x1b80001f, 0x20000006, 0x18f00000, - 0x17c07c1f, 0x18f00000, 0x17c07c1f, 0xa0d11803, 0xa0d01803, 0xe0000003, - 0x1b80001f, 0x20000006, 0xe8208000, 0x1001af0c, 0x06003c97, 0x1b80001f, - 0x20000006, 0x1800001f, 0x1001af00, 0x18d0001f, 0x1101531c, 0xe0000003, - 0x1b80001f, 0x20000006, 0x1240101f, 0x1246241f, 0x8a400009, 0x000001ff, - 0x1256241f, 0x1810001f, 0x11015310, 0xa8c00009, 0x80000000, 0xe0000003, - 0x1b80001f, 0x20000006, 0x10007c1f, 0x1850001f, 0x11015314, 0x1b80001f, - 0x20000006, 0x18f00001, 0x17c07c1f, 0x18f00001, 0x17c07c1f, 0x88c00003, - 0x001fffff, 0x60600c09, 0xd8004c21, 0x17c07c1f, 0x68600000, 0x00000064, - 0xd8004a61, 0x17c07c1f, 0x00001800, 0x1b80001f, 0x20000104, 0xd00047a0, - 0x17c07c1f, 0x1810001f, 0x0012a3a8, 0xa0120006, 0x1a00001f, 0x0012a3a8, - 0xe2000000, 0x1a00001f, 0x0012a3ac, 0xe2000009, 0x1a00001f, 0x0012a3b0, - 0xe2000003, 0xd00047a0, 0x17c07c1f, 0x88c00003, 0x001fffff, 0x1810001f, - 0x11015318, 0x1b80001f, 0x20000006, 0x18700000, 0x17c07c1f, 0x88400001, - 0xffe00000, 0xa8400001, 0x80000000, 0xa0c00403, 0xe0000003, 0x1b80001f, - 0x20000006, 0x1800001f, 0x1001af00, 0x10c07c1f, 0xe0000003, 0x1b80001f, - 0x20000006, 0xe8208000, 0x11015444, 0x00000001, 0xf0000000, 0x17c07c1f, - 0x20602805, 0xd8205061, 0x17c07c1f, 0xc1002b80, 0x17c07c1f, 0xc1002f80, + 0x1850001f, 0x11015320, 0x1052841f, 0xa2000408, 0xe0c00008, 0xf0000000, + 0x17c07c1f, 0x1003ac1f, 0x88000000, 0x0000001f, 0x18c0001f, 0x1001a274, + 0xe8208000, 0x11015444, 0x00000001, 0x1a10001f, 0x11015444, 0xd82030c8, + 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a300003, 0x17c07c1f, 0x1a50001f, + 0x1101531c, 0x80501809, 0xd8203321, 0x17c07c1f, 0x8a000008, 0xfffffc1f, + 0xa2128008, 0x80509809, 0xd82033e1, 0x17c07c1f, 0x8a000008, 0xffff83ff, + 0xa2150008, 0x80519809, 0xd82034a1, 0x17c07c1f, 0x8a000008, 0xffffffe0, + 0xa2100008, 0x80511809, 0xd8203561, 0x17c07c1f, 0x8a000008, 0xfff07fff, + 0xa2178008, 0xe0c00008, 0x1b80001f, 0x20000006, 0xe8208000, 0x11015444, + 0x00000001, 0x1b80001f, 0x20000104, 0xf0000000, 0x17c07c1f, 0x18c0001f, + 0x0012a08c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, + 0x18c0001f, 0x0012a11c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, + 0x17c07c1f, 0x18c0001f, 0x0012a23c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, + 0xf0000000, 0x17c07c1f, 0x1800001f, 0x1001a270, 0xe8208000, 0x11015444, + 0x00000001, 0x18d0001f, 0x11015444, 0xd8203983, 0x17c07c1f, 0x1b80001f, + 0x20000006, 0x18d0001f, 0x1001a270, 0x1850001f, 0x11015330, 0x80c00403, + 0x1850001f, 0x1101532c, 0xa0c00403, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1002101f, 0x88000000, 0x00000007, 0x101c001f, 0x18d0001f, 0x11015318, + 0x1b80001f, 0x20000006, 0x18700003, 0x17c07c1f, 0x88400001, 0xf8ffffff, + 0xa8400001, 0x80000000, 0xa0400001, 0xe0c00001, 0x1b80001f, 0x20000104, + 0x1800001f, 0x1001a270, 0x1b80001f, 0x20000006, 0x18d0001f, 0x1001a270, + 0x1850001f, 0x11015330, 0x80c00403, 0x1850001f, 0x11015328, 0xa0c00403, + 0xe0000003, 0x1b80001f, 0x20000006, 0xe8208000, 0x11015444, 0x00000001, + 0xf0000000, 0x17c07c1f, 0x1810001f, 0x1101530c, 0x1850001f, 0x11015318, + 0xe8208000, 0x11015444, 0x00000001, 0x18d0001f, 0x11015444, 0xd8204143, + 0x17c07c1f, 0x1b80001f, 0x20000006, 0x18f00001, 0x17c07c1f, 0x88c00003, + 0x001fffff, 0xa8c00003, 0x80000000, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1810001f, 0x11015304, 0x1b80001f, 0x20000006, 0x18f00000, 0x17c07c1f, + 0x18f00000, 0x17c07c1f, 0xa0d11803, 0xa0d01803, 0xe0000003, 0x1b80001f, + 0x20000006, 0xe8208000, 0x1001af0c, 0x06003c97, 0x1b80001f, 0x20000006, + 0x1800001f, 0x1001af00, 0x18d0001f, 0x1101531c, 0xe0000003, 0x1b80001f, + 0x20000006, 0x1240101f, 0x1246241f, 0x8a400009, 0x000001ff, 0x1256241f, + 0x1810001f, 0x11015310, 0xa8c00009, 0x80000000, 0xe0000003, 0x1b80001f, + 0x20000006, 0x10007c1f, 0x1850001f, 0x11015314, 0x1b80001f, 0x20000006, + 0x18f00001, 0x17c07c1f, 0x18f00001, 0x17c07c1f, 0x88c00003, 0x001fffff, + 0x60600c09, 0xd8004cc1, 0x17c07c1f, 0x68600000, 0x00000064, 0xd8004b01, + 0x17c07c1f, 0x00001800, 0x1b80001f, 0x20000104, 0xd0004840, 0x17c07c1f, + 0x1810001f, 0x0012a3a8, 0xa0120006, 0x1a00001f, 0x0012a3a8, 0xe2000000, + 0x1a00001f, 0x0012a3ac, 0xe2000009, 0x1a00001f, 0x0012a3b0, 0xe2000003, + 0xd0004840, 0x17c07c1f, 0x88c00003, 0x001fffff, 0x1810001f, 0x11015318, + 0x1b80001f, 0x20000006, 0x18700000, 0x17c07c1f, 0x88400001, 0xffe00000, + 0xa8400001, 0x80000000, 0xa0c00403, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1800001f, 0x1001af00, 0x10c07c1f, 0xe0000003, 0x1b80001f, 0x20000006, + 0xe8208000, 0x11015444, 0x00000001, 0xf0000000, 0x17c07c1f, 0x10007c1f, + 0xc0002b80, 0x17c07c1f, 0x20602805, 0xd8205121, 0x17c07c1f, 0xc1003020, 0x17c07c1f, 0x1002101f, 0x88000000, 0x00000007, 0x10c2081f, 0x88c00003, - 0x00000007, 0x20600c00, 0xd82051c1, 0x17c07c1f, 0xc20038a0, 0x17c07c1f, - 0xc1004020, 0x17c07c1f, 0x1002101f, 0x88000000, 0x00000007, 0x18d0001f, + 0x00000007, 0x20600c00, 0xd8205281, 0x17c07c1f, 0xc2003940, 0x17c07c1f, + 0xc10040c0, 0x17c07c1f, 0x1002101f, 0x88000000, 0x00000007, 0x18d0001f, 0x11015318, 0xe8208000, 0x11015444, 0x00000001, 0x1a50001f, 0x11015444, - 0xd82052a9, 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a700003, 0x17c07c1f, + 0xd8205369, 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a700003, 0x17c07c1f, 0xe8208000, 0x11015444, 0x00000001, 0x124c241f, 0x8a400009, 0x00000007, - 0x40602400, 0xd8205561, 0x17c07c1f, 0xc20038a0, 0x17c07c1f, 0x40602805, - 0xd8205641, 0x17c07c1f, 0xc1002f80, 0x17c07c1f, 0xc1002b80, 0x17c07c1f, + 0x40602400, 0xd8205621, 0x17c07c1f, 0xc2003940, 0x17c07c1f, 0x40602805, + 0xd82056c1, 0x17c07c1f, 0xc1003020, 0x17c07c1f, 0xc1002b80, 0x17c07c1f, 0x1800001f, 0x11015828, 0xe0000006, 0xf0000000, 0x17c07c1f, 0x1a00001f, - 0x11015304, 0x12407c1f, 0x68600009, 0x0000000c, 0xd80058c1, 0x17c07c1f, + 0x11015304, 0x12407c1f, 0x68600009, 0x0000000c, 0xd8005981, 0x17c07c1f, 0x18f00000, 0x17c07c1f, 0xe2000003, 0x00111800, 0x02111808, 0x02401809, - 0xd0005740, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x1800001f, 0x11015608, - 0x12407c1f, 0x68600009, 0x00000007, 0xd8005ae1, 0x17c07c1f, 0x18f00000, - 0x17c07c1f, 0xe2000003, 0x00111800, 0x02111808, 0x02401809, 0xd0005960, + 0xd0005800, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x1800001f, 0x11015608, + 0x12407c1f, 0x68600009, 0x00000007, 0xd8005ba1, 0x17c07c1f, 0x18f00000, + 0x17c07c1f, 0xe2000003, 0x00111800, 0x02111808, 0x02401809, 0xd0005a20, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x8a400009, 0x00007fff, 0x1255a41f, 0x88c00002, 0x000000f0, 0xa2518c09, 0x89000002, 0x00007f00, 0xa2441009, 0x89400002, 0x003f0000, 0xa2551409, 0xf0000000, 0x17c07c1f, 0x1a00001f, 0x11015624, 0x02002808, 0x18b00008, 0x17c07c1f, 0x1840001f, 0x00120000, 0x00c00801, 0xe0c00009, 0x08800002, 0x00000018, 0x0940000a, 0x0000cff8, - 0x71201402, 0xd8005f24, 0x17c07c1f, 0x0880000a, 0x0000a3d0, 0xe2000002, + 0x71201402, 0xd8005fe4, 0x17c07c1f, 0x0880000a, 0x0000a3d0, 0xe2000002, 0x00c00801, 0xe0c0001f, 0xf0000000, 0x17c07c1f, 0x1a50001f, 0x11015150, - 0x12807c1f, 0xc2805ce0, 0x17c07c1f, 0x1a50001f, 0x1101563c, 0x1890001f, - 0x11015614, 0xc2405b20, 0x17c07c1f, 0x1291181f, 0xc2805ce0, 0x17c07c1f, - 0x1a50001f, 0x11015640, 0x1890001f, 0x11015618, 0xc2405b20, 0x17c07c1f, - 0x0291180a, 0xc2805ce0, 0x17c07c1f, 0x1a50001f, 0x11015644, 0x1890001f, - 0x1101561c, 0xc2405b20, 0x17c07c1f, 0x0291180a, 0xc2805ce0, 0x17c07c1f, - 0x12407c1f, 0x1890001f, 0x11015620, 0xc2405b20, 0x17c07c1f, 0x0291180a, - 0xc2805ce0, 0x17c07c1f, 0x12407c1f, 0xc10026e0, 0x17c07c1f, 0xd82067e4, + 0x12807c1f, 0xc2805da0, 0x17c07c1f, 0x1a50001f, 0x1101563c, 0x1890001f, + 0x11015614, 0xc2405be0, 0x17c07c1f, 0x1291181f, 0xc2805da0, 0x17c07c1f, + 0x1a50001f, 0x11015640, 0x1890001f, 0x11015618, 0xc2405be0, 0x17c07c1f, + 0x0291180a, 0xc2805da0, 0x17c07c1f, 0x1a50001f, 0x11015644, 0x1890001f, + 0x1101561c, 0xc2405be0, 0x17c07c1f, 0x0291180a, 0xc2805da0, 0x17c07c1f, + 0x12407c1f, 0x1890001f, 0x11015620, 0xc2405be0, 0x17c07c1f, 0x0291180a, + 0xc2805da0, 0x17c07c1f, 0x12407c1f, 0xc10026e0, 0x17c07c1f, 0xd8206804, + 0x17c07c1f, 0x1a10001f, 0x102224c8, 0x8a000008, 0x0000ff00, 0xa2532009, + 0x1a10001f, 0x10222498, 0x8a000008, 0x0007f000, 0xa242a009, 0x1a10001f, + 0x102224cc, 0x8a000008, 0x7f000000, 0xa24c2009, 0x0291180a, 0xc2805da0, + 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x8a40000a, 0x000000f0, 0x1a00001f, + 0x110151a0, 0x02002408, 0x18300008, 0x17c07c1f, 0x1a00001f, 0x110151a4, + 0x02002408, 0x18700008, 0x17c07c1f, 0x30a00400, 0xd8006ae2, 0x17c07c1f, + 0x10c0001f, 0xd0006b00, 0x17c07c1f, 0x10c0041f, 0x1a00001f, 0x110151a8, + 0x02002408, 0x18300008, 0x17c07c1f, 0x1a00001f, 0x110151ac, 0x02002408, + 0x18700008, 0x17c07c1f, 0x30a00400, 0xd8006d02, 0x17c07c1f, 0x1100001f, + 0xd0006d20, 0x17c07c1f, 0x1100041f, 0x30a01003, 0xd8006da2, 0x17c07c1f, + 0x11000c1f, 0x8a40000a, 0x0000000f, 0x1a00001f, 0x1101563c, 0x02002408, + 0xe2000004, 0x1a00001f, 0x11015054, 0x02002808, 0x18300008, 0x17c07c1f, + 0x88000000, 0x000000ff, 0x00a39000, 0x1a40001f, 0x000003ff, 0x1a00001f, + 0x11015050, 0x02002808, 0x18300008, 0x17c07c1f, 0x80080009, 0x00c00800, + 0x1a00001f, 0x11015044, 0x02002808, 0x18300008, 0x17c07c1f, 0x80080009, + 0x30600003, 0xd80071e1, 0x17c07c1f, 0xd8207241, 0x17c07c1f, 0x10c0001f, + 0xd00072c0, 0x17c07c1f, 0x40707c03, 0xd82072c1, 0x17c07c1f, 0x10c07c1f, + 0x1980001f, 0x11015048, 0x01802806, 0x18300006, 0x17c07c1f, 0x80080009, + 0x1040081f, 0x1140341f, 0x1a00001f, 0x1101504c, 0x02002808, 0x18300008, + 0x17c07c1f, 0x80080009, 0x10400c1f, 0x01403405, 0x18300006, 0x17c07c1f, + 0x1014001f, 0xb8008000, 0x0000ff00, 0x000000ff, 0x01400005, 0x1146141f, + 0x1a00001f, 0x11015050, 0x02002808, 0x10180c1f, 0xe2000000, 0x8980000a, + 0x0000000f, 0x1a00001f, 0x11015614, 0x02001808, 0x18300008, 0x17c07c1f, + 0x88000000, 0xffffff0f, 0x89400005, 0x0000000f, 0xa0121400, 0xe2000000, + 0x1980001f, 0x00000001, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x1980001f, 0x00000001, + 0xe8208000, 0x11015048, 0x008e0076, 0xe8208000, 0x1101504c, 0x001d0000, + 0xe8208000, 0x11015054, 0x00000010, 0xe8208000, 0x1101505c, 0x008e0066, + 0xe8208000, 0x11015060, 0x001d0000, 0xe8208000, 0x11015068, 0x0000002e, + 0xe8208000, 0x11015070, 0x0067002e, 0xe8208000, 0x11015074, 0x00260000, + 0xe8208000, 0x1101507c, 0x00000073, 0xe8208000, 0x110150a0, 0x00000003, + 0x1310981f, 0x80c0b006, 0xd8208423, 0x17c07c1f, 0x12807c1f, 0xc28068a0, + 0x17c07c1f, 0x1a80001f, 0x00000014, 0xc28068a0, 0x17c07c1f, 0x1a80001f, + 0x00000028, 0xc28068a0, 0x17c07c1f, 0x12807c1f, 0xc28010a0, 0x17c07c1f, + 0xc2801260, 0x17c07c1f, 0xc2801420, 0x17c07c1f, 0x1810001f, 0x11015608, + 0x1850001f, 0x1101560c, 0x1890001f, 0x11015610, 0x18c0001f, 0x1101583c, + 0xe0c00000, 0x00d11803, 0xe0c00001, 0x00d11803, 0xe0c00002, 0xc1001e80, + 0x17c07c1f, 0xc0801be0, 0x17c07c1f, 0xd8208964, 0x17c07c1f, 0xc0800860, + 0x17c07c1f, 0xc1001f20, 0x17c07c1f, 0xc0801cc0, 0x17c07c1f, 0xd8208a64, + 0x17c07c1f, 0xc0800a80, 0x17c07c1f, 0xc1001fc0, 0x17c07c1f, 0xc0801da0, + 0x17c07c1f, 0xd8208b64, 0x17c07c1f, 0xc0800ca0, 0x17c07c1f, 0xc1001940, + 0x17c07c1f, 0xc0801700, 0x17c07c1f, 0xc0c00780, 0x17c07c1f, 0x20601003, + 0xd8208cc1, 0x17c07c1f, 0xc1000860, 0x17c07c1f, 0x20600c02, 0xd8208d61, + 0x17c07c1f, 0xc0800860, 0x17c07c1f, 0xc1001a20, 0x17c07c1f, 0xc08017c0, + 0x17c07c1f, 0xc0c009a0, 0x17c07c1f, 0x20601003, 0xd8208ec1, 0x17c07c1f, + 0xc1000a80, 0x17c07c1f, 0x20600c02, 0xd8208f61, 0x17c07c1f, 0xc0800a80, + 0x17c07c1f, 0xc1001b00, 0x17c07c1f, 0xc0801880, 0x17c07c1f, 0xc0c00bc0, + 0x17c07c1f, 0x20601003, 0xd82090c1, 0x17c07c1f, 0xc1000ca0, 0x17c07c1f, + 0x20600c02, 0xd8209161, 0x17c07c1f, 0xc0800ca0, 0x17c07c1f, 0xc2802060, + 0x17c07c1f, 0xd820926a, 0x17c07c1f, 0xc1000000, 0x17c07c1f, 0xc1000860, + 0x17c07c1f, 0xc28010a0, 0x17c07c1f, 0xc2402100, 0x17c07c1f, 0xd82093a9, + 0x17c07c1f, 0xc10001e0, 0x17c07c1f, 0xc1000a80, 0x17c07c1f, 0xc2401260, + 0x17c07c1f, 0xc20021a0, 0x17c07c1f, 0xd82094e8, 0x17c07c1f, 0xc10003c0, + 0x17c07c1f, 0xc1000ca0, 0x17c07c1f, 0xc2001420, 0x17c07c1f, 0x8140240a, + 0x81402005, 0xd800d005, 0x17c07c1f, 0xe8208000, 0x11015424, 0x00000001, + 0x1a10001f, 0x11015424, 0xd82095a8, 0x17c07c1f, 0xe8258000, 0x11015804, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1a00001f, + 0x1101582c, 0xc10025a0, 0x17c07c1f, 0xc0802060, 0x17c07c1f, 0xa1000804, + 0xd8009a44, 0x17c07c1f, 0x10807c1f, 0xc0800860, 0x17c07c1f, 0xc0802100, + 0x17c07c1f, 0xd8209a42, 0x17c07c1f, 0xe2000006, 0xc1002640, 0x17c07c1f, + 0xc0802100, 0x17c07c1f, 0xa1000804, 0xd8009c24, 0x17c07c1f, 0x10807c1f, + 0xc0800a80, 0x17c07c1f, 0xc0802060, 0x17c07c1f, 0xd8209c22, 0x17c07c1f, + 0xe2000006, 0xc10026e0, 0x17c07c1f, 0xc08021a0, 0x17c07c1f, 0xa1000804, + 0xd8009de4, 0x17c07c1f, 0x1090981f, 0xc0800ca0, 0x17c07c1f, 0xc0800480, + 0x17c07c1f, 0xd000c960, 0x17c07c1f, 0x1a00001f, 0x0012a368, 0xc20059c0, + 0x17c07c1f, 0xc10025a0, 0x17c07c1f, 0xd820a0e4, 0x17c07c1f, 0xc1400780, + 0x17c07c1f, 0x1100141f, 0x18c0001f, 0x0012a088, 0x00f19403, 0x19700003, + 0x17c07c1f, 0x1800001f, 0x11015804, 0xe0000005, 0xc10036a0, 0x17c07c1f, + 0x1800001f, 0x11015808, 0xe0000004, 0xc1002640, 0x17c07c1f, 0xd820a364, + 0x17c07c1f, 0xc14009a0, 0x17c07c1f, 0x1100141f, 0x18c0001f, 0x0012a118, + 0x00f19403, 0x19700003, 0x17c07c1f, 0x1800001f, 0x1101580c, 0xe0000005, + 0xc1003780, 0x17c07c1f, 0x1800001f, 0x11015810, 0xe0000004, 0xc10026e0, + 0x17c07c1f, 0xd820a584, 0x17c07c1f, 0xc1400bc0, 0x17c07c1f, 0x1100141f, + 0xc140d0e0, 0x17c07c1f, 0x1800001f, 0x11015814, 0xe0000005, 0xc1003860, + 0x17c07c1f, 0x1800001f, 0x11015818, 0xe0000004, 0x1a90001f, 0x11015808, + 0x1950001f, 0x11015810, 0x2060140a, 0xd820a801, 0x17c07c1f, 0x1950001f, + 0x11015818, 0x2060140a, 0xd820a781, 0x17c07c1f, 0xc280d620, 0x17c07c1f, + 0xd000a960, 0x17c07c1f, 0xc140d620, 0x17c07c1f, 0xd000a960, 0x17c07c1f, + 0x1a90001f, 0x11015818, 0x20602805, 0xd820a921, 0x17c07c1f, 0xc140d620, + 0x17c07c1f, 0xd000a960, 0x17c07c1f, 0xc280d620, 0x17c07c1f, 0x1850001f, + 0x1101582c, 0xd800aca1, 0x17c07c1f, 0x1910001f, 0x1101581c, 0x1283901f, + 0x89000004, 0x0000007f, 0xc080d460, 0x17c07c1f, 0xc140d540, 0x17c07c1f, + 0x20600804, 0xd820abe1, 0x17c07c1f, 0xc0c0dc20, 0x17c07c1f, 0xd000aca0, + 0x17c07c1f, 0x40600804, 0xd820aca1, 0x17c07c1f, 0x1800001f, 0x11015824, + 0xe0000006, 0xc1400000, 0x17c07c1f, 0xc2800780, 0x17c07c1f, 0x00602805, + 0xd820b001, 0x17c07c1f, 0x1800001f, 0x0000000a, 0xc0002980, 0x17c07c1f, + 0xc1402980, 0x17c07c1f, 0xc2802980, 0x17c07c1f, 0x1800001f, 0x11015334, + 0xc00057a0, 0x17c07c1f, 0x1080141f, 0xc08036a0, 0x17c07c1f, 0x1100281f, + 0xc10036a0, 0x17c07c1f, 0xc1005020, 0x17c07c1f, 0xc14001e0, 0x17c07c1f, + 0xc28009a0, 0x17c07c1f, 0x00602805, 0xd820b361, 0x17c07c1f, 0x1800001f, + 0x0000000b, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, 0xc2802980, + 0x17c07c1f, 0x1800001f, 0x11015364, 0xc00057a0, 0x17c07c1f, 0x1080141f, + 0xc0803780, 0x17c07c1f, 0x1100281f, 0xc1003780, 0x17c07c1f, 0xc1005020, + 0x17c07c1f, 0xc14003c0, 0x17c07c1f, 0xc2800bc0, 0x17c07c1f, 0x00602805, + 0xd820c221, 0x17c07c1f, 0x1100281f, 0xc1003860, 0x17c07c1f, 0x1800001f, + 0x0000000d, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, 0xc2802980, + 0x17c07c1f, 0xe8208000, 0x1101531c, 0x00000008, 0x70607c0a, 0xd820b6a1, + 0x17c07c1f, 0xc1003020, 0x17c07c1f, 0x1800001f, 0x10222470, 0x18f00000, + 0x17c07c1f, 0xa0d31803, 0xe0000003, 0x8a400003, 0x0000f000, 0x88c00003, + 0xffff0fff, 0xa8c00003, 0x00003000, 0xe0000003, 0x10007c1f, 0x60739800, + 0xd800bd01, 0x17c07c1f, 0x00001800, 0x1b80001f, 0x20000034, 0x18d0001f, + 0x102224c8, 0x80d09803, 0xd820b863, 0x17c07c1f, 0x1b80001f, 0x2000001a, + 0x1200281f, 0xc200d0e0, 0x17c07c1f, 0x18c0001f, 0x10222498, 0x1006a01f, + 0xe0c00000, 0x1840001f, 0x0012a3a4, 0xe0400000, 0x1b80001f, 0x2000001a, + 0x38600000, 0x0003b999, 0xd820bca1, 0x17c07c1f, 0xe8208000, 0x102224c0, + 0x00028d00, 0xd000bd00, 0x17c07c1f, 0xe8208000, 0x102224c0, 0x00014333, + 0x1800001f, 0x10222470, 0x18f00000, 0x17c07c1f, 0x88c00003, 0xffff0fff, + 0xa0c02403, 0xe0000003, 0x1b80001f, 0x2000001a, 0x80f31803, 0xe0000003, + 0x60607c0a, 0xd820bf21, 0x17c07c1f, 0xc1003020, 0x17c07c1f, 0x1910001f, + 0x11015814, 0x1283901f, 0x8a80000a, 0x0000007f, 0x89000004, 0x0000007f, + 0x1850001f, 0x1101561c, 0x88400001, 0xffff80ff, 0xa0541001, 0x18c0001f, + 0x1101561c, 0xe0c00001, 0x1850001f, 0x1101561c, 0x88400001, 0xff80ffff, + 0xa0582801, 0xe0c00001, 0x1800001f, 0x11015828, 0xe0000006, 0xc14005a0, + 0x17c07c1f, 0xc2800de0, 0x17c07c1f, 0x00602805, 0xd820c581, 0x17c07c1f, + 0x1800001f, 0x0000000c, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, + 0xc2802980, 0x17c07c1f, 0x1800001f, 0x11015394, 0xc00057a0, 0x17c07c1f, + 0x1080141f, 0xc080d2a0, 0x17c07c1f, 0x1100281f, 0xc100d2a0, 0x17c07c1f, + 0xc1005020, 0x17c07c1f, 0x1850001f, 0x11015824, 0xd820c761, 0x17c07c1f, + 0x1910001f, 0x1101581c, 0x1283901f, 0x89000004, 0x0000007f, 0xc080d460, + 0x17c07c1f, 0xc140d540, 0x17c07c1f, 0xc0c0dc20, 0x17c07c1f, 0xc2800de0, + 0x17c07c1f, 0xc2800660, 0x17c07c1f, 0xc2800780, 0x17c07c1f, 0xc28000c0, + 0x17c07c1f, 0xc28009a0, 0x17c07c1f, 0xc28002a0, 0x17c07c1f, 0xc2800bc0, + 0x17c07c1f, 0xc2800480, 0x17c07c1f, 0xc10025a0, 0x17c07c1f, 0xc0802060, + 0x17c07c1f, 0xa1000804, 0xd800ca84, 0x17c07c1f, 0xc1802240, 0x17c07c1f, + 0xc1002640, 0x17c07c1f, 0xc0802100, 0x17c07c1f, 0xa1000804, 0xd800cba4, + 0x17c07c1f, 0xc1802360, 0x17c07c1f, 0xc10026e0, 0x17c07c1f, 0xc08021a0, + 0x17c07c1f, 0xa1000804, 0xd800ccc4, 0x17c07c1f, 0xc1802480, 0x17c07c1f, + 0x1850001f, 0x11015828, 0xd820cd81, 0x17c07c1f, 0xc0c06080, 0x17c07c1f, + 0xc1801420, 0x17c07c1f, 0xc1801260, 0x17c07c1f, 0xc18010a0, 0x17c07c1f, + 0xc18015e0, 0x17c07c1f, 0x1a00001f, 0x0012a384, 0xc20059c0, 0x17c07c1f, + 0x1a00001f, 0x0012a3a0, 0x18d0001f, 0x11015604, 0xe2000003, 0xe8208000, + 0x11015424, 0x00000001, 0xa1db9807, 0x81fb9807, 0x1b80001f, 0x2000001a, + 0xd0008400, 0x17c07c1f, 0xf0000000, 0x18c0001f, 0x0012a238, 0x00f1ac03, + 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x0012a1a8, + 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x18c0001f, + 0x0012a1ac, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x1101561c, 0x12c42c1f, 0x8ac0000b, 0x0000007f, 0xf0000000, + 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x12c42c1f, 0x8ac0000b, 0x0000007f, + 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x12c82c1f, 0x8ac0000b, + 0x0000007f, 0xf0000000, 0x17c07c1f, 0x8800000b, 0x0000000f, 0xc000d1c0, + 0x17c07c1f, 0x18d0001f, 0x11015804, 0x20600003, 0xd820d761, 0x17c07c1f, + 0x10000c1f, 0x18d0001f, 0x1101580c, 0x20600003, 0xd820d821, 0x17c07c1f, + 0x10000c1f, 0x18c0001f, 0x1101581c, 0xe0c00000, 0x1212181f, 0x02201808, + 0x1240201f, 0xd820da29, 0x17c07c1f, 0xc240d1c0, 0x17c07c1f, 0x50600009, + 0xd800da21, 0x17c07c1f, 0x02201808, 0xd000d8c0, 0x17c07c1f, 0x1240201f, + 0xc240d2a0, 0x17c07c1f, 0x18c0001f, 0x11015820, 0xe0c00009, 0x1850001f, + 0x11015620, 0x88400001, 0xffffff0f, 0xa0522001, 0x18c0001f, 0x11015620, + 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x28600004, 0x0000005a, 0xd820dce1, + 0x17c07c1f, 0x1900001f, 0x0000005a, 0x48600004, 0x00000020, 0xd820dda1, + 0x17c07c1f, 0x1900001f, 0x00000020, 0x60600804, 0xd820de41, 0x17c07c1f, + 0xd000e5e0, 0x17c07c1f, 0x20600804, 0xd820e241, 0x17c07c1f, 0x1200081f, + 0x1240141f, 0x60602004, 0xd820df81, 0x17c07c1f, 0xd000e5e0, 0x17c07c1f, + 0x0a000008, 0x0000000a, 0x20601008, 0xd820e041, 0x17c07c1f, 0x1200101f, + 0x60602809, 0xd800e141, 0x17c07c1f, 0x02511809, 0x20602809, 0xd820e141, + 0x17c07c1f, 0x1240281f, 0xc240f340, 0x17c07c1f, 0xc200eb60, 0x17c07c1f, + 0x1b80001f, 0x20000300, 0xd000dee0, 0x17c07c1f, 0x1200081f, 0x1240141f, + 0x60602004, 0xd820e321, 0x17c07c1f, 0xd000e5e0, 0x17c07c1f, 0x0a200008, + 0x0000000a, 0x40601008, 0xd820e3e1, 0x17c07c1f, 0x1200101f, 0xc200eb60, + 0x17c07c1f, 0x60602809, 0xd800e521, 0x17c07c1f, 0x02711809, 0x40602809, + 0xd820e521, 0x17c07c1f, 0x1240281f, 0xc240f340, 0x17c07c1f, 0x1b80001f, + 0x20000300, 0xd000e280, 0x17c07c1f, 0x1850001f, 0x11015620, 0x88400001, + 0xffff80ff, 0xa0541001, 0x18c0001f, 0x11015620, 0xe0c00001, 0x1850001f, + 0x11015620, 0x88400001, 0xff80ffff, 0xa0582801, 0xe0c00001, 0x1850001f, + 0x11015614, 0x88400001, 0xffff80ff, 0xa0541001, 0x18c0001f, 0x11015614, + 0xe0c00001, 0x1850001f, 0x11015614, 0x88400001, 0xff80ffff, 0xa0582801, + 0xe0c00001, 0x1850001f, 0x11015618, 0x88400001, 0xffff80ff, 0xa0541001, + 0x18c0001f, 0x11015618, 0xe0c00001, 0x1850001f, 0x11015618, 0x88400001, + 0xff80ffff, 0xa0582801, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0xe8208000, + 0x1100e004, 0x000000d0, 0xe8208000, 0x1100e008, 0x000000f8, 0xe8208000, + 0x1100e010, 0x00000028, 0xe8208000, 0x1100e014, 0x00000002, 0xe8208000, + 0x1100e018, 0x00000001, 0xe8208000, 0x1100e01c, 0x00000002, 0xe8208000, + 0x1100e020, 0x00001001, 0xe8208000, 0x1100e028, 0x00001800, 0xe8208000, + 0x1100e040, 0x00000000, 0xe8208000, 0x1100e048, 0x00000102, 0xe8208000, + 0x1100e054, 0x00000000, 0xe8208000, 0x1100e06c, 0x00000000, 0x1840001f, + 0x1100e000, 0xe06000d7, 0xe040000b, 0xe8208000, 0x1100e024, 0x00000001, + 0x18d0001f, 0x1100e00c, 0x88c00003, 0x00000007, 0xd820f0c3, 0x17c07c1f, + 0x1840001f, 0x1100e00c, 0xe0400003, 0x18c0001f, 0x0012a360, 0x1850001f, + 0x0012a360, 0xa054040b, 0xe0c00001, 0x1800001f, 0x11015828, 0xe0000006, + 0xf0000000, 0x17c07c1f, 0x10007c1f, 0x10c07c1f, 0x00711803, 0xd820f461, + 0x17c07c1f, 0xa014000b, 0x00c01803, 0xd000f380, 0x17c07c1f, 0x18c0001f, + 0x10001f9c, 0xe0c00000, 0x18c0001f, 0x10001fa0, 0xe0c00000, 0x18c0001f, + 0x0012a364, 0x1850001f, 0x0012a364, 0xa054040b, 0xe0c00001, 0xf0000000, + 0x17c07c1f +}; +static struct pcm_desc dvfs_pcm = { + .version = "pcm_dvfs_v0.2_160125_02", + .base = dvfs_binary, + .size = 1969, + .sess = 2, + .replace = 0, + .addr_2nd = 0, +}; + +#else + +static const u32 dvfs_binary[] = { + 0x1ad0001f, 0x11015614, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, + 0x1850001f, 0x11015614, 0xb8400161, 0xfffffff0, 0x18c0001f, 0x11015614, + 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015618, 0x8ac0000b, + 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015618, 0xb8400161, + 0xfffffff0, 0x18c0001f, 0x11015618, 0xe0c00001, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x1101561c, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, + 0x1850001f, 0x1101561c, 0xb8400161, 0xfffffff0, 0x18c0001f, 0x1101561c, + 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x8ac0000b, + 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015620, 0xb8400161, + 0xfffffff0, 0x18c0001f, 0x11015620, 0xe0c00001, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x11015614, 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, + 0x17c07c1f, 0x1850001f, 0x11015614, 0x88400001, 0xffffff0f, 0xa0522c01, + 0x18c0001f, 0x11015614, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, + 0x11015618, 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, + 0x1850001f, 0x11015618, 0x88400001, 0xffffff0f, 0xa0522c01, 0x18c0001f, + 0x11015618, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x1101561c, + 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1850001f, + 0x1101561c, 0x88400001, 0xffffff0f, 0xa0522c01, 0x18c0001f, 0x1101561c, + 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x12c22c1f, + 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015620, + 0x88400001, 0xffffff0f, 0xa0522c01, 0x18c0001f, 0x11015620, 0xe0c00001, + 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015614, 0x82c7ac06, 0xf0000000, + 0x17c07c1f, 0x1850001f, 0x11015614, 0x80779801, 0xa057ac01, 0x18c0001f, + 0x11015614, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015618, + 0x82c7ac06, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015618, 0x80779801, + 0xa057ac01, 0x18c0001f, 0x11015618, 0xe0c00001, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x1101561c, 0x82c7ac06, 0xf0000000, 0x17c07c1f, 0x1850001f, + 0x1101561c, 0x80779801, 0xa057ac01, 0x18c0001f, 0x1101561c, 0xe0c00001, + 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x82c7ac06, 0xf0000000, + 0x17c07c1f, 0x1850001f, 0x11015620, 0x80779801, 0xa057ac01, 0x18c0001f, + 0x11015620, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x1101583c, + 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015840, + 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015844, + 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x1101583c, + 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, + 0x11015840, 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x11015844, 0x12c22c1f, 0x8ac0000b, 0x0000000f, 0xf0000000, + 0x17c07c1f, 0x1ad0001f, 0x1101583c, 0x12c42c1f, 0x8ac0000b, 0x0000000f, + 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015840, 0x12c42c1f, 0x8ac0000b, + 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015844, 0x12c42c1f, + 0x8ac0000b, 0x0000000f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x1101583c, + 0x82c62c06, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015840, 0x82c62c06, + 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015844, 0x82c62c06, 0xf0000000, + 0x17c07c1f, 0x1ad0001f, 0x1101583c, 0x82c6ac06, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x11015840, 0x82c6ac06, 0xf0000000, 0x17c07c1f, 0x1ad0001f, + 0x11015844, 0x82c6ac06, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015608, + 0x80769801, 0xa056ac01, 0x18c0001f, 0x11015608, 0xe0c00001, 0xf0000000, + 0x17c07c1f, 0x1850001f, 0x1101560c, 0x80769801, 0xa056ac01, 0x18c0001f, + 0x1101560c, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x1850001f, 0x11015610, + 0x80769801, 0xa056ac01, 0x18c0001f, 0x11015610, 0xe0c00001, 0xf0000000, + 0x17c07c1f, 0x1ad0001f, 0x1101583c, 0x82c72c06, 0xf0000000, 0x17c07c1f, + 0x1ad0001f, 0x11015840, 0x82c72c06, 0xf0000000, 0x17c07c1f, 0x1ad0001f, + 0x11015844, 0x82c72c06, 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x11015600, + 0x1850001f, 0x11015600, 0xa052040b, 0xe0c00001, 0xf0000000, 0x17c07c1f, + 0x18c0001f, 0x11015600, 0x1850001f, 0x11015600, 0xa054040b, 0xe0c00001, + 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x11015604, 0x1850001f, 0x11015604, + 0xa052040b, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x11015604, + 0x1850001f, 0x11015604, 0xa054040b, 0xe0c00001, 0xf0000000, 0x17c07c1f, + 0x1a10001f, 0x10220744, 0x1850001f, 0x11015320, 0x1052841f, 0x82200408, + 0x18c0001f, 0x10220744, 0xe0c00008, 0x100aac1f, 0x88000000, 0x0000001f, + 0x1850001f, 0x11015324, 0x82000408, 0x1a50001f, 0x1101531c, 0x80501809, + 0xd8202e21, 0x17c07c1f, 0xa2148008, 0x80509809, 0xd8202ea1, 0x17c07c1f, + 0xa2188008, 0x80511809, 0xd8202f21, 0x17c07c1f, 0xa2108008, 0xe0c00008, + 0x1850001f, 0x11015320, 0x1052841f, 0xa2000408, 0xe0c00008, 0xf0000000, + 0x17c07c1f, 0x1003ac1f, 0x88000000, 0x0000001f, 0x18c0001f, 0x1001a274, + 0xe8208000, 0x11015444, 0x00000001, 0x1a10001f, 0x11015444, 0xd82030c8, + 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a300003, 0x17c07c1f, 0x1a50001f, + 0x1101531c, 0x80501809, 0xd8203321, 0x17c07c1f, 0x8a000008, 0xfffffc1f, + 0xa2128008, 0x80509809, 0xd82033e1, 0x17c07c1f, 0x8a000008, 0xffff83ff, + 0xa2150008, 0x80519809, 0xd82034a1, 0x17c07c1f, 0x8a000008, 0xffffffe0, + 0xa2100008, 0x80511809, 0xd8203561, 0x17c07c1f, 0x8a000008, 0xfff07fff, + 0xa2178008, 0xe0c00008, 0x1b80001f, 0x20000006, 0xe8208000, 0x11015444, + 0x00000001, 0x1b80001f, 0x20000104, 0xf0000000, 0x17c07c1f, 0x18c0001f, + 0x0012a08c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, + 0x18c0001f, 0x0012a11c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, + 0x17c07c1f, 0x18c0001f, 0x0012a23c, 0x00f1ac03, 0x1af00003, 0x17c07c1f, + 0xf0000000, 0x17c07c1f, 0x1800001f, 0x1001a270, 0xe8208000, 0x11015444, + 0x00000001, 0x18d0001f, 0x11015444, 0xd8203983, 0x17c07c1f, 0x1b80001f, + 0x20000006, 0x18d0001f, 0x1001a270, 0x1850001f, 0x11015330, 0x80c00403, + 0x1850001f, 0x1101532c, 0xa0c00403, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1002101f, 0x88000000, 0x00000007, 0x101c001f, 0x18d0001f, 0x11015318, + 0x1b80001f, 0x20000006, 0x18700003, 0x17c07c1f, 0x88400001, 0xf8ffffff, + 0xa8400001, 0x80000000, 0xa0400001, 0xe0c00001, 0x1b80001f, 0x20000104, + 0x1800001f, 0x1001a270, 0x1b80001f, 0x20000006, 0x18d0001f, 0x1001a270, + 0x1850001f, 0x11015330, 0x80c00403, 0x1850001f, 0x11015328, 0xa0c00403, + 0xe0000003, 0x1b80001f, 0x20000006, 0xe8208000, 0x11015444, 0x00000001, + 0xf0000000, 0x17c07c1f, 0x1810001f, 0x1101530c, 0x1850001f, 0x11015318, + 0xe8208000, 0x11015444, 0x00000001, 0x18d0001f, 0x11015444, 0xd8204143, + 0x17c07c1f, 0x1b80001f, 0x20000006, 0x18f00001, 0x17c07c1f, 0x88c00003, + 0x001fffff, 0xa8c00003, 0x80000000, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1810001f, 0x11015304, 0x1b80001f, 0x20000006, 0x18f00000, 0x17c07c1f, + 0x18f00000, 0x17c07c1f, 0xa0d11803, 0xa0d01803, 0xe0000003, 0x1b80001f, + 0x20000006, 0xe8208000, 0x1001af0c, 0x06003c97, 0x1b80001f, 0x20000006, + 0x1800001f, 0x1001af00, 0x18d0001f, 0x1101531c, 0xe0000003, 0x1b80001f, + 0x20000006, 0x1240101f, 0x1246241f, 0x8a400009, 0x000001ff, 0x1256241f, + 0x1810001f, 0x11015310, 0xa8c00009, 0x80000000, 0xe0000003, 0x1b80001f, + 0x20000006, 0x10007c1f, 0x1850001f, 0x11015314, 0x1b80001f, 0x20000006, + 0x18f00001, 0x17c07c1f, 0x18f00001, 0x17c07c1f, 0x88c00003, 0x001fffff, + 0x60600c09, 0xd8004cc1, 0x17c07c1f, 0x68600000, 0x00000064, 0xd8004b01, + 0x17c07c1f, 0x00001800, 0x1b80001f, 0x20000104, 0xd0004840, 0x17c07c1f, + 0x1810001f, 0x0012a3a8, 0xa0120006, 0x1a00001f, 0x0012a3a8, 0xe2000000, + 0x1a00001f, 0x0012a3ac, 0xe2000009, 0x1a00001f, 0x0012a3b0, 0xe2000003, + 0xd0004840, 0x17c07c1f, 0x88c00003, 0x001fffff, 0x1810001f, 0x11015318, + 0x1b80001f, 0x20000006, 0x18700000, 0x17c07c1f, 0x88400001, 0xffe00000, + 0xa8400001, 0x80000000, 0xa0c00403, 0xe0000003, 0x1b80001f, 0x20000006, + 0x1800001f, 0x1001af00, 0x10c07c1f, 0xe0000003, 0x1b80001f, 0x20000006, + 0xe8208000, 0x11015444, 0x00000001, 0xf0000000, 0x17c07c1f, 0x10007c1f, + 0xc0002b80, 0x17c07c1f, 0x20602805, 0xd8205121, 0x17c07c1f, 0xc1003020, + 0x17c07c1f, 0x1002101f, 0x88000000, 0x00000007, 0x10c2081f, 0x88c00003, + 0x00000007, 0x20600c00, 0xd8205281, 0x17c07c1f, 0xc2003940, 0x17c07c1f, + 0xc10040c0, 0x17c07c1f, 0x1002101f, 0x88000000, 0x00000007, 0x18d0001f, + 0x11015318, 0xe8208000, 0x11015444, 0x00000001, 0x1a50001f, 0x11015444, + 0xd8205369, 0x17c07c1f, 0x1b80001f, 0x20000006, 0x1a700003, 0x17c07c1f, + 0xe8208000, 0x11015444, 0x00000001, 0x124c241f, 0x8a400009, 0x00000007, + 0x40602400, 0xd8205621, 0x17c07c1f, 0xc2003940, 0x17c07c1f, 0x40602805, + 0xd82056c1, 0x17c07c1f, 0xc1003020, 0x17c07c1f, 0xc1002b80, 0x17c07c1f, + 0x1800001f, 0x11015828, 0xe0000006, 0xf0000000, 0x17c07c1f, 0x1a00001f, + 0x11015304, 0x12407c1f, 0x68600009, 0x0000000c, 0xd8005981, 0x17c07c1f, + 0x18f00000, 0x17c07c1f, 0xe2000003, 0x00111800, 0x02111808, 0x02401809, + 0xd0005800, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x1800001f, 0x11015608, + 0x12407c1f, 0x68600009, 0x00000007, 0xd8005ba1, 0x17c07c1f, 0x18f00000, + 0x17c07c1f, 0xe2000003, 0x00111800, 0x02111808, 0x02401809, 0xd0005a20, + 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x8a400009, 0x00007fff, 0x1255a41f, + 0x88c00002, 0x000000f0, 0xa2518c09, 0x89000002, 0x00007f00, 0xa2441009, + 0x89400002, 0x003f0000, 0xa2551409, 0xf0000000, 0x17c07c1f, 0x1a00001f, + 0x11015624, 0x02002808, 0x18b00008, 0x17c07c1f, 0x1840001f, 0x00120000, + 0x00c00801, 0xe0c00009, 0x08800002, 0x00000018, 0x0940000a, 0x0000cff8, + 0x71201402, 0xd8005fe4, 0x17c07c1f, 0x0880000a, 0x0000a3d0, 0xe2000002, + 0x00c00801, 0xe0c0001f, 0xf0000000, 0x17c07c1f, 0x1a50001f, 0x11015150, + 0x12807c1f, 0xc2805da0, 0x17c07c1f, 0x1a50001f, 0x1101563c, 0x1890001f, + 0x11015614, 0xc2405be0, 0x17c07c1f, 0x1291181f, 0xc2805da0, 0x17c07c1f, + 0x1a50001f, 0x11015640, 0x1890001f, 0x11015618, 0xc2405be0, 0x17c07c1f, + 0x0291180a, 0xc2805da0, 0x17c07c1f, 0x1a50001f, 0x11015644, 0x1890001f, + 0x1101561c, 0xc2405be0, 0x17c07c1f, 0x0291180a, 0xc2805da0, 0x17c07c1f, + 0x12407c1f, 0x1890001f, 0x11015620, 0xc2405be0, 0x17c07c1f, 0x0291180a, + 0xc2805da0, 0x17c07c1f, 0x12407c1f, 0xc10026e0, 0x17c07c1f, 0xd82068a4, 0x17c07c1f, 0x1a10001f, 0x10222510, 0x8a000008, 0x0f800000, 0x1251a01f, 0x1a10001f, 0x102224c8, 0x8a000008, 0x0000ff00, 0xa2552009, 0x1a10001f, 0x10222498, 0x8a000008, 0x0007fc00, 0xa240a009, 0x1a10001f, 0x102224cc, - 0x8a000008, 0x7fc00000, 0xa24b2009, 0x0291180a, 0xc2805ce0, 0x17c07c1f, + 0x8a000008, 0x7fc00000, 0xa24b2009, 0x0291180a, 0xc2805da0, 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, @@ -206,7 +550,6 @@ static const u32 dvfs_binary[] = { 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, - 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x1980001f, 0x00000001, 0x1b80001f, 0x20003365, 0x12807c1f, 0xc28010a0, 0x17c07c1f, 0xc2801260, 0x17c07c1f, 0xc2801420, 0x17c07c1f, 0x1810001f, 0x11015608, 0x1850001f, @@ -229,7 +572,7 @@ static const u32 dvfs_binary[] = { 0x17c07c1f, 0xc08001e0, 0x17c07c1f, 0xc0800a80, 0x17c07c1f, 0x1080181f, 0xc0801260, 0x17c07c1f, 0xc10021a0, 0x17c07c1f, 0xd8209064, 0x17c07c1f, 0xc08003c0, 0x17c07c1f, 0xc0800ca0, 0x17c07c1f, 0x1080181f, 0xc0801420, - 0x17c07c1f, 0xd000d480, 0x17c07c1f, 0x10807c1f, 0xc0801420, 0x17c07c1f, + 0x17c07c1f, 0xd000d780, 0x17c07c1f, 0x10807c1f, 0xc0801420, 0x17c07c1f, 0xd0009a20, 0x17c07c1f, 0x10807c1f, 0xc0801260, 0x17c07c1f, 0xc10021a0, 0x17c07c1f, 0xd8209304, 0x17c07c1f, 0xc08003c0, 0x17c07c1f, 0xc0800ca0, 0x17c07c1f, 0x1080181f, 0xc0801420, 0x17c07c1f, 0xd0009a20, 0x17c07c1f, @@ -253,72 +596,76 @@ static const u32 dvfs_binary[] = { 0xc0800a80, 0x17c07c1f, 0xc0802060, 0x17c07c1f, 0xd820a0a2, 0x17c07c1f, 0xe2000006, 0xc10026e0, 0x17c07c1f, 0xc08021a0, 0x17c07c1f, 0xa1000804, 0xd800a264, 0x17c07c1f, 0x1090981f, 0xc0800ca0, 0x17c07c1f, 0xc0800480, - 0x17c07c1f, 0xd000cde0, 0x17c07c1f, 0x1a00001f, 0x0012a368, 0xc2005900, + 0x17c07c1f, 0xd000d0e0, 0x17c07c1f, 0x1a00001f, 0x0012a368, 0xc20059c0, 0x17c07c1f, 0xc10025a0, 0x17c07c1f, 0xd820a564, 0x17c07c1f, 0xc1400780, 0x17c07c1f, 0x1100141f, 0x18c0001f, 0x0012a088, 0x00f19403, 0x19700003, - 0x17c07c1f, 0x1800001f, 0x11015804, 0xe0000005, 0xc1003600, 0x17c07c1f, + 0x17c07c1f, 0x1800001f, 0x11015804, 0xe0000005, 0xc10036a0, 0x17c07c1f, 0x1800001f, 0x11015808, 0xe0000004, 0xc1002640, 0x17c07c1f, 0xd820a7e4, 0x17c07c1f, 0xc14009a0, 0x17c07c1f, 0x1100141f, 0x18c0001f, 0x0012a118, 0x00f19403, 0x19700003, 0x17c07c1f, 0x1800001f, 0x1101580c, 0xe0000005, - 0xc10036e0, 0x17c07c1f, 0x1800001f, 0x11015810, 0xe0000004, 0xc10026e0, + 0xc1003780, 0x17c07c1f, 0x1800001f, 0x11015810, 0xe0000004, 0xc10026e0, 0x17c07c1f, 0xd820aa04, 0x17c07c1f, 0xc1400bc0, 0x17c07c1f, 0x1100141f, - 0xc140d4e0, 0x17c07c1f, 0x1800001f, 0x11015814, 0xe0000005, 0xc10037c0, + 0xc140d7e0, 0x17c07c1f, 0x1800001f, 0x11015814, 0xe0000005, 0xc1003860, 0x17c07c1f, 0x1800001f, 0x11015818, 0xe0000004, 0x1a90001f, 0x11015808, 0x1950001f, 0x11015810, 0x2060140a, 0xd820ac81, 0x17c07c1f, 0x1950001f, - 0x11015818, 0x2060140a, 0xd820ac01, 0x17c07c1f, 0xc280da20, 0x17c07c1f, - 0xd000ade0, 0x17c07c1f, 0xc140da20, 0x17c07c1f, 0xd000ade0, 0x17c07c1f, - 0x1a90001f, 0x11015818, 0x20602805, 0xd820ada1, 0x17c07c1f, 0xc140da20, - 0x17c07c1f, 0xd000ade0, 0x17c07c1f, 0xc280da20, 0x17c07c1f, 0x1850001f, + 0x11015818, 0x2060140a, 0xd820ac01, 0x17c07c1f, 0xc280dd20, 0x17c07c1f, + 0xd000ade0, 0x17c07c1f, 0xc140dd20, 0x17c07c1f, 0xd000ade0, 0x17c07c1f, + 0x1a90001f, 0x11015818, 0x20602805, 0xd820ada1, 0x17c07c1f, 0xc140dd20, + 0x17c07c1f, 0xd000ade0, 0x17c07c1f, 0xc280dd20, 0x17c07c1f, 0x1850001f, 0x1101582c, 0xd800b121, 0x17c07c1f, 0x1910001f, 0x1101581c, 0x1283901f, - 0x89000004, 0x0000007f, 0xc080d860, 0x17c07c1f, 0xc140d940, 0x17c07c1f, - 0x20600804, 0xd820b061, 0x17c07c1f, 0xc0c0e020, 0x17c07c1f, 0xd000b120, + 0x89000004, 0x0000007f, 0xc080db60, 0x17c07c1f, 0xc140dc40, 0x17c07c1f, + 0x20600804, 0xd820b061, 0x17c07c1f, 0xc0c0e320, 0x17c07c1f, 0xd000b120, 0x17c07c1f, 0x40600804, 0xd820b121, 0x17c07c1f, 0x1800001f, 0x11015824, 0xe0000006, 0xc1400000, 0x17c07c1f, 0xc2800780, 0x17c07c1f, 0x00602805, 0xd820b481, 0x17c07c1f, 0x1800001f, 0x0000000a, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, 0xc2802980, 0x17c07c1f, 0x1800001f, 0x11015334, - 0xc00056e0, 0x17c07c1f, 0x1080141f, 0xc0803600, 0x17c07c1f, 0x1100281f, - 0xc1003600, 0x17c07c1f, 0xc1004f80, 0x17c07c1f, 0xc14001e0, 0x17c07c1f, + 0xc00057a0, 0x17c07c1f, 0x1080141f, 0xc08036a0, 0x17c07c1f, 0x1100281f, + 0xc10036a0, 0x17c07c1f, 0xc1005020, 0x17c07c1f, 0xc14001e0, 0x17c07c1f, 0xc28009a0, 0x17c07c1f, 0x00602805, 0xd820b7e1, 0x17c07c1f, 0x1800001f, 0x0000000b, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, 0xc2802980, - 0x17c07c1f, 0x1800001f, 0x11015364, 0xc00056e0, 0x17c07c1f, 0x1080141f, - 0xc08036e0, 0x17c07c1f, 0x1100281f, 0xc10036e0, 0x17c07c1f, 0xc1004f80, - 0x17c07c1f, 0xc14003c0, 0x17c07c1f, 0xc2800bc0, 0x17c07c1f, 0x00602805, - 0xd820c6a1, 0x17c07c1f, 0x1100281f, 0xc10037c0, 0x17c07c1f, 0x1800001f, - 0x0000000d, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, 0xc2802980, - 0x17c07c1f, 0xe8208000, 0x1101531c, 0x00000008, 0x70607c0a, 0xd820bb21, - 0x17c07c1f, 0xc1002f80, 0x17c07c1f, 0x1800001f, 0x10222470, 0x18f00000, - 0x17c07c1f, 0xa0d31803, 0xe0000003, 0x8a400003, 0x0000f000, 0x88c00003, - 0xffff0fff, 0xa8c00003, 0x00003000, 0xe0000003, 0x10007c1f, 0x60739800, - 0xd800c181, 0x17c07c1f, 0x00001800, 0x1b80001f, 0x20000034, 0x18d0001f, - 0x102224c8, 0x80d09803, 0xd820bce3, 0x17c07c1f, 0x1b80001f, 0x2000001a, - 0x1200281f, 0xc200d4e0, 0x17c07c1f, 0x18c0001f, 0x10222498, 0x1006a01f, - 0xe0c00000, 0x1840001f, 0x0012a3a4, 0xe0400000, 0x1b80001f, 0x2000001a, - 0x38600000, 0x0003b999, 0xd820c121, 0x17c07c1f, 0xe8208000, 0x102224c0, - 0x00028d00, 0xd000c180, 0x17c07c1f, 0xe8208000, 0x102224c0, 0x00014333, - 0x1800001f, 0x10222470, 0x18f00000, 0x17c07c1f, 0x88c00003, 0xffff0fff, - 0xa0c02403, 0xe0000003, 0x1b80001f, 0x2000001a, 0x80f31803, 0xe0000003, - 0x60607c0a, 0xd820c3a1, 0x17c07c1f, 0xc1002f80, 0x17c07c1f, 0x1910001f, + 0x17c07c1f, 0x1800001f, 0x11015364, 0xc00057a0, 0x17c07c1f, 0x1080141f, + 0xc0803780, 0x17c07c1f, 0x1100281f, 0xc1003780, 0x17c07c1f, 0xc1005020, + 0x17c07c1f, 0xc10026e0, 0x17c07c1f, 0xd820c9a4, 0x17c07c1f, 0xc14003c0, + 0x17c07c1f, 0xc2800bc0, 0x17c07c1f, 0x00602805, 0x1200281f, 0xc200d7e0, + 0x17c07c1f, 0x1206a01f, 0x18c0001f, 0x10222498, 0x1a700003, 0x17c07c1f, + 0x00202408, 0xa0400001, 0xd820c9a1, 0x17c07c1f, 0x1100281f, 0xc1003860, + 0x17c07c1f, 0x1800001f, 0x0000000d, 0xc0002980, 0x17c07c1f, 0xc1402980, + 0x17c07c1f, 0xc2802980, 0x17c07c1f, 0xe8208000, 0x11015414, 0x00000001, + 0x1a10001f, 0x11015414, 0xd820bbe8, 0x17c07c1f, 0xe8208000, 0x1101531c, + 0x00000008, 0x70607c0a, 0xd820bdc1, 0x17c07c1f, 0xc1003020, 0x17c07c1f, + 0x1800001f, 0x10222470, 0x18f00000, 0x17c07c1f, 0xa0d31803, 0xe0000003, + 0x8a400003, 0x0000f000, 0x88c00003, 0xffff0fff, 0xa8c00003, 0x00003000, + 0xe0000003, 0x10007c1f, 0x60739800, 0xd800c421, 0x17c07c1f, 0x00001800, + 0x1b80001f, 0x20000034, 0x18d0001f, 0x102224c8, 0x80d09803, 0xd820bf83, + 0x17c07c1f, 0x1b80001f, 0x2000001a, 0x1200281f, 0xc200d7e0, 0x17c07c1f, + 0x18c0001f, 0x10222498, 0x1006a01f, 0xe0c00000, 0x1840001f, 0x0012a3a4, + 0xe0400000, 0x1b80001f, 0x2000001a, 0x38600000, 0x0003b999, 0xd820c3c1, + 0x17c07c1f, 0xe8208000, 0x102224c0, 0x00028d00, 0xd000c420, 0x17c07c1f, + 0xe8208000, 0x102224c0, 0x00014333, 0x1800001f, 0x10222470, 0x18f00000, + 0x17c07c1f, 0x88c00003, 0xffff0fff, 0xa0c02403, 0xe0000003, 0x1b80001f, + 0x2000001a, 0x80f31803, 0xe0000003, 0x60607c0a, 0xd820c641, 0x17c07c1f, + 0xc1003020, 0x17c07c1f, 0xe8208000, 0x11015414, 0x00000001, 0x1910001f, 0x11015814, 0x1283901f, 0x8a80000a, 0x0000007f, 0x89000004, 0x0000007f, 0x1850001f, 0x1101561c, 0x88400001, 0xffff80ff, 0xa0541001, 0x18c0001f, 0x1101561c, 0xe0c00001, 0x1850001f, 0x1101561c, 0x88400001, 0xff80ffff, 0xa0582801, 0xe0c00001, 0x1800001f, 0x11015828, 0xe0000006, 0xc14005a0, - 0x17c07c1f, 0xc2800de0, 0x17c07c1f, 0x00602805, 0xd820ca01, 0x17c07c1f, + 0x17c07c1f, 0xc2800de0, 0x17c07c1f, 0x00602805, 0xd820cd01, 0x17c07c1f, 0x1800001f, 0x0000000c, 0xc0002980, 0x17c07c1f, 0xc1402980, 0x17c07c1f, - 0xc2802980, 0x17c07c1f, 0x1800001f, 0x11015394, 0xc00056e0, 0x17c07c1f, - 0x1080141f, 0xc080d6a0, 0x17c07c1f, 0x1100281f, 0xc100d6a0, 0x17c07c1f, - 0xc1004f80, 0x17c07c1f, 0x1850001f, 0x11015824, 0xd820cbe1, 0x17c07c1f, - 0x1910001f, 0x1101581c, 0x1283901f, 0x89000004, 0x0000007f, 0xc080d860, - 0x17c07c1f, 0xc140d940, 0x17c07c1f, 0xc0c0e020, 0x17c07c1f, 0xc2800de0, + 0xc2802980, 0x17c07c1f, 0x1800001f, 0x11015394, 0xc00057a0, 0x17c07c1f, + 0x1080141f, 0xc080d9a0, 0x17c07c1f, 0x1100281f, 0xc100d9a0, 0x17c07c1f, + 0xc1005020, 0x17c07c1f, 0x1850001f, 0x11015824, 0xd820cee1, 0x17c07c1f, + 0x1910001f, 0x1101581c, 0x1283901f, 0x89000004, 0x0000007f, 0xc080db60, + 0x17c07c1f, 0xc140dc40, 0x17c07c1f, 0xc0c0e320, 0x17c07c1f, 0xc2800de0, 0x17c07c1f, 0xc2800660, 0x17c07c1f, 0xc2800780, 0x17c07c1f, 0xc28000c0, 0x17c07c1f, 0xc28009a0, 0x17c07c1f, 0xc28002a0, 0x17c07c1f, 0xc2800bc0, 0x17c07c1f, 0xc2800480, 0x17c07c1f, 0xc10025a0, 0x17c07c1f, 0xc0802060, - 0x17c07c1f, 0xa1000804, 0xd800cf04, 0x17c07c1f, 0xc1802240, 0x17c07c1f, - 0xc1002640, 0x17c07c1f, 0xc0802100, 0x17c07c1f, 0xa1000804, 0xd800d024, + 0x17c07c1f, 0xa1000804, 0xd800d204, 0x17c07c1f, 0xc1802240, 0x17c07c1f, + 0xc1002640, 0x17c07c1f, 0xc0802100, 0x17c07c1f, 0xa1000804, 0xd800d324, 0x17c07c1f, 0xc1802360, 0x17c07c1f, 0xc10026e0, 0x17c07c1f, 0xc08021a0, - 0x17c07c1f, 0xa1000804, 0xd800d144, 0x17c07c1f, 0xc1802480, 0x17c07c1f, - 0x1850001f, 0x11015828, 0xd820d201, 0x17c07c1f, 0xc0c05fc0, 0x17c07c1f, + 0x17c07c1f, 0xa1000804, 0xd800d444, 0x17c07c1f, 0xc1802480, 0x17c07c1f, + 0x1850001f, 0x11015828, 0xd820d501, 0x17c07c1f, 0xc0c06080, 0x17c07c1f, 0xc1801420, 0x17c07c1f, 0xc1801260, 0x17c07c1f, 0xc18010a0, 0x17c07c1f, - 0xc18015e0, 0x17c07c1f, 0x1a00001f, 0x0012a384, 0xc2005900, 0x17c07c1f, + 0xc18015e0, 0x17c07c1f, 0x1a00001f, 0x0012a384, 0xc20059c0, 0x17c07c1f, 0x1a00001f, 0x0012a3a0, 0x18d0001f, 0x11015604, 0xe2000003, 0xe8208000, 0x11015424, 0x00000001, 0xd0008040, 0x17c07c1f, 0xf0000000, 0x18c0001f, 0x0012a238, 0x00f1ac03, 0x1af00003, 0x17c07c1f, 0xf0000000, 0x17c07c1f, @@ -328,27 +675,27 @@ static const u32 dvfs_binary[] = { 0x0000007f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x12c42c1f, 0x8ac0000b, 0x0000007f, 0xf0000000, 0x17c07c1f, 0x1ad0001f, 0x11015620, 0x12c82c1f, 0x8ac0000b, 0x0000007f, 0xf0000000, 0x17c07c1f, 0x8800000b, - 0x0000000f, 0xc000d5c0, 0x17c07c1f, 0x18d0001f, 0x11015804, 0x20600003, - 0xd820db61, 0x17c07c1f, 0x10000c1f, 0x18d0001f, 0x1101580c, 0x20600003, - 0xd820dc21, 0x17c07c1f, 0x10000c1f, 0x18c0001f, 0x1101581c, 0xe0c00000, - 0x1212181f, 0x02201808, 0x1240201f, 0xd820de29, 0x17c07c1f, 0xc240d5c0, - 0x17c07c1f, 0x50600009, 0xd800de21, 0x17c07c1f, 0x02201808, 0xd000dcc0, - 0x17c07c1f, 0x1240201f, 0xc240d6a0, 0x17c07c1f, 0x18c0001f, 0x11015820, + 0x0000000f, 0xc000d8c0, 0x17c07c1f, 0x18d0001f, 0x11015804, 0x20600003, + 0xd820de61, 0x17c07c1f, 0x10000c1f, 0x18d0001f, 0x1101580c, 0x20600003, + 0xd820df21, 0x17c07c1f, 0x10000c1f, 0x18c0001f, 0x1101581c, 0xe0c00000, + 0x1212181f, 0x02201808, 0x1240201f, 0xd820e129, 0x17c07c1f, 0xc240d8c0, + 0x17c07c1f, 0x50600009, 0xd800e121, 0x17c07c1f, 0x02201808, 0xd000dfc0, + 0x17c07c1f, 0x1240201f, 0xc240d9a0, 0x17c07c1f, 0x18c0001f, 0x11015820, 0xe0c00009, 0x1850001f, 0x11015620, 0x88400001, 0xffffff0f, 0xa0522001, 0x18c0001f, 0x11015620, 0xe0c00001, 0xf0000000, 0x17c07c1f, 0x28600004, - 0x0000005a, 0xd820e0e1, 0x17c07c1f, 0x1900001f, 0x0000005a, 0x48600004, - 0x00000020, 0xd820e1a1, 0x17c07c1f, 0x1900001f, 0x00000020, 0x60600804, - 0xd820e241, 0x17c07c1f, 0xd000e9e0, 0x17c07c1f, 0x20600804, 0xd820e641, - 0x17c07c1f, 0x1200081f, 0x1240141f, 0x60602004, 0xd820e381, 0x17c07c1f, - 0xd000e9e0, 0x17c07c1f, 0x0a000008, 0x0000000a, 0x20601008, 0xd820e441, - 0x17c07c1f, 0x1200101f, 0x60602809, 0xd800e541, 0x17c07c1f, 0x02511809, - 0x20602809, 0xd820e541, 0x17c07c1f, 0x1240281f, 0xc240f740, 0x17c07c1f, - 0xc200ef60, 0x17c07c1f, 0x1b80001f, 0x20000300, 0xd000e2e0, 0x17c07c1f, - 0x1200081f, 0x1240141f, 0x60602004, 0xd820e721, 0x17c07c1f, 0xd000e9e0, - 0x17c07c1f, 0x0a200008, 0x0000000a, 0x40601008, 0xd820e7e1, 0x17c07c1f, - 0x1200101f, 0xc200ef60, 0x17c07c1f, 0x60602809, 0xd800e921, 0x17c07c1f, - 0x02711809, 0x40602809, 0xd820e921, 0x17c07c1f, 0x1240281f, 0xc240f740, - 0x17c07c1f, 0x1b80001f, 0x20000300, 0xd000e680, 0x17c07c1f, 0x1850001f, + 0x0000005a, 0xd820e3e1, 0x17c07c1f, 0x1900001f, 0x0000005a, 0x48600004, + 0x00000020, 0xd820e4a1, 0x17c07c1f, 0x1900001f, 0x00000020, 0x60600804, + 0xd820e541, 0x17c07c1f, 0xd000ece0, 0x17c07c1f, 0x20600804, 0xd820e941, + 0x17c07c1f, 0x1200081f, 0x1240141f, 0x60602004, 0xd820e681, 0x17c07c1f, + 0xd000ece0, 0x17c07c1f, 0x0a000008, 0x0000000a, 0x20601008, 0xd820e741, + 0x17c07c1f, 0x1200101f, 0x60602809, 0xd800e841, 0x17c07c1f, 0x02511809, + 0x20602809, 0xd820e841, 0x17c07c1f, 0x1240281f, 0xc240fa40, 0x17c07c1f, + 0xc200f260, 0x17c07c1f, 0x1b80001f, 0x20000300, 0xd000e5e0, 0x17c07c1f, + 0x1200081f, 0x1240141f, 0x60602004, 0xd820ea21, 0x17c07c1f, 0xd000ece0, + 0x17c07c1f, 0x0a200008, 0x0000000a, 0x40601008, 0xd820eae1, 0x17c07c1f, + 0x1200101f, 0xc200f260, 0x17c07c1f, 0x60602809, 0xd800ec21, 0x17c07c1f, + 0x02711809, 0x40602809, 0xd820ec21, 0x17c07c1f, 0x1240281f, 0xc240fa40, + 0x17c07c1f, 0x1b80001f, 0x20000300, 0xd000e980, 0x17c07c1f, 0x1850001f, 0x11015620, 0x88400001, 0xffff80ff, 0xa0541001, 0x18c0001f, 0x11015620, 0xe0c00001, 0x1850001f, 0x11015620, 0x88400001, 0xff80ffff, 0xa0582801, 0xe0c00001, 0x1850001f, 0x11015614, 0x88400001, 0xffff80ff, 0xa0541001, @@ -364,21 +711,22 @@ static const u32 dvfs_binary[] = { 0x00000102, 0xe8208000, 0x1100e054, 0x00000000, 0xe8208000, 0x1100e06c, 0x00000000, 0x1840001f, 0x1100e000, 0xe06000d7, 0xe040000b, 0xe8208000, 0x1100e024, 0x00000001, 0x18d0001f, 0x1100e00c, 0x88c00003, 0x00000007, - 0xd820f4c3, 0x17c07c1f, 0x1840001f, 0x1100e00c, 0xe0400003, 0x18c0001f, + 0xd820f7c3, 0x17c07c1f, 0x1840001f, 0x1100e00c, 0xe0400003, 0x18c0001f, 0x0012a360, 0x1850001f, 0x0012a360, 0xa054040b, 0xe0c00001, 0x1800001f, 0x11015828, 0xe0000006, 0xf0000000, 0x17c07c1f, 0x10007c1f, 0x10c07c1f, - 0x00711803, 0xd820f861, 0x17c07c1f, 0xa014000b, 0x00c01803, 0xd000f780, + 0x00711803, 0xd820fb61, 0x17c07c1f, 0xa014000b, 0x00c01803, 0xd000fa80, 0x17c07c1f, 0x18c0001f, 0x10001f9c, 0xe0c00000, 0x18c0001f, 0x10001fa0, 0xe0c00000, 0x18c0001f, 0x0012a364, 0x1850001f, 0x0012a364, 0xa054040b, 0xe0c00001, 0xf0000000, 0x17c07c1f }; static struct pcm_desc dvfs_pcm = { - .version = "pcm_dvfs_v0.1_160114_01", + .version = "pcm_dvfs_v0.1_160131_02", .base = dvfs_binary, - .size = 2001, + .size = 2025, .sess = 2, .replace = 0, .addr_2nd = 0, }; +#endif #endif /* _MT_CPUFREQ_HYBRID_FW_ */ diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_eem.c b/drivers/misc/mediatek/base/power/mt6797/mt_eem.c index e62fa7d1d03b..931741661163 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_eem.c +++ b/drivers/misc/mediatek/base/power/mt6797/mt_eem.c @@ -124,10 +124,18 @@ unsigned int bigFreq_SB_7[16] = { 2522000, 2392000, 2327000, 2262000, 2223000, 2158000, 2093000, 1885000, 1677000, 1495000, 1378000, 1131000, 1001000, 845000, 676000, 338000}; +unsigned int bigFreq_SBP_7[16] = { + 2587000, 2431000, 2327000, 2262000, 2223000, 2158000, 2093000, 1885000, + 1677000, 1495000, 1378000, 1131000, 1001000, 845000, 676000, 338000}; + unsigned int bigFreq_MB_7[16] = { 2106000, 1989000, 1963000, 1898000, 1859000, 1768000, 1586000, 1495000, 1339000, 1222000, 1118000, 1001000, 897000, 741000, 598000, 304000}; +unsigned int bigFreq_LB_7[16] = { + 1794000, 1729000, 1690000, 1625000, 1573000, 1495000, 1339000, 1261000, + 1092000, 949000, 897000, 793000, 702000, 598000, 507000, 304000}; + /* GPU */ unsigned int gpuFreq_FY_7[16] = { 780000, 780000, 700000, 700000, 610000, 610000, 520000, 520000, @@ -137,26 +145,38 @@ unsigned int gpuFreq_SB_7[16] = { 850000, 850000, 700000, 700000, 610000, 610000, 520000, 520000, 442500, 442500, 365000, 365000, 238000, 238000, 154500, 154500}; +unsigned int gpuFreq_SBP_7[16] = { + 900000, 900000, 780000, 780000, 610000, 610000, 520000, 520000, + 442500, 442500, 365000, 365000, 238000, 238000, 154500, 154500}; + unsigned int gpuFreq_MB_7[16] = { 700000, 700000, 610000, 610000, 520000, 520000, 442500, 442500, 365000, 365000, 301500, 301500, 238000, 238000, 154500, 154500}; +unsigned int gpuFreq_LB_7[16] = { + 600000, 600000, 522500, 522500, 445000, 445000, 379000, 379000, + 313000, 313000, 258500, 258500, 204000, 204000, 154500, 154500}; + /* L */ unsigned int L_Freq_FY_7[16] = { 1846000, 1781000, 1703000, 1625000, 1495000, 1417000, 1274000, 1209000, - 1079000, 949000, 832000, 741000, 650000, 559000, 468000, 325000}; + 1092000, 949000, 832000, 741000, 650000, 559000, 468000, 325000}; unsigned int L_Freq_SB_7[16] = { 2002000, 1950000, 1885000, 1820000, 1755000, 1703000, 1625000, 1495000, - 1352000, 1209000, 1079000, 962000, 832000, 650000, 468000 , 325000}; + 1352000, 1209000, 1092000, 962000, 832000, 650000, 468000 , 325000}; unsigned int L_Freq_MB_7[16] = { 1846000, 1781000, 1703000, 1625000, 1495000, 1417000, 1274000, 1209000, - 1079000, 949000, 832000, 741000, 650000, 559000, 468000, 325000}; + 1092000, 949000, 832000, 741000, 650000, 559000, 468000, 325000}; + +unsigned int L_Freq_LB_7[16] = { + 1599000, 1534000, 1456000, 1378000, 1274000, 1209000, 1092000, 949000, + 936000, 845000, 754000, 689000, 611000, 546000, 468000, 325000}; /* LL */ unsigned int LL_Freq_FY_7[16] = { - 1391000, 1339000, 1287000, 1222000, 1118000, 1066000, 949000, 897000, + 1391000, 1339000, 1287000, 1222000, 1118000, 1092000, 949000, 897000, 806000, 715000, 624000, 559000, 481000, 416000, 338000, 221000}; unsigned int LL_Freq_SB_7[16] = { @@ -164,7 +184,11 @@ unsigned int LL_Freq_SB_7[16] = { 1014000, 897000, 806000, 715000, 624000, 481000, 338000, 221000}; unsigned int LL_Freq_MB_7[16] = { - 1391000, 1339000, 1287000, 1222000, 1118000, 1066000, 949000, 897000, + 1391000, 1339000, 1287000, 1222000, 1118000, 1092000, 949000, 897000, + 806000, 715000, 624000, 559000, 481000, 416000, 338000, 221000}; + +unsigned int LL_Freq_LB_7[16] = { + 1391000, 1339000, 1287000, 1222000, 1118000, 1092000, 949000, 897000, 806000, 715000, 624000, 559000, 481000, 416000, 338000, 221000}; /* CCI */ @@ -180,6 +204,10 @@ unsigned int cciFreq_MB_7[16] = { 923000, 884000, 858000, 819000, 754000, 715000, 637000, 611000, 533000, 481000, 416000, 377000, 325000, 286000, 234000, 169000}; +unsigned int cciFreq_LB_7[16] = { + 806000, 767000, 728000, 689000, 637000, 611000, 546000, 520000, + 468000, 429000, 377000, 338000, 312000, 273000, 234000, 169000}; + /* [25:21] dcmdiv [20:12] DDS @@ -195,6 +223,7 @@ unsigned int cciFreq_MB_7[16] = { unsigned int tFyTbl[6] = {0x1F, 0x16C, 0x8, 0x0, 0xF, 0x2F51F};/* 2.366 */ unsigned int tSbTbl[6] = {0x1F, 0x18C, 0x8, 0x0, 0xF, 0x337AE};/* 2.574 */ unsigned int tMbTbl[6] = {0x1E, 0x14C, 0x8, 0x0, 0xF, 0x2B28F};/* 2.158 */ +unsigned int tLbTbl[6] = {0x1A, 0x11C, 0x8, 0x0, 0xF, 0x24EB8};/* 1.846 */ unsigned int fyTbl_7[][8] = { /* dcmdiv, DDS, clk_div, post_div, CF_index, iDVFS, Vsram, Vproc */ @@ -203,7 +232,7 @@ unsigned int fyTbl_7[][8] = { {0x12, 0x0C6, 0x8, 0x0, 0xA, 0x0, 0x0F, 0x55},/* 1.287 */ {0x11, 0x0BC, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x53},/* 1.222 */ {0x0F, 0x0AC, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x4F},/* 1.118 */ - {0x0F, 0x0A4, 0x8, 0x0, 0x7, 0x0, 0x0E, 0x4D},/* 1.066 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x8, 0x0, 0x0E, 0x4D},/* 1.092 */ {0x0D, 0x124, 0x8, 0x1, 0x6, 0x0, 0x0C, 0x48},/* 0.949 */ {0x0C, 0x114, 0x8, 0x1, 0x6, 0x0, 0x0B, 0x46},/* 0.897 */ {0x0B, 0x0F8, 0x8, 0x1, 0x5, 0x0, 0x0A, 0x43},/* 0.806 */ @@ -223,7 +252,7 @@ unsigned int fyTbl_7[][8] = { {0x14, 0x0DA, 0x8, 0x0, 0xA, 0x0, 0x0E, 0x4D},/* 1.417 */ {0x12, 0x0C4, 0x8, 0x0, 0x9, 0x0, 0x0C, 0x48},/* 1.274 */ {0x11, 0x0BA, 0x8, 0x0, 0x8, 0x0, 0x0B, 0x46},/* 1.209 */ - {0x0F, 0x0A6, 0x8, 0x0, 0x8, 0x0, 0x0A, 0x43},/* 1.079 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x8, 0x0, 0x0A, 0x43},/* 1.092 */ {0x0D, 0x124, 0x8, 0x1, 0x6, 0x0, 0x09, 0x40},/* 0.949 */ {0x0B, 0x100, 0x8, 0x1, 0x5, 0x0, 0x07, 0x3C},/* 0.832 */ {0x0A, 0x0E4, 0x8, 0x1, 0x4, 0x0, 0x07, 0x3A},/* 0.741 */ @@ -295,7 +324,7 @@ unsigned int sbTbl_7[][8] = { {0x15, 0x0E6, 0x8, 0x0, 0x8, 0x0, 0x0E, 0x4D},/* 1.495 */ {0x13, 0x0D0, 0x8, 0x0, 0x7, 0x0, 0x0D, 0x4A},/* 1.352 */ {0x11, 0x0BA, 0x8, 0x0, 0x6, 0x0, 0x0B, 0x46},/* 1.209 */ - {0x0F, 0x0A6, 0x8, 0x0, 0x6, 0x0, 0x0A, 0x43},/* 1.079 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x6, 0x0, 0x0A, 0x43},/* 1.092 */ {0x0D, 0x128, 0x8, 0x1, 0x4, 0x0, 0x09, 0x40},/* 0.962 */ {0x0B, 0x100, 0x8, 0x1, 0x3, 0x0, 0x07, 0x3C},/* 0.832 */ {0x09, 0x0C8, 0x8, 0x1, 0x2, 0x0, 0x07, 0x37},/* 0.65 */ @@ -337,6 +366,76 @@ unsigned int sbTbl_7[][8] = { {0x04, 0x09C, 0x1a, 0x1, 0x0, 0x6C29, 0x07, 0x32},/* 0.338 */ }; +unsigned int sbpTbl_7[][8] = { + {0x16, 0x0EE, 0x8, 0x0, 0x9, 0x0, 0x0F, 0x5A},/* 1.547 (LL)*/ + {0x15, 0x0E6, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x59},/* 1.495 */ + {0x14, 0x0DE, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x57},/* 1.443 */ + {0x13, 0x0D6, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x55},/* 1.391 */ + {0x13, 0x0CE, 0x8, 0x0, 0x7, 0x0, 0x0F, 0x54},/* 1.339 */ + {0x12, 0x0C4, 0x8, 0x0, 0x7, 0x0, 0x0F, 0x53},/* 1.274 */ + {0x11, 0x0BC, 0x8, 0x0, 0x6, 0x0, 0x0F, 0x50},/* 1.222 */ + {0x0F, 0x0AC, 0x8, 0x0, 0x6, 0x0, 0x0E, 0x4D},/* 1.118 */ + {0x0E, 0x138, 0x8, 0x1, 0x5, 0x0, 0x0D, 0x4A},/* 1.014 */ + {0x0C, 0x114, 0x8, 0x1, 0x4, 0x0, 0x0B, 0x46},/* 0.897 */ + {0x0B, 0x0F8, 0x8, 0x1, 0x3, 0x0, 0x0A, 0x43},/* 0.806 */ + {0x0A, 0x0DC, 0x8, 0x1, 0x3, 0x0, 0x09, 0x40},/* 0.715 */ + {0x08, 0x0C0, 0x8, 0x1, 0x2, 0x0, 0x07, 0x3C},/* 0.624 */ + {0x06, 0x128, 0xa, 0x1, 0x2, 0x0, 0x07, 0x37},/* 0.481 */ + {0x04, 0x0D0, 0xa, 0x1, 0x0, 0x0, 0x07, 0x32},/* 0.338 */ + {0x03, 0x110, 0xb, 0x1, 0x0, 0x0, 0x07, 0x2F},/* 0.221 */ + + {0x1C, 0x134, 0x8, 0x0, 0xF, 0x0, 0x0F, 0x5A},/* 2.002 (L) */ + {0x1B, 0x12C, 0x8, 0x0, 0xE, 0x0, 0x0F, 0x59},/* 1.95 */ + {0x1A, 0x122, 0x8, 0x0, 0xE, 0x0, 0x0F, 0x57},/* 1.885 */ + {0x1A, 0x118, 0x8, 0x0, 0xC, 0x0, 0x0F, 0x55},/* 1.82 */ + {0x19, 0x10E, 0x8, 0x0, 0xB, 0x0, 0x0F, 0x54},/* 1.755 */ + {0x18, 0x106, 0x8, 0x0, 0xB, 0x0, 0x0F, 0x53},/* 1.703 */ + {0x17, 0x0FA, 0x8, 0x0, 0x9, 0x0, 0x0F, 0x50},/* 1.625 */ + {0x15, 0x0E6, 0x8, 0x0, 0x8, 0x0, 0x0E, 0x4D},/* 1.495 */ + {0x13, 0x0D0, 0x8, 0x0, 0x7, 0x0, 0x0D, 0x4A},/* 1.352 */ + {0x11, 0x0BA, 0x8, 0x0, 0x6, 0x0, 0x0B, 0x46},/* 1.209 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x6, 0x0, 0x0A, 0x43},/* 1.092 */ + {0x0D, 0x128, 0x8, 0x1, 0x4, 0x0, 0x09, 0x40},/* 0.962 */ + {0x0B, 0x100, 0x8, 0x1, 0x3, 0x0, 0x07, 0x3C},/* 0.832 */ + {0x09, 0x0C8, 0x8, 0x1, 0x2, 0x0, 0x07, 0x37},/* 0.65 */ + {0x06, 0x120, 0xa, 0x1, 0x1, 0x0, 0x07, 0x32},/* 0.468 */ + {0x04, 0x0C8, 0xa, 0x1, 0x0, 0x0, 0x07, 0x2F},/* 0.325 */ + + {0x0E, 0x130, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x5A},/* 0.988 (CCI) */ + {0x0D, 0x12C, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x59},/* 0.975 */ + {0x0D, 0x120, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x57},/* 0.936 */ + {0x0D, 0x118, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x55},/* 0.91 */ + {0x0C, 0x110, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x54},/* 0.884 */ + {0x0C, 0x104, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x53},/* 0.845 */ + {0x0B, 0x0FC, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x50},/* 0.819 */ + {0x0A, 0x0E8, 0x8, 0x1, 0x0, 0x0, 0x0E, 0x4D},/* 0.754 */ + {0x09, 0x0D0, 0x8, 0x1, 0x0, 0x0, 0x0D, 0x4A},/* 0.676 */ + {0x08, 0x0BC, 0x8, 0x1, 0x0, 0x0, 0x0B, 0x46},/* 0.611 */ + {0x07, 0x148, 0xa, 0x1, 0x0, 0x0, 0x0A, 0x43},/* 0.533 */ + {0x06, 0x128, 0xa, 0x1, 0x0, 0x0, 0x09, 0x40},/* 0.481 */ + {0x05, 0x100, 0xa, 0x1, 0x0, 0x0, 0x07, 0x3C},/* 0.416 */ + {0x04, 0x0C8, 0xa, 0x1, 0x0, 0x0, 0x07, 0x37},/* 0.325 */ + {0x03, 0x120, 0xb, 0x1, 0x0, 0x0, 0x07, 0x32},/* 0.234 */ + {0x02, 0x0D0, 0xb, 0x1, 0x0, 0x0, 0x07, 0x2F},/* 0.169 */ + + {0x1F, 0x18E, 0x8, 0x0, 0xF, 0x33BD7, 0x0F, 0x5A},/* 2.587 (BIG) */ + {0x1F, 0x176, 0x8, 0x0, 0xF, 0x309EC, 0x0F, 0x58},/* 2.431 */ + {0x1F, 0x166, 0x8, 0x0, 0xF, 0x2E8A4, 0x0F, 0x56},/* 2.327 */ + {0x1F, 0x15C, 0x8, 0x0, 0xF, 0x2D3D7, 0x0F, 0x55},/* 2.262 */ + {0x1F, 0x156, 0x8, 0x0, 0xF, 0x2C75C, 0x0F, 0x54},/* 2.223 */ + {0x1E, 0x14C, 0x8, 0x0, 0xF, 0x2B28F, 0x0F, 0x53},/* 2.158 */ + {0x1D, 0x142, 0x8, 0x0, 0xF, 0x29DC3, 0x0F, 0x51},/* 2.093 */ + {0x1A, 0x122, 0x8, 0x0, 0xE, 0x25B33, 0x0F, 0x4E},/* 1.885 */ + {0x17, 0x102, 0x8, 0x0, 0xA, 0x218A4, 0x0D, 0x4A},/* 1.677 */ + {0x15, 0x0E6, 0x8, 0x0, 0x8, 0x1DE66, 0x0B, 0x46},/* 1.495 */ + {0x13, 0x0D4, 0x8, 0x0, 0x8, 0x1B8F6, 0x0B, 0x44},/* 1.378 */ + {0x10, 0x0AE, 0x8, 0x0, 0x6, 0x169EC, 0x09, 0x3F},/* 1.131 */ + {0x0E, 0x134, 0x8, 0x1, 0x5, 0x14052, 0x07, 0x3C},/* 1.001 */ + {0x0C, 0x104, 0x8, 0x1, 0x4, 0x10E66, 0x07, 0x3A},/* 0.845 */ + {0x09, 0x0D0, 0x8, 0x1, 0x3, 0xD852, 0x07, 0x37},/* 0.676 */ + {0x04, 0x09C, 0x1a, 0x1, 0x0, 0x6C29, 0x07, 0x32},/* 0.338 */ +}; + /* dcmdiv, DDS, clk_div, post_div, CF_index, iDVFS, Vsram, Vproc */ unsigned int mbTbl_7[][8] = { {0x13, 0x0D6, 0x8, 0x0, 0xA, 0x0, 0x0F, 0x5A},/* 1.391 (LL) */ @@ -344,7 +443,7 @@ unsigned int mbTbl_7[][8] = { {0x12, 0x0C6, 0x8, 0x0, 0xA, 0x0, 0x0F, 0x55},/* 1.287 */ {0x11, 0x0BC, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x53},/* 1.222 */ {0x0F, 0x0AC, 0x8, 0x0, 0x8, 0x0, 0x0F, 0x4F},/* 1.118 */ - {0x0F, 0x0A4, 0x8, 0x0, 0x7, 0x0, 0x0E, 0x4D},/* 1.066 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x8, 0x0, 0x0E, 0x4D},/* 1.092 */ {0x0D, 0x124, 0x8, 0x1, 0x6, 0x0, 0x0C, 0x48},/* 0.949 */ {0x0C, 0x114, 0x8, 0x1, 0x6, 0x0, 0x0B, 0x46},/* 0.897 */ {0x0B, 0x0F8, 0x8, 0x1, 0x5, 0x0, 0x0A, 0x43},/* 0.806 */ @@ -364,7 +463,7 @@ unsigned int mbTbl_7[][8] = { {0x14, 0x0DA, 0x8, 0x0, 0xA, 0x0, 0x0E, 0x4D},/* 1.417 */ {0x12, 0x0C4, 0x8, 0x0, 0x9, 0x0, 0x0C, 0x48},/* 1.274 */ {0x11, 0x0BA, 0x8, 0x0, 0x8, 0x0, 0x0B, 0x46},/* 1.209 */ - {0x0F, 0x0A6, 0x8, 0x0, 0x8, 0x0, 0x0A, 0x43},/* 1.079 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x8, 0x0, 0x0A, 0x43},/* 1.092 */ {0x0D, 0x124, 0x8, 0x1, 0x6, 0x0, 0x09, 0x40},/* 0.949 */ {0x0B, 0x100, 0x8, 0x1, 0x5, 0x0, 0x07, 0x3C},/* 0.832 */ {0x0A, 0x0E4, 0x8, 0x1, 0x4, 0x0, 0x07, 0x3A},/* 0.741 */ @@ -408,14 +507,110 @@ unsigned int mbTbl_7[][8] = { {0x04, 0x09C, 0x12, 0x1, 0x0, 0x6148, 0x07, 0x32},/* 0.304 */ }; +/* dcmdiv, DDS, clk_div, post_div, CF_index, iDVFS, Vsram, Vproc */ +unsigned int lbTbl_7[][8] = { + {0x13, 0x0D6, 0x8, 0x0, 0xD, 0x0, 0x0F, 0x5A},/* 1.391 (LL) */ + {0x13, 0x0CE, 0x8, 0x0, 0xC, 0x0, 0x0F, 0x58},/* 1.339 */ + {0x12, 0x0C6, 0x8, 0x0, 0xC, 0x0, 0x0F, 0x55},/* 1.287 */ + {0x11, 0x0BC, 0x8, 0x0, 0xA, 0x0, 0x0F, 0x53},/* 1.222 */ + {0x0F, 0x0AC, 0x8, 0x0, 0xA, 0x0, 0x0F, 0x4F},/* 1.118 */ + {0x0F, 0x0A8, 0x8, 0x0, 0xA, 0x0, 0x0E, 0x4D},/* 1.092 */ + {0x0D, 0x124, 0x8, 0x1, 0x8, 0x0, 0x0C, 0x48},/* 0.949 */ + {0x0C, 0x114, 0x8, 0x1, 0x7, 0x0, 0x0B, 0x46},/* 0.897 */ + {0x0B, 0x0F8, 0x8, 0x1, 0x6, 0x0, 0x0A, 0x43},/* 0.806 */ + {0x0A, 0x0DC, 0x8, 0x1, 0x5, 0x0, 0x09, 0x40},/* 0.715 */ + {0x08, 0x0C0, 0x8, 0x1, 0x3, 0x0, 0x07, 0x3C},/* 0.624 */ + {0x07, 0x0AC, 0x8, 0x1, 0x3, 0x0, 0x07, 0x3A},/* 0.559 */ + {0x06, 0x128, 0xa, 0x1, 0x2, 0x0, 0x07, 0x37},/* 0.481 */ + {0x05, 0x100, 0xa, 0x1, 0x1, 0x0, 0x07, 0x35},/* 0.416 */ + {0x04, 0x0D0, 0xa, 0x1, 0x0, 0x0, 0x07, 0x32},/* 0.338 */ + {0x03, 0x110, 0xb, 0x1, 0x0, 0x0, 0x07, 0x30},/* 0.221 */ + + {0x16, 0x0F6, 0x8, 0x0, 0xF, 0x0, 0x0F, 0x5A},/* 1.599 (L) */ + {0x15, 0x0EC, 0x8, 0x0, 0xE, 0x0, 0x0F, 0x58},/* 1.534 */ + {0x14, 0x0E0, 0x8, 0x0, 0xD, 0x0, 0x0F, 0x55},/* 1.456 */ + {0x13, 0x0D4, 0x8, 0x0, 0xC, 0x0, 0x0F, 0x53},/* 1.378 */ + {0x12, 0x0C4, 0x8, 0x0, 0xB, 0x0, 0x0F, 0x4F},/* 1.274 */ + {0x11, 0x0BA, 0x8, 0x0, 0xA, 0x0, 0x0E, 0x4D},/* 1.209 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x9, 0x0, 0x0C, 0x48},/* 1.092 */ + {0x0D, 0x124, 0x8, 0x1, 0x8, 0x0, 0x0B, 0x46},/* 0.949 */ + {0x0D, 0x120, 0x8, 0x1, 0x7, 0x0, 0x0A, 0x43},/* 0.936 */ + {0x0C, 0x104, 0x8, 0x1, 0x6, 0x0, 0x09, 0x40},/* 0.845 */ + {0x0A, 0x0E8, 0x8, 0x1, 0x5, 0x0, 0x07, 0x3C},/* 0.754 */ + {0x09, 0x0D4, 0x8, 0x1, 0x5, 0x0, 0x07, 0x3A},/* 0.689 */ + {0x08, 0x0BC, 0x8, 0x1, 0x3, 0x0, 0x07, 0x37},/* 0.611 */ + {0x07, 0x0A8, 0x8, 0x1, 0x2, 0x0, 0x07, 0x35},/* 0.546 */ + {0x06, 0x120, 0xa, 0x1, 0x1, 0x0, 0x07, 0x32},/* 0.468 */ + {0x04, 0x0C8, 0xa, 0x1, 0x0, 0x0, 0x07, 0x30},/* 0.325 */ + + {0x0B, 0x0F8, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x5A},/* 0.806 (CCI) */ + {0x0A, 0x0EC, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x58},/* 0.767 */ + {0x0A, 0x0E0, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x55},/* 0.728 */ + {0x09, 0x0D4, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x53},/* 0.689 */ + {0x09, 0x0C4, 0x8, 0x1, 0x0, 0x0, 0x0F, 0x4F},/* 0.637 */ + {0x08, 0x0BC, 0x8, 0x1, 0x0, 0x0, 0x0E, 0x4D},/* 0.611 */ + {0x07, 0x0A8, 0x8, 0x1, 0x0, 0x0, 0x0C, 0x48},/* 0.546 */ + {0x07, 0x0A0, 0x8, 0x1, 0x0, 0x0, 0x0B, 0x46},/* 0.520 */ + {0x06, 0x120, 0xa, 0x1, 0x0, 0x0, 0x0A, 0x43},/* 0.468 */ + {0x06, 0x108, 0xa, 0x1, 0x0, 0x0, 0x09, 0x40},/* 0.429 */ + {0x05, 0x0E8, 0xa, 0x1, 0x0, 0x0, 0x07, 0x3C},/* 0.377 */ + {0x04, 0x0D0, 0xa, 0x1, 0x0, 0x0, 0x07, 0x3A},/* 0.338 */ + {0x04, 0x0C0, 0xa, 0x1, 0x0, 0x0, 0x07, 0x37},/* 0.312 */ + {0x03, 0x0A8, 0xa, 0x1, 0x0, 0x0, 0x07, 0x35},/* 0.273 */ + {0x03, 0x120, 0xb, 0x1, 0x0, 0x0, 0x07, 0x32},/* 0.234 */ + {0x02, 0x0D0, 0xb, 0x1, 0x0, 0x0, 0x07, 0x30},/* 0.169 */ + + {0x19, 0x114, 0x8, 0x0, 0xF, 0x23E14, 0x0F, 0x5A},/* 1.794 (BIG) */ + {0x18, 0x10A, 0x8, 0x0, 0xF, 0x22948, 0x0F, 0x57},/* 1.729 */ + {0x18, 0x104, 0x8, 0x0, 0xF, 0x21CCD, 0x0F, 0x56},/* 1.690 */ + {0x17, 0x0FA, 0x8, 0x0, 0xF, 0x20800, 0x0F, 0x54},/* 1.625 */ + {0x16, 0x0F2, 0x8, 0x0, 0xF, 0x1F75C, 0x0F, 0x53},/* 1.573 */ + {0x15, 0x0E6, 0x8, 0x0, 0xE, 0x1DE66, 0x0F, 0x51},/* 1.495 */ + {0x13, 0x0CE, 0x8, 0x0, 0xC, 0x1AC7B, 0x0E, 0x4D},/* 1.339 */ + {0x12, 0x0C2, 0x8, 0x0, 0xB, 0x19385, 0x0D, 0x4B},/* 1.261 */ + {0x0F, 0x0A8, 0x8, 0x0, 0x9, 0x15D71, 0x0B, 0x46},/* 1.092 */ + {0x0D, 0x124, 0x8, 0x1, 0x8, 0x12FAE, 0x0B, 0x44},/* 0.949 */ + {0x0C, 0x114, 0x8, 0x1, 0x7, 0x11F0A, 0x09, 0x41},/* 0.897 */ + {0x0B, 0x0F4, 0x8, 0x1, 0x6, 0x0FDC3, 0x09, 0x3F},/* 0.793 */ + {0x0A, 0x0D8, 0x8, 0x1, 0x5, 0x0E0A4, 0x07, 0x3C},/* 0.702 */ + {0x08, 0x0B8, 0x8, 0x1, 0x3, 0x0BF5C, 0x07, 0x3A},/* 0.598 */ + {0x07, 0x09C, 0x8, 0x1, 0x2, 0x0A23D, 0x07, 0x37},/* 0.507 */ + {0x04, 0x09C, 0x12, 0x1, 0xF, 0x6148, 0x07, 0x32},/* 0.152 */ +}; + +#ifdef CONFIG_REGULATOR_RT5735 +/* RT5735 */ +unsigned int gpuFy_7_rt5735[16] = {0x54, 0x54, 0x4E, 0x4E, 0x46, 0x46, 0x40, 0x40, + 0x38, 0x38, 0x31, 0x31, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuSb_7_rt5735[16] = {0x58, 0x58, 0x4C, 0x4C, 0x46, 0x46, 0x3E, 0x3E, + 0x38, 0x38, 0x31, 0x31, 0x27, 0x27, 0x21, 0x21}; + +unsigned int gpuSbp_7_rt5735[16] = {0x58, 0x58, 0x50, 0x50, 0x42, 0x42, 0x3C, 0x3C, + 0x35, 0x35, 0x31, 0x31, 0x27, 0x27, 0x21, 0x21}; + +unsigned int gpuMb_7_rt5735[16] = {0x54, 0x54, 0x4C, 0x4C, 0x40, 0x40, 0x3C, 0x3C, + 0x31, 0x31, 0x2F, 0x2F, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuLb_7_rt5735[16] = {0x54, 0x54, 0x4C, 0x4C, 0x42, 0x42, 0x3C, 0x3C, + 0x33, 0x33, 0x2D, 0x2D, 0x27, 0x27, 0x21, 0x21}; +#endif + +/* FAN53555 */ unsigned int gpuFy_7[16] = {0x29, 0x29, 0x26, 0x26, 0x22, 0x22, 0x1F, 0x1F, 0x1B, 0x1B, 0x18, 0x18, 0x14, 0x14, 0x10, 0x10}; -unsigned int gpuSb_7[16] = {0x29, 0x29, 0x24, 0x24, 0x20, 0x20, 0x1D, 0x1D, +unsigned int gpuSb_7[16] = {0x2B, 0x2B, 0x25, 0x25, 0x22, 0x22, 0x1E, 0x1E, + 0x1B, 0x1B, 0x18, 0x18, 0x13, 0x13, 0x10, 0x10}; + +unsigned int gpuSbp_7[16] = {0x2B, 0x2B, 0x27, 0x27, 0x20, 0x20, 0x1D, 0x1D, 0x1A, 0x1A, 0x18, 0x18, 0x13, 0x13, 0x10, 0x10}; unsigned int gpuMb_7[16] = {0x29, 0x29, 0x25, 0x25, 0x1F, 0x1F, 0x1D, 0x1D, 0x18, 0x18, 0x17, 0x17, 0x14, 0x14, 0x10, 0x10}; + +unsigned int gpuLb_7[16] = {0x29, 0x29, 0x25, 0x25, 0x20, 0x20, 0x1D, 0x1D, + 0x19, 0x19, 0x16, 0x16, 0x13, 0x13, 0x10, 0x10}; /* These tables are for version 7 use end */ @@ -723,6 +918,28 @@ unsigned int mbTbl[][8] = { {0x04, 0x09C, 0x12, 0x1, 0x0, 0x6158, 0x07, 0x32},/* 0.304 */ }; +#ifdef CONFIG_REGULATOR_RT5735 +/* RT5735 */ +unsigned int gpuFy_6_rt5735[16] = {0x54, 0x54, 0x4E, 0x4E, 0x46, 0x46, 0x40, 0x40, + 0x38, 0x38, 0x31, 0x31, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuSb_6_rt5735[16] = {0x54, 0x54, 0x4A, 0x4A, 0x44, 0x44, 0x3E, 0x3E, + 0x38, 0x38, 0x31, 0x31, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuMb_6_rt5735[16] = {0x54, 0x54, 0x4C, 0x4C, 0x40, 0x40, 0x3C, 0x3C, + 0x31, 0x31, 0x2F, 0x2F, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuFy_5_rt5735[16] = {0x54, 0x54, 0x4C, 0x4C, 0x40, 0x40, 0x3C, 0x3C, + 0x31, 0x31, 0x2F, 0x2F, 0x29, 0x29, 0x21, 0x21}; + +unsigned int gpuSb_5_rt5735[16] = {0x54, 0x54, 0x4A, 0x4A, 0x42, 0x42, 0x3C, 0x3C, + 0x35, 0x35, 0x31, 0x31, 0x27, 0x27, 0x21, 0x21}; + +unsigned int gpuMb_5_rt5735[16] = {0x54, 0x54, 0x4E, 0x4E, 0x46, 0x46, 0x3E, 0x3E, + 0x35, 0x35, 0x2F, 0x2F, 0x29, 0x29, 0x21, 0x21}; +#endif + +/* FAN53555 */ unsigned int gpuFy_6[16] = {0x29, 0x29, 0x26, 0x26, 0x22, 0x22, 0x1F, 0x1F, 0x1B, 0x1B, 0x18, 0x18, 0x14, 0x14, 0x10, 0x10}; @@ -740,6 +957,7 @@ unsigned int gpuSb_5[16] = {0x29, 0x29, 0x24, 0x24, 0x20, 0x20, 0x1D, 0x1D, unsigned int gpuMb_5[16] = {0x29, 0x29, 0x26, 0x26, 0x21, 0x21, 0x1E, 0x1E, 0x1A, 0x1A, 0x17, 0x17, 0x14, 0x14, 0x10, 0x10}; + /* These tables are for less version 7 use end */ @@ -821,10 +1039,15 @@ static unsigned int cpu_speed; #include "mt_cpufreq.h" #include "mt_ptp.h" #include "mt_defptp.h" + #include <mach/mt_secure_api.h> #include "spm_v2/mt_spm_idle.h" #include "spm_v2/mt_spm.h" #include "../../../power/mt6797/da9214.h" #include "../../../power/mt6797/fan53555.h" + #include "mt_idvfs.h" +#ifdef CONFIG_REGULATOR_RT5735 + #include "../../../power/mt6797/mtk_gpuregulator_intf.h" +#endif #else #include "mach/mt_cpufreq.h" #include "mach/mt_ptp.h" @@ -929,6 +1152,10 @@ static void eem_restore_eem_volt(struct eem_det *det); #define MAX_ITURBO_OFFSET (2000) /* 20mV */ /* GPU */ +#ifdef CONFIG_REGULATOR_RT5735 + #define GPU_PMIC_BASE_RT5735 (60000) + #define GPU_PMIC_STEP_RT5735 (625) +#endif #define GPU_PMIC_BASE (60300) #define GPU_PMIC_STEP (1282) @@ -936,7 +1163,7 @@ static void eem_restore_eem_volt(struct eem_det *det); #define VMIN_VAL_BIG (80000) /* 82500 for MT6313; 80000 for DA9214 */ #define VMAX_SRAM (120000) #define VMIN_SRAM (100000) -#define VMAX_VAL_GPU (112900) +#define VMAX_VAL_GPU (115000) #define VMIN_VAL_GPU (80000) #define VMAX_VAL_LITTLE (120000) #define VMIN_VAL_LITTLE (78000) @@ -1117,6 +1344,9 @@ enum { #ifdef CONFIG_OF void __iomem *eem_base; +void __iomem *g_semaphore_base; +static unsigned long g_reg_sema0_m0; +static unsigned long g_reg_cspm_poweron_en; static u32 eem_irq_number; #endif @@ -1423,6 +1653,46 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, static struct notifier_block __refdata _mt_eem_cpu_notifier = { .notifier_call = _mt_eem_cpu_CB, }; + +static int eem_get_semaphore(void) +{ + int i; + + eem_debug("eem_get_semaphore+"); + + /* mt6797-dvfsp enable internal CG bit */ + eem_write(g_reg_cspm_poweron_en, 0x0b160001); + + + eem_debug("0x1001AXXX sema get %lx\n", g_reg_sema0_m0); + + for (i = 0; i < 200; i++) { + eem_write(g_reg_sema0_m0, 0x1); + if (eem_read(g_reg_sema0_m0) & 0x1) + return 0; + + udelay(10); + } + + eem_error("0x1001AXXX SEMA_USER GET TIMEOUT"); + BUG_ON(1); + + return -EBUSY; +} + +/* HW semaphore0 M0 release. + * For ATF, SPM and kernel protecting 0x1001AXXX access + */ +static void eem_release_semaphore(void) +{ + eem_debug("0x1001AXXX sema release\n"); + + if (eem_read(g_reg_sema0_m0) & 0x1) { + eem_write(g_reg_sema0_m0, 0x1); + BUG_ON(eem_read(g_reg_sema0_m0) & 0x1); /* semaphore release failed */ + } +} + #endif /** @@ -2466,6 +2736,28 @@ static void get_freq_table_cpu(struct eem_det *det) else recordTbl = &mbTbl_7[0][0]; #endif + } else if (binLevel == 0x0F) { + det->freq_tbl[i] = + PERCENT((det_to_id(det) == EEM_DET_BIG) ? (bigFreq_LB_7[i]) : + (det_to_id(det) == EEM_DET_L) ? (L_Freq_LB_7[i]) : + (det_to_id(det) == EEM_DET_2L) ? (LL_Freq_LB_7[i]) : + (cciFreq_LB_7[i]) + , + det->max_freq_khz); + #if defined(__MTK_SLT_) + recordTbl = &lbTbl_7[0][0]; + #endif + } else if (binLevel == 0x04) { + det->freq_tbl[i] = + PERCENT((det_to_id(det) == EEM_DET_BIG) ? (bigFreq_SBP_7[i]) : + (det_to_id(det) == EEM_DET_L) ? (L_Freq_SB_7[i]) : + (det_to_id(det) == EEM_DET_2L) ? (LL_Freq_SB_7[i]) : + (cciFreq_SB_7[i]) + , + det->max_freq_khz); + #if defined(__MTK_SLT_) + recordTbl = &sbpTbl_7[0][0]; + #endif } else { det->freq_tbl[i] = PERCENT((det_to_id(det) == EEM_DET_BIG) ? ((ateVer < 7) ? bigFreq_FY[i] : bigFreq_FY_7[i]) : @@ -2559,47 +2851,82 @@ static void get_freq_table_gpu(struct eem_det *det) ((ateVer < 6) ? gpuFreq_FY_5[i] : gpuFreq_FY_6[i]) : gpuFreq_FY_7[i]), det->max_freq_khz); - #if defined(__MTK_SLT_) + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) gpuTbl = (ateVer < 7) ? - ((ateVer < 6) ? &gpuFy_5[0] : &gpuFy_6[0]) : - &gpuFy_7[0]; + ((ateVer < 6) ? &gpuFy_5_rt5735[0] : &gpuFy_6_rt5735[0]) : + &gpuFy_7_rt5735[0]; #endif + if (is_fan53555_exist()) + gpuTbl = (ateVer < 7) ? + ((ateVer < 6) ? &gpuFy_5[0] : &gpuFy_6[0]) : + &gpuFy_7[0]; } else if ((binLevel == 1) || (binLevel == 6)) { det->freq_tbl[i] = PERCENT(((ateVer < 7) ? ((ateVer < 6) ? gpuFreq_SB_5[i] : gpuFreq_SB_6[i]) : gpuFreq_SB_7[i]), det->max_freq_khz); - #if defined(__MTK_SLT_) + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) gpuTbl = (ateVer < 7) ? - ((ateVer < 6) ? &gpuSb_5[0] : &gpuSb_6[0]) : - &gpuSb_7[0]; + ((ateVer < 6) ? &gpuSb_5_rt5735[0] : &gpuSb_6_rt5735[0]) : + &gpuSb_7_rt5735[0]; #endif + if (is_fan53555_exist()) + gpuTbl = (ateVer < 7) ? + ((ateVer < 6) ? &gpuSb_5[0] : &gpuSb_6[0]) : + &gpuSb_7[0]; } else if ((binLevel == 2) || (binLevel == 7)) { det->freq_tbl[i] = PERCENT(((ateVer < 7) ? ((ateVer < 6) ? gpuFreq_MB_5[i] : gpuFreq_MB_6[i]) : gpuFreq_MB_7[i]), det->max_freq_khz); - #if defined(__MTK_SLT_) + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) gpuTbl = (ateVer < 7) ? - ((ateVer < 6) ? &gpuMb_5[0] : &gpuMb_6[0]) : - &gpuMb_7[0]; + ((ateVer < 6) ? &gpuMb_5_rt5735[0] : &gpuMb_6_rt5735[0]) : + &gpuMb_7_rt5735[0]; #endif + if (is_fan53555_exist()) + gpuTbl = (ateVer < 7) ? + ((ateVer < 6) ? &gpuMb_5[0] : &gpuMb_6[0]) : + &gpuMb_7[0]; + } else if (binLevel == 0x0F) { + det->freq_tbl[i] = PERCENT((gpuFreq_LB_7[i]), det->max_freq_khz); + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) + gpuTbl = &gpuLb_7_rt5735[0]; + #endif + if (is_fan53555_exist()) + gpuTbl = &gpuLb_7[0]; + } else if (binLevel == 0x04) { + det->freq_tbl[i] = PERCENT((gpuFreq_SBP_7[i]), det->max_freq_khz); + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) + gpuTbl = &gpuSbp_7_rt5735[0]; + #endif + if (is_fan53555_exist()) + gpuTbl = &gpuSbp_7[0]; } else { det->freq_tbl[i] = PERCENT(((ateVer < 7) ? ((ateVer < 6) ? gpuFreq_FY_5[i] : gpuFreq_FY_6[i]) : gpuFreq_FY_7[i]), det->max_freq_khz); - #if defined(__MTK_SLT_) + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) gpuTbl = (ateVer < 7) ? - ((ateVer < 6) ? &gpuFy_5[0] : &gpuFy_6[0]) : - &gpuFy_7[0]; + ((ateVer < 6) ? &gpuFy_5_rt5735[0] : &gpuFy_6_rt5735[0]) : + &gpuFy_7_rt5735[0]; #endif + if (is_fan53555_exist()) + gpuTbl = (ateVer < 7) ? + ((ateVer < 6) ? &gpuFy_5[0] : &gpuFy_6[0]) : + &gpuFy_7[0]; } if (0 == det->freq_tbl[i]) break; } - FUNC_EXIT(FUNC_LV_HELP); det->num_freq_tbl = i; @@ -2884,14 +3211,15 @@ static int eem_volt_thread_handler(void *data) } #endif det->ops->set_volt(det); - eem_error("B=%d,T=%d,DC=%x,V30=%x,F30=%x,sts=%x,250=%x\n", - det->ctrl_id, - det->ops->get_temp(det), - det->dcvalues[EEM_PHASE_INIT01], - det->vop30[EEM_PHASE_MON], - det->freqpct30[EEM_PHASE_MON], - det->ops->get_status(det), - det->t250); + if (eem_log_en) + eem_error("B=%d,T=%d,DC=%x,V30=%x,F30=%x,sts=%x,250=%x\n", + det->ctrl_id, + det->ops->get_temp(det), + det->dcvalues[EEM_PHASE_INIT01], + det->vop30[EEM_PHASE_MON], + det->freqpct30[EEM_PHASE_MON], + det->ops->get_status(det), + det->t250); #if (defined(CONFIG_EEM_AEE_RR_REC) && !defined(EARLY_PORTING)) if (temp >= EEM_CPU_BIG_IS_SET_VOLT) @@ -3042,6 +3370,13 @@ static void eem_init_det(struct eem_det *det, struct eem_devinfo *devinfo) break; case EEM_DET_GPU: + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) { + det->VBOOT = 100000; + det->pmic_base = GPU_PMIC_BASE_RT5735; + det->pmic_step = GPU_PMIC_STEP_RT5735; + } + #endif det->MDES = devinfo->GPU_MDES; det->BDES = devinfo->GPU_BDES; det->DCMDET = devinfo->GPU_DCMDET; @@ -3221,11 +3556,13 @@ static void eem_set_eem_volt(struct eem_det *det) break; case EEM_CTRL_L: + /* if (1 == ITurboRunSet) { ITurbo_offset[i] = det->ops->volt_2_eem(det, MAX_ITURBO_OFFSET + det->eem_v_base) * (det->volt_tbl[i] - det->volt_tbl[NR_FREQ-1]) / (det->volt_tbl[0] - det->volt_tbl[NR_FREQ-1]); } else + */ ITurbo_offset[i] = 0; det->volt_tbl_pmic[i] = @@ -3640,12 +3977,10 @@ static inline void handle_init02_isr(struct eem_det *det) #endif /* eem_error("init02_[%s].volt_tbl[%d] = 0x%X (%d)\n", - det->name, i, det->volt_tbl[i], det->ops->pmic_2_volt(det, det->volt_tbl[i])); - - if (NR_FREQ > 8) { - eem_error("init02_[%s].volt_tbl[%d] = 0x%X (%d)\n", - det->name, i+1, det->volt_tbl[i+1], det->ops->pmic_2_volt(det, det->volt_tbl[i+1])); - } + det->name, + i, + det->volt_tbl[i], + det->ops->pmic_2_volt(det, det->ops->eem_2_pmic(det, det->volt_tbl[i]))); */ } #if defined(__MTK_SLT_) @@ -4154,6 +4489,7 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, unsigned long flags; unsigned int cpu = (unsigned long)hcpu; unsigned int online_cpus = num_online_cpus(); + unsigned int swReq; struct device *dev; struct eem_det *det; enum mt_eem_cpu_id cluster_id; @@ -4175,6 +4511,8 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, tTbl = tSbTbl; else if ((cpuBinLevel == 2) || (cpuBinLevel == 7)) tTbl = tMbTbl; + else if (cpuBinLevel == 0x0F) + tTbl = tLbTbl; else tTbl = tFyTbl; @@ -4220,7 +4558,6 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, ((tTbl[3] & 0x7) << 4) | (tTbl[4] & 0xF); mb(); /* SRAM writing */ - eem_set_eem_volt(det); mt_ptp_unlock(&flags); } else { if (eem_log_en) @@ -4246,7 +4583,6 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, ((*(recordTbl + (48 * 8) + 3) & 0x7) << 4) | (*(recordTbl + (48 * 8) + 4) & 0xF); mb(); /* SRAM writing */ - eem_set_eem_volt(det); mt_ptp_unlock(&flags); } else { if (eem_log_en) @@ -4269,7 +4605,6 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, ((tTbl[3] & 0x7) << 4) | (tTbl[4] & 0xF); mb(); /* SRAM writing */ - eem_set_eem_volt(det); mt_ptp_unlock(&flags); } else if ((1 == ITurboRun) && (ITURBO_CPU_NUM == big_cpus) && (MT_EEM_CPU_B == cluster_id)) { if (eem_log_en) @@ -4286,8 +4621,34 @@ static int __cpuinit _mt_eem_cpu_CB(struct notifier_block *nfb, ((*(recordTbl + (48 * 8) + 3) & 0x7) << 4) | (*(recordTbl + (48 * 8) + 4) & 0xF); mb(); /* SRAM writing */ - eem_set_eem_volt(det); mt_ptp_unlock(&flags); + + /* Set semaphore and adjust back frequence to original */ + eem_error("The freq percentage is : (%d)\n", + (*(recordTbl + (48 * 8) + 5) & 0x3FFFF) * 100 / 2048); + + swReq = 0; + while ((mt_secure_call(0x8200035F, 0x10222498, 0, 0) >> 1) > + (*(recordTbl + (48 * 8) + 5) & 0x3FFFF)) { + udelay(120); + if (eem_log_en) + eem_error("SWREQ = %x", + mt_secure_call(0x8200035F, 0x10222498, 0, 0) >> 1); + + if (swReq >= 100) { + eem_get_semaphore(); + BigIDVFSFreq((*(recordTbl + (48 * 8) + 5) & 0x3FFFF) * 100 / 2048); + eem_release_semaphore(); + break; + } + swReq++; + } + udelay(120); + + if (((mt_secure_call(0x8200035F, 0x10222498, 0, 0) >> 1) > + (*(recordTbl + (48 * 8) + 5) & 0x3FFFF)) && (swReq >= 100)) + BUG_ON(swReq); + } else { if (eem_log_en) eem_error("Turbo(%d)ed !! UP (%d), BIG_cc(%d)\n", @@ -4387,7 +4748,12 @@ void eem_init01(void) da9214_config_interface(0x0, 0x1, 0xF, 0); /* select to page 2,3 */ da9214_config_interface(0xD2, 0x1, 0x3, 0); /* Disable Buck B PWM Mode for BIG */ /* set non_PWM mode for FAN5355 */ - fan53555_config_interface(0x0, 0x0, 0x1, 6); /* Disable PWM mode for GPU */ + if (is_fan53555_exist()) + fan53555_config_interface(0x0, 0x0, 0x1, 6); /* Disable PWM mode for GPU */ + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) + rt_enable_force_pwm(0, 0); /* Disable PWM mode for GPU */ + #endif #ifdef __KERNEL__ #ifndef EARLY_PORTING @@ -4398,10 +4764,10 @@ void eem_init01(void) #endif mt_gpufreq_enable_by_ptpod(); /* enable gpu DVFS */ mt_ppm_ptpod_policy_deactivate(); -#ifndef CONFIG_BIG_OFF + #ifndef CONFIG_BIG_OFF if (cpu_online(8)) cpu_down(8); -#endif + #endif /* enable frequency hopping (main PLL) */ /* mt_fh_popod_restore(); */ #endif @@ -4656,11 +5022,11 @@ static int eem_probe(struct platform_device *pdev) /* disable frequency hopping (main PLL) */ /* mt_fh_popod_save(); */ -#ifndef CONFIG_BIG_OFF + #ifndef CONFIG_BIG_OFF set_cpu_present(8, true); /* enable big cluster */ if (!cpu_online(8)) cpu_up(8); -#endif + #endif /* disable DVFS and set vproc = 1v (LITTLE = 689 MHz)(BIG = 1196 MHz) */ mt_ppm_ptpod_policy_activate(); mt_gpufreq_disable_by_ptpod(); @@ -4693,7 +5059,12 @@ static int eem_probe(struct platform_device *pdev) da9214_config_interface(0x0, 0x1, 0xF, 0); /* select to page 2,3 */ da9214_config_interface(0xD2, 0x2, 0x3, 0); /* Enable Buck B PWM Mode for BIG */ /* set PWM mode for FAN5355 */ - fan53555_config_interface(0x00, 0x01, 0x01, 6); /* Set PWM mode for GPU */ + if (is_fan53555_exist()) + fan53555_config_interface(0x00, 0x01, 0x01, 6); /* Set PWM mode for GPU */ + #ifdef CONFIG_REGULATOR_RT5735 + if (rt_is_hw_exist()) + rt_enable_force_pwm(0, 1); /* Set PWM mode for GPU */ + #endif /* for slow idle */ ptp_data[0] = 0xffffffff; @@ -5147,6 +5518,8 @@ static ssize_t eem_cur_volt_proc_write(struct file *file, /* if (!kstrtoint(buf, 10, &voltValue)) { */ if (2 == sscanf(buf, "%u %u", &voltValue, &index)) { + if ((index < 0) || (index > 15)) + index = 0; if ((EEM_CTRL_GPU != det->ctrl_id) && (EEM_CTRL_SOC != det->ctrl_id)) { ret = 0; det->recordRef[NR_FREQ * 2] = 0x00000000; @@ -5884,41 +6257,39 @@ static int __init eem_conf(void) if ((binLevel == 0) || (binLevel == 3)) { if (ate_Ver < 7) { - gpuTbl = (ate_Ver < 6) ? &gpuFy_5[0] : &gpuFy_6[0]; recordTbl = &fyTbl[0][0]; eem_error("@The table ----->(fyTbl)\n"); } else { - gpuTbl = &gpuFy_7[0]; recordTbl = &fyTbl_7[0][0]; eem_error("@The table ----->(fyTbl_7)\n"); } } else if ((binLevel == 1) || (binLevel == 6)) { if (ate_Ver < 7) { - gpuTbl = (ate_Ver < 6) ? &gpuSb_5[0] : &gpuSb_6[0]; recordTbl = &sbTbl[0][0]; eem_error("@The table ----->(sbTbl)\n"); } else { - gpuTbl = &gpuSb_7[0]; recordTbl = &sbTbl_7[0][0]; eem_error("@The table ----->(sbTbl_7)\n"); } } else if ((binLevel == 2) || (binLevel == 7)) { if (ate_Ver < 7) { - gpuTbl = (ate_Ver < 6) ? &gpuMb_5[0] : &gpuMb_6[0]; recordTbl = &mbTbl[0][0]; eem_error("@The table ----->(mbTbl)\n"); } else { - gpuTbl = &gpuMb_7[0]; recordTbl = &mbTbl_7[0][0]; eem_error("@The table ----->(mbTbl_7)\n"); } + } else if (binLevel == 0x0F) { + recordTbl = &lbTbl_7[0][0]; + eem_error("@The table ----->(lbTbl_7)\n"); + } else if (binLevel == 0x04) { + recordTbl = &sbpTbl_7[0][0]; + eem_error("@The table ----->(sbpTbl_7)\n"); } else { if (ate_Ver < 7) { - gpuTbl = (ate_Ver < 6) ? &gpuFy_5[0] : &gpuFy_6[0]; recordTbl = &fyTbl[0][0]; eem_error("@The table ----->(unknown fyTbl)\n"); } else { - gpuTbl = &gpuFy_7[0]; recordTbl = &fyTbl_7[0][0]; eem_error("@The table ----->(fyTbl_7)\n"); } @@ -6087,6 +6458,16 @@ int __init eem_init(void) return 0; } eem_debug("[EEM] new_eem_val=%d, ctrl_EEM_Enable=%d\n", new_eem_val, ctrl_EEM_Enable); + + /* DVFSP HW semaphore init. */ + { + g_semaphore_base = ioremap_nocache(0x11015000, 0x1000); + g_reg_sema0_m0 = (unsigned long)g_semaphore_base + (0x410); + g_reg_cspm_poweron_en = (unsigned long)g_semaphore_base; + eem_write(g_reg_cspm_poweron_en, 0x0b160001); /* mt6797-dvfsp enable internal CG bit */ + eem_error("g_reg_sema0_m0:0x%lx\n", (unsigned long)g_reg_sema0_m0); + eem_error("g_reg_cspm_poweron_en:0x%lx\n", (unsigned long)g_reg_cspm_poweron_en); + } #endif get_devinfo(&eem_devinfo); @@ -6113,7 +6494,7 @@ int __init eem_init(void) } /* Read E-Fuse to control ITurbo mode */ - if ((ateVer > 7) && (eem_devinfo.BIG_TURBO)) + if ((ateVer >= 7) && (eem_devinfo.BIG_TURBO) && (4 != GET_BITS_VAL(3:0, get_devinfo_with_index(22)))) ctrl_ITurbo = 1; #ifdef __KERNEL__ diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_core.c b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_core.c index 202a04026ed1..68460f2c98bb 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_core.c +++ b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_core.c @@ -30,6 +30,7 @@ /* local includes */ #include "mt_hotplug_strategy_internal.h" #include "mt_hotplug_strategy.h" +#include <trace/events/sched.h> /* forward references */ @@ -108,7 +109,20 @@ static void hps_get_sysinfo(void) int i, j, idx; char *str1_ptr = str1; char *str2_ptr = str2; - + int scaled_tlp, avg_tlp; + /* AHT: Average heavy task */ + int lastpoll_htask1 = 0, lastpoll_htask2 = 0; + int avg_htask = 0, avg_htask_scal = 0; + int max; + int heavy_task_threshold = get_heavy_task_threshold(); + int avg_heavy_task_threshold = get_avg_heavy_task_threshold(); + int lastpoll_htask_idx1_1 = 0; + int lastpoll_htask_idx1_2 = 0; + int lastpoll_htask_idx2_1 = 0; + int lastpoll_htask_idx2_2 = 0; + int avg_htask_scal_idx1 = 0; + int avg_htask_scal_idx2 = 0; + int max_idx1 = 0; /* * calculate cpu loading */ @@ -134,15 +148,64 @@ static void hps_get_sysinfo(void) /*Get heavy task information */ /*hps_ctxt.cur_nr_heavy_task = hps_cpu_get_nr_heavy_task(); */ for (idx = 0; idx < hps_sys.cluster_num; idx++) { - if (hps_ctxt.heavy_task_enabled) - hps_sys.cluster_info[idx].hvyTsk_value = sched_get_nr_heavy_task2(idx); - else + if (hps_ctxt.heavy_task_enabled) { +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (idx == 0) { + /* in cluster LL, heavy task by last_poll */ + hps_sys.cluster_info[idx].hvyTsk_value = + sched_get_nr_heavy_task_by_threshold(idx, heavy_task_threshold); + } else if (idx == 1) { + /* in cluster L, heavy task by max of average(w/o remainder) and last_poll */ + lastpoll_htask1 = sched_get_nr_heavy_task_by_threshold(idx, heavy_task_threshold); + lastpoll_htask2 = sched_get_nr_heavy_running_avg(idx, &avg_htask_scal); + lastpoll_htask_idx1_1 = lastpoll_htask1; + lastpoll_htask_idx1_2 = lastpoll_htask2; + avg_htask_scal_idx1 = avg_htask_scal; + + avg_htask = ((avg_htask_scal%100) + >= avg_heavy_task_threshold)?(avg_htask_scal/100+1):(avg_htask_scal/100); + + max_idx1 = max = max(max(lastpoll_htask1, lastpoll_htask2), avg_htask); + hps_sys.cluster_info[idx].hvyTsk_value = max; + + trace_sched_avg_heavy_task(lastpoll_htask1, lastpoll_htask2, avg_htask_scal, idx, max); + } else if (idx == 2) { + /* in cluster B, heavy task by max of average(with L's remainder) and last_poll */ + lastpoll_htask1 = sched_get_nr_heavy_task_by_threshold(idx, heavy_task_threshold); + lastpoll_htask2 = sched_get_nr_heavy_running_avg(idx, &avg_htask_scal); + + lastpoll_htask_idx2_1 = lastpoll_htask1 + lastpoll_htask_idx1_1; + lastpoll_htask_idx2_2 = lastpoll_htask2 + lastpoll_htask_idx1_2; + avg_htask_scal_idx2 = avg_htask_scal+avg_htask_scal_idx1; + + avg_htask = ((avg_htask_scal_idx2%100) >= avg_heavy_task_threshold)?( + avg_htask_scal_idx2/100+1):(avg_htask_scal_idx2/100); + + max = max(max(lastpoll_htask_idx2_1, lastpoll_htask_idx2_2), avg_htask); + hps_sys.cluster_info[idx].hvyTsk_value = (max - max_idx1); + + trace_sched_avg_heavy_task(lastpoll_htask1, lastpoll_htask2, avg_htask_scal, + idx, + (max-max_idx1)); + } else + BUG_ON(1); +#else + hps_sys.cluster_info[idx].hvyTsk_value = 0; +#endif + } else hps_sys.cluster_info[idx].hvyTsk_value = 0; } - /*Get sys TLP information */ - hps_cpu_get_tlp(&hps_ctxt.cur_tlp, &hps_ctxt.cur_iowait); + scaled_tlp = hps_cpu_get_tlp(&avg_tlp, &hps_ctxt.cur_iowait); + /* + * scaled_tlp: tasks number of the last pill, which X 100. + * avg_tlp: average tasks number during the detection period. + * To pick max of scaled_tlp and avg_tlp. + */ + hps_ctxt.cur_tlp = max_t(int, scaled_tlp, (int)avg_tlp); + mt_sched_printf(sched_log, "[heavy_task] :%s, scaled_tlp:%d, avg_tlp:%d, max:%d", + __func__, scaled_tlp, (int)avg_tlp, (int)hps_ctxt.cur_tlp); #if 0 ppm_lock(&ppm_main_info.lock); ppm_hps_algo_data.ppm_cur_loads = hps_ctxt.cur_loads; diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_cpu.c b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_cpu.c index c407958ab514..175dfe440bd2 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_cpu.c +++ b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_cpu.c @@ -142,13 +142,18 @@ unsigned int hps_cpu_get_nr_heavy_task(void) #endif } -void hps_cpu_get_tlp(unsigned int *avg, unsigned int *iowait_avg) +int hps_cpu_get_tlp(unsigned int *avg, unsigned int *iowait_avg) { + int scaled_tlp = 0; /* The scaled tasks number of the last poll */ #ifdef CONFIG_MTK_SCHED_RQAVG_KS - sched_get_nr_running_avg((int *)avg, (int *)iowait_avg); + scaled_tlp = sched_get_nr_running_avg((int *)avg, (int *)iowait_avg); + + return scaled_tlp; #else *avg = 0; *iowait_avg = 0; + + return scaled_tlp; #endif } diff --git a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_internal.h b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_internal.h index 153331d60331..8cce0b3e13bf 100644..100755 --- a/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_internal.h +++ b/drivers/misc/mediatek/base/power/mt6797/mt_hotplug_strategy_internal.h @@ -321,7 +321,7 @@ DECLARE_PER_CPU(hps_cpu_ctxt_t, hps_percpu_ctxt); extern struct cpumask cpu_domain_big_mask; /* definition in kernel-3.10/arch/arm/kernel/topology.c */ extern struct cpumask cpu_domain_little_mask; /* definition in kernel-3.10/arch/arm/kernel/topology.c */ -extern void sched_get_nr_running_avg(int *avg, int *iowait_avg); +extern int sched_get_nr_running_avg(int *avg, int *iowait_avg); /* definition in mediatek/kernel/kernel/sched/rq_stats.c */ /*=============================================================*/ @@ -387,14 +387,20 @@ extern int hps_cpu_is_cpu_big(int cpu); extern int hps_cpu_is_cpu_little(int cpu); extern unsigned int hps_cpu_get_percpu_load(int cpu); extern unsigned int hps_cpu_get_nr_heavy_task(void); -extern void hps_cpu_get_tlp(unsigned int *avg, unsigned int *iowait_avg); +extern int hps_cpu_get_tlp(unsigned int *avg, unsigned int *iowait_avg); +#ifdef CONFIG_MTK_SCHED_RQAVG_US extern unsigned int sched_get_nr_heavy_task2(int cluster_id); +#endif +extern int get_avg_heavy_task_threshold(void); +extern int get_heavy_task_threshold(void); +extern unsigned int sched_get_nr_heavy_task_by_threshold(int cluster_id, unsigned int threshold); +extern int sched_get_nr_heavy_running_avg(int cid, int *avg); /*=============================================================*/ /* End */ /*=============================================================*/ extern struct cpumask cpu_domain_big_mask; extern struct cpumask cpu_domain_little_mask; -extern void sched_get_nr_running_avg(int *avg, int *iowait_avg); +extern int sched_get_nr_running_avg(int *avg, int *iowait_avg); extern unsigned int sched_get_percpu_load(int cpu, bool reset, bool use_maxfreq); extern unsigned int sched_get_nr_heavy_task(void); diff --git a/drivers/misc/mediatek/base/power/ppm_v1/inc/mt_ppm_internal.h b/drivers/misc/mediatek/base/power/ppm_v1/inc/mt_ppm_internal.h index dc533c092e4f..b6427220ead3 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/inc/mt_ppm_internal.h +++ b/drivers/misc/mediatek/base/power/ppm_v1/inc/mt_ppm_internal.h @@ -210,6 +210,7 @@ struct ppm_policy_data { /* status */ bool is_enabled; bool is_activated; + bool is_limit_updated; /* lock */ struct mutex lock; /* list link */ @@ -352,6 +353,16 @@ extern struct proc_dir_entry *profile_dir; extern unsigned int ppm_func_lv_mask; extern unsigned int ppm_debug; extern met_set_ppm_state_funcMET g_pSet_PPM_State; +#ifdef PPM_USE_EFFICIENCY_TABLE +extern int *freq_idx_mapping_tbl; +extern int *freq_idx_mapping_tbl_r; +extern int *freq_idx_mapping_tbl_big; +extern int *freq_idx_mapping_tbl_big_r; +extern int *efficiency_B[3]; +extern int *efficiency_LxLL[5][5]; +extern int *delta_power_B[3]; +extern int *delta_power_LxLL[5][5]; +#endif /*==============================================================*/ /* APIs */ @@ -378,7 +389,7 @@ extern struct ppm_power_tbl_data ppm_get_power_table(void); #ifdef PPM_THERMAL_ENHANCEMENT extern struct ppm_power_tbl_data ppm_get_tlp3_power_table(void); #endif -extern void ppm_main_pwr_tbl_calibration(void); +extern void ppm_pwr_tbl_calibration(void); #else extern const struct ppm_power_tbl_data ppm_get_power_table(void); #ifdef PPM_THERMAL_ENHANCEMENT @@ -402,6 +413,9 @@ extern int ppm_get_table_idx_by_pwr(enum ppm_power_state state, unsigned int pwr extern int ppm_get_tlp3_table_idx_by_pwr(enum ppm_power_state state, unsigned int pwr_idx); extern bool ppm_is_need_to_check_tlp3_table(enum ppm_power_state state, unsigned int pwr_idx); #endif +#ifdef PPM_USE_EFFICIENCY_TABLE +extern void ppm_init_efficiency_table(void); +#endif /* main */ extern void ppm_main_update_req_by_pwr(enum ppm_power_state new_state, struct ppm_policy_req *req); diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_efficiency_table.h b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_efficiency_table.h new file mode 100755 index 000000000000..c625892e168c --- /dev/null +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_efficiency_table.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2015 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +static int efficiency_B_FY[3][8] = { + {0, 0, 0, 0, 0, 0, 0}, + {48, 64, 75, 90, 105, 149, 169, 1150}, + {54, 72, 84, 102, 118, 167, 189, 1700} +}; + +static int efficiency_LxLL_FY[5][5][8] = { + { + {0, 0, 0, 0, 0, 0, 0}, + {88, 111, 136, 170, 183, 244, 270, 1930}, + {111, 139, 171, 212, 230, 304, 339, 3840}, + {121, 152, 187, 232, 252, 331, 371, 3840}, + {127, 159, 196, 243, 264, 347, 389, 3840} + }, + { + {70, 89, 104, 136, 157, 182, 212, 1760}, + {76, 97, 116, 148, 166, 205, 233, 1760}, + {89, 113, 136, 172, 191, 241, 273, 1760}, + {98, 124, 150, 189, 209, 267, 301, 1760}, + {105, 132, 160, 201, 222, 285, 321, 1760} + }, + { + {83, 105, 123, 161, 187, 216, 252, 2850}, + {84, 107, 126, 163, 186, 223, 257, 2850}, + {93, 117, 140, 179, 201, 248, 283, 2850}, + {99, 125, 150, 191, 214, 266, 303, 2850}, + {104, 131, 159, 201, 223, 281, 319, 2850} + }, + { + {89, 112, 131, 172, 199, 231, 269, 2850}, + {89, 112, 132, 171, 196, 233, 269, 2850}, + {95, 120, 142, 183, 207, 251, 288, 2850}, + {100, 126, 151, 192, 217, 266, 304, 2850}, + {104, 131, 157, 200, 224, 278, 317, 2850} + }, + { + {92, 116, 136, 178, 206, 238, 278, 2850}, + {91, 115, 136, 176, 202, 239, 277, 2850}, + {96, 121, 144, 185, 211, 254, 292, 2850}, + {100, 126, 151, 193, 219, 266, 305, 2850}, + {104, 131, 156, 200, 225, 277, 316, 2850} + } + + +}; + +static int delta_power_B_FY[3][8] = { + {0, 0, 0, 0, 0, 0, 0}, + {323, 386, 301, 216, 186, 172, 79, 348}, + {572, 686, 535, 384, 331, 308, 142, 236} +}; + +static int delta_power_LxLL_FY[5][5][8] = { + { + {0, 0, 0, 0, 0, 0, 0}, + {83, 61, 53, 46, 21, 25, 23, 75}, + {131, 97, 85, 74, 34, 40, 36, 38}, + {180, 133, 117, 101, 47, 56, 50, 38}, + {229, 169, 149, 129, 59, 71, 63, 38} + }, + { + {144, 107, 92, 82, 39, 43, 40, 120}, + {227, 168, 145, 128, 60, 68, 62, 120}, + {275, 204, 177, 156, 73, 83, 76, 120}, + {324, 240, 209, 183, 86, 99, 89, 120}, + {373, 276, 240, 211, 98, 114, 103, 120} + }, + { + {242, 180, 155, 139, 66, 72, 67, 75}, + {325, 241, 208, 185, 87, 98, 89, 75}, + {374, 277, 240, 212, 100, 113, 103, 75}, + {422, 313, 271, 240, 113, 128, 116, 75}, + {471, 349, 303, 268, 125, 143, 130, 75} + }, + { + {340, 254, 217, 195, 93, 102, 94, 75}, + {423, 314, 271, 241, 114, 127, 116, 75}, + {472, 350, 302, 269, 127, 142, 130, 75}, + {520, 387, 334, 297, 139, 157, 143, 75}, + {569, 423, 366, 324, 152, 173, 157, 75} + }, + { + {439, 327, 280, 252, 120, 131, 121, 75}, + {521, 388, 333, 298, 141, 157, 143, 75}, + {570, 424, 365, 326, 154, 172, 157, 75}, + {619, 460, 397, 353, 166, 187, 170, 75}, + {667, 496, 429, 381, 179, 202, 184, 75} + } + +}; + +static int freq_idx_mapping_tbl_fy[8] = {0, 3, 5, 7, 9, 10, 12, 14}; +static int freq_idx_mapping_tbl_fy_r[16] = {0, 1, 1, 1, 2 , 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 7}; +static int freq_idx_mapping_tbl_fy_big[8] = {0, 4, 6, 8, 10, 12, 14, 15}; +static int freq_idx_mapping_tbl_fy_big_r[16] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7}; + +static int efficiency_B_SB[3][8] = { + {0, 0, 0, 0, 0, 0, 0}, + {50, 48, 77, 56, 56, 126, 156, 1150}, + {56, 54, 86, 63, 64, 140, 174, 1700} +}; + +static int efficiency_LxLL_SB[5][5][8] = { + { + {0, 0, 0, 0, 0, 0, 0}, + {68, 80, 110, 131, 190, 128, 237, 1820}, + {85, 101, 138, 164, 235, 164, 298, 3630}, + {93, 111, 150, 179, 256, 181, 326, 3630}, + {98, 116, 158, 188, 268, 190, 341, 3630} + }, + { + {57, 67, 86, 101, 150, 114, 183, 1660}, + {61, 72, 95, 112, 164, 119, 203, 1660}, + {70, 83, 111, 131, 190, 138, 238, 1660}, + {77, 91, 122, 145, 208, 151, 263, 1660}, + {82, 97, 130, 155, 222, 160, 281, 1660} + }, + { + {68, 79, 103, 120, 176, 137, 217, 2700}, + {68, 79, 104, 123, 180, 135, 222, 2700}, + {74, 87, 115, 135, 197, 146, 246, 2700}, + {78, 93, 123, 145, 210, 155, 264, 2700}, + {82, 97, 129, 153, 220, 163, 278, 2700} + }, + { + {72, 84, 109, 128, 188, 147, 232, 2700}, + {71, 84, 109, 128, 188, 143, 233, 2700}, + {76, 89, 117, 138, 201, 152, 251, 2700}, + {79, 94, 124, 146, 211, 158, 265, 2700}, + {82, 97, 129, 152, 219, 164, 277, 2700} + }, + { + {75, 87, 113, 132, 194, 152, 240, 2700}, + {74, 86, 113, 132, 193, 148, 240, 2700}, + {77, 91, 119, 140, 203, 155, 254, 2700}, + {80, 94, 124, 146, 211, 160, 265, 2700}, + {83, 97, 128, 151, 219, 165, 275, 2700} + } +}; + +static int delta_power_B_SB[3][8] = { + {0, 0, 0, 0, 0, 0, 0}, + {331, 323, 428, 258, 165, 237, 251, 348}, + {589, 572, 766, 454, 290, 425, 450, 235} +}; + +static int delta_power_LxLL_SB[5][5][8] = { + { + {0, 0, 0, 0, 0, 0, 0}, + {99, 90, 82, 39, 41, 30, 52, 80}, + {158, 143, 130, 61, 66, 48, 83, 40}, + {216, 197, 178, 84, 92, 65, 113, 40}, + {274, 250, 227, 107, 117, 82, 144, 40} + }, + { + {177, 160, 142, 67, 75, 54, 89, 128}, + {276, 250, 224, 105, 116, 84, 141, 128}, + {334, 303, 273, 128, 141, 101, 171, 128}, + {393, 356, 321, 151, 166, 119, 202, 128}, + {451, 409, 369, 174, 192, 136, 233, 128} + }, + { + {297, 268, 240, 112, 127, 90, 149, 79}, + {397, 359, 322, 151, 168, 120, 201, 79}, + {455, 412, 370, 173, 193, 137, 232, 79}, + {513, 465, 418, 196, 218, 155, 263, 79}, + {571, 518, 467, 219, 244, 172, 293, 79} + }, + { + {418, 377, 337, 158, 179, 126, 210, 79}, + {517, 468, 419, 196, 220, 156, 261, 79}, + {575, 521, 467, 219, 245, 173, 292, 79}, + {634, 574, 516, 242, 271, 191, 323, 79}, + {692, 627, 564, 265, 296, 208, 354, 79} + }, + { + {539, 486, 435, 203, 231, 162, 270, 79}, + {638, 576, 516, 241, 272, 192, 322, 79}, + {696, 629, 565, 264, 297, 209, 353, 79}, + {754, 682, 613, 287, 323, 227, 383, 79}, + {813, 736, 662, 310, 348, 244, 414, 79} + } +}; + +static int freq_idx_mapping_tbl_sb[8] = {0, 3, 6, 8, 9, 11, 12, 14}; +static int freq_idx_mapping_tbl_sb_r[16] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 7}; +static int freq_idx_mapping_tbl_sb_big[8] = {0, 3, 6, 8, 9, 10, 12, 15}; +static int freq_idx_mapping_tbl_sb_big_r[16] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 5, 6, 6, 7, 7, 7}; diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_platform.h b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_platform.h index 2294dcde0ecf..27f70060a2a1 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_platform.h +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_platform.h @@ -68,6 +68,16 @@ extern unsigned int hps_get_hvytsk(unsigned int cluster_id); #define PPM_DISABLE_BIG_FOR_LP_MODE (1) +#define PPM_USE_EFFICIENCY_TABLE (1) +#ifdef PPM_USE_EFFICIENCY_TABLE +#define PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT (1) +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT +#define PPM_EFFICIENCY_TABLE_MAX_FREQ_IDX 8 +#else +#define PPM_EFFICIENCY_TABLE_MAX_FREQ_IDX 7 +#endif +#endif + /* DLPT mode */ #define PPM_DLPT_DEFAULT_MODE (HYBRID_MODE) #define DLPT_MAX_REAL_POWER_FY (12504) diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_power_state.c b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_power_state.c index 69d1934819d5..9c05b0c1aafd 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_power_state.c +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mach/mt6797/mt_ppm_power_state.c @@ -1543,7 +1543,7 @@ static void ppm_main_pwr_tbl_cpy(struct ppm_power_tbl *dest, struct ppm_power_tb } } -void ppm_main_pwr_tbl_calibration(void) +void ppm_pwr_tbl_calibration(void) { struct ppm_power_tbl_data power_table = ppm_get_power_table(); #ifdef PPM_THERMAL_ENHANCEMENT @@ -1683,3 +1683,55 @@ void ppm_main_pwr_tbl_calibration(void) } #endif +#ifdef PPM_USE_EFFICIENCY_TABLE +#include "mt_ppm_efficiency_table.h" + +int *freq_idx_mapping_tbl; +int *freq_idx_mapping_tbl_r; +int *freq_idx_mapping_tbl_big; +int *freq_idx_mapping_tbl_big_r; +int *efficiency_B[3]; +int *efficiency_LxLL[5][5]; +int *delta_power_B[3]; +int *delta_power_LxLL[5][5]; + +void ppm_init_efficiency_table(void) +{ + int i, j; + + if (ppm_main_info.dvfs_tbl_type == DVFS_TABLE_TYPE_SB) { + freq_idx_mapping_tbl = freq_idx_mapping_tbl_sb; + freq_idx_mapping_tbl_r = freq_idx_mapping_tbl_sb_r; + freq_idx_mapping_tbl_big = freq_idx_mapping_tbl_sb_big; + freq_idx_mapping_tbl_big_r = freq_idx_mapping_tbl_sb_big_r; + + for (i = 0; i < 3; i++) { + efficiency_B[i] = efficiency_B_SB[i]; + delta_power_B[i] = delta_power_B_SB[i]; + } + for (i = 0; i < 5; i++) { + for (j = 0; j < 5; j++) { + efficiency_LxLL[i][j] = efficiency_LxLL_SB[i][j]; + delta_power_LxLL[i][j] = delta_power_LxLL_SB[i][j]; + } + } + } else { + freq_idx_mapping_tbl = freq_idx_mapping_tbl_fy; + freq_idx_mapping_tbl_r = freq_idx_mapping_tbl_fy_r; + freq_idx_mapping_tbl_big = freq_idx_mapping_tbl_fy_big; + freq_idx_mapping_tbl_big_r = freq_idx_mapping_tbl_fy_big_r; + + for (i = 0; i < 3; i++) { + efficiency_B[i] = efficiency_B_FY[i]; + delta_power_B[i] = delta_power_B_FY[i]; + } + for (i = 0; i < 5; i++) { + for (j = 0; j < 5; j++) { + efficiency_LxLL[i][j] = efficiency_LxLL_FY[i][j]; + delta_power_LxLL[i][j] = delta_power_LxLL_FY[i][j]; + } + } + } +} +#endif + diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_api.c b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_api.c index dc30f04857eb..3843b64eedb1 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_api.c +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_api.c @@ -39,11 +39,17 @@ void mt_ppm_set_dvfs_table(unsigned int cpu, struct cpufreq_frequency_table *tbl for (j = 0; j < num; j++) ppm_info("%d: %d KHz\n", j, ppm_main_info.cluster_info[i].dvfs_tbl[j].frequency); + /* data init after CPU segment is confirmed */ + if (i == ppm_main_info.cluster_num - 1) { #ifdef PPM_POWER_TABLE_CALIBRATION - /* start calibration after receiving last cluster's DVFS table */ - if (i == ppm_main_info.cluster_num - 1) - ppm_main_pwr_tbl_calibration(); + /* start calibration after receiving last cluster's DVFS table */ + ppm_pwr_tbl_calibration(); #endif +#ifdef PPM_USE_EFFICIENCY_TABLE + /* init efficiency table */ + ppm_init_efficiency_table(); +#endif + } ppm_unlock(&ppm_main_info.lock); diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_main.c b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_main.c index 0e2e529ca790..4f3b49fbc1c8 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_main.c +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_main.c @@ -85,6 +85,308 @@ struct ppm_data ppm_main_info = { .ppm_event = ATOMIC_INIT(0), }; +#ifdef PPM_USE_EFFICIENCY_TABLE +int prev_max_cpufreq_idx[3] = {0, 0, 0}; +int Core_limit[3] = {4, 4, 2}; + +void ppm_main_update_req_by_pwr(enum ppm_power_state new_state, struct ppm_policy_req *req) +{ + int power_budget = req->power_budget; + /* lookup efficiency table */ + int opp[3]; + int i; + struct cpumask cluster_cpu, online_cpu; + int delta_power; + int activeCoreNumB; + int activeCoreNumL; + int activeCoreNumLL; + int LxLL; + unsigned int power; + /* Get power index of current OPP */ + unsigned int curr_power = 0/* = mt_ppm_thermal_get_cur_power()*/; + struct ppm_cluster_status cluster_status[3]; + struct ppm_cluster_status cluster_status_rebase[3]; + int LxLLisLimited = 0; +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + int B_limit; + int L_limit; + int LL_limit; +#endif + + /* skip if DVFS is not ready (we cannot get current freq...) */ + if (!ppm_main_info.client_info[PPM_CLIENT_DVFS].limit_cb) + return; + + for_each_ppm_clusters(i) { + arch_get_cluster_cpus(&cluster_cpu, i); + cpumask_and(&online_cpu, &cluster_cpu, cpu_online_mask); + + cluster_status[i].core_num = cpumask_weight(&online_cpu); + cluster_status[i].volt = 0; /* don't care */ + if (!cluster_status[i].core_num) + cluster_status[i].freq_idx = -1; + else +#ifdef PPM_FAST_ATM_SUPPORT + cluster_status[i].freq_idx = ppm_main_freq_to_idx(i, + mt_cpufreq_get_cur_phy_freq_no_lock(i), CPUFREQ_RELATION_L); +#else + cluster_status[i].freq_idx = ppm_main_freq_to_idx(i, + mt_cpufreq_get_cur_phy_freq(i), CPUFREQ_RELATION_L); +#endif + ppm_ver("[%d] core = %d, freq_idx = %d\n", + i, cluster_status[i].core_num, cluster_status[i].freq_idx); + /* copy cluster_status data structure */ + cluster_status_rebase[i] = cluster_status[i]; + } + +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + for (i = 0; i <= 2; i++) { + if (cluster_status_rebase[i].core_num > Core_limit[i]) + cluster_status_rebase[i].core_num = Core_limit[i]; + if (req->limit[i].max_cpu_core < Core_limit[i]) + Core_limit[i] = req->limit[i].max_cpu_core; + } +#endif + if (cluster_status_rebase[0].core_num == 0 && cluster_status_rebase[1].core_num == 0) { + if (Core_limit[0] > 0) { + cluster_status_rebase[0].core_num = 1; + cluster_status_rebase[0].freq_idx = 0; + } else { + cluster_status_rebase[1].core_num = 1; + cluster_status_rebase[1].freq_idx = 0; + } + } + + /* use L cluster frequency */ + if (cluster_status_rebase[1].core_num > 0) + cluster_status_rebase[0].freq_idx = cluster_status_rebase[1].freq_idx; + + if (cluster_status_rebase[0].freq_idx <= prev_max_cpufreq_idx[0]) + LxLLisLimited = 1; + if (cluster_status_rebase[1].freq_idx <= prev_max_cpufreq_idx[1]) + LxLLisLimited = 1; + + power = ppm_find_pwr_idx(cluster_status_rebase); + curr_power = (power == -1) ? mt_ppm_thermal_get_max_power() : (unsigned int)power; + + /* convert current OPP(frequency only) from 16 to 8 */ + if (cluster_status_rebase[2].freq_idx >= 0) + opp[0] = freq_idx_mapping_tbl_big_r[cluster_status_rebase[2].freq_idx]; + else + opp[0] = -1; + if (cluster_status_rebase[1].freq_idx >= 0) + opp[1] = freq_idx_mapping_tbl_r[cluster_status_rebase[1].freq_idx]; + else + opp[1] = -1; + if (cluster_status_rebase[0].freq_idx >= 0) + opp[2] = freq_idx_mapping_tbl_r[cluster_status_rebase[0].freq_idx]; + else + opp[2] = -1; + + delta_power = power_budget - curr_power; + + /* Get Active Core number of each cluster */ + activeCoreNumB = cluster_status_rebase[2].core_num; + activeCoreNumL = cluster_status_rebase[1].core_num; + activeCoreNumLL = cluster_status_rebase[0].core_num; + + /* Which Cluster in L and LL is active (1: L is on 2: L is off) */ + LxLL = 0; + if (activeCoreNumL > 0) + LxLL = 1; + else if (activeCoreNumLL > 0) + LxLL = 2; + +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + B_limit = Core_limit[2]; + L_limit = Core_limit[1]; + LL_limit = Core_limit[0]; + req->limit[0].max_cpu_core = LL_limit; + req->limit[1].max_cpu_core = L_limit; + req->limit[2].max_cpu_core = B_limit; +#endif + + if (activeCoreNumB < 0) + activeCoreNumB = 0; + if (activeCoreNumL < 0) + activeCoreNumL = 0; + if (activeCoreNumLL < 0) + activeCoreNumLL = 0; + + ppm_ver("power_budget %d delta_power %d curr_power %d opp %d%d%d %d%d%d\n", + power_budget, delta_power, curr_power, opp[0], opp[1], opp[2], + activeCoreNumB, activeCoreNumL, activeCoreNumLL); + + /* increase ferquency limit */ + if (delta_power >= 0) { + while (1) { + int ChoosenCluster = -1, MaxEfficiency = 0, ChoosenPower = 0; + + /* Big Clister */ + if (activeCoreNumB > 0 && opp[0] > 0 + && delta_power > delta_power_B[activeCoreNumB][opp[0]-1]) { + MaxEfficiency = efficiency_B[activeCoreNumB][opp[0]-1]; + ChoosenCluster = 0; + ChoosenPower = delta_power_B[activeCoreNumB][opp[0]-1]; + } + + ppm_ver("power_budget %d delta_power %d curr_power %d opp %d%d%d %d%d%d %d %d\n", + power_budget, delta_power, curr_power, opp[0], opp[1], opp[2], + activeCoreNumB, activeCoreNumL, activeCoreNumLL, + prev_max_cpufreq_idx[LxLL], cluster_status_rebase[2-LxLL].freq_idx); + ppm_ver("prev_max_cpufreq_idx[LxLL] %d opp[LxLL] %d\n", + prev_max_cpufreq_idx[LxLL], opp[LxLL]); + + /* LxLL Cluster */ + if (LxLL && opp[LxLL] > 0 + && delta_power > delta_power_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]-1] + && efficiency_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]-1] > MaxEfficiency + && (LxLLisLimited || opp[0])) { + MaxEfficiency = efficiency_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]-1]; + ChoosenCluster = 1; + ChoosenPower = delta_power_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]-1]; + } + + /* exceed power budget or all active core is highest freq. */ + if (ChoosenCluster == -1) { +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + if (opp[LxLL] != 0) + goto end; + + /* PPM state L_ONLY --> LL core remain turned off */ + if (new_state != PPM_POWER_STATE_L_ONLY) { + while (LL_limit < 4 && delta_power > + delta_power_LxLL[activeCoreNumL][LL_limit+1][7]) { + delta_power -= delta_power_LxLL[activeCoreNumL][LL_limit + 1][7]; + req->limit[0].max_cpu_core = ++LL_limit; + } + } + /* PPM state LL_ONLY --> L core remain turned off */ + if (new_state != PPM_POWER_STATE_LL_ONLY) { + while (L_limit < 4 && delta_power > + delta_power_LxLL[L_limit+1][activeCoreNumLL][7]) { + delta_power -= delta_power_LxLL[L_limit+1][activeCoreNumLL][7]; + req->limit[1].max_cpu_core = ++L_limit; + } + } + /* PPM state L_ONLY or LL_ONLY--> B core remain turned off */ + if (new_state != PPM_POWER_STATE_LL_ONLY && new_state != PPM_POWER_STATE_L_ONLY) { + while (B_limit < 2 && delta_power > delta_power_B[B_limit+1][7]) { + delta_power -= delta_power_B[B_limit+1][7]; + req->limit[2].max_cpu_core = ++B_limit; + } + } +end: +#endif + break; + } + /* if choose Cluster LxLL, change opp of active cluster only */ + if (ChoosenCluster == 1) { + if (activeCoreNumL > 0) + opp[1] -= 1; + if (activeCoreNumLL > 0) + opp[2] -= 1; + } else + opp[ChoosenCluster] -= 1; + + delta_power -= ChoosenPower; + /* curr_power += ChoosenPower; */ + + } + } else { + while (delta_power < 0) { + int ChoosenCluster = -1; + int MinEfficiency = 10000; /* should be bigger than max value of efficiency_* array */ + int ChoosenPower = 0; + + /* B */ + if (activeCoreNumB > 0 && opp[0] < PPM_EFFICIENCY_TABLE_MAX_FREQ_IDX) { + MinEfficiency = efficiency_B[activeCoreNumB][opp[0]]; + ChoosenCluster = 0; + ChoosenPower = delta_power_B[activeCoreNumB][opp[0]]; + } + /* LxLL */ + if (LxLL && opp[LxLL] < PPM_EFFICIENCY_TABLE_MAX_FREQ_IDX + && efficiency_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]] < MinEfficiency) { + MinEfficiency = efficiency_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]]; + ChoosenCluster = 1; + ChoosenPower = delta_power_LxLL[activeCoreNumL][activeCoreNumLL][opp[LxLL]]; + } + if (ChoosenCluster == -1) { + ppm_err("Failed to find lower OPP: budget %d delta %d curr_power %d opp %d%d%d %d%d%d\n", + power_budget, delta_power, curr_power, opp[0], opp[1], opp[2], + activeCoreNumB, activeCoreNumL, activeCoreNumLL); + break; + } + + /* if choose Cluster LxLL, change opp of active cluster only */ + if (ChoosenCluster == 1) { + if (activeCoreNumL > 0) + opp[1] += 1; + if (activeCoreNumLL > 0) + opp[2] += 1; + } else + opp[ChoosenCluster] += 1; + /* Limit Core */ +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + if (opp[0] == 8 && activeCoreNumB > 0) { + req->limit[2].max_cpu_core = --activeCoreNumB; + opp[0] = 7; + } else if (opp[LxLL] == 8) { + if (activeCoreNumL > 1 || (activeCoreNumLL > 0 && activeCoreNumL > 0)) + req->limit[1].max_cpu_core = --activeCoreNumL; + else if (activeCoreNumLL > 1) + req->limit[0].max_cpu_core = --activeCoreNumLL; + if (activeCoreNumL > 0) + opp[1] = 7; + if (activeCoreNumLL > 0) + opp[2] = 7; + } +#endif + + delta_power += ChoosenPower; + curr_power -= ChoosenPower; + } + } + + ppm_ver("power_budget %d delta_power %d curr_power %d opp %d%d%d\n", + power_budget, delta_power, curr_power, opp[0], opp[1], opp[2]); + + /* Set frequency limit */ + /* For non share buck */ +#if 0 + if (opp[2] >= 0 && activeCoreNumLL > 0) + req->limit[0].max_cpufreq_idx = freq_idx_mapping_tbl[opp[2]]; + if (opp[1] >= 0 && activeCoreNumL > 0) + req->limit[1].max_cpufreq_idx = freq_idx_mapping_tbl[opp[1]]; +#endif + + /* Set all frequency limit of the cluster */ + /* Set OPP of Cluser n to opp[n] */ + req->limit[0].max_cpufreq_idx = freq_idx_mapping_tbl[opp[LxLL]]; + req->limit[1].max_cpufreq_idx = freq_idx_mapping_tbl[opp[LxLL]]; + + if (opp[0] >= 0 && activeCoreNumB > 0) + req->limit[2].max_cpufreq_idx = freq_idx_mapping_tbl_big[opp[0]]; + else + req->limit[2].max_cpufreq_idx = 0; + +#if 0 + /* prevent hotplug from HICA */ + req->limit[0].max_cpu_core = 4; + req->limit[1].max_cpu_core = 4; + req->limit[2].max_cpu_core = 2; +#endif + + for (i = 0; i < req->cluster_num; i++) { + /* error check */ + if (req->limit[i].max_cpufreq_idx > req->limit[i].min_cpufreq_idx) + req->limit[i].min_cpufreq_idx = req->limit[i].max_cpufreq_idx; + if (req->limit[i].max_cpu_core < req->limit[i].min_cpu_core) + req->limit[i].min_cpu_core = req->limit[i].max_cpu_core; + } +} +#else void ppm_main_update_req_by_pwr(enum ppm_power_state new_state, struct ppm_policy_req *req) { int index, i; @@ -126,6 +428,7 @@ tbl_lookup_done: } else ppm_dbg(MAIN, "@%s: index not found!", __func__); } +#endif int ppm_main_freq_to_idx(unsigned int cluster_id, unsigned int freq, unsigned int relation) @@ -384,7 +687,7 @@ static void ppm_main_calc_new_limit(void) { struct ppm_policy_data *pos; int i, active_cnt = 0; - bool is_ptp_activate = false; + bool is_ptp_activate = false, is_all_cluster_zero = true; struct ppm_client_req *c_req = &(ppm_main_info.client_req); struct ppm_client_req *last_req = &(ppm_main_info.last_req); @@ -394,7 +697,10 @@ static void ppm_main_calc_new_limit(void) list_for_each_entry(pos, &ppm_main_info.policy_list, link) { ppm_lock(&pos->lock); - if ((pos->is_enabled && pos->is_activated) || pos->policy == PPM_POLICY_HICA) { + if ((pos->is_enabled && pos->is_activated && pos->is_limit_updated) + || pos->policy == PPM_POLICY_HICA) { + pos->is_limit_updated = false; + for_each_ppm_clusters(i) { ppm_ver("@%s: applying policy %s cluster %d limit...\n", __func__, pos->name, i); ppm_main_update_limit(pos, @@ -425,6 +731,9 @@ static void ppm_main_calc_new_limit(void) /* set freq idx to previous limit if nr_cpu in the cluster is 0 */ for (i = 0; i < c_req->cluster_num; i++) { + if (c_req->cpu_limit[i].max_cpu_core) + is_all_cluster_zero = false; + if ((!c_req->cpu_limit[i].min_cpu_core && !c_req->cpu_limit[i].max_cpu_core) || (c_req->cpu_limit[i].has_advise_core && !c_req->cpu_limit[i].advise_cpu_core)) { c_req->cpu_limit[i].min_cpufreq_idx = last_req->cpu_limit[i].min_cpufreq_idx; @@ -432,6 +741,10 @@ static void ppm_main_calc_new_limit(void) c_req->cpu_limit[i].has_advise_freq = last_req->cpu_limit[i].has_advise_freq; c_req->cpu_limit[i].advise_cpufreq_idx = last_req->cpu_limit[i].advise_cpufreq_idx; } +#ifdef PPM_USE_EFFICIENCY_TABLE + prev_max_cpufreq_idx[i] = c_req->cpu_limit[i].max_cpufreq_idx; + Core_limit[i] = c_req->cpu_limit[i].max_cpu_core; +#endif ppm_ver("Final Result: [%d] --> (%d)(%d)(%d)(%d) (%d)(%d)(%d)(%d)\n", i, @@ -452,6 +765,34 @@ static void ppm_main_calc_new_limit(void) /* fill ptpod activate flag */ c_req->is_ptp_policy_activate = is_ptp_activate; + /* Trigger exception if all cluster max core limit is 0 */ + if (is_all_cluster_zero) { + struct ppm_policy_data *pos; + unsigned int i = 0; + + ppm_err("all cluster max core limit are 0, dump all active policy data...\n"); + + /* dump all policy data for debugging */ + ppm_info("Current state = %s\n", ppm_get_power_state_name(ppm_main_info.cur_power_state)); + + list_for_each_entry(pos, &ppm_main_info.policy_list, link) { + ppm_lock(&pos->lock); + if (pos->is_activated) { + ppm_info("[%d] %s: perf_idx = %d, pwr_bdgt = %d\n", + pos->policy, pos->name, pos->req.perf_idx, pos->req.power_budget); + for_each_ppm_clusters(i) { + ppm_info("cluster %d: (%d)(%d)(%d)(%d)\n", i, + pos->req.limit[i].min_cpufreq_idx, pos->req.limit[i].max_cpufreq_idx, + pos->req.limit[i].min_cpu_core, pos->req.limit[i].max_cpu_core); + } + ppm_info("\n"); + } + ppm_unlock(&pos->lock); + } + + BUG(); + } + FUNC_EXIT(FUNC_LV_MAIN); } @@ -559,6 +900,20 @@ int mt_ppm_main(void) next_state = ppm_main_hica_state_decision(); ppm_main_info.cur_power_state = next_state; +#ifdef PPM_EFFICIENCY_TABLE_USE_CORE_LIMIT + /* reset Core_limit if state changed */ + if (prev_state != next_state) { + struct ppm_power_state_data *state_info = ppm_get_power_state_info(); + + for (i = 0; i < ppm_main_info.cluster_num; i++) { + if (next_state >= PPM_POWER_STATE_NONE) + Core_limit[i] = get_cluster_max_cpu_core(i); + else + Core_limit[i] = state_info[next_state].cluster_limit->state_limit[i].max_cpu_core; + } + } +#endif + /* update active policy's limit according to current state */ list_for_each_entry(pos, &ppm_main_info.policy_list, link) { if ((pos->is_activated || pos->policy == PPM_POLICY_HICA) @@ -566,6 +921,7 @@ int mt_ppm_main(void) ppm_lock(&pos->lock); policy_mask |= 1 << pos->policy; pos->update_limit_cb(next_state); + pos->is_limit_updated = true; ppm_unlock(&pos->lock); } } @@ -642,8 +998,9 @@ int mt_ppm_main(void) notify_dvfs = true; /* check for log reduction */ - if (!(max_freq < 8 && max_freq_ori < 8 && abs(max_freq - max_freq_ori) < 5) - || !(min_freq > 8 && min_freq_ori > 8 && abs(min_freq - min_freq_ori) < 5)) + if (c_req->cpu_limit[i].max_cpu_core != 0 + && (abs(max_freq - max_freq_ori) >= 5 + || abs(min_freq - min_freq_ori) >= 5)) log_print = true; } diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_thermal.c b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_thermal.c index d96303b2279c..70830e2beb4e 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_thermal.c +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_thermal.c @@ -82,7 +82,25 @@ unsigned int mt_ppm_thermal_get_min_power(void) unsigned int mt_ppm_thermal_get_max_power(void) { +#ifdef PPM_USE_EFFICIENCY_TABLE + struct ppm_cluster_status cluster_status_rebase[3]; + unsigned int power; + + cluster_status_rebase[0].core_num = 4; + cluster_status_rebase[0].freq_idx = 0; + cluster_status_rebase[1].core_num = 4; + cluster_status_rebase[1].freq_idx = 0; + cluster_status_rebase[2].core_num = 2; + cluster_status_rebase[2].freq_idx = 0; + + power = ppm_find_pwr_idx(cluster_status_rebase); + if (power > 0) + return power; + else + return ppm_get_power_table().power_tbl[0].power_idx; +#else return ppm_get_power_table().power_tbl[0].power_idx; +#endif } unsigned int mt_ppm_thermal_get_cur_power(void) diff --git a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_ut.c b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_ut.c index ba25603c388b..1dde6ac5a4c0 100644..100755 --- a/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_ut.c +++ b/drivers/misc/mediatek/base/power/ppm_v1/src/mt_ppm_policy_ut.c @@ -21,6 +21,7 @@ static enum ppm_power_state ppm_ut_get_power_state_cb(enum ppm_power_state cur_state); +static void ppm_ut_update_limit_cb(enum ppm_power_state new_state); /* other members will init by ppm_main */ static struct ppm_policy_data ut_policy = { @@ -29,7 +30,7 @@ static struct ppm_policy_data ut_policy = { .policy = PPM_POLICY_UT, .priority = PPM_POLICY_PRIO_HIGHEST, .get_power_state_cb = ppm_ut_get_power_state_cb, - .update_limit_cb = NULL, + .update_limit_cb = ppm_ut_update_limit_cb, .status_change_cb = NULL, .mode_change_cb = NULL, }; @@ -53,6 +54,10 @@ static enum ppm_power_state ppm_ut_get_power_state_cb(enum ppm_power_state cur_s return cur_state; } +static void ppm_ut_update_limit_cb(enum ppm_power_state new_state) +{ +} + static int ppm_ut_fix_core_num_proc_show(struct seq_file *m, void *v) { int i; diff --git a/drivers/misc/mediatek/cameraisp/src/mt6797/camera_isp.c b/drivers/misc/mediatek/cameraisp/src/mt6797/camera_isp.c index 493d57894882..c7b3d3a4edc6 100644..100755 --- a/drivers/misc/mediatek/cameraisp/src/mt6797/camera_isp.c +++ b/drivers/misc/mediatek/cameraisp/src/mt6797/camera_isp.c @@ -1,3 +1,16 @@ +/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + /****************************************************************************** * camera_isp.c - MT6797 Linux ISP Device Driver * @@ -6872,6 +6885,12 @@ static long ISP_ioctl(struct file *pFile, unsigned int Cmd, unsigned long Param) if (copy_from_user(DebugFlag, (void *)Param, sizeof(MUINT32)) == 0) { MUINT32 currentPPB = m_CurrentPPB; MUINT32 lock_key = ISP_IRQ_TYPE_AMOUNT; + + if (DebugFlag[0] >= ISP_IRQ_TYPE_AMOUNT) { + LOG_ERR("unsupported module:0x%x\n", DebugFlag[0]); + Ret = -EFAULT; + break; + } if (DebugFlag[0] == ISP_IRQ_TYPE_INT_CAM_B_ST) { lock_key = ISP_IRQ_TYPE_INT_CAM_A_ST; } else { diff --git a/drivers/misc/mediatek/ext_disp/extd_hdmi.c b/drivers/misc/mediatek/ext_disp/extd_hdmi.c index f4de3599b550..0b62a6cf04d4 100755 --- a/drivers/misc/mediatek/ext_disp/extd_hdmi.c +++ b/drivers/misc/mediatek/ext_disp/extd_hdmi.c @@ -114,7 +114,10 @@ static unsigned int hdmi_layer_num; static unsigned long ovl_config_address[EXTD_OVERLAY_CNT]; static unsigned int hdmi_resolution_param_table[][3] = { {720, 480, 60}, + {1440, 480, 60}, {1280, 720, 60}, + {0, 0, 0}, + {0, 0, 0}, {1920, 1080, 30}, {1920, 1080, 60}, }; @@ -510,8 +513,10 @@ int hdmi_audio_config(int format) static void _hdmi_rdma_irq_handler(DISP_MODULE_ENUM module, unsigned int param) { - if (!is_hdmi_active()) - return; + if (is_lcm_connected()) { + if (!is_hdmi_active()) + return; + } if (param & 0x2) { /* start */ atomic_set(&hdmi_fence_release_event, 1); @@ -643,7 +648,8 @@ static int hdmi_fence_release_kthread(void *data) else layer_3d_format = HDMI_VOUT_FORMAT_2D; - hdmi_video_config(p->output_video_resolution, HDMI_VIN_FORMAT_RGB888, + if (hdmi_drv->get_state() == HDMI_STATE_ACTIVE) + hdmi_video_config(p->output_video_resolution, HDMI_VIN_FORMAT_RGB888, HDMI_VOUT_FORMAT_RGB888 | layer_3d_format); if (kthread_should_stop()) break; @@ -828,6 +834,8 @@ static void hdmi_state_reset(void) hdmi_drv->get_params(hdmi_params); hdmi_resume(); } + if (!is_lcm_connected()) + hdmi_resume(); hdmi_state_reset(); } @@ -1018,7 +1026,8 @@ void hdmi_state_callback(enum HDMI_STATE state) #ifdef MHL_DYNAMIC_VSYNC_OFFSET ged_dvfs_vsync_offset_event_switch(GED_DVFS_VSYNC_OFFSET_MHL_EVENT, false); #endif - hdmi_suspend(); + if (is_lcm_connected()) + hdmi_suspend(); switch_set_state(&hdmi_switch_data, HDMI_STATE_NO_DEVICE); switch_set_state(&hdmires_switch_data, 0); hdmi_enable_dvfs(false); @@ -1133,6 +1142,8 @@ int hdmi_power_enable(int enable) } hdmi_power_on(); } else { + if (!is_lcm_connected()) + hdmi_suspend(); hdmi_power_off(); switch_set_state(&hdmi_switch_data, HDMI_STATE_NO_DEVICE); } @@ -1288,7 +1299,9 @@ int hdmi_set_resolution(int res) int hdmi_get_dev_info(int is_sf, void *info) { int ret = 0; - + if (!is_lcm_connected()) { + hdmi_enable(1); + } if (is_sf == AP_GET_INFO) { int displayid = 0; mtk_dispif_info_t hdmi_info; @@ -1334,6 +1347,7 @@ int hdmi_get_dev_info(int is_sf, void *info) hdmi_info.vsyncFPS = 24; else hdmi_info.vsyncFPS = 60; + hdmi_info.vsyncFPS *= 100; if (copy_to_user(info, &hdmi_info, sizeof(hdmi_info))) { MMProfileLogEx(ddp_mmp_get_events()->Extd_ErrorInfo, MMProfileFlagPulse, Devinfo, 1); @@ -1375,6 +1389,7 @@ int hdmi_get_dev_info(int is_sf, void *info) dispif_info->vsyncFPS = 24; else dispif_info->vsyncFPS = 60; + dispif_info->vsyncFPS *= 100; if (dispif_info->displayWidth * dispif_info->displayHeight <= 240 * 432) dispif_info->physicalHeight = dispif_info->physicalWidth = 0; @@ -1584,6 +1599,7 @@ int hdmi_post_init(void) #ifdef HDMI_OPEN_PACAKAGE_SUPPORT init_waitqueue_head(&hdmi_para_config_wq); + hdmi_resolution_setting(HDMI_VIDEO_1280x720p_60Hz); #endif Extd_DBG_Init(); return 0; diff --git a/drivers/misc/mediatek/ext_disp/mt6797/external_display.c b/drivers/misc/mediatek/ext_disp/mt6797/external_display.c index 109a31e5f91f..38545f2eeed1 100644..100755 --- a/drivers/misc/mediatek/ext_disp/mt6797/external_display.c +++ b/drivers/misc/mediatek/ext_disp/mt6797/external_display.c @@ -1398,3 +1398,13 @@ int ext_disp_is_dim_layer(unsigned long mva) return ret; } + +int is_lcm_connected(void) +{ + int ret = 0; + if (islcmconnected) + ret = 1; + else + ret = 0; + return ret; +} diff --git a/drivers/misc/mediatek/ext_disp/mt6797/external_display.h b/drivers/misc/mediatek/ext_disp/mt6797/external_display.h index e0ff9aeb571e..9fcaca51113f 100644..100755 --- a/drivers/misc/mediatek/ext_disp/mt6797/external_display.h +++ b/drivers/misc/mediatek/ext_disp/mt6797/external_display.h @@ -127,4 +127,6 @@ bool ext_disp_path_source_is_RDMA(unsigned int session); int ext_disp_is_dim_layer(unsigned long mva); extern int is_dim_layer(unsigned long mva); +int is_lcm_connected(void); + #endif diff --git a/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_config_platform.c b/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_config_platform.c index f6f342f4bdda..b1d5ed26de81 100755 --- a/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_config_platform.c +++ b/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_config_platform.c @@ -127,7 +127,6 @@ static volatile void *g_0x10018_base; static volatile void *g_0x10019_base; static volatile void *g_0x10201_base; static volatile void *g_0x13000_base; -static volatile void *g_0x13040_base; #define _mtk_dump_register(mtklog, pa, offset, dsize) \ __mtk_dump_register(mtklog, g_##pa##_base, pa##000, offset, dsize) @@ -214,7 +213,6 @@ void mtk_debug_dump_registers(void) if (g_is_power_on) { _mtk_dump_register(mtklog, 0x13000, 0x0, 0x470); - _mtk_dump_register(mtklog, 0x13040, 0x0, 0x4000); } else { @@ -237,7 +235,6 @@ void mtk_debbug_register_init(void) DEBUG_INIT_BASE(0x10019, 0x1000); DEBUG_INIT_BASE(0x10201, 0x1000); DEBUG_INIT_BASE(0x13000, 0x1000); - DEBUG_INIT_BASE(0x13040, 0x4000); } void mtk_debug_mfg_reset(void) @@ -309,6 +306,9 @@ static int mtk_pm_callback_power_on(void) MFG_write32(0x448, MFG_read32(0x448) | 0x1); #endif + /* timing */ + MFG_write32(0x1c, MFG_read32(0x1c) | config->async_value); + /* enable PMU */ MFG_write32(0x3e0, 0xffffffff); MFG_write32(0x3e4, 0xffffffff); @@ -677,6 +677,8 @@ int mtk_platform_init(struct platform_device *pdev, struct kbase_device *kbdev) config->min_volt = 860; config->min_freq = mt_gpufreq_get_freq_by_idx(mt_gpufreq_get_dvfs_table_num()-2); + config->async_value = config->max_freq >= 780000 ? 0xa : 0x5; + g_config = kbdev->mtk_config = config; #ifdef MTK_GPU_SPM diff --git a/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_kbase_spm.h b/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_kbase_spm.h index e392f463cb41..7af0ead9a68a 100755 --- a/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_kbase_spm.h +++ b/drivers/misc/mediatek/gpu/gpu_mali/mali_midgard/mali-r7p0/drivers/gpu/arm/midgard/platform/mt6797/mtk_kbase_spm.h @@ -64,6 +64,8 @@ struct mtk_config { unsigned int max_freq; unsigned int min_volt; unsigned int min_freq; + + int32_t async_value; }; #define MFG_DEBUG_SEL (0x180) diff --git a/drivers/misc/mediatek/imgsensor/src/mt6797/camera_hw/kd_camera_hw.c b/drivers/misc/mediatek/imgsensor/src/mt6797/camera_hw/kd_camera_hw.c index d7ec4ca01736..e796707cf04a 100755 --- a/drivers/misc/mediatek/imgsensor/src/mt6797/camera_hw/kd_camera_hw.c +++ b/drivers/misc/mediatek/imgsensor/src/mt6797/camera_hw/kd_camera_hw.c @@ -586,7 +586,7 @@ int mtkcam_gpio_set(int PinIdx, int PwrType, int Val) PK_ERR("Please check AVDD pin control\n"); mAVDD_usercounter = 0; - // pinctrl_select_state(camctrl, cam_ldo_vcama_l); ////by zhaowan del,2016/07/18 + pinctrl_select_state(camctrl, cam_ldo_vcama_l); ////by zhaowan del,2016/07/18 } } @@ -607,7 +607,7 @@ int mtkcam_gpio_set(int PinIdx, int PwrType, int Val) PK_ERR("Please check DVDD pin control\n"); mDVDD_usercounter = 0; - // pinctrl_select_state(camctrl, cam_ldo_vcamd_l); //by zhaowan del,2016/07/18 + pinctrl_select_state(camctrl, cam_ldo_vcamd_l); //by zhaowan del,2016/07/18 } } else if (Val == 1 && !IS_ERR(cam_ldo_vcamd_h)) diff --git a/drivers/misc/mediatek/lcm/inc/lcm_drv.h b/drivers/misc/mediatek/lcm/inc/lcm_drv.h index 6d315d2128bc..32602d7b68c0 100644..100755 --- a/drivers/misc/mediatek/lcm/inc/lcm_drv.h +++ b/drivers/misc/mediatek/lcm/inc/lcm_drv.h @@ -636,8 +636,10 @@ typedef struct { LCM_DBI_PARAMS dbi; LCM_DPI_PARAMS dpi; LCM_DSI_PARAMS dsi; - unsigned int physical_width; - unsigned int physical_height; + unsigned int physical_width; /* length: mm, for legacy use */ + unsigned int physical_height; /* length: mm, for legacy use */ + unsigned int physical_width_um; /* length: um, for more precise precision */ + unsigned int physical_height_um; /* length: um, for more precise precision */ unsigned int od_table_size; void *od_table; } LCM_PARAMS; diff --git a/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797.c b/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797.c index daac46e8dae3..cf14926aac46 100644..100755 --- a/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797.c +++ b/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797/otm1906b_fhd_dsi_cmd_jdi_tps65132_mt6797.c @@ -551,8 +551,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; #if (LCM_DSI_CMD_MODE) params->dsi.mode = CMD_MODE; diff --git a/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797.c b/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797.c index 93879df06f57..ec8e512c2b9d 100644..100755 --- a/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797.c +++ b/drivers/misc/mediatek/lcm/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797/otm1906b_fhd_dsi_vdo_jdi_tps65132_mt6797.c @@ -551,8 +551,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; #if (LCM_DSI_CMD_MODE) params->dsi.mode = CMD_MODE; diff --git a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok/r63419_wqhd_truly_phantom_2k_cmd_ok.c b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok/r63419_wqhd_truly_phantom_2k_cmd_ok.c index 64c0742c8fd0..1289cefabcfa 100644..100755 --- a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok/r63419_wqhd_truly_phantom_2k_cmd_ok.c +++ b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok/r63419_wqhd_truly_phantom_2k_cmd_ok.c @@ -462,8 +462,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; params->lcm_if = LCM_INTERFACE_DSI_DUAL; params->lcm_cmd_if = LCM_INTERFACE_DSI0; diff --git a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.c b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.c index 4afa35b37c42..82410e7bf579 100644..100755 --- a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.c +++ b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.c @@ -457,8 +457,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; params->lcm_if = LCM_INTERFACE_DSI_DUAL; params->lcm_cmd_if = LCM_INTERFACE_DSI0; diff --git a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok/r63419_wqhd_truly_phantom_2k_vdo_ok.c b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok/r63419_wqhd_truly_phantom_2k_vdo_ok.c index 406ac2cf211e..cade9f96282f 100644..100755 --- a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok/r63419_wqhd_truly_phantom_2k_vdo_ok.c +++ b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok/r63419_wqhd_truly_phantom_2k_vdo_ok.c @@ -447,8 +447,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; params->lcm_if = LCM_INTERFACE_DSI_DUAL; params->lcm_cmd_if = LCM_INTERFACE_DSI0; diff --git a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797.c b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797.c index d3fd4d828085..ebb610b4501c 100644..100755 --- a/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797.c +++ b/drivers/misc/mediatek/lcm/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797/r63419_wqhd_truly_phantom_2k_vdo_ok_mt6797.c @@ -443,8 +443,10 @@ static void lcm_get_params(LCM_PARAMS *params) params->width = FRAME_WIDTH; params->height = FRAME_HEIGHT; - params->physical_width = LCM_PHYSICAL_WIDTH; - params->physical_height = LCM_PHYSICAL_HEIGHT; + params->physical_width = LCM_PHYSICAL_WIDTH/1000; + params->physical_height = LCM_PHYSICAL_HEIGHT/1000; + params->physical_width_um = LCM_PHYSICAL_WIDTH; + params->physical_height_um = LCM_PHYSICAL_HEIGHT; params->lcm_if = LCM_INTERFACE_DSI_DUAL; params->lcm_cmd_if = LCM_INTERFACE_DSI0; diff --git a/drivers/misc/mediatek/led_96board/led_96board.c b/drivers/misc/mediatek/led_96board/led_96board.c index fc4d8b78a28e..a1353c8369db 100755 --- a/drivers/misc/mediatek/led_96board/led_96board.c +++ b/drivers/misc/mediatek/led_96board/led_96board.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ + #include "led_96board.h" #include <mt-plat/mt_gpio.h> #include <mach/gpio_const.h> diff --git a/drivers/misc/mediatek/lens/common/lc898212xdaf_f/LC89821x_STMV.c b/drivers/misc/mediatek/lens/common/lc898212xdaf_f/LC89821x_STMV.c index 7b3257510530..4f11d95adfef 100644..100755 --- a/drivers/misc/mediatek/lens/common/lc898212xdaf_f/LC89821x_STMV.c +++ b/drivers/misc/mediatek/lens/common/lc898212xdaf_f/LC89821x_STMV.c @@ -1,233 +1,242 @@ -
-#include <linux/delay.h>
-#include "LC89821x_STMV.h"
-
-#define DEBUG_LOG
-#ifdef DEBUG_LOG
-#include <linux/fs.h>
-#endif
-
-#ifdef DEBUG_LOG
-#define AF_REGDUMP "REGDUMP"
-#define LOG_INF(format, args...) pr_info(AF_REGDUMP " " format, ##args)
-#endif
-/* /////////////////////////////////////// */
-
-#define DeviceAddr 0xE4 /* Device address of driver IC */
-
-/*--------------------------------------------------------
- IIC wrtie 2 bytes function
- Parameters: addr, data
---------------------------------------------------------*/
-static void RamWriteA(unsigned short addr, unsigned short data)
-{
- /* To call your IIC function here */
- u8 puSendCmd[3] = { (u8) (addr & 0xFF), (u8) (data >> 8), (u8) (data & 0xFF) };
-
- s4AF_WriteReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), DeviceAddr);
-
- #ifdef DEBUG_LOG
- LOG_INF("RAMW\t%x\t%x\n", addr, data );
- #endif
-}
-
-
-/*------------------------------------------------------
- IIC read 2 bytes function
- Parameters: addr, *data
--------------------------------------------------------*/
-static void RamReadA(unsigned short addr, unsigned short *data)
-{
- /* To call your IIC function here */
- u8 buf[2];
- u8 puSendCmd[1] = { (u8) (addr & 0xFF) };
-
- s4AF_ReadReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), buf, 2, DeviceAddr);
- *data = (buf[0] << 8) | (buf[1] & 0x00FF);
-
- #ifdef DEBUG_LOG
- LOG_INF("RAMR\t%x\t%x\n", addr, *data );
- #endif
-}
-
-
-/*--------------------------------------------------------
- IIC wrtie 1 byte function
- Parameters: addr, data
---------------------------------------------------------*/
-static void RegWriteA(unsigned short addr, unsigned char data)
-{
- /* To call your IIC function here */
- u8 puSendCmd[2] = { (u8) (addr & 0xFF), (u8) (data & 0xFF) };
-
- s4AF_WriteReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), DeviceAddr);
-
- #ifdef DEBUG_LOG
- LOG_INF("REGW\t%x\t%x\n", addr, data );
- #endif
-}
-
-
-/*--------------------------------------------------------
- IIC read 1 byte function
- Parameters: addr, *data
---------------------------------------------------------*/
-static void RegReadA(unsigned short addr, unsigned char *data)
-{
- /* To call your IIC function here */
- u8 puSendCmd[1] = { (u8) (addr & 0xFF) };
-
- s4AF_ReadReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), data, 1, DeviceAddr);
-
- #ifdef DEBUG_LOG
- LOG_INF("REGR\t%x\t%x\n", addr, *data );
- #endif
-}
-
-
-/*--------------------------------------------------------
- Wait function
- Parameters: msec
---------------------------------------------------------*/
-static void WaitTime(unsigned short msec)
-{
- /* To call your Wait function here */
- usleep_range(msec * 1000, (msec + 1) * 1000);
-}
-
-
-/* /////////////////////////////////////// */
-
-
-/* ************************** */
-/* Definations */
-/* ************************** */
-
-#define REG_ADDR_START 0x80 /* REG Start address */
-
-/*--------------------------
- Local defination
----------------------------*/
-static stSmvPar StSmvPar;
-
-
-static void StmvSet(stSmvPar StSetSmv)
-{
- unsigned char UcSetEnb;
- unsigned char UcSetSwt;
- unsigned short UsParSiz;
- unsigned char UcParItv;
- short SsParStt; /* StepMove Start Position */
-
- StSmvPar.UsSmvSiz = StSetSmv.UsSmvSiz;
- StSmvPar.UcSmvItv = StSetSmv.UcSmvItv;
- StSmvPar.UcSmvEnb = StSetSmv.UcSmvEnb;
-
- RegWriteA(AFSEND_211, 0x00); /* StepMove Enable Bit Clear */
-
- RegReadA(ENBL_211, &UcSetEnb);
- UcSetEnb &= (unsigned char)0xFD;
- RegWriteA(ENBL_211, UcSetEnb); /* Measuremenet Circuit1 Off */
-
- RegReadA(SWTCH_211, &UcSetSwt);
- UcSetSwt &= (unsigned char)0x7F;
- RegWriteA(SWTCH_211, UcSetSwt); /* RZ1 Switch Cut Off */
-
- RamReadA(RZ_211H, (unsigned short *)&SsParStt); /* Get Start Position */
- UsParSiz = StSetSmv.UsSmvSiz; /* Get StepSize */
- UcParItv = StSetSmv.UcSmvItv; /* Get StepInterval */
-
- RamWriteA(ms11a_211H, (unsigned short)0x0800); /* Set Coefficient Value For StepMove */
- RamWriteA(MS1Z22_211H, (unsigned short)SsParStt); /* Set Start Positon */
- RamWriteA(MS1Z12_211H, UsParSiz); /* Set StepSize */
- RegWriteA(STMINT_211, UcParItv); /* Set StepInterval */
-
- UcSetSwt |= (unsigned char)0x80;
- RegWriteA(SWTCH_211, UcSetSwt); /* RZ1 Switch ON */
-}
-
-static unsigned char StmvTo(short SsSmvEnd)
-{
- unsigned short UsSmvDpl;
- short SsParStt; /* StepMove Start Position */
-
- /* PIOA_SetOutput(_PIO_PA29); // Monitor I/O Port */
-
- RamReadA(RZ_211H, (unsigned short *)&SsParStt); /* Get Start Position */
- UsSmvDpl = abs(SsParStt - SsSmvEnd);
-
- if ((UsSmvDpl <= StSmvPar.UsSmvSiz) && ((StSmvPar.UcSmvEnb & STMSV_ON) == STMSV_ON)) {
- if (StSmvPar.UcSmvEnb & STMCHTG_ON) {
- RegWriteA(MSSET_211, INI_MSSET_211 | (unsigned char)0x01);
- }
- RamWriteA(MS1Z22_211H, SsSmvEnd); /* Handling Single Step For ES1 */
- StSmvPar.UcSmvEnb |= STMVEN_ON; /* Combine StepMove Enable Bit & StepMove Mode Bit */
- } else {
- if (SsParStt < SsSmvEnd) { /* Check StepMove Direction */
- RamWriteA(MS1Z12_211H, StSmvPar.UsSmvSiz);
- } else if (SsParStt > SsSmvEnd) {
- RamWriteA(MS1Z12_211H, -StSmvPar.UsSmvSiz);
- }
-
- RamWriteA(STMVENDH_211, SsSmvEnd); /* Set StepMove Target Positon */
- StSmvPar.UcSmvEnb |= STMVEN_ON; /* Combine StepMove Enable Bit & StepMove Mode Bit */
- RegWriteA(STMVEN_211, StSmvPar.UcSmvEnb); /* Start StepMove */
- }
-
- return 0;
-}
-static void AfInit(unsigned char hall_off, unsigned char hall_bias)
-{
- #define DataLen sizeof(Init_Table_F) / sizeof(IniData_F)
- unsigned short i;
- unsigned short pos;
-
- for (i = 0; i < DataLen; i++) {
- if (Init_Table_F[i].addr == WAIT) {
- WaitTime(Init_Table_F[i].data);
- continue;
- }
-
- if (Init_Table_F[i].addr >= REG_ADDR_START) {
- RegWriteA(Init_Table_F[i].addr, (unsigned char)(Init_Table_F[i].data & 0x00ff));
- } else {
- RamWriteA(Init_Table_F[i].addr, (unsigned short)Init_Table_F[i].data);
- }
- }
-
- RegWriteA(0x28, hall_off); /* Hall Offset */
- RegWriteA(0x29, hall_bias); /* Hall Bias */
-
- RamReadA(0x3C, &pos);
- RamWriteA(0x04, pos); /* Direct move target position */
- RamWriteA(0x18, pos); /* Step move start position */
-}
-
-static void ServoOn(void)
-{
- RegWriteA(0x85, 0x80); /* Clear PID Ram Data */
- WaitTime(1);
- RegWriteA(0x87, 0x85); /* Servo ON */
-}
-
-
-void LC898212XDAF_F_MONO_init(unsigned char Hall_Off, unsigned char Hall_Bias)
-{
- stSmvPar StSmvPar;
-
- AfInit(Hall_Off, Hall_Bias); /* Initialize driver IC */
-
- /* Step move parameter set */
- StSmvPar.UsSmvSiz = STMV_SIZE;
- StSmvPar.UcSmvItv = STMV_INTERVAL;
- StSmvPar.UcSmvEnb = STMCHTG_SET | STMSV_SET | STMLFF_SET;
- StmvSet(StSmvPar);
-
- ServoOn(); /* Close loop ON */
-}
-
-unsigned char LC898212XDAF_F_MONO_moveAF(short SsSmvEnd)
-{
- return StmvTo(SsSmvEnd);
-}
-
+/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + +#include <linux/delay.h> +#include "LC89821x_STMV.h" + +#define DEBUG_LOG +#ifdef DEBUG_LOG +#include <linux/fs.h> +#endif + +#ifdef DEBUG_LOG +#define AF_REGDUMP "REGDUMP" +#define LOG_INF(format, args...) pr_info(AF_REGDUMP " " format, ##args) +#endif +/* /////////////////////////////////////// */ + +#define DeviceAddr 0xE4 /* Device address of driver IC */ + +/*-------------------------------------------------------- + IIC wrtie 2 bytes function + Parameters: addr, data +--------------------------------------------------------*/ +static void RamWriteA(unsigned short addr, unsigned short data) +{ + /* To call your IIC function here */ + u8 puSendCmd[3] = { (u8) (addr & 0xFF), (u8) (data >> 8), (u8) (data & 0xFF) }; + + s4AF_WriteReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), DeviceAddr); + + #ifdef DEBUG_LOG + LOG_INF("RAMW\t%x\t%x\n", addr, data); + #endif +} + + +/*------------------------------------------------------ + IIC read 2 bytes function + Parameters: addr, *data +-------------------------------------------------------*/ +static void RamReadA(unsigned short addr, unsigned short *data) +{ + /* To call your IIC function here */ + u8 buf[2]; + u8 puSendCmd[1] = { (u8) (addr & 0xFF) }; + + s4AF_ReadReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), buf, 2, DeviceAddr); + *data = (buf[0] << 8) | (buf[1] & 0x00FF); + + #ifdef DEBUG_LOG + LOG_INF("RAMR\t%x\t%x\n", addr, *data); + #endif +} + + +/*-------------------------------------------------------- + IIC wrtie 1 byte function + Parameters: addr, data +--------------------------------------------------------*/ +static void RegWriteA(unsigned short addr, unsigned char data) +{ + /* To call your IIC function here */ + u8 puSendCmd[2] = { (u8) (addr & 0xFF), (u8) (data & 0xFF) }; + + s4AF_WriteReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), DeviceAddr); + + #ifdef DEBUG_LOG + LOG_INF("REGW\t%x\t%x\n", addr, data); + #endif +} + + +/*-------------------------------------------------------- + IIC read 1 byte function + Parameters: addr, *data +--------------------------------------------------------*/ +static void RegReadA(unsigned short addr, unsigned char *data) +{ + /* To call your IIC function here */ + u8 puSendCmd[1] = { (u8) (addr & 0xFF) }; + + s4AF_ReadReg_LC898212XDAF_F(puSendCmd, sizeof(puSendCmd), data, 1, DeviceAddr); + + #ifdef DEBUG_LOG + LOG_INF("REGR\t%x\t%x\n", addr, *data); + #endif +} + + +/*-------------------------------------------------------- + Wait function + Parameters: msec +--------------------------------------------------------*/ +static void WaitTime(unsigned short msec) +{ + /* To call your Wait function here */ + usleep_range(msec * 1000, (msec + 1) * 1000); +} + + +/* /////////////////////////////////////// */ + + +/* ************************** */ +/* Definations */ +/* ************************** */ + +#define REG_ADDR_START 0x80 /* REG Start address */ + +/*-------------------------- + Local defination +---------------------------*/ +static stSmvPar StSmvPar; + + +static void StmvSet(stSmvPar StSetSmv) +{ + unsigned char UcSetEnb; + unsigned char UcSetSwt; + unsigned short UsParSiz; + unsigned char UcParItv; + short SsParStt; /* StepMove Start Position */ + + StSmvPar.UsSmvSiz = StSetSmv.UsSmvSiz; + StSmvPar.UcSmvItv = StSetSmv.UcSmvItv; + StSmvPar.UcSmvEnb = StSetSmv.UcSmvEnb; + + RegWriteA(AFSEND_211, 0x00); /* StepMove Enable Bit Clear */ + + RegReadA(ENBL_211, &UcSetEnb); + UcSetEnb &= (unsigned char)0xFD; + RegWriteA(ENBL_211, UcSetEnb); /* Measuremenet Circuit1 Off */ + + RegReadA(SWTCH_211, &UcSetSwt); + UcSetSwt &= (unsigned char)0x7F; + RegWriteA(SWTCH_211, UcSetSwt); /* RZ1 Switch Cut Off */ + + RamReadA(RZ_211H, (unsigned short *)&SsParStt); /* Get Start Position */ + UsParSiz = StSetSmv.UsSmvSiz; /* Get StepSize */ + UcParItv = StSetSmv.UcSmvItv; /* Get StepInterval */ + + RamWriteA(ms11a_211H, (unsigned short)0x0800); /* Set Coefficient Value For StepMove */ + RamWriteA(MS1Z22_211H, (unsigned short)SsParStt); + RamWriteA(MS1Z12_211H, UsParSiz); /* Set StepSize */ + RegWriteA(STMINT_211, UcParItv); /* Set StepInterval */ + + UcSetSwt |= (unsigned char)0x80; + RegWriteA(SWTCH_211, UcSetSwt); /* RZ1 Switch ON */ +} + +static unsigned char StmvTo(short SsSmvEnd) +{ + unsigned short UsSmvDpl; + short SsParStt; /* StepMove Start Position */ + + RamReadA(RZ_211H, (unsigned short *)&SsParStt); /* Get Start Position */ + UsSmvDpl = abs(SsParStt - SsSmvEnd); + + if ((UsSmvDpl <= StSmvPar.UsSmvSiz) && ((StSmvPar.UcSmvEnb & STMSV_ON) == STMSV_ON)) { + if (StSmvPar.UcSmvEnb & STMCHTG_ON) + RegWriteA(MSSET_211, INI_MSSET_211 | (unsigned char)0x01); + + RamWriteA(MS1Z22_211H, SsSmvEnd); /* Handling Single Step For ES1 */ + StSmvPar.UcSmvEnb |= STMVEN_ON; /* Combine StepMove Enable Bit & StepMove Mode Bit */ + } else { + if (SsParStt < SsSmvEnd) { /* Check StepMove Direction */ + RamWriteA(MS1Z12_211H, StSmvPar.UsSmvSiz); + } else if (SsParStt > SsSmvEnd) { + RamWriteA(MS1Z12_211H, -StSmvPar.UsSmvSiz); + } + + RamWriteA(STMVENDH_211, SsSmvEnd); + StSmvPar.UcSmvEnb |= STMVEN_ON; /* Combine StepMove Enable Bit & StepMove Mode Bit */ + RegWriteA(STMVEN_211, StSmvPar.UcSmvEnb); /* Start StepMove */ + } + + return 0; +} +static void AfInit(unsigned char hall_off, unsigned char hall_bias) +{ + #define DataLen (sizeof(Init_Table_F) / sizeof(IniData_F)) + unsigned short i; + unsigned short pos; + + for (i = 0; i < DataLen; i++) { + if (Init_Table_F[i].addr == WAIT) { + WaitTime(Init_Table_F[i].data); + continue; + } + + if (Init_Table_F[i].addr >= REG_ADDR_START) + RegWriteA(Init_Table_F[i].addr, (unsigned char)(Init_Table_F[i].data & 0x00ff)); + else + RamWriteA(Init_Table_F[i].addr, (unsigned short)Init_Table_F[i].data); + } + + RegWriteA(0x28, hall_off); /* Hall Offset */ + RegWriteA(0x29, hall_bias); /* Hall Bias */ + + RamReadA(0x3C, &pos); + RamWriteA(0x04, pos); /* Direct move target position */ + RamWriteA(0x18, pos); /* Step move start position */ +} + +static void ServoOn(void) +{ + RegWriteA(0x85, 0x80); /* Clear PID Ram Data */ + WaitTime(1); + RegWriteA(0x87, 0x85); /* Servo ON */ +} + + +void LC898212XDAF_F_MONO_init(unsigned char Hall_Off, unsigned char Hall_Bias) +{ + stSmvPar StSmvPar; + + AfInit(Hall_Off, Hall_Bias); /* Initialize driver IC */ + + /* Step move parameter set */ + StSmvPar.UsSmvSiz = STMV_SIZE; + StSmvPar.UcSmvItv = STMV_INTERVAL; + StSmvPar.UcSmvEnb = STMCHTG_SET | STMSV_SET | STMLFF_SET; + StmvSet(StSmvPar); + + ServoOn(); /* Close loop ON */ +} + +unsigned char LC898212XDAF_F_MONO_moveAF(short SsSmvEnd) +{ + return StmvTo(SsSmvEnd); +} + diff --git a/drivers/misc/mediatek/lens/common/lc898212xdaf_f/inc/LC898212XDAF_F.h b/drivers/misc/mediatek/lens/common/lc898212xdaf_f/inc/LC898212XDAF_F.h index 7eb32f051c23..2591839f6408 100644..100755 --- a/drivers/misc/mediatek/lens/common/lc898212xdaf_f/inc/LC898212XDAF_F.h +++ b/drivers/misc/mediatek/lens/common/lc898212xdaf_f/inc/LC898212XDAF_F.h @@ -1,8 +1,21 @@ -#ifndef __LC898212XDAF_F__
-#define __LC898212XDAF_F__
-
-extern void LC898212XDAF_F_MONO_init(unsigned char Hall_Off, unsigned char Hall_Bias);
-
-extern unsigned char LC898212XDAF_F_MONO_moveAF(short SsSmvEnd);
-
+/* + * Copyright (C) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + +#ifndef __LC898212XDAF_F__ +#define __LC898212XDAF_F__ + +extern void LC898212XDAF_F_MONO_init(unsigned char Hall_Off, unsigned char Hall_Bias); + +extern unsigned char LC898212XDAF_F_MONO_moveAF(short SsSmvEnd); + #endif
\ No newline at end of file diff --git a/drivers/misc/mediatek/performance/fliper/mt6797/fliper.c b/drivers/misc/mediatek/performance/fliper/mt6797/fliper.c index e7f028181d71..fbddd21714e2 100644..100755 --- a/drivers/misc/mediatek/performance/fliper/mt6797/fliper.c +++ b/drivers/misc/mediatek/performance/fliper/mt6797/fliper.c @@ -31,7 +31,7 @@ #include <mt_vcorefs_manager.h> #include <mach/mt_emi_bm.h> -#include "mt_cpufreq.h" +#include <mach/mt_ppm_api.h> #define SEQ_printf(m, x...)\ do {\ @@ -93,12 +93,15 @@ static unsigned int emi_polling(unsigned int *__restrict__ emi_value) /******* FLIPER SETTING *********/ static void enable_fliper_polling(void) { + l_boost_flag = 0; + mt_ppm_sysboost_freq(BOOST_BY_PERFSERV, 0); pr_debug(TAG"fliper polling start\n"); mod_timer(&mt_pp_transfer_timer, jiffies + msecs_to_jiffies(X_ms)); } static void disable_fliper_polling(void) { + mt_ppm_sysboost_freq(BOOST_BY_PERFSERV, 0); pr_crit("fliper polling disable ---\n"); del_timer(&mt_pp_transfer_timer); } @@ -254,6 +257,7 @@ static ssize_t mt_fliper_write(struct file *filp, const char *ubuf, if (arg1 == Default) { pr_debug(TAG"POWER_MODE: default\n"); enable_cg_fliper(1); + enable_fliper_polling(); cg_set_threshold(CG_DEFAULT_LPM, CG_DEFAULT_HPM); vcorefs_request_dvfs_opp(KIR_PERF, OPPI_UNREQ); } else if (arg1 == Low_Power_Mode) { @@ -264,16 +268,19 @@ static ssize_t mt_fliper_write(struct file *filp, const char *ubuf, vcorefs_request_dvfs_opp(KIR_PERF, OPPI_UNREQ); #else enable_cg_fliper(0); + disable_fliper_polling(); vcorefs_request_dvfs_opp(KIR_PERF, OPPI_UNREQ); #endif } else if (arg1 == Just_Make_Mode) { pr_debug(TAG"POWER_MODE: JUST_MAKE\n"); enable_cg_fliper(1); + enable_fliper_polling(); cg_set_threshold(CG_JUST_MAKE_LPM, CG_JUST_MAKE_HPM); vcorefs_request_dvfs_opp(KIR_PERF, OPPI_UNREQ); } else if (arg1 == Performance_Mode) { pr_debug(TAG"POWER_MODE: PERFORMANCE\n"); enable_cg_fliper(1); + enable_fliper_polling(); #if 0 cg_set_threshold(CG_PERFORMANCE_LPM, CG_PERFORMANCE_HPM); #else @@ -334,7 +341,9 @@ fliper_pm_callback(struct notifier_block *nb, case PM_POST_SUSPEND: pr_debug(TAG"Resume, restore CG configuration\n"); - cg_set_threshold(cg_lpm_bw_threshold, cg_hpm_bw_threshold); + pre_bw1 = BW_THRESHOLD_MAX; + pre_bw2 = BW_THRESHOLD_MAX; + cg_set_threshold(CG_DEFAULT_LPM, CG_DEFAULT_HPM); enable_fliper_polling(); break; @@ -379,15 +388,17 @@ static void mt_power_pef_transfer_work(void) cg_set_threshold(cg_lpm_bw_threshold, cg_hpm_bw_threshold); step = Y_steps; l_boost_flag = 1; + mt_ppm_sysboost_freq(BOOST_BY_PERFSERV, 1066000); } if (count > 26 && cg_lpm_bw_threshold >= MIN_DEFAULT_LPM) step = Y_steps; if (count <= 26) step--; - if (step <= 0) { + if (step <= 0 && l_boost_flag == 1) { cg_restore_threshold(); l_boost_flag = 0; + mt_ppm_sysboost_freq(BOOST_BY_PERFSERV, 0); } } /*--------------------INIT------------------------*/ diff --git a/drivers/misc/mediatek/sched/rq_stats.c b/drivers/misc/mediatek/sched/rq_stats.c index 43c486a8d5aa..e1647dd15517 100644..100755 --- a/drivers/misc/mediatek/sched/rq_stats.c +++ b/drivers/misc/mediatek/sched/rq_stats.c @@ -35,6 +35,8 @@ #define MAX_LONG_SIZE 24 #define DEFAULT_RQ_POLL_JIFFIES 1 #define DEFAULT_DEF_TIMER_JIFFIES 5 +#define HEAVY_TASK_ENABLE 1 + #ifdef CONFIG_SCHED_HMP_PRIO_FILTER static unsigned int heavy_task_prio = NICE_TO_PRIO(CONFIG_SCHED_HMP_PRIO_FILTER_VAL); #define task_low_priority(prio) ((prio >= heavy_task_prio)?1:0) @@ -50,7 +52,9 @@ static int cpufreq_variant = 1; /* set to 1 if per cpu load is cpu freq. variant struct notifier_block freq_transition; #endif /* CONFIG_CPU_FREQ */ struct notifier_block cpu_hotplug; -static unsigned int heavy_task_threshold = 650; /* max=1023 */ +static unsigned int heavy_task_threshold = 920; /* max=1023, for last_poll, threshold */ +static unsigned int heavy_task_threshold2 = 920; /* max=1023 for AHT, threshold */ +static unsigned int avg_heavy_task_threshold = 65; /* max=99 for AHT, admission control */ static int htask_cpucap_ctrl = 1; struct cpu_load_data { @@ -70,6 +74,16 @@ struct cpu_load_data { static DEFINE_PER_CPU(struct cpu_load_data, cpuload); static DEFINE_PER_CPU(struct cpufreq_policy, cpupolicy); +int get_avg_heavy_task_threshold(void) +{ + return avg_heavy_task_threshold; +} + +int get_heavy_task_threshold(void) +{ + return heavy_task_threshold; +} + #ifdef CONFIG_CPU_FREQ #include <linux/cpufreq.h> #else /* !CONFIG_CPU_FREQ */ @@ -342,6 +356,53 @@ static int ack_by_curcap(int cpu, int cluster_id, int max_cluster_id) return acked; } +int is_ack_curcap(int cpu) +{ + int cluster_id, cluster_nr; + + cluster_nr = arch_get_nr_clusters(); + cluster_id = arch_get_cluster_id(cpu); + + return ack_by_curcap(cpu, cluster_id, cluster_nr-1); +} +EXPORT_SYMBOL(is_ack_curcap); + +int is_heavy_task(struct task_struct *p) +{ + int is_heavy = 0; + + if (!HEAVY_TASK_ENABLE) + return 0; + + if (!p) + return 0; + +#ifdef CONFIG_SCHED_HMP_PRIO_FILTER + if (task_low_priority(p->prio)) + return 0; +#endif + + if (p->se.avg.loadwop_avg_contrib >= heavy_task_threshold2) + is_heavy = 1; + + return is_heavy; +} +EXPORT_SYMBOL(is_heavy_task); + +int inc_nr_heavy_running(const char *invoker, struct task_struct *p, int inc, bool ack_cap) +{ + if (is_heavy_task(p)) { +#ifdef CONFIG_MTK_SCHED_RQAVG_KS + sched_update_nr_heavy_prod(invoker, cpu_of(task_rq(p)), inc, ack_cap); + trace_sched_avg_heavy_task_load(p); +#endif + return inc; + } + + return 0; +} +EXPORT_SYMBOL(inc_nr_heavy_running); + static unsigned int htask_statistic; unsigned int sched_get_nr_heavy_task_by_threshold(int cluster_id, unsigned int threshold) { @@ -401,7 +462,21 @@ EXPORT_SYMBOL(sched_get_nr_heavy_task); unsigned int sched_get_nr_heavy_task2(int cluster_id) { - return sched_get_nr_heavy_task_by_threshold(cluster_id, heavy_task_threshold); + int lastpoll_htask1 = 0, lastpoll_htask2 = 0; + int avg_htask = 0, avg_htask_scal = 0; + int max; + + lastpoll_htask1 = sched_get_nr_heavy_task_by_threshold(cluster_id, heavy_task_threshold); +#ifdef CONFIG_MTK_SCHED_RQAVG_KS + lastpoll_htask2 = sched_get_nr_heavy_running_avg(cluster_id, &avg_htask_scal); +#endif + avg_htask = (avg_htask_scal%100 >= avg_heavy_task_threshold)?(avg_htask_scal/100+1):(avg_htask_scal/100); + + max = max(max(lastpoll_htask1, lastpoll_htask2), avg_htask); + + trace_sched_avg_heavy_task(lastpoll_htask1, lastpoll_htask2, avg_htask_scal, cluster_id, max); + + return max; } EXPORT_SYMBOL(sched_get_nr_heavy_task2); @@ -495,6 +570,7 @@ static int cpu_hotplug_handler(struct notifier_block *nb, spin_lock_irqsave(&this_cpu->cpu_load_lock, flags); update_average_load(0, cpu); spin_unlock_irqrestore(&this_cpu->cpu_load_lock, flags); + break; case CPU_ONLINE_FROZEN: case CPU_UP_PREPARE: @@ -502,6 +578,13 @@ static int cpu_hotplug_handler(struct notifier_block *nb, spin_lock_irqsave(&this_cpu->cpu_load_lock, flags); update_average_load(0, cpu); spin_unlock_irqrestore(&this_cpu->cpu_load_lock, flags); + +#ifdef CONFIG_MTK_SCHED_RQAVG_KS + /* clear per_cpu variables for heavy task if needed */ + if (val == CPU_UP_PREPARE) + WARN_ON(reset_heavy_task_stats(cpu)); +#endif + break; case CPU_DOWN_PREPARE: /* cpu_online()=1 here, flush previous load */ @@ -693,6 +776,23 @@ static ssize_t show_heavy_tasks(struct kobject *kobj, return len; } +static struct kobj_attribute htasks_attr = + __ATTR(htasks, S_IRUSR, show_heavy_tasks, + NULL); + +static ssize_t htask_cpucap_ctrl_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + unsigned int val = 0; + + if (0 != sscanf(buf, "%iu", &val)) + htask_cpucap_ctrl = (val == 0 ? 0 : 1); + + return count; +} +static struct kobj_attribute htask_cpucap_ctrl_attr = __ATTR_WO(htask_cpucap_ctrl); + +/* For read/write heavy_task_threshold */ static ssize_t store_heavy_task_threshold(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { @@ -700,25 +800,87 @@ static ssize_t store_heavy_task_threshold(struct kobject *kobj, if (0 != sscanf(buf, "%iu", &val)) sched_set_heavy_task_threshold(val); - return count; } -static struct kobj_attribute htasks_attr = - __ATTR(htasks, S_IWUSR | S_IRUSR, show_heavy_tasks, - store_heavy_task_threshold); +static ssize_t show_heavy_task_threshold(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + unsigned int len = 0; + unsigned int max_len = 4096; -static ssize_t htask_cpucap_ctrl_store(struct kobject *kobj, + len += snprintf(buf, max_len, "%d\n", heavy_task_threshold); + + return len; +} + +static struct kobj_attribute htasks_thresh_attr = +__ATTR(htasks_thresh, S_IWUSR | S_IRUSR, show_heavy_task_threshold, + store_heavy_task_threshold); + +/* For read/write admission control for average heavy task */ +static ssize_t store_avg_heavy_task_ac(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { unsigned int val = 0; - if (0 != sscanf(buf, "%iu", &val)) - htask_cpucap_ctrl = (val == 0 ? 0 : 1); + if (0 != sscanf(buf, "%iu", &val)) { + if (val >= 0 && val < 100) { + avg_heavy_task_threshold = val; +#ifdef CONFIG_MTK_SCHED_RQAVG_KS + heavy_thresh_chg_notify(); +#endif + } + } + return count; +} +static ssize_t show_avg_heavy_task_ac(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + unsigned int len = 0; + unsigned int max_len = 4096; + + len += snprintf(buf, max_len, "%d\n", avg_heavy_task_threshold); + + return len; +} + +static struct kobj_attribute avg_htasks_ac_attr = + __ATTR(avg_htasks_ac, S_IWUSR | S_IRUSR, show_avg_heavy_task_ac, + store_avg_heavy_task_ac); + +/* For read/write threshold for average heavy task */ +static ssize_t store_avg_heavy_task_thresh(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + unsigned int val = 0; + + if (0 != sscanf(buf, "%iu", &val)) { + if (val >= 0 && val < 1024) { + heavy_task_threshold2 = val; +#ifdef CONFIG_MTK_SCHED_RQAVG_KS + heavy_thresh_chg_notify(); +#endif + } + } return count; } -static struct kobj_attribute htask_cpucap_ctrl_attr = __ATTR_WO(htask_cpucap_ctrl); + +static ssize_t show_avg_heavy_task_thresh(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + unsigned int len = 0; + unsigned int max_len = 4096; + + len += snprintf(buf, max_len, "%d\n", heavy_task_threshold2); + + return len; +} + +static struct kobj_attribute avg_htasks_thresh_attr = +__ATTR(avg_htasks_thresh, S_IWUSR | S_IRUSR, show_avg_heavy_task_thresh, + store_avg_heavy_task_thresh); static struct attribute *rq_attrs[] = { &cpu_normalized_load_attr.attr, @@ -728,6 +890,9 @@ static struct attribute *rq_attrs[] = { &hotplug_disabled_attr.attr, &htasks_attr.attr, &htask_cpucap_ctrl_attr.attr, + &htasks_thresh_attr.attr, + &avg_htasks_thresh_attr.attr, + &avg_htasks_ac_attr.attr, NULL, }; diff --git a/drivers/misc/mediatek/sched/rq_stats.h b/drivers/misc/mediatek/sched/rq_stats.h index 0accf3889a63..ecf85fae7c66 100644..100755 --- a/drivers/misc/mediatek/sched/rq_stats.h +++ b/drivers/misc/mediatek/sched/rq_stats.h @@ -30,3 +30,11 @@ struct rq_data { extern spinlock_t rq_lock; extern struct rq_data rq_info; extern struct workqueue_struct *rq_wq; + +/* For heavy task detection */ +extern int sched_get_nr_heavy_running_avg(int cid, int *avg); +extern void sched_update_nr_heavy_prod(const char *invoker, int cpu, int heavy_nr_inc, bool ack_cap); +extern int reset_heavy_task_stats(int cpu); +extern int is_ack_curcap(int cpu); +extern int is_heavy_task(struct task_struct *p); +extern void heavy_thresh_chg_notify(void); /* need to invoke if any threshold of htasks changed */ diff --git a/drivers/misc/mediatek/sched/sched_avg.c b/drivers/misc/mediatek/sched/sched_avg.c index 04f3f51e2850..bd77f1936093 100644..100755 --- a/drivers/misc/mediatek/sched/sched_avg.c +++ b/drivers/misc/mediatek/sched/sched_avg.c @@ -18,24 +18,42 @@ #include <linux/hrtimer.h> #include <linux/sched.h> #include <linux/math64.h> +#include <trace/events/sched.h> +#ifdef CONFIG_MTK_SCHED_RQAVG_US +#include "rq_stats.h" +#endif static DEFINE_PER_CPU(u64, nr_prod_sum); +static DEFINE_PER_CPU(u64, nr_heavy_prod_sum); static DEFINE_PER_CPU(u64, last_time); +static DEFINE_PER_CPU(u64, last_heavy_time); static DEFINE_PER_CPU(u64, nr); +static DEFINE_PER_CPU(u64, nr_heavy); static DEFINE_PER_CPU(unsigned long, iowait_prod_sum); static DEFINE_PER_CPU(spinlock_t, nr_lock) = __SPIN_LOCK_UNLOCKED(nr_lock); +static DEFINE_PER_CPU(spinlock_t, nr_heavy_lock) = __SPIN_LOCK_UNLOCKED(nr_heavy_lock); static u64 last_get_time; +static int init_heavy; + +struct cluster_heavy_tbl_t { + u64 last_get_heavy_time; +}; + +struct cluster_heavy_tbl_t *cluster_heavy_tbl; + +static int init_heavy_tlb(void); /** * sched_get_nr_running_avg * @return: Average nr_running and iowait value since last poll. - * Returns the avg * 100 to return up to two decimal points - * of accuracy. + * Returns the avg * 100 to return up to two decimal points + * of accuracy. + * And return scaled tasks number of the last poll. * * Obtains the average nr_running value since the last poll. * This function may not be called concurrently with itself */ -void sched_get_nr_running_avg(int *avg, int *iowait_avg) +int sched_get_nr_running_avg(int *avg, int *iowait_avg) { int cpu; u64 curr_time = sched_clock(); @@ -43,12 +61,13 @@ void sched_get_nr_running_avg(int *avg, int *iowait_avg) u64 tmp_avg = 0, tmp_iowait = 0, old_lgt; bool clk_faulty = 0; u32 cpumask = 0; + int scaled_tlp = 0; /* the tasks number of last poll */ *avg = 0; *iowait_avg = 0; if (!diff) - return; + return 0; WARN(diff < 0, "[sched_get_nr_running_avg] time last:%llu curr:%llu ", last_get_time, curr_time); @@ -66,6 +85,7 @@ void sched_get_nr_running_avg(int *avg, int *iowait_avg) } /* ////// */ tmp_avg += per_cpu(nr_prod_sum, cpu); + scaled_tlp += per_cpu(nr, cpu); /* record tasks nr of last poll */ tmp_avg += per_cpu(nr, cpu) * (curr_time - per_cpu(last_time, cpu)); tmp_iowait = per_cpu(iowait_prod_sum, cpu); tmp_iowait += nr_iowait_cpu(cpu) * (curr_time - per_cpu(last_time, cpu)); @@ -80,7 +100,7 @@ void sched_get_nr_running_avg(int *avg, int *iowait_avg) *avg = 0; *iowait_avg = 0; pr_warn("[%s] **** CPU (0x%08x)clock may unstable !!\n", __func__, cpumask); - return; + return 0; } /* ///// */ @@ -95,9 +115,148 @@ void sched_get_nr_running_avg(int *avg, int *iowait_avg) *iowait_avg, tmp_iowait, diff, old_lgt, curr_time); if (unlikely(*iowait_avg < 0)) *iowait_avg = 0; + + return scaled_tlp*100; } EXPORT_SYMBOL(sched_get_nr_running_avg); +int reset_heavy_task_stats(int cpu) +{ + int nr_heavy_tasks; + unsigned long flags; + + spin_lock_irqsave(&per_cpu(nr_heavy_lock, cpu), flags); + nr_heavy_tasks = per_cpu(nr_heavy, cpu); + if (nr_heavy_tasks) { + pr_warn("[heavy_task] %s: nr_heavy_tasks=%d in cpu%d\n", __func__, + nr_heavy_tasks, cpu); + per_cpu(nr_heavy, cpu) = 0; + } + spin_unlock_irqrestore(&per_cpu(nr_heavy_lock, cpu), flags); + + return nr_heavy_tasks; +} +EXPORT_SYMBOL(reset_heavy_task_stats); + +void heavy_thresh_chg_notify(void) +{ + int nr_heavy_task; + int cpu; + unsigned long flags; + struct task_struct *p; + + for_each_online_cpu(cpu) { + u64 curr_time = sched_clock(); + + nr_heavy_task = 0; + + raw_spin_lock_irqsave(&cpu_rq(cpu)->lock, flags); + list_for_each_entry(p, &cpu_rq(cpu)->cfs_tasks, se.group_node) { +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (is_heavy_task(p)) + nr_heavy_task++; +#endif + } + + /* Threshold for heavy is changed. Need to reset stats */ + spin_lock(&per_cpu(nr_heavy_lock, cpu)); + per_cpu(nr_heavy_prod_sum, cpu) = 0; + per_cpu(nr_heavy, cpu) = nr_heavy_task; + per_cpu(last_heavy_time, cpu) = curr_time; + spin_unlock(&per_cpu(nr_heavy_lock, cpu)); + + raw_spin_unlock_irqrestore(&cpu_rq(cpu)->lock, flags); + } +} + + +int sched_get_nr_heavy_running_avg(int cluster_id, int *avg) +{ + u64 curr_time = sched_clock(); + s64 diff; + + u64 tmp_avg = 0, old_lgt; + u32 cpumask = 0; + bool clk_faulty = 0; + unsigned long flags; + int cpu = 0; + int cluster_nr; + struct cpumask cls_cpus; + int ack_cap = 0; + + u64 last_heavy_nr = 0; + + /* Need to make sure initialization done. */ + if (!init_heavy) { + *avg = 0; + return -1; + } + + /* cluster_id need reasonale. */ + cluster_nr = arch_get_nr_clusters(); + if (cluster_id < 0 || cluster_id >= cluster_nr) { + pr_warn("[%s] invalid cluster id %d\n", __func__, cluster_id); + return -1; + } + + /* Time diff can't be zero. */ + diff = (s64)(curr_time - cluster_heavy_tbl[cluster_id].last_get_heavy_time); + if (!diff) { + *avg = 0; + return -1; + } + old_lgt = cluster_heavy_tbl[cluster_id].last_get_heavy_time; + + arch_get_cluster_cpus(&cls_cpus, cluster_id); + cluster_heavy_tbl[cluster_id].last_get_heavy_time = curr_time; + + /* visit all cpus of this cluster */ + for_each_cpu_mask(cpu, cls_cpus) { + spin_lock_irqsave(&per_cpu(nr_heavy_lock, cpu), flags); + if ((s64) (curr_time - per_cpu(last_heavy_time, cpu) < 0)) { + clk_faulty = 1; + cpumask |= 1 << cpu; + } + + last_heavy_nr += per_cpu(nr_heavy, cpu); + + tmp_avg += per_cpu(nr_heavy_prod_sum, cpu); +#ifdef CONFIG_MTK_SCHED_RQAVG_US + ack_cap = is_ack_curcap(cpu); + if (ack_cap) + tmp_avg += per_cpu(nr_heavy, cpu) * (curr_time - per_cpu(last_heavy_time, cpu)); + + trace_sched_avg_heavy_nr("hps_main", per_cpu(nr_heavy, cpu), + (curr_time - per_cpu(last_heavy_time, cpu)), ack_cap, cpu); +#else + ack_cap = -1; + tmp_avg += per_cpu(nr_heavy, cpu) * (curr_time - per_cpu(last_heavy_time, cpu)); +#endif + per_cpu(last_heavy_time, cpu) = curr_time; + + /* clear prod_sum */ + per_cpu(nr_heavy_prod_sum, cpu) = 0; + + spin_unlock_irqrestore(&per_cpu(nr_heavy_lock, cpu), flags); + } + + if (clk_faulty) { + *avg = 0; + trace_sched_avg_heavy_time(-1, -1, cluster_id); + return -1; + } + + *avg = (int)div64_u64(tmp_avg * 100, (u64) diff); + + trace_sched_avg_heavy_time(diff, old_lgt, cluster_id); + + mt_sched_printf(sched_log, "[heavy_task] avg:%d(%llu/%llu), last:%llu curr:%llu, last_heavy:%llu cid%d, ack:%d", + *avg, tmp_avg, diff, old_lgt, curr_time, last_heavy_nr, cluster_id, ack_cap); + + return 0; +} +EXPORT_SYMBOL(sched_get_nr_heavy_running_avg); + /** * sched_update_nr_prod * @cpu: The core id of the nr running driver. @@ -130,6 +289,80 @@ void sched_update_nr_prod(int cpu, unsigned long nr_running, int inc) per_cpu(nr_prod_sum, cpu) += nr_running * diff; per_cpu(iowait_prod_sum, cpu) += nr_iowait_cpu(cpu) * diff; + spin_unlock_irqrestore(&per_cpu(nr_lock, cpu), flags); } EXPORT_SYMBOL(sched_update_nr_prod); + +void sched_update_nr_heavy_prod(const char *invoker, int cpu, int heavy_nr_inc, bool ack_cap_req) +{ + s64 diff; + u64 curr_time; + unsigned long flags; + unsigned long prev_heavy_nr; + int ack_cap = -1; + + if (!init_heavy) { + init_heavy_tlb(); + BUG_ON(!init_heavy); + } + + spin_lock_irqsave(&per_cpu(nr_heavy_lock, cpu), flags); + curr_time = sched_clock(); + diff = (s64) (curr_time - per_cpu(last_heavy_time, cpu)); + /* skip this problematic clock violation */ + if (diff < 0) { + spin_unlock_irqrestore(&per_cpu(nr_heavy_lock, cpu), flags); + return; + } + + /* for heavy task avg */ + per_cpu(last_heavy_time, cpu) = curr_time; + prev_heavy_nr = per_cpu(nr_heavy, cpu); + per_cpu(nr_heavy, cpu) = prev_heavy_nr + heavy_nr_inc; + BUG_ON(per_cpu(nr_heavy, cpu) < 0); + + /* for current opp control */ +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (ack_cap_req) { + ack_cap = is_ack_curcap(cpu); + per_cpu(nr_heavy_prod_sum, cpu) += prev_heavy_nr*diff*ack_cap; + trace_sched_avg_heavy_nr(invoker, prev_heavy_nr, diff, ack_cap, cpu); + } else { + ack_cap = -1; + per_cpu(nr_heavy_prod_sum, cpu) += prev_heavy_nr*diff; + trace_sched_avg_heavy_nr(invoker, prev_heavy_nr, diff, ack_cap, cpu); + } +#else + ack_cap = -1; + per_cpu(nr_heavy_prod_sum, cpu) += prev_heavy_nr*diff; +#endif + + mt_sched_printf(sched_log, "[heavy_task] %s: nr_heavy:(%ld), diff:(%llu) for cpu:%d, ack_cap:%d", + __func__, (long)per_cpu(nr_heavy, cpu), diff, cpu, ack_cap); + + spin_unlock_irqrestore(&per_cpu(nr_heavy_lock, cpu), flags); +} +EXPORT_SYMBOL(sched_update_nr_heavy_prod); + +static int init_heavy_tlb(void) +{ + if (!init_heavy) { + /* init variables */ + int tmp_cpu, cluster_nr; + + pr_info("%s start.\n", __func__); + + for_each_possible_cpu(tmp_cpu) { + per_cpu(nr_heavy, tmp_cpu) = 0; + } + + cluster_nr = arch_get_nr_clusters(); + cluster_heavy_tbl = kcalloc(cluster_nr, sizeof(struct cluster_heavy_tbl_t), GFP_ATOMIC); + if (!cluster_heavy_tbl) + return 0; + init_heavy = 1; + } + + return init_heavy; +} diff --git a/drivers/misc/mediatek/video/include/disp_session.h b/drivers/misc/mediatek/video/include/disp_session.h index dff4a8a9a6fb..108d901ffa68 100644..100755 --- a/drivers/misc/mediatek/video/include/disp_session.h +++ b/drivers/misc/mediatek/video/include/disp_session.h @@ -310,8 +310,10 @@ typedef struct disp_session_info_t { unsigned int displayFormat; DISP_IF_MODE displayMode; unsigned int vsyncFPS; - unsigned int physicalWidth; - unsigned int physicalHeight; + unsigned int physicalWidth; /* length: mm, for legacy use */ + unsigned int physicalHeight; /* length: mm, for legacy use */ + unsigned int physicalWidthUm; /* length: um, for more precise precision */ + unsigned int physicalHeightUm; /* length: um, for more precise precision */ unsigned int isConnected; unsigned int isHDCPSupported; unsigned int isOVLDisabled; @@ -370,6 +372,7 @@ typedef enum { DISP_FEATURE_TIME_SHARING = 0x00000001, DISP_FEATURE_HRT = 0x00000002, DISP_FEATURE_PARTIAL = 0x00000004, + DISP_FEATURE_NO_LCM = 0x10000000, } DISP_FEATURE; typedef struct disp_caps_t { diff --git a/drivers/misc/mediatek/video/include/disp_svp.h b/drivers/misc/mediatek/video/include/disp_svp.h index 65d7dbf8ae7d..d81c89584ecc 100644..100755 --- a/drivers/misc/mediatek/video/include/disp_svp.h +++ b/drivers/misc/mediatek/video/include/disp_svp.h @@ -235,8 +235,10 @@ typedef struct disp_session_info_t { unsigned int displayFormat; DISP_IF_MODE displayMode; unsigned int vsyncFPS; - unsigned int physicalWidth; - unsigned int physicalHeight; + unsigned int physicalWidth; /* length: mm, for legacy use */ + unsigned int physicalHeight; /* length: mm, for legacy use */ + unsigned int physicalWidthUm; /* length: um, for more precise precision */ + unsigned int physicalHeightUm; /* length: um, for more precise precision */ unsigned int isConnected; } disp_session_info; diff --git a/drivers/misc/mediatek/video/include/mtkfb.h b/drivers/misc/mediatek/video/include/mtkfb.h index 25acba1ffb4e..14c44937e60a 100644..100755 --- a/drivers/misc/mediatek/video/include/mtkfb.h +++ b/drivers/misc/mediatek/video/include/mtkfb.h @@ -376,6 +376,9 @@ extern long hdmi_handle_cmd(unsigned int cmd, unsigned long arg); #if defined(CONFIG_ARCH_MT6797) extern unsigned int vramsize; +#ifdef CONFIG_OF +extern unsigned int islcmconnected; +#endif #endif #if defined(CONFIG_ARCH_MT6735) || defined(CONFIG_ARCH_MT6735M) || defined(CONFIG_ARCH_MT6753) diff --git a/drivers/misc/mediatek/video/mt6797/dispsys/ddp_manager.c b/drivers/misc/mediatek/video/mt6797/dispsys/ddp_manager.c index cb20a96fe733..b59c067ceb84 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/dispsys/ddp_manager.c +++ b/drivers/misc/mediatek/video/mt6797/dispsys/ddp_manager.c @@ -1716,7 +1716,7 @@ int dpmgr_wait_event_timeout(disp_path_handle dp_handle, DISP_PATH_EVENT event, wq_handle = &handle->wq_list[event]; if (wq_handle->init) { - cur_time = sched_clock(); + cur_time = ktime_to_ns(ktime_get()); ret = wait_event_interruptible_timeout(wq_handle->wq, cur_time < wq_handle->data, timeout); @@ -1757,7 +1757,7 @@ int _dpmgr_wait_event(disp_path_handle dp_handle, DISP_PATH_EVENT event, unsigne return -2; } - cur_time = sched_clock(); + cur_time = ktime_to_ns(ktime_get()); ret = wait_event_interruptible(wq_handle->wq, cur_time < wq_handle->data); if (ret < 0) { @@ -1791,7 +1791,7 @@ int dpmgr_signal_event(disp_path_handle dp_handle, DISP_PATH_EVENT event) wq_handle = &handle->wq_list[event]; if (handle->wq_list[event].init) { - wq_handle->data = sched_clock(); + wq_handle->data = ktime_to_ns(ktime_get()); wake_up_interruptible(&(handle->wq_list[event].wq)); } return 0; @@ -1818,7 +1818,7 @@ static void dpmgr_irq_handler(DISP_MODULE_ENUM module, unsigned int regvalue) if (handle->wq_list[j].init && irq_bit == handle->irq_event_map[j].irq_bit) { dprec_stub_event(j); - handle->wq_list[j].data = sched_clock(); + handle->wq_list[j].data = ktime_to_ns(ktime_get()); DDPIRQ("irq signal event %s on cycle %llu on scenario %s\n", path_event_name(j), handle->wq_list[j].data, diff --git a/drivers/misc/mediatek/video/mt6797/dispsys/ddp_path.c b/drivers/misc/mediatek/video/mt6797/dispsys/ddp_path.c index 2299d4722785..aedde083f9cc 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/dispsys/ddp_path.c +++ b/drivers/misc/mediatek/video/mt6797/dispsys/ddp_path.c @@ -1211,6 +1211,12 @@ int ddp_path_top_clock_on(void) ddp_clk_prepare_enable(DISP0_SMI_LARB5); } else { need_enable = 1; + if (!islcmconnected) { + ddp_clk_prepare_enable(DISP_MTCMOS_CLK); + ddp_clk_prepare_enable(DISP0_SMI_COMMON); + ddp_clk_prepare_enable(DISP0_SMI_LARB0); + ddp_clk_prepare_enable(DISP0_SMI_LARB5); + } if (disp_helper_get_option(DISP_OPT_DYNAMIC_SWITCH_MMSYSCLK)) ;/*ddp_clk_prepare_enable(MM_VENCPLL);*/ } diff --git a/drivers/misc/mediatek/video/mt6797/videox/disp_lcm.c b/drivers/misc/mediatek/video/mt6797/videox/disp_lcm.c index 0eaa2c512566..c1ab3f5a75b6 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/videox/disp_lcm.c +++ b/drivers/misc/mediatek/video/mt6797/videox/disp_lcm.c @@ -443,6 +443,8 @@ void parse_lcm_params_dt_node(struct device_node *np, LCM_PARAMS *lcm_params) disp_of_getprop_u32(np, "lcm_params-dsi-vertical_vfp_lp", &lcm_params->dsi.vertical_vfp_lp); disp_of_getprop_u32(np, "lcm_params-physical_width", &lcm_params->physical_width); disp_of_getprop_u32(np, "lcm_params-physical_height", &lcm_params->physical_height); + disp_of_getprop_u32(np, "lcm_params-physical_width_um", &lcm_params->physical_width_um); + disp_of_getprop_u32(np, "lcm_params-physical_height_um", &lcm_params->physical_height_um); disp_of_getprop_u32(np, "lcm_params-od_table_size", &lcm_params->od_table_size); disp_of_getprop_u32(np, "lcm_params-od_table", (u32 *) (&lcm_params->od_table)); } diff --git a/drivers/misc/mediatek/video/mt6797/videox/mtk_disp_mgr.c b/drivers/misc/mediatek/video/mt6797/videox/mtk_disp_mgr.c index 960b08d00ef5..98fa638e7fd6 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/videox/mtk_disp_mgr.c +++ b/drivers/misc/mediatek/video/mt6797/videox/mtk_disp_mgr.c @@ -72,6 +72,7 @@ #include "ddp_mmp.h" #include "mtkfb_fence.h" #include "extd_multi_control.h" +#include "external_display.h" #include "m4u.h" #include "mtk_hrt.h" #include "compat_mtk_disp_mgr.h" @@ -159,7 +160,11 @@ int disp_create_session(disp_session_config *config) int ret = 0; int is_session_inited = 0; unsigned int session = MAKE_DISP_SESSION(config->type, config->device_id); + unsigned int mem_session = MAKE_DISP_SESSION(DISP_SESSION_MEMORY, DEV_WFD); int i, idx = -1; + + if ((!is_lcm_connected()) && (session == mem_session)) + return -1; /* 1.To check if this session exists already */ mutex_lock(&disp_session_lock); for (i = 0; i < MAX_SESSION_COUNT; i++) { @@ -1322,6 +1327,9 @@ int _ioctl_get_display_caps(unsigned long arg) if (disp_helper_get_option(DISP_OPT_HRT)) caps_info.disp_feature |= DISP_FEATURE_HRT; + if (!islcmconnected) + caps_info.disp_feature |= DISP_FEATURE_NO_LCM; + DISPDBG("%s mode:%d, pass:%d, max_layer_num:%d\n", __func__, caps_info.output_mode, caps_info.output_pass, caps_info.max_layer_num); @@ -1390,7 +1398,35 @@ int _ioctl_query_valid_layer(unsigned long arg) ret = -EFAULT; } - ret = dispsys_hrt_calc(&disp_info_user); + if (is_lcm_connected()) + ret = dispsys_hrt_calc(&disp_info_user); + else { + disp_info_user.disp_mode[1] = disp_info_user.disp_mode[0]; + disp_info_user.layer_num[1] = disp_info_user.layer_num[0]; + disp_info_user.gles_head[1] = disp_info_user.gles_head[0]; + disp_info_user.gles_tail[1] = disp_info_user.gles_tail[0]; + disp_info_user.input_config[1] = disp_info_user.input_config[0]; + + disp_info_user.disp_mode[0] = 0; + disp_info_user.layer_num[0] = 0; + disp_info_user.gles_head[0] = 0; + disp_info_user.gles_tail[0] = 0; + disp_info_user.input_config[0] = NULL; + + ret = dispsys_hrt_calc(&disp_info_user); + + disp_info_user.disp_mode[0] = disp_info_user.disp_mode[1]; + disp_info_user.layer_num[0] = disp_info_user.layer_num[1]; + disp_info_user.gles_head[0] = disp_info_user.gles_head[1]; + disp_info_user.gles_tail[0] = disp_info_user.gles_tail[1]; + disp_info_user.input_config[0] = disp_info_user.input_config[1]; + + disp_info_user.disp_mode[1] = 0; + disp_info_user.layer_num[1] = 0; + disp_info_user.gles_head[1] = 0; + disp_info_user.gles_tail[1] = 0; + disp_info_user.input_config[1] = NULL; + } if (copy_to_user(argp, &disp_info_user, sizeof(disp_info_user))) { DISPERR("[FB]: copy_to_user failed! line:%d\n", __LINE__); diff --git a/drivers/misc/mediatek/video/mt6797/videox/mtkfb.c b/drivers/misc/mediatek/video/mt6797/videox/mtkfb.c index 4a2de6f56f6e..a814354fb04d 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/videox/mtkfb.c +++ b/drivers/misc/mediatek/video/mt6797/videox/mtkfb.c @@ -270,6 +270,8 @@ exit: #if defined(CONFIG_PM_AUTOSLEEP) static int mtkfb_blank(int blank_mode, struct fb_info *info) { + if (!islcmconnected) + return 0; switch (blank_mode) { case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: @@ -1823,6 +1825,8 @@ static int mtkfb_fbinfo_init(struct fb_info *info) DISPFUNC(); BUG_ON(!fbdev->fb_va_base); + if (!islcmconnected) + mtkfb_ops.fb_blank = NULL; info->fbops = &mtkfb_ops; info->flags = FBINFO_FLAG_DEFAULT; info->screen_base = (char *)fbdev->fb_va_base; diff --git a/drivers/misc/mediatek/video/mt6797/videox/primary_display.c b/drivers/misc/mediatek/video/mt6797/videox/primary_display.c index c820caa0c5ed..3caad71068a8 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/videox/primary_display.c +++ b/drivers/misc/mediatek/video/mt6797/videox/primary_display.c @@ -5452,6 +5452,8 @@ int primary_display_get_info(disp_session_info *info) dispif_info->physicalWidth = DISP_GetActiveWidth(); dispif_info->physicalHeight = DISP_GetActiveHeight(); + dispif_info->physicalWidthUm = DISP_GetActiveWidthUm(); + dispif_info->physicalHeightUm = DISP_GetActiveHeightUm(); dispif_info->vsyncFPS = pgc->lcm_fps; @@ -5905,6 +5907,34 @@ UINT32 DISP_GetActiveWidth(void) return 0; } +uint32_t DISP_GetActiveHeightUm(void) +{ + if (pgc->plcm == NULL) { + DISPERR("lcm handle is null\n"); + return 0; + } + + if (pgc->plcm->params) + return pgc->plcm->params->physical_height_um; + + DISPERR("lcm_params is null!\n"); + return 0; +} + +uint32_t DISP_GetActiveWidthUm(void) +{ + if (pgc->plcm == NULL) { + DISPERR("lcm handle is null\n"); + return 0; + } + + if (pgc->plcm->params) + return pgc->plcm->params->physical_width_um; + + DISPERR("lcm_params is null!\n"); + return 0; +} + LCM_PARAMS *DISP_GetLcmPara(void) { if (pgc->plcm == NULL) { diff --git a/drivers/misc/mediatek/video/mt6797/videox/primary_display.h b/drivers/misc/mediatek/video/mt6797/videox/primary_display.h index 847d5df8dd23..d3777d65bb11 100644..100755 --- a/drivers/misc/mediatek/video/mt6797/videox/primary_display.h +++ b/drivers/misc/mediatek/video/mt6797/videox/primary_display.h @@ -292,6 +292,8 @@ UINT32 DISP_GetScreenWidth(void); UINT32 DISP_GetScreenHeight(void); UINT32 DISP_GetActiveHeight(void); UINT32 DISP_GetActiveWidth(void); +UINT32 DISP_GetActiveHeightUm(void); +UINT32 DISP_GetActiveWidthUm(void); unsigned long get_dim_layer_mva_addr(void); int disp_hal_allocate_framebuffer(phys_addr_t pa_start, phys_addr_t pa_end, unsigned long *va, unsigned long *mva); diff --git a/include/dt-bindings/lcm/hx8392a_dsi_cmd.dtsi b/include/dt-bindings/lcm/hx8392a_dsi_cmd.dtsi index dcd319c867dc..a93d6540ad08 100644..100755 --- a/include/dt-bindings/lcm/hx8392a_dsi_cmd.dtsi +++ b/include/dt-bindings/lcm/hx8392a_dsi_cmd.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/hx8392a_dsi_cmd_fwvga.dtsi b/include/dt-bindings/lcm/hx8392a_dsi_cmd_fwvga.dtsi index 68a6e129e212..0c9cf92a05fe 100644..100755 --- a/include/dt-bindings/lcm/hx8392a_dsi_cmd_fwvga.dtsi +++ b/include/dt-bindings/lcm/hx8392a_dsi_cmd_fwvga.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/hx8392a_vdo_cmd.dtsi b/include/dt-bindings/lcm/hx8392a_vdo_cmd.dtsi index fa574e309d74..08d794780c34 100644..100755 --- a/include/dt-bindings/lcm/hx8392a_vdo_cmd.dtsi +++ b/include/dt-bindings/lcm/hx8392a_vdo_cmd.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/otm9608_qhd_dsi_cmd.dtsi b/include/dt-bindings/lcm/otm9608_qhd_dsi_cmd.dtsi index de5b5b9944fb..975467f0b54f 100644..100755 --- a/include/dt-bindings/lcm/otm9608_qhd_dsi_cmd.dtsi +++ b/include/dt-bindings/lcm/otm9608_qhd_dsi_cmd.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/otm9608_qhd_dsi_vdo.dtsi b/include/dt-bindings/lcm/otm9608_qhd_dsi_vdo.dtsi index 9ed4f350be1c..020bb5bc3139 100644..100755 --- a/include/dt-bindings/lcm/otm9608_qhd_dsi_vdo.dtsi +++ b/include/dt-bindings/lcm/otm9608_qhd_dsi_vdo.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi b/include/dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi index 2e7e5608387d..97f275247c8d 100644..100755 --- a/include/dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi +++ b/include/dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi @@ -183,6 +183,8 @@ lcm_params-dsi-vertical_vfp_lp; lcm_params-physical_width; lcm_params-physical_height; + lcm_params-physical_width_um; + lcm_params-physical_height_um; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/dt-bindings/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.dtsi b/include/dt-bindings/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.dtsi index 0307e3e1ae40..c5963a9ac3c5 100644..100755 --- a/include/dt-bindings/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.dtsi +++ b/include/dt-bindings/lcm/r63419_wqhd_truly_phantom_2k_cmd_ok_mt6797.dtsi @@ -183,8 +183,10 @@ lcm_params-dsi-lane_swap1 = <2 4 3 1 0 4>; /* lane_swap[1][0~5] */ lcm_params-dsi-vertical_vfp_lp; - lcm_params-physical_width = <74520>; - lcm_params-physical_height = <132480>; + lcm_params-physical_width = <74>; + lcm_params-physical_height = <132>; + lcm_params-physical_width_um = <74520>; + lcm_params-physical_height_um = <132480>; lcm_params-od_table_size; lcm_params-od_table; }; diff --git a/include/linux/mm.h b/include/linux/mm.h index 710fbc8838c3..710fbc8838c3 100644..100755 --- a/include/linux/mm.h +++ b/include/linux/mm.h diff --git a/include/linux/random.h b/include/linux/random.h index 0fe49a14daa5..0fe49a14daa5 100644..100755 --- a/include/linux/random.h +++ b/include/linux/random.h diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h index 82be33c03637..7f28bdf9072b 100644..100755 --- a/include/trace/events/sched.h +++ b/include/trace/events/sched.h @@ -1344,6 +1344,111 @@ TRACE_EVENT(sched_heavy_task, ), TP_printk("%s", __get_str(s)) ); + +/* + * Tracepoint for average heavy task calculation. + */ +TRACE_EVENT(sched_avg_heavy_task, + + TP_PROTO(int last_poll1, int last_poll2, int avg, int cluster_id, int max), + + TP_ARGS(last_poll1, last_poll2, avg, cluster_id, max), + + TP_STRUCT__entry( + __field(int, last_poll1) + __field(int, last_poll2) + __field(int, avg) + __field(int, cid) + __field(int, max) + ), + + TP_fast_assign( + __entry->last_poll1 = last_poll1; + __entry->last_poll2 = last_poll2; + __entry->avg = avg; + __entry->cid = cluster_id; + __entry->max = max; + ), + + TP_printk("last_poll1=%d last_poll2=%d, avg=%d, max:%d, cid:%d", + __entry->last_poll1, + __entry->last_poll2, + __entry->avg, + __entry->max, + __entry->cid) +); + +TRACE_EVENT(sched_avg_heavy_nr, + TP_PROTO(const char *func_name, int nr_heavy, long long int diff, int ack_cap, int cpu), + + TP_ARGS(func_name, nr_heavy, diff, ack_cap, cpu), + + TP_STRUCT__entry( + __array(char, func_name, 32) + __field(int, nr_heavy) + __field(long long int, diff) + __field(int, ack_cap) + __field(int, cpu) + ), + + TP_fast_assign( + memcpy(__entry->func_name, func_name, 32); + __entry->nr_heavy = nr_heavy; + __entry->diff = diff; + __entry->ack_cap = ack_cap; + __entry->cpu = cpu; + ), + + TP_printk("%s nr_heavy=%d time diff:%lld ack_cap:%d cpu:%d", + __entry->func_name, + __entry->nr_heavy, __entry->diff, __entry->ack_cap, __entry->cpu + ) +); + +TRACE_EVENT(sched_avg_heavy_time, + TP_PROTO(long long int time_period, long long int last_get_heavy_time, int cid), + + TP_ARGS(time_period, last_get_heavy_time, cid), + + TP_STRUCT__entry( + __field(long long int, time_period) + __field(long long int, last_get_heavy_time) + __field(int, cid) + ), + + TP_fast_assign( + __entry->time_period = time_period; + __entry->last_get_heavy_time = last_get_heavy_time; + __entry->cid = cid; + ), + + TP_printk("time_period:%lld last_get_heavy_time:%lld cid:%d", + __entry->time_period, __entry->last_get_heavy_time, __entry->cid + ) +) + +TRACE_EVENT(sched_avg_heavy_task_load, + TP_PROTO(struct task_struct *t), + + TP_ARGS(t), + + TP_STRUCT__entry( + __array(char, comm, TASK_COMM_LEN) + __field(pid_t, pid) + __field(long long int, load) + ), + + TP_fast_assign( + memcpy(__entry->comm, t->comm, TASK_COMM_LEN); + __entry->pid = t->pid; + __entry->load = t->se.avg.loadwop_avg_contrib; + ), + + TP_printk("heavy_task_detect comm:%s pid:%d load:%lld", + __entry->comm, __entry->pid, __entry->load + ) +) + #endif /* _TRACE_SCHED_H */ /* This part must be outside protection */ diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig index cc02862c95ce..86c93bef3cfe 100644..100755 --- a/kernel/power/Kconfig +++ b/kernel/power/Kconfig @@ -100,299 +100,6 @@ config PM_STD_PARTITION suspended image to. It will simply pick the first available swap device. -menuconfig TOI_CORE - tristate "Enhanced Hibernation (TuxOnIce)" - depends on HIBERNATION - default n - ---help--- - TuxOnIce is the 'new and improved' suspend support. - - See the TuxOnIce home page (tuxonice.net) - for FAQs, HOWTOs and other documentation. - - comment "Image Storage (you need at least one allocator)" - depends on TOI_CORE - - config TOI_FILE - tristate "File Allocator" - depends on TOI_CORE - default y - ---help--- - This option enables support for storing an image in a - simple file. You might want this if your swap is - sometimes full enough that you don't have enough spare - space to store an image. - - config TOI_SWAP - tristate "Swap Allocator" - depends on TOI_CORE && SWAP - default y - ---help--- - This option enables support for storing an image in your - swap space. - - comment "General Options" - depends on TOI_CORE - - config TOI_PRUNE - tristate "Image pruning support" - depends on TOI_CORE && CRYPTO && BROKEN - default y - ---help--- - This option adds support for using cryptoapi hashing - algorithms to identify pages with the same content. We - then write a much smaller pointer to the first copy of - the data instead of a complete (perhaps compressed) - additional copy. - - You probably want this, so say Y here. - - comment "No image pruning support available without Cryptoapi support." - depends on TOI_CORE && !CRYPTO - - config TOI_CRYPTO - tristate "Compression support" - depends on TOI_CORE && CRYPTO - default y - ---help--- - This option adds support for using cryptoapi compression - algorithms. Compression is particularly useful as it can - more than double your suspend and resume speed (depending - upon how well your image compresses). - - You probably want this, so say Y here. - - comment "No compression support available without Cryptoapi support." - depends on TOI_CORE && !CRYPTO - - config TOI_USERUI - tristate "Userspace User Interface support" - depends on TOI_CORE && NET && (VT || SERIAL_CONSOLE) - default y - ---help--- - This option enabled support for a userspace based user interface - to TuxOnIce, which allows you to have a nice display while suspending - and resuming, and also enables features such as pressing escape to - cancel a cycle or interactive debugging. - - config TOI_USERUI_DEFAULT_PATH - string "Default userui program location" - default "/usr/local/sbin/tuxoniceui_text" - depends on TOI_USERUI - ---help--- - This entry allows you to specify a default path to the userui binary. - - config TOI_DEFAULT_IMAGE_SIZE_LIMIT - int "Default image size limit" - range -2 65536 - default "-2" - depends on TOI_CORE - ---help--- - This entry allows you to specify a default image size limit. It can - be overridden at run-time using /sys/power/tuxonice/image_size_limit. - - config TOI_KEEP_IMAGE - bool "Allow Keep Image Mode" - depends on TOI_CORE - ---help--- - This option allows you to keep and image and reuse it. It is intended - __ONLY__ for use with systems where all filesystems are mounted read- - only (kiosks, for example). To use it, compile this option in and boot - normally. Set the KEEP_IMAGE flag in /sys/power/tuxonice and suspend. - When you resume, the image will not be removed. You will be unable to turn - off swap partitions (assuming you are using the swap allocator), but future - suspends simply do a power-down. The image can be updated using the - kernel command line parameter suspend_act= to turn off the keep image - bit. Keep image mode is a little less user friendly on purpose - it - should not be used without thought! - - config TOI_INCREMENTAL - bool "Incremental Image Support" - depends on TOI_CORE && 64BIT - default n - ---help--- - This option enables the work in progress toward using the dirty page - tracking to record changes to pages. It is hoped that - this will be an initial step toward implementing storing just - the differences between consecutive images, which will - increase the amount of storage needed for the image, but also - increase the speed at which writing an image occurs and - reduce the wear and tear on drives. - - At the moment, all that is implemented is the first step of keeping - an existing image and then comparing it to the contents in memory - (by setting /sys/power/tuxonice/verify_image to 1 and triggering a - (fake) resume) to see what the page change tracking should find to be - different. If you have verify_image set to 1, TuxOnIce will automatically - invalidate the old image when you next try to hibernate, so there's no - greater chance of disk corruption than normal. - - comment "No incremental image support available without Keep Image support." - depends on TOI_CORE && !TOI_KEEP_IMAGE - - config TOI_REPLACE_SWSUSP - bool "Replace swsusp by default" - default y - depends on TOI_CORE - ---help--- - TuxOnIce can replace swsusp. This option makes that the default state, - requiring you to echo 0 > /sys/power/tuxonice/replace_swsusp if you want - to use the vanilla kernel functionality. Note that your initrd/ramfs will - need to do this before trying to resume, too. - With overriding swsusp enabled, echoing disk to /sys/power/state will - start a TuxOnIce cycle. If resume= doesn't specify an allocator and both - the swap and file allocators are compiled in, the swap allocator will be - used by default. - - config TOI_IGNORE_LATE_INITCALL - bool "Wait for initrd/ramfs to run, by default" - default n - depends on TOI_CORE - ---help--- - When booting, TuxOnIce can check for an image and start to resume prior - to any initrd/ramfs running (via a late initcall). - - If you don't have an initrd/ramfs, this is what you want to happen - - otherwise you won't be able to safely resume. You should set this option - to 'No'. - - If, however, you want your initrd/ramfs to run anyway before resuming, - you need to tell TuxOnIce to ignore that earlier opportunity to resume. - This can be done either by using this compile time option, or by - overriding this option with the boot-time parameter toi_initramfs_resume_only=1. - - Note that if TuxOnIce can't resume at the earlier opportunity, the - value of this option won't matter - the initramfs/initrd (if any) will - run anyway. - - menuconfig TOI_CLUSTER - tristate "Cluster support" - default n - depends on TOI_CORE && NET && BROKEN - ---help--- - Support for linking multiple machines in a cluster so that they suspend - and resume together. - - config TOI_DEFAULT_CLUSTER_INTERFACE - string "Default cluster interface" - depends on TOI_CLUSTER - ---help--- - The default interface on which to communicate with other nodes in - the cluster. - - If no value is set here, cluster support will be disabled by default. - - config TOI_DEFAULT_CLUSTER_KEY - string "Default cluster key" - default "Default" - depends on TOI_CLUSTER - ---help--- - The default key used by this node. All nodes in the same cluster - have the same key. Multiple clusters may coexist on the same lan - by using different values for this key. - - config TOI_CLUSTER_IMAGE_TIMEOUT - int "Timeout when checking for image" - default 15 - depends on TOI_CLUSTER - ---help--- - Timeout (seconds) before continuing to boot when waiting to see - whether other nodes might have an image. Set to -1 to wait - indefinitely. In WAIT_UNTIL_NODES is non zero, we might continue - booting sooner than this timeout. - - config TOI_CLUSTER_WAIT_UNTIL_NODES - int "Nodes without image before continuing" - default 0 - depends on TOI_CLUSTER - ---help--- - When booting and no image is found, we wait to see if other nodes - have an image before continuing to boot. This value lets us - continue after seeing a certain number of nodes without an image, - instead of continuing to wait for the timeout. Set to 0 to only - use the timeout. - - config TOI_DEFAULT_CLUSTER_PRE_HIBERNATE - string "Default pre-hibernate script" - depends on TOI_CLUSTER - ---help--- - The default script to be called when starting to hibernate. - - config TOI_DEFAULT_CLUSTER_POST_HIBERNATE - string "Default post-hibernate script" - depends on TOI_CLUSTER - ---help--- - The default script to be called after resuming from hibernation. - - config TOI_DEFAULT_WAIT - int "Default waiting time for emergency boot messages" - default "25" - range -1 32768 - depends on TOI_CORE - help - TuxOnIce can display warnings very early in the process of resuming, - if (for example) it appears that you have booted a kernel that doesn't - match an image on disk. It can then give you the opportunity to either - continue booting that kernel, or reboot the machine. This option can be - used to control how long to wait in such circumstances. -1 means wait - forever. 0 means don't wait at all (do the default action, which will - generally be to continue booting and remove the image). Values of 1 or - more indicate a number of seconds (up to 255) to wait before doing the - default. - - config TOI_DEFAULT_EXTRA_PAGES_ALLOWANCE - int "Default extra pages allowance" - default "2000" - range 500 32768 - depends on TOI_CORE - help - This value controls the default for the allowance TuxOnIce makes for - drivers to allocate extra memory during the atomic copy. The default - value of 2000 will be okay in most cases. If you are using - DRI, the easiest way to find what value to use is to try to hibernate - and look at how many pages were actually needed in the sysfs entry - /sys/power/tuxonice/debug_info (first number on the last line), adding - a little extra because the value is not always the same. - - config TOI_CHECKSUM - bool "Checksum pageset2" - default n - depends on TOI_CORE - select CRYPTO - select CRYPTO_ALGAPI - select CRYPTO_MD4 - ---help--- - Adds support for checksumming pageset2 pages, to ensure you really get an - atomic copy. Since some filesystems (XFS especially) change metadata even - when there's no other activity, we need this to check for pages that have - been changed while we were saving the page cache. If your debugging output - always says no pages were resaved, you may be able to safely disable this - option. - -config TOI - bool - depends on TOI_CORE!=n - default y - -config TOI_EXPORTS - bool - depends on TOI_SWAP=m || TOI_FILE=m || \ - TOI_CRYPTO=m || TOI_CLUSTER=m || \ - TOI_USERUI=m || TOI_CORE=m - default y - -config TOI_ZRAM_SUPPORT - def_bool y - depends on TOI && ZRAM!=n - -config TOI_FIXUP - def_bool y - depends on TOI - -config TOI_ENHANCE - def_bool y - depends on TOI - config PM_SLEEP def_bool y depends on SUSPEND || HIBERNATE_CALLBACKS diff --git a/kernel/power/Makefile b/kernel/power/Makefile index af5e6e48749a..74c713ba61b0 100644..100755 --- a/kernel/power/Makefile +++ b/kernel/power/Makefile @@ -1,37 +1,6 @@ ccflags-$(CONFIG_PM_DEBUG) := -DDEBUG -tuxonice_core-y := tuxonice_modules.o - -obj-$(CONFIG_TOI) += tuxonice_builtin.o - -tuxonice_core-$(CONFIG_PM_DEBUG) += tuxonice_alloc.o - -# Compile these in after allocation debugging, if used. - -tuxonice_core-y += tuxonice_sysfs.o tuxonice_highlevel.o \ - tuxonice_io.o tuxonice_pagedir.o tuxonice_prepare_image.o \ - tuxonice_extent.o tuxonice_pageflags.o tuxonice_ui.o \ - tuxonice_power_off.o tuxonice_atomic_copy.o - -tuxonice_core-$(CONFIG_TOI_CHECKSUM) += tuxonice_checksum.o - -tuxonice_core-$(CONFIG_NET) += tuxonice_storage.o tuxonice_netlink.o - -obj-$(CONFIG_TOI_CORE) += tuxonice_core.o -obj-$(CONFIG_TOI_PRUNE) += tuxonice_prune.o -obj-$(CONFIG_TOI_INCREMENTAL) += tuxonice_incremental.o -obj-$(CONFIG_TOI_CRYPTO) += tuxonice_compress.o - -tuxonice_bio-y := tuxonice_bio_core.o tuxonice_bio_chains.o \ - tuxonice_bio_signature.o - -obj-$(CONFIG_TOI_SWAP) += tuxonice_bio.o tuxonice_swap.o -obj-$(CONFIG_TOI_FILE) += tuxonice_bio.o tuxonice_file.o -obj-$(CONFIG_TOI_CLUSTER) += tuxonice_cluster.o - -obj-$(CONFIG_TOI_USERUI) += tuxonice_userui.o - obj-y += qos.o obj-$(CONFIG_PM) += main.o obj-$(CONFIG_VT_CONSOLE_SLEEP) += console.o diff --git a/kernel/power/autosleep.c b/kernel/power/autosleep.c index 4892e1947800..9567a8c50e99 100644..100755 --- a/kernel/power/autosleep.c +++ b/kernel/power/autosleep.c @@ -9,7 +9,6 @@ #include <linux/device.h> #include <linux/mutex.h> #include <linux/pm_wakeup.h> -#include <mtk_hibernate_core.h> #include "power.h" diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c index 4cee981a8e59..e00f9319ac0c 100644..100755 --- a/kernel/power/hibernate.c +++ b/kernel/power/hibernate.c @@ -30,8 +30,6 @@ #include <linux/genhd.h> #include <trace/events/power.h> -#include "tuxonice.h" - static int nocompress; static int noresume; diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index 0bd751fd2fba..7cfbf03f8d63 100644..100755 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -34,10 +34,6 @@ #include <asm/tlbflush.h> #include <asm/io.h> -#include "tuxonice_modules.h" -#include "tuxonice_builtin.h" -#include "tuxonice_alloc.h" -#include "tuxonice_pageflags.h" #include "power.h" static int swsusp_page_is_free(struct page *); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index c7935590d7c3..4da8335c0258 100644..100755 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -2599,6 +2599,7 @@ static inline u64 __synchronize_entity_decay(struct sched_entity *se) u64 decays = atomic64_read(&cfs_rq->decay_counter); decays -= se->avg.decay_count; + se->avg.decay_count = 0; if (!decays) return 0; @@ -2606,8 +2607,6 @@ static inline u64 __synchronize_entity_decay(struct sched_entity *se) se->avg.utilization_avg_contrib = decay_load(se->avg.utilization_avg_contrib, decays); - se->avg.decay_count = 0; - return decays; } @@ -2895,16 +2894,30 @@ static inline void update_entity_load_avg(struct sched_entity *se, else now = cfs_rq_clock_task(group_cfs_rq(se)); +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (entity_is_task(se) && se->on_rq) + inc_nr_heavy_running("update_entity_load_avg-", task_of(se), -1, false); +#endif if (!__update_entity_runnable_avg(now, cpu, &se->avg, se->on_rq, cfs_rq->curr == se)) { /* sched: add trace_sched */ if (entity_is_task(se)) trace_sched_task_entity_avg(2, task_of(se), &se->avg); + +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (entity_is_task(se) && se->on_rq) + inc_nr_heavy_running("update_entity_load_avg+", task_of(se), 1, false); +#endif return; } contrib_delta = __update_entity_load_avg_contrib(se); __update_entity_utilization_avg_contrib(se, &running_delta, &runnable_delta); +#ifdef CONFIG_MTK_SCHED_RQAVG_US + if (entity_is_task(se) && se->on_rq) + inc_nr_heavy_running("update_entity_load_avg++", task_of(se), 1, false); +#endif + if (!update_cfs_rq) return; @@ -4803,6 +4816,11 @@ enqueue_task_fair(struct rq *rq, struct task_struct *p, int flags) if (!se) { update_rq_runnable_avg(rq, rq->nr_running); add_nr_running(rq, 1); + +#ifdef CONFIG_MTK_SCHED_RQAVG_US + inc_nr_heavy_running(__func__, p, 1, false); +#endif + #ifndef CONFIG_CFS_BANDWIDTH BUG_ON(rq->cfs.nr_running > rq->cfs.h_nr_running); #endif @@ -4877,6 +4895,9 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) BUG_ON(rq->cfs.nr_running > rq->cfs.h_nr_running); #endif update_rq_runnable_avg(rq, 1); +#ifdef CONFIG_MTK_SCHED_RQAVG_US + inc_nr_heavy_running(__func__, p, -1, false); +#endif } hrtick_update(rq); #ifdef CONFIG_MTK_SCHED_CMP_TGS diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index bf9670a20bbb..5f50345c8afc 100644..100755 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1267,6 +1267,11 @@ extern void init_task_runnable_average(struct task_struct *p); #ifdef CONFIG_MTK_SCHED_RQAVG_KS void sched_update_nr_prod(int cpu, unsigned long nr_running, int inc); #endif + +#ifdef CONFIG_MTK_SCHED_RQAVG_US +extern int inc_nr_heavy_running(const char *invoker, struct task_struct *p, int inc, bool ack_cap); +#endif + static inline void add_nr_running(struct rq *rq, unsigned count) { unsigned prev_nr = rq->nr_running; |