diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2014-06-19 21:52:23 +0000 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-07-13 07:11:40 -0700 |
| commit | 15ebb05248d025534773c9ef64915bd888f04e4b (patch) | |
| tree | 787b460d82493dbd8129865c317b620066395d06 | |
| parent | c556bcddc78096caeb46dbe3ad0314dd951f1665 (diff) | |
clk: spear3xx: Use proper control register offset
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
| -rw-r--r-- | drivers/clk/spear/spear3xx_clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index c2d204315546..125eba86c844 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { } /* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 -#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) +#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) #define SPEAR320_UARTX_PCLK_MASK 0x1 |