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authorDaniel Thompson <daniel.thompson@linaro.org>2015-12-16 16:36:48 +0000
committerDaniel Thompson <daniel.thompson@linaro.org>2015-12-16 16:36:48 +0000
commitf13d98a9b1fd9440edddf2b0d8752018f2b5f56f (patch)
treed453beeb0e4b381e9dbfc9dc20e07e389908911e
parent5d2b2d9c3a7d37a0b52701159593974e315b8ff8 (diff)
downloadlinux-f13d98a9b1fd9440edddf2b0d8752018f2b5f56f.tar.gz
irqchip/gic: Identify and report any reserved SGI IDsdev/arm_backtrace_on_apq8064
It is possible for the secure world to reserve certain SGI IDs for itself. Currently we have limited visibility of which IDs are safe to use for IPIs. Modify the GIC initialization code to actively search for reserved SGI IDs and report if any are found. Warn even more loudly if the reserved SGIs overlap with the normal IPI range. When run on an Inforce IFC6410 (Snapdragon 600) this code produces the following messages: ~~~ cut here ~~~ CPU0: Detected reserved SGI IDs: 14-15 CPU1: Detected reserved SGI IDs: 15 CPU2: Detected reserved SGI IDs: 15 CPU3: Detected reserved SGI IDs: 15 ~~~ cut here ~~~ Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
-rw-r--r--drivers/irqchip/irq-gic.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index abf2ffaed392..541622da7049 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -490,6 +490,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
void __iomem *base = gic_data_cpu_base(gic);
unsigned int cpu_mask, cpu = smp_processor_id();
int i;
+ DECLARE_BITMAP(sgi_mask, 16);
/*
* Setting up the CPU map is only relevant for the primary GIC
@@ -511,6 +512,58 @@ static void gic_cpu_init(struct gic_chip_data *gic)
for (i = 0; i < NR_GIC_CPU_IF; i++)
if (i != cpu)
gic_cpu_map[i] &= ~cpu_mask;
+
+ /*
+ * Fiddle with the SGI set/clear registers to try identify
+ * any IPIs that are reserved for secure world.
+ */
+ bitmap_fill(sgi_mask, 16);
+
+ for (i = 0; i < 16; i++) {
+ void __iomem *set_reg =
+ dist_base + GIC_DIST_SGI_PENDING_SET + (i & ~3);
+ void __iomem *clear_reg =
+ dist_base + GIC_DIST_SGI_PENDING_CLEAR + (i & ~3);
+ unsigned long mask = cpu_mask << (8*(i%4));
+ unsigned long flags, pending, after_clear, after_set;
+
+ local_irq_save(flags);
+
+ /* record original value */
+ pending = readl_relaxed(set_reg);
+
+ /* clear, test, set, and test again */
+ writel_relaxed(mask, clear_reg);
+ after_clear = readl_relaxed(set_reg);
+ writel_relaxed(mask, set_reg);
+ after_set = readl_relaxed(set_reg);
+
+ /* restore original value */
+ writel_relaxed(mask & ~pending, clear_reg);
+
+ local_irq_restore(flags);
+
+ if (mask & ~after_clear && mask & after_set)
+ clear_bit(i, sgi_mask);
+ }
+
+ /*
+ * Show the SGI mask if it is "interesting". Here interesting
+ * means that the set/clear register is implemented
+ * (mask is not full) and it tells us that the secure world
+ * has reserved some SGIs (mask is not empty).
+ */
+ if (!bitmap_full(sgi_mask, 16) && !bitmap_empty(sgi_mask, 16))
+ pr_info("CPU%d: Detected reserved SGI IDs: %*pbl\n",
+ cpu, 16, sgi_mask);
+
+ /*
+ * Yell if the reserved IDs make the system unviable.
+ */
+ if (!bitmap_full(sgi_mask, 16) &&
+ find_first_bit(sgi_mask, 16) < NR_IPI)
+ pr_crit("CPU%d: Not enough SGI IDs; expect failure\n",
+ cpu);
}
gic_cpu_config(dist_base, NULL);