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authorDaniel Thompson <daniel.thompson@linaro.org>2017-01-27 16:07:13 +0000
committerDaniel Thompson <daniel.thompson@linaro.org>2017-03-29 17:02:10 +0100
commite6daa5a0ef457ecdc187d078eebd3f425744eab5 (patch)
tree177814479264ac34731811fcc47ec7017a87cfcc
parent660f38b6a61ab655d65bf3370fe909c8ed0f6d2c (diff)
downloadlinux-dev/arm64_nmi-v4.10.tar.gz
WIP: Migrating PMR interrupt locking away from kernel_entrydev/arm64_nmi-v4.10
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
-rw-r--r--arch/arm64/kernel/entry.S12
-rw-r--r--drivers/irqchip/irq-gic-v3.c27
-rw-r--r--kernel/rcu/tree.c1
3 files changed, 37 insertions, 3 deletions
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 96a36b8..3acc5cf 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -125,8 +125,6 @@ alternative_endif
lsl x20, x20, #PSR_G_PMR_G_SHIFT // Shift to a PSTATE RES0 bit
eor x20, x20, #PSR_G_BIT // Invert bit
orr x23, x20, x23 // Store PMR within PSTATE
- mov x20, #ICC_PMR_EL1_MASKED
- msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
1:
#endif
@@ -370,6 +368,8 @@ tsk .req x28 // current thread_info
* Interrupt handling.
*/
.macro irq_handler
+ mov x20, #ICC_PMR_EL1_MASKED
+ msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
ldr_l x1, handle_arch_irq
mov x0, sp
irq_stack_entry
@@ -419,6 +419,8 @@ END(vectors)
*/
.macro inv_entry, el, reason, regsize = 64
kernel_entry \el, \regsize
+ mov x20, #ICC_PMR_EL1_MASKED
+ msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
mov x0, sp
mov x1, #\reason
mrs x2, esr_el1
@@ -473,6 +475,8 @@ ENDPROC(el1_error_invalid)
.align 6
el1_sync:
kernel_entry 1
+ mov x20, #ICC_PMR_EL1_MASKED
+ msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
mrs x1, esr_el1 // read the syndrome register
lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
@@ -605,6 +609,8 @@ el1_preempt:
.align 6
el0_sync:
kernel_entry 0
+ mov x20, #ICC_PMR_EL1_MASKED
+ msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
mrs x25, esr_el1 // read the syndrome register
lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
@@ -633,6 +639,8 @@ el0_sync:
.align 6
el0_sync_compat:
kernel_entry 0, 32
+ mov x20, #ICC_PMR_EL1_MASKED
+ msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
mrs x25, esr_el1 // read the syndrome register
lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 3923201..9ca08aa 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -343,7 +343,7 @@ static u64 gic_mpidr_to_affinity(unsigned long mpidr)
}
#ifdef CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS
-static bool gic_handle_nmi(struct pt_regs *regs)
+static bool __maybe_unused gic_handle_nmi(struct pt_regs *regs)
{
u64 irqnr;
struct pt_regs *old_regs;
@@ -393,12 +393,37 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
{
u32 irqnr;
+#if 1
+ local_irq_disable();
+
if (gic_handle_nmi(regs))
return;
+#endif
do {
irqnr = gic_read_iar();
+#if 0
+ printk_ratelimited(KERN_INFO "irqnr %d\n", irqnr);
+
+ if (unlikely(SMP_IPI_NMI_MASK & (1 << irqnr))) {
+ struct pt_regs *old_regs;
+
+ old_regs = set_irq_regs(regs);
+ nmi_enter();
+
+ gic_write_eoir(irqnr);
+ if (static_key_true(&supports_deactivate))
+ gic_write_dir(irqnr);
+
+ nmi_cpu_backtrace(regs);
+
+ nmi_exit();
+ set_irq_regs(old_regs);
+ continue;
+ }
+#endif
+
if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
int err;
diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
index cb4e205..9c241c8 100644
--- a/kernel/rcu/tree.c
+++ b/kernel/rcu/tree.c
@@ -1372,6 +1372,7 @@ static void print_other_cpu_stall(struct rcu_state *rsp, unsigned long gpnum)
}
print_cpu_stall_info_end();
+ trigger_all_cpu_backtrace();
for_each_possible_cpu(cpu)
totqlen += per_cpu_ptr(rsp->rda, cpu)->qlen;
pr_cont("(detected by %d, t=%ld jiffies, g=%ld, c=%ld, q=%lu)\n",