diff options
| author | Kevin Hilman <khilman@deeprootsystems.com> | 2009-01-08 16:34:08 -0800 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-01-08 16:34:08 -0800 |
| commit | abe4cfb64c63ba195ca344acbb221c6c7be22a1d (patch) | |
| tree | 6ab83f2daa7fb88d334b8e0bce1eb8f7b6fd8e7b | |
| parent | 276df4adceef525c7fe108a0b7e6570ee781eb06 (diff) | |
DaVinci: FB: fix memory addressing warnings by using physical addressesv2.6.28-davinci1
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| -rw-r--r-- | drivers/video/davincifb.c | 16 | ||||
| -rw-r--r-- | include/video/davincifb.h | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/drivers/video/davincifb.c b/drivers/video/davincifb.c index 49f86cc1c938..9d478d1e89dc 100644 --- a/drivers/video/davincifb.c +++ b/drivers/video/davincifb.c @@ -51,20 +51,20 @@ /* * display controller register I/O routines */ -static __inline__ u32 dispc_reg_in(u32 offset) +static __inline__ u32 dispc_reg_in(u32 reg) { - return (inl(offset)); + return davinci_readl(reg); } -static __inline__ u32 dispc_reg_out(u32 offset, u32 val) +static __inline__ u32 dispc_reg_out(u32 reg, u32 val) { - outl(val, offset); + davinci_writel(val, reg); return (val); } -static __inline__ u32 dispc_reg_merge(u32 offset, u32 val, u32 mask) +static __inline__ u32 dispc_reg_merge(u32 reg, u32 val, u32 mask) { - u32 addr = offset; - u32 new_val = (inl(addr) & ~mask) | (val & mask); - outl(new_val, addr); + u32 new_val = (davinci_readl(reg) & ~mask) | (val & mask); + + davinci_writel(new_val, reg); return (new_val); } diff --git a/include/video/davincifb.h b/include/video/davincifb.h index 13fa23763855..96b5c20c349c 100644 --- a/include/video/davincifb.h +++ b/include/video/davincifb.h @@ -16,9 +16,9 @@ #include <mach/io.h> /* Base registers */ -#define VPBE_REG_BASE IO_ADDRESS(0x01c72780) -#define VENC_REG_BASE IO_ADDRESS(0x01c72400) -#define OSD_REG_BASE IO_ADDRESS(0x01c72600) +#define VPBE_REG_BASE 0x01c72780 +#define VENC_REG_BASE 0x01c72400 +#define OSD_REG_BASE 0x01c72600 #define OSD_REG_SIZE 0x00000180 /* VPBE Global Registers */ @@ -26,7 +26,7 @@ #define VPBE_PCR (VPBE_BASE + 0x4) /* VPSS Clock Control Register */ -#define VPSS_CLKCTL IO_ADDRESS(0x01c40044) +#define VPSS_CLKCTL 0x01c40044 /* VPBE Video Encoder / Digital LCD Subsystem Registers (VENC) */ #define VENC_VMOD (VENC_REG_BASE + 0x00) |