diff options
| author | Andrey Konovalov <andrey.konovalov@linaro.org> | 2015-10-22 01:02:49 +0300 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2015-10-22 01:02:49 +0300 |
| commit | 0fdf6766312c360e76210eb633e9919ed2390819 (patch) | |
| tree | 1cddaa34b683ee8e8e2d1e40fbff88139d653a86 | |
| parent | 08ce61329b063d1ad0e96a19c4b4276b8e2abdfe (diff) | |
| parent | 75c4eeeb4c1cec3f7eb75cfbe52217d157ad4689 (diff) | |
Automatically merging tracking-integration-hilt-linux-linaro into merge-linux-linaro
Conflicting files:
drivers/misc/Kconfig
drivers/misc/Makefile
27 files changed, 4418 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt new file mode 100644 index 000000000000..3dfb0b0ecd33 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt @@ -0,0 +1,57 @@ +Hisilicon Hi6220 Mailbox Driver +=============================== + +Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel +is unidirectional with a maximum message size of 8 words. I/O is +performed using register access (there is no DMA) and the cell +raises an interrupt when messages are received. + +Mailbox Device Node: +==================== + +Required properties: +-------------------- +- compatible: Shall be "hisilicon,hi6220-mbox" +- reg: Contains the mailbox register address range (base + address and length); the first item is for IPC + registers, the second item is shared buffer for + slots. +- #mbox-cells Common mailbox binding property to identify the number + of cells required for the mailbox specifier. Should be 1. +- interrupts: Contains the interrupt information for the mailbox + device. The format is dependent on which interrupt + controller the SoCs use. + +Example: +-------- + + mailbox: mailbox@F7510000 { + #mbox-cells = <1>; + compatible = "hisilicon,hi6220-mbox"; + reg = <0x0 0xF7510000 0x0 0x1000>, /* IPC_S */ + <0x0 0x06DFF800 0x0 0x0800>; /* Mailbox */ + interrupt-parent = <&gic>; + interrupts = <0 94 4>; + }; + + +Mailbox client +=============== + +"mboxes" and the optional "mbox-names" (please see +Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value +of the mboxes property should contain a phandle to the mailbox controller +device node and second argument is the channel index. It must be 0 (hardware +support only one channel). The equivalent "mbox-names" property value can be +used to give a name to the communication channel to be used by the client user. + +Example: +-------- + + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mbox-names = "mbox-tx"; + mboxes = <&mailbox 1>; + }; diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt new file mode 100644 index 000000000000..17bd8caa904c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt @@ -0,0 +1,80 @@ +Hisilicon hi655x Power Management Integrated Circuit (PMIC) + +hi655x consists of a large and varied group of sub-devices: + +Device Supply Names Description +------ ------------ ----------- +hi655x-powerkey : : Powerkey +hi655x-regulator-pmic : : Regulators +hi655x-usbvbus : : USB plug detection +hi655x-pmu-rtc : : RTC +hi655x-coul : : Coulomb + +Required properties: +- compatible : Should be "hisilicon,hi655x-pmic-driver" +- reg: Base address of PMIC on hi6220 soc +- #interrupt-cells: Should be 2, is the local IRQ number for hi655x. +- interrupt-controller: hi655x has internal IRQs (has own IRQ domain). +- pmu_irq_gpio: should be &gpio_pmu_irq_n, is the IRQ gpio of hi655x. + +Example: + pmic: pmic@F8000000 { + compatible = "hisilicon,hi655x-pmic-driver"; + reg = <0x0 0xF8000000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + pmu_irq_gpio = <&gpio_pmu_irq_n>; + status = "ok"; + + ponkey:ponkey@b1{ + compatible = "hisilicon,hi655x-powerkey"; + interrupt-parent = <&pmic>; + interrupts = <6 0>, <5 0>, <4 0>; + interrupt-names = "down", "up", "hold 1s"; + }; + + coul: coul@1 { + compatible = "hisilicon,hi655x-coul"; + interrupt-parent = <&pmic>; + interrupts = <24 0>, <25 0>, <26 0>, <27 0>; + interrupt-names = "cl_int_i", "cl_out_i", "cl_in_i", "vbat_int_i"; + battery_product_index = <0>; + status = "ok"; + }; + + rtc: rtc@1 { + compatible = "hisilicon,hi655x-pmu-rtc"; + interrupt-parent = <&pmic>; + interrupts = <20 0>; + interrupt-names = "hi655x_pmu_rtc"; + board_id = <1>; + }; + + usbvbus:usbvbus@b2{ + compatible = "hisilicon,hi655x-usbvbus"; + interrupt-parent = <&pmic>; + interrupts = <9 0>, <8 0>; + interrupt-names = "connect", "disconnect"; + }; + + ldo2: regulator@a21 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + hisilicon,valid-modes-mask = <0x02>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x029 0x02a 0x02b>; + hisilicon,ctrl-data = <0x1 0x1>; + hisilicon,vset-regs = <0x072>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "sensor_analog"; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt b/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt new file mode 100644 index 000000000000..748ac6284634 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi6220-mtcmos.txt @@ -0,0 +1,32 @@ +Hi6220 mtcmos Voltage regulators + +Required parent device properties: +- compatible: Must be "hisilicon,hi6220-mtcmos-driver" +- hisilicon,mtcmos-steady-us: The time to wait for power steady +- hisilicon,mtcmos-sc-on-base: address of hi6220 soc control register + +Required child device properties: +- regulator-name: The name of mtcmos +- hisilicon,ctrl-regs: offset of ctrl-regs +- hisilicon,ctrl-data: the bit to ctrl the regulator + +Example: + mtcmos { + compatible = "hisilicon,hi6220-mtcmos-driver"; + hisilicon,mtcmos-steady-us = <10>; + hisilicon,mtcmos-sc-on-base = <0xf7800000>; + hisilicon,mtcmos-acpu-on-base = <0xf65a0000>; + + mtcmos1: regulator@a1{ + regulator-name = "G3D_PD_VDD"; + regulator-compatible = "mtcmos1"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <1 0x1>; + }; + mtcmos2: regulator@a2{ + regulator-name = "SOC_MED"; + regulator-compatible = "mtcmos2"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <2 0x1>; + }; + }; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 23800a19a7bc..bb4b1d043407 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -35,6 +35,8 @@ config ARCH_FSL_LS2085A config ARCH_HISI bool "Hisilicon SoC Family" + select ARM_TIMER_SP804 + select HI6220_SYSCFG help This enables support for Hisilicon ARMv8 SoC family diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e36a539468a5..802fc4ea976a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -7,9 +7,8 @@ /dts-v1/; -/*Reserved 1MB memory for MCU*/ -/memreserve/ 0x05e00000 0x00100000; - +#include "hikey-gpio.dtsi" +#include "hikey-pinctrl.dtsi" #include "hi6220.dtsi" / { @@ -18,14 +17,26 @@ aliases { serial0 = &uart0; + serial3 = &uart3; }; chosen { stdout-path = "serial0:115200n8"; }; + /* + * Reserve below regions from memory node: + * + * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using + * - 0x06df,f000 - 0x06df,ffff: Mailbox message data + * - 0x0740,f000 - 0x0740,ffff: MCU firmware section + * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE + */ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, + <0x00000000 0x05f00000 0x00000000 0x00eff000>, + <0x00000000 0x06e00000 0x00000000 0x0060f000>, + <0x00000000 0x07410000 0x00000000 0x36bf0000>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380815b6..62a46ab54aab 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -5,6 +5,8 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/clock/hi6220-clock.h> / { compatible = "hisilicon,hi6220"; @@ -57,6 +59,18 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&stub_clock 0>; + clock-latency = <0>; + operating-points = < + /* kHz */ + 1200000 0 + 960000 0 + 729000 0 + 432000 0 + 208000 0 + >; + #cooling-cells = <2>; /* min followed by max */ + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@1 { @@ -64,6 +78,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@2 { @@ -71,6 +86,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@3 { @@ -78,6 +94,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@100 { @@ -85,6 +102,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu5: cpu@101 { @@ -92,6 +110,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu6: cpu@102 { @@ -99,6 +118,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; }; cpu7: cpu@103 { @@ -106,6 +126,30 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; }; }; @@ -136,6 +180,11 @@ #size-cells = <2>; ranges; + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; + ao_ctrl: ao_ctrl@f7800000 { compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; @@ -160,6 +209,101 @@ #clock-cells = <1>; }; + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mboxes = <&mailbox 1>; + }; + + dual_timer0: dual_timer@f8008000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xf8008000 0x0 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ao_ctrl 27>, <&ao_ctrl 27>; + clock-names = "apb_pclk", "apb_pclk"; + }; + + dwmmc_0: dwmmc0@f723d000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + cap-mmc-highspeed; + non-removable; + reg = <0x0 0xf723d000 0x0 0x1000>; + interrupts = <0x0 0x48 0x4>; + clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; + clock-names = "ciu", "biu"; + bus-width = <0x8>; + vmmc-supply = <&ldo19>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func + &emmc_cfg_func &emmc_rst_cfg_func>; + }; + + dwmmc_1: dwmmc1@f723e000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + card-detect-delay = <200>; + hisilicon,peripheral-syscon = <&ao_ctrl>; + cap-sd-highspeed; + reg = <0x0 0xf723e000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; + clock-names = "ciu", "biu"; + vqmmc-supply = <&ldo7>; + vmmc-supply = <&ldo10>; + bus-width = <0x4>; + disable-wp; + cd-gpios = <&gpio1 0 1>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; + }; + + dwmmc_2: dwmmc2@f723f000 { + compatible = "hisilicon,hi6220-dw-mshc"; + status = "okay"; + num-slots = <0x1>; + reg = <0x0 0xf723f000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; + clock-names = "ciu", "biu"; + bus-width = <0x4>; + broken-cd; + ti,non-removable; + non-removable; + /* WL_EN */ + vmmc-supply = <&wlan_en_reg>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; + pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + }; + + wlan_en_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* WLAN_EN GPIO */ + gpio = <&gpio0 5 0>; + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; @@ -167,5 +311,768 @@ clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; clock-names = "uartclk", "apb_pclk"; }; + + uart3: uart@f7113000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7113000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_ctrl 19>, <&sys_ctrl 19>; + clock-names = "uartclk", "apb_pclk"; + }; + + pmx0: pinmux@f7010000 { + compatible = "pinctrl-single"; + reg = <0x0 0xf7010000 0x0 0x27c>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-range = < + &range 80 8 MUX_M0 /* gpio 3: [0..7] */ + &range 88 8 MUX_M0 /* gpio 4: [0..7] */ + &range 96 8 MUX_M0 /* gpio 5: [0..7] */ + &range 104 8 MUX_M0 /* gpio 6: [0..7] */ + &range 112 8 MUX_M0 /* gpio 7: [0..7] */ + &range 120 2 MUX_M0 /* gpio 8: [0..1] */ + &range 2 6 MUX_M1 /* gpio 8: [2..7] */ + &range 8 8 MUX_M1 /* gpio 9: [0..7] */ + &range 0 1 MUX_M1 /* gpio 10: [0] */ + &range 16 7 MUX_M1 /* gpio 10: [1..7] */ + &range 23 3 MUX_M1 /* gpio 11: [0..2] */ + &range 28 5 MUX_M1 /* gpio 11: [3..7] */ + &range 33 3 MUX_M1 /* gpio 12: [0..2] */ + &range 43 5 MUX_M1 /* gpio 12: [3..7] */ + &range 48 8 MUX_M1 /* gpio 13: [0..7] */ + &range 56 8 MUX_M1 /* gpio 14: [0..7] */ + &range 74 6 MUX_M1 /* gpio 15: [0..5] */ + &range 122 1 MUX_M1 /* gpio 15: [6] */ + &range 126 1 MUX_M1 /* gpio 15: [7] */ + &range 127 8 MUX_M1 /* gpio 16: [0..7] */ + &range 135 8 MUX_M1 /* gpio 17: [0..7] */ + &range 143 8 MUX_M1 /* gpio 18: [0..7] */ + &range 151 8 MUX_M1 /* gpio 19: [0..7] */ + >; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmx1: pinmux@f7010800 { + compatible = "pinconf-single"; + reg = <0x0 0xf7010800 0x0 0x28c>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + }; + + pmx2: pinmux@f8001800 { + compatible = "pinconf-single"; + reg = <0x0 0xf8001800 0x0 0x78>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + }; + + gpio0: gpio@f8011000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8011000 0x0 0x1000>; + interrupts = <0 52 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio1: gpio@f8012000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8012000 0x0 0x1000>; + interrupts = <0 53 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio2: gpio@f8013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8013000 0x0 0x1000>; + interrupts = <0 54 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio3: gpio@f8014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8014000 0x0 0x1000>; + interrupts = <0 55 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 80 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio4: gpio@f7020000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7020000 0x0 0x1000>; + interrupts = <0 56 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 88 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio5: gpio@f7021000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7021000 0x0 0x1000>; + interrupts = <0 57 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 96 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio6: gpio@f7022000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7022000 0x0 0x1000>; + interrupts = <0 58 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 104 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio7: gpio@f7023000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7023000 0x0 0x1000>; + interrupts = <0 59 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 112 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio8: gpio@f7024000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7024000 0x0 0x1000>; + interrupts = <0 60 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio9: gpio@f7025000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7025000 0x0 0x1000>; + interrupts = <0 61 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 8 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio10: gpio@f7026000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7026000 0x0 0x1000>; + interrupts = <0 62 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio11: gpio@f7027000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7027000 0x0 0x1000>; + interrupts = <0 63 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio12: gpio@f7028000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7028000 0x0 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio13: gpio@f7029000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7029000 0x0 0x1000>; + interrupts = <0 65 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 48 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio14: gpio@f702a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702a000 0x0 0x1000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 56 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio15: gpio@f702b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702b000 0x0 0x1000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < + &pmx0 0 74 6 + &pmx0 6 122 1 + &pmx0 7 126 1 + >; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio16: gpio@f702c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702c000 0x0 0x1000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 127 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio17: gpio@f702d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702d000 0x0 0x1000>; + interrupts = <0 69 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 135 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio18: gpio@f702e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702e000 0x0 0x1000>; + interrupts = <0 70 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 143 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio19: gpio@f702f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702f000 0x0 0x1000>; + interrupts = <0 71 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 151 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + i2c2: i2c@f7102000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xf7102000 0x0 0x1000>; + interrupts = <0 46 4>; + + clocks = <&sys_ctrl HI6220_I2C2_CLK>; + clock-names = "clk_i2c2"; + i2c-sda-hold-time-ns = <300>; + delay-reg = <0x0 0x0f8 0x0 4>; + reset-controller-reg = <0x330 0x334 0x338 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "ok"; + }; + + mailbox: mailbox@f7510000 { + #mbox-cells = <1>; + compatible = "hisilicon,hi6220-mbox"; + reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ + <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + }; + + tsensor: tsensor@0,f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0x0 0xf7030700 0x0 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_ctrl 22>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + local: local { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 0>; + + trips { + local_alert: local_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + local_crit: local_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + cluster1: cluster1 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 1>; + + trips { + cluster1_alert: cluster1_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cluster1_crit: cluster1_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + cluster0: cluster0 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 2>; + + trips { + cluster0_alert: cluster0_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cluster0_crit: cluster0_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cluster0_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu: gpu { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 3>; + + trips { + gpu_alert: gpu_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + }; + + mtcmos { + compatible = "hisilicon,hi6220-mtcmos-driver"; + hisilicon,mtcmos-steady-us = <10>; + hisilicon,mtcmos-sc-on-base = <0xf7800000>; + hisilicon,mtcmos-acpu-on-base = <0xf65a0000>; + + mtcmos1: regulator@a1{ + regulator-name = "G3D_PD_VDD"; + regulator-compatible = "mtcmos1"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <1 0x1>; + }; + + mtcmos2: regulator@a2{ + regulator-name = "SOC_MED"; + regulator-compatible = "mtcmos2"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <2 0x1>; + }; + }; + }; + + pmic: pmic@F8000000 { + compatible = "hisilicon,hi655x-pmic-driver"; + reg = <0x0 0xf8000000 0x0 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + pmu_irq_gpio = <&gpio_pmu_irq_n>; + status = "ok"; + + ldo2: regulator@a21 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo2"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + hisilicon,valid-modes-mask = <0x02>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x029 0x02a 0x02b>; + hisilicon,ctrl-data = <0x1 0x1>; + hisilicon,vset-regs = <0x072>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <2500000>,<2600000>, + <2700000>,<2800000>, + <2900000>,<3000000>, + <3100000>,<3200000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "sensor_analog"; + }; + + ldo7: regulator@a26 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + hisilicon,valid-modes-mask = <0x0a>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x029 0x02a 0x02b>; + hisilicon,ctrl-data = <0x6 0x1>; + hisilicon,vset-regs = <0x078>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1800000>,<1850000>, + <2850000>,<2900000>, + <3000000>,<3100000>, + <3200000>,<3300000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "sd_card_io"; + }; + + ldo10: regulator@a29 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + hisilicon,valid-modes-mask = <0x0a>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <360>; + hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; + hisilicon,ctrl-data = <0x1 0x1>; + hisilicon,vset-regs = <0x07b>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1800000>,<1850000>, + <1900000>,<2750000>, + <2800000>,<2850000>, + <2900000>,<3000000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "sd_card"; + }; + + ldo13: regulator@a32 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo13"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + hisilicon,valid-modes-mask = <0x0a>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; + hisilicon,ctrl-data = <0x4 0x1>; + hisilicon,vset-regs = <0x07e>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1600000>,<1650000>, + <1700000>,<1750000>, + <1800000>,<1850000>, + <1900000>,<1950000>; + hisilicon,num_consumer_supplies = <3>; + hisilicon,consumer-supplies = "scamera_core", + "mcamera_io", + "scamera_io"; + }; + + ldo14: regulator@a33 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo14"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + hisilicon,valid-modes-mask = <0x02>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; + hisilicon,ctrl-data = <0x5 0x1>; + hisilicon,vset-regs = <0x07f>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <2500000>,<2600000>, + <2700000>,<2800000>, + <2900000>,<3000000>, + <3100000>,<3200000>; + hisilicon,num_consumer_supplies = <3>; + hisilicon,consumer-supplies = "scamera_avdd", + "mcamera_avdd", + "mcamera_vcm"; + }; + + ldo15: regulator@a34 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo15"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + hisilicon,valid-modes-mask = <0x0a>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; + hisilicon,ctrl-data = <0x6 0x1>; + hisilicon,vset-regs = <0x080>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1600000>,<1650000>, + <1700000>,<1750000>, + <1800000>,<1850000>, + <1900000>,<1950000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "codec_analog"; + }; + + ldo17: regulator@a36 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo17"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + hisilicon,valid-modes-mask = <0x02>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02f 0x030 0x031>; + hisilicon,ctrl-data = <0x0 0x1>; + hisilicon,vset-regs = <0x082>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <2500000>,<2600000>, + <2700000>,<2800000>, + <2900000>,<3000000>, + <3100000>,<3200000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "vibrator"; + }; + + ldo19: regulator@a38 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + hisilicon,valid-modes-mask = <0x0a>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <360>; + hisilicon,ctrl-regs = <0x02f 0x030 0x031>; + hisilicon,ctrl-data = <0x2 0x1>; + hisilicon,vset-regs = <0x084>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1800000>,<1850000>, + <1900000>,<2750000>, + <2800000>,<2850000>, + <2900000>,<3000000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "emmc_vddm"; + }; + + ldo21: regulator@a40 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo21"; regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + hisilicon,valid-modes-mask = <0x02>; hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02f 0x030 0x031>; + hisilicon,ctrl-data = <0x4 0x1>; + hisilicon,vset-regs = <0x086>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <1650000>,<1700000>, + <1750000>,<1800000>, + <1850000>,<1900000>, + <1950000>,<2000000>; + }; + + ldo22: regulator@a41 { + compatible = "hisilicon,hi655x-regulator-pmic"; + regulator-name = "ldo22"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + hisilicon,valid-modes-mask = <0x02>; + hisilicon,valid-ops-mask = <0x01d>; + hisilicon,initial-mode = <0x02>; + hisilicon,regulator-type = <0x01>; + + hisilicon,off-on-delay = <120>; + hisilicon,ctrl-regs = <0x02f 0x030 0x031>; + hisilicon,ctrl-data = <0x5 0x1>; + hisilicon,vset-regs = <0x087>; + hisilicon,vset-data = <0 0x3>; + hisilicon,regulator-n-vol = <8>; + hisilicon,vset-table = <900000>,<1000000>, + <1050000>,<1100000>, + <1150000>,<1175000>, + <1185000>,<1200000>; + hisilicon,num_consumer_supplies = <1>; + hisilicon,consumer-supplies = "mcamera_core"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi new file mode 100644 index 000000000000..8be51ca93f96 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi @@ -0,0 +1,607 @@ +/ { + gpio_rstout_n:gpio_rstout_n { + gpios; + }; + gpio_pmu_peri_en:gpio_pmu_peri_en { + gpios; + }; + gpio_sysclk0_en:gpio_sysclk0_en { + gpios; + }; + gpio_jtag_tdo:gpio_jtag_tdo { + gpios; + }; + /* LCB: PWR_HOLD_GPIO0_0 */ + gpio_pwr_hold:gpio_pwr_hold { + gpios = <&gpio0 0 0>; + }; + /* LCB: DSI_SEL_GPIO0_1 */ + gpio_dsi_sel:gpio_dsi_sel { + gpios = <&gpio0 1 0>; + }; + /* LCB: USB_HUB_RESET_N_GPIO0_2 */ + gpio_usb_hub_reset_n:gpio_usb_hub_reset_n { + gpios = <&gpio0 2 0>; + }; + /* LCB: USB_SEL_GPIO0_3 */ + gpio_usb_sel:gpio_usb_sel { + gpios = <&gpio0 3 0>; + }; + /* LCB: HDMI_PD_GPIO0_4 */ + gpio_hdmi_pd:gpio_hdmi_pd { + gpios = <&gpio0 4 0>; + }; + /* LCB: WL_REG_ON_GPIO0_5 */ + gpio_wl_en:gpio_wl_en { + gpios = <&gpio0 5 0>; + }; + /* LCB: PWRON_DET_GPIO0_6 */ + gpio_pwron_det:gpio_pwron_det { + gpios = <&gpio0 6 0>; + }; + /* LCB: 5V_HUB_EN_GPIO0_7 */ + gpio_usb_dev_det:gpio_usb_dev_det { + gpios = <&gpio0 7 0>; + }; + /* LCB: SD_DET_GPIO1_0 */ + gpio_sd_det:gpio_sd_det { + gpios = <&gpio1 0 0>; + }; + /* LCB: HDMI_INT_GPIO1_1 */ + gpio_hdmi_int:gpio_hdmi_int { + gpios = <&gpio1 1 0>; + }; + /* LCB: PMU_IRQ_N_GPIO1_2 */ + gpio_pmu_irq_n:gpio_pmu_irq_n { + gpios = <&gpio1 2 0>; + }; + /* LCB: WL_HOST_WAKE_GPIO1_3 */ + gpio_wl_host_wake:gpio_wl_host_wake { + gpios = <&gpio1 3 0>; + }; + gpio_nfc_int:gpio_nfc_int { + gpios = <&gpio1 4 0>; + }; + gpio_unused_001:gpio_unused_001 { + gpios = <&gpio1 5 0>; + }; + /* LCB: BT_REG_ON_GPIO1_7 */ + gpio_bt_reg_on:gpio_bt_reg_on { + gpios = <&gpio1 7 0>; + }; + /* LCB: GPIO2_0, J2 */ + gpio_j2_2_0:gpio_j2_2_0 { + gpios = <&gpio2 0 0>; + }; + /* LCB: GPIO2_1, J2 */ + gpio_j2_2_1:gpio_j2_2_1 { + gpios = <&gpio2 1 0>; + }; + /* LCB: GPIO2_2, J2 */ + gpio_j2_2_2:gpio_j2_2_2 { + gpios = <&gpio2 2 0>; + }; + /* LCB: GPIO2_3, J2 */ + gpio_j2_2_3:gpio_j2_2_3 { + gpios = <&gpio2 3 0>; + }; + /* LCB: GPIO2_4, J2 */ + gpio_j2_2_4:gpio_j2_2_4 { + gpios = <&gpio2 4 0>; + }; + /* LCB: USB_ID_DET_GPIO2_5 */ + gpio_usb_id_det:gpio_usb_id_det { + gpios = <&gpio2 5 0>; + }; + /* LCB: USB_VBUS_DET_GPIO2_6 */ + gpio_vbus_det:gpio_vbus_det { + gpios = <&gpio2 6 0>; + }; + /* LCB: GPIO2_7, J2 */ + gpio_j2_2_7:gpio_j2_2_7 { + gpios = <&gpio2 7 0>; + }; + gpio_rf_reset0:gpio_rf_reset0 { + gpios; + }; + gpio_rf_reset1:gpio_rf_reset1 { + gpios; + }; + gpio_boot_sel:gpio_boot_sel { + gpios = <&gpio10 0 0>; + }; + gpio_pmu_ssi:gpio_pmu_ssi { + gpios; + }; + gpio_gps_ref_clk:gpio_gps_ref_clk { + gpios = <&gpio8 2 0>; + }; + gpio_sd_clk:gpio_sd_clk { + gpios = <&gpio8 3 0>; + }; + gpio_sd_cmd:gpio_sd_cmd { + gpios = <&gpio8 4 0>; + }; + gpio_sd_data0:gpio_sd_data0 { + gpios = <&gpio8 5 0>; + }; + gpio_sd_data1:gpio_sd_data1 { + gpios = <&gpio8 6 0>; + }; + gpio_sd_data2:gpio_sd_data2 { + gpios = <&gpio8 7 0>; + }; + gpio_sd_data3:gpio_sd_data3 { + gpios = <&gpio9 0 0>; + }; + gpio_unused_002:gpio_unused_002 { + gpios; + }; + gpio_mcam_pwdn:gpio_mcam_pwdn { + gpios = <&gpio9 1 0>; + }; + gpio_vcm_pwdn:gpio_vcm_pwdn { + gpios = <&gpio9 2 0>; + }; + gpio_scam_pwdn:gpio_scam_pwdn { + gpios = <&gpio9 3 0>; + }; + gpio_cam_id0:gpio_cam_id0 { + gpios = <&gpio9 4 0>; + }; + gpio_cam_id1:gpio_cam_id1 { + gpios = <&gpio9 5 0>; + }; + gpio_flash_strobe:gpio_flash_strobe { + gpios = <&gpio9 6 0>; + }; + gpio_mcam_mclk:gpio_mcam_mclk { + gpios = <&gpio9 7 0>; + }; + gpio_scam_mclk:gpio_scam_mclk { + gpios = <&gpio10 1 0>; + }; + gpio_cam_reset0:gpio_cam_reset0 { + gpios = <&gpio10 2 0>; + }; + gpio_cam_reset1:gpio_cam_reset1 { + gpios = <&gpio10 3 0>; + }; + gpio_tp_rst_n:gpio_tp_rst_n { + gpios = <&gpio10 4 0>; + }; + gpio_unused_003:gpio_unused_003 { + gpios = <&gpio10 5 0>; + }; + gpio_isp_sda0:gpio_isp_sda0 { + gpios = <&gpio10 6 0>; + }; + gpio_isp_scl0:gpio_isp_scl0 { + gpios = <&gpio10 7 0>; + }; + gpio_isp_sda1:gpio_isp_sda1 { + gpios = <&gpio11 0 0>; + }; + gpio_isp_scl1:gpio_isp_scl1 { + gpios = <&gpio11 1 0>; + }; + gpio_mdm_rst:gpio_mdm_rst { + gpios = <&gpio11 2 0>; + }; + gpio_hkadc_ssi:gpio_hkadc_ssi { + gpios; + }; + gpio_codec_clk:gpio_codec_clk { + gpios; + }; + gpio_ap_wakeup_mdm:gpio_ap_wakeup_mdm { + gpios = <&gpio11 3 0>; + }; + gpio_codec_sync:gpio_codec_sync { + gpios = <&gpio11 4 0>; + }; + gpio_codec_datain:gpio_codec_datain { + gpios = <&gpio11 5 0>; + }; + gpio_codec_dataout:gpio_codec_dataout { + gpios = <&gpio11 6 0>; + }; + gpio_fm_xclk:gpio_fm_xclk { + gpios = <&gpio11 7 0>; + }; + gpio_fm_xfs:gpio_fm_xfs { + gpios = <&gpio12 0 0>; + }; + gpio_fm_di:gpio_fm_di { + gpios = <&gpio12 1 0>; + }; + gpio_fm_do:gpio_fm_do { + gpios = <&gpio12 2 0>; + }; + gpio_bt_xclk:gpio_bt_xclk { + gpios; + }; + gpio_bt_xfs:gpio_bt_xfs { + gpios; + }; + gpio_bt_di:gpio_bt_di { + gpios; + }; + gpio_bt_do:gpio_bt_do { + gpios; + }; + gpio_usim0_clk:gpio_usim0_clk { + gpios; + }; + gpio_usim0_data:gpio_usim0_data { + gpios; + }; + gpio_usim0_rst:gpio_usim0_rst { + gpios; + }; + gpio_usim1_clk:gpio_usim1_clk { + gpios = <&gpio12 3 0>; + }; + gpio_usim1_data:gpio_usim1_data { + gpios = <&gpio12 4 0>; + }; + gpio_usim1_rst:gpio_usim1_rst { + gpios = <&gpio12 5 0>; + }; + gpio_unused_004:gpio_unused_004 { + gpios = <&gpio12 6 0>; + }; + gpio_unused_005:gpio_unused_005 { + gpios = <&gpio12 7 0>; + }; + gpio_uart0_rxd:gpio_uart0_rxd { + gpios = <&gpio13 0 0>; + }; + gpio_uart0_txd:gpio_uart0_txd { + gpios = <&gpio13 1 0>; + }; + gpio_bt_uart_cts_n:gpio_bt_uart_cts_n { + gpios = <&gpio13 2 0>; + }; + gpio_bt_uart_rts_n:gpio_bt_uart_rts_n { + gpios = <&gpio13 3 0>; + }; + gpio_bt_uart_rxd:gpio_bt_uart_rxd { + gpios = <&gpio13 4 0>; + }; + gpio_bt_uart_txd:gpio_bt_uart_txd { + gpios = <&gpio13 5 0>; + }; + gpio_gps_uart_cts_n:gpio_gps_uart_cts_n { + gpios = <&gpio13 6 0>; + }; + gpio_gps_uart_rts_n:gpio_gps_uart_rts_n { + gpios = <&gpio13 7 0>; + }; + gpio_gps_uart_rxd:gpio_gps_uart_rxd { + gpios = <&gpio14 0 0>; + }; + gpio_gps_uart_txd:gpio_gps_uart_txd { + gpios = <&gpio14 1 0>; + }; + gpio_i2c0_scl:gpio_i2c0_scl { + gpios = <&gpio14 2 0>; + }; + gpio_i2c0_sda:gpio_i2c0_sda { + gpios = <&gpio14 3 0>; + }; + gpio_i2c1_scl:gpio_i2c1_scl { + gpios = <&gpio14 4 0>; + }; + gpio_i2c1_sda:gpio_i2c1_sda { + gpios = <&gpio14 5 0>; + }; + gpio_i2c2_scl:gpio_i2c2_scl { + gpios = <&gpio14 6 0>; + }; + gpio_i2c2_sda:gpio_i2c2_sda { + gpios = <&gpio14 7 0>; + }; + gpio_emmc_clk:gpio_emmc_clk { + gpios; + }; + gpio_emmc_cmd:gpio_emmc_cmd { + gpios; + }; + gpio_emmc_data0:gpio_emmc_data0 { + gpios; + }; + gpio_emmc_data1:gpio_emmc_data1 { + gpios; + }; + gpio_emmc_data2:gpio_emmc_data2 { + gpios; + }; + gpio_emmc_data3:gpio_emmc_data3 { + gpios; + }; + gpio_emmc_data4:gpio_emmc_data4 { + gpios; + }; + gpio_emmc_data5:gpio_emmc_data5 { + gpios; + }; + gpio_emmc_data6:gpio_emmc_data6 { + gpios; + }; + gpio_emmc_data7:gpio_emmc_data7 { + gpios; + }; + gpio_emmc_rst_n:gpio_emmc_rst_n { + gpios; + }; + gpio_unused_006:gpio_unused_006 { + gpios; + }; + gpio_sdio_clk:gpio_sdio_clk { + gpios = <&gpio15 0 0>; + }; + gpio_sdio_cmd:gpio_sdio_cmd { + gpios = <&gpio15 1 0>; + }; + gpio_sdio_data0:gpio_sdio_data0 { + gpios = <&gpio15 2 0>; + }; + gpio_sdio_data1:gpio_sdio_data1 { + gpios = <&gpio15 3 0>; + }; + gpio_sdio_data2:gpio_sdio_data2 { + gpios = <&gpio15 4 0>; + }; + gpio_sdio_data3:gpio_sdio_data3 { + gpios = <&gpio15 5 0>; + }; + gpio_unused_007:gpio_unused_007 { + gpios; + }; + /* LCB: GPIO3_0, on J15, as general purpose input */ + gpio_j15_3_0:gpio_j15_3_0 { + gpios = <&gpio3 0 0>; + }; + gpio_jtag_sel0:gpio_jtag_sel0 { + gpios = <&gpio3 1 0>; + }; + gpio_jtag_sel1:gpio_jtag_sel1 { + gpios = <&gpio3 2 0>; + }; + gpio_lcd_rst_n:gpio_lcd_rst_n { + gpios = <&gpio3 3 0>; + }; + gpio_aux_ssi0:gpio_aux_ssi0 { + gpios = <&gpio3 4 0>; + }; + /* LCB: WLAN_ACTIVE_GPIO3_5, connects to led, as general purpose */ + gpio_wlan_active_led:gpio_wlan_active_led { + gpios = <&gpio3 5 0>; + }; + gpio_unused_008:gpio_unused_008 { + gpios = <&gpio3 6 0>; + }; + gpio_ap_wakeup_bt:gpio_ap_wakeup_bt { + gpios = <&gpio3 7 0>; + }; + /* LCB: USER_LED1_GPIO4_0 */ + gpio_user_led_1:gpio_user_led_1 { + gpios = <&gpio4 0 0>; + }; + /* LCB: USER_LED1_GPIO4_1 */ + gpio_user_led_2:gpio_user_led_2 { + gpios = <&gpio4 1 0>; + }; + /* LCB: USER_LED1_GPIO4_2 */ + gpio_user_led_3:gpio_user_led_3 { + gpios = <&gpio4 2 0>; + }; + /* LCB: USER_LED1_GPIO4_3 */ + gpio_user_led_4:gpio_user_led_4 { + gpios = <&gpio4 3 0>; + }; + gpio_i2c3_scl:gpio_i2c3_scl { + gpios = <&gpio4 4 0>; + }; + gpio_i2c3_sda:gpio_i2c3_sda { + gpios = <&gpio4 5 0>; + }; + gpio_wlan_bt_priority:gpio_wlan_bt_priority { + gpios = <&gpio4 6 0>; + }; + /* LCB: BT_ACTIVE_GPIO4_7, connects to led, as general purpose */ + gpio_bt_active_led:gpio_bt_active_led { + gpios = <&gpio4 7 0>; + }; + gpio_uart3_cts_n:gpio_uart3_cts_n { + gpios = <&gpio5 0 0>; + }; + gpio_uart3_rts_n:gpio_uart3_rts_n { + gpios = <&gpio5 1 0>; + }; + gpio_uart3_rxd:gpio_uart3_rxd { + gpios = <&gpio5 2 0>; + }; + gpio_uart3_txd:gpio_uart3_txd { + gpios = <&gpio5 3 0>; + }; + gpio_aux_ssi1:gpio_aux_ssi1 { + gpios = <&gpio5 4 0>; + }; + gpio_unused_009:gpio_unused_009 { + gpios = <&gpio5 5 0>; + }; + gpio_modem_pcm_xclk:gpio_modem_pcm_xclk { + gpios = <&gpio5 6 0>; + }; + gpio_modem_pcm_xfs:gpio_modem_pcm_xfs { + gpios = <&gpio5 7 0>; + }; + gpio_spi0_di:gpio_spi0_di { + gpios = <&gpio6 0 0>; + }; + gpio_spi0_do:gpio_spi0_do { + gpios = <&gpio6 1 0>; + }; + gpio_spi0_cs_n:gpio_spi0_cs_n { + gpios = <&gpio6 2 0>; + }; + gpio_spi0_clk:gpio_spi0_clk { + gpios = <&gpio6 3 0>; + }; + gpio_lte_tx_active:gpio_lte_tx_active { + gpios = <&gpio6 4 0>; + }; + gpio_lte_rx_active:gpio_lte_rx_active { + gpios = <&gpio6 5 0>; + }; + gpio_lcd_id0:gpio_lcd_id0 { + gpios = <&gpio6 6 0>; + }; + /* LCB: GPIO6_7_DSI_TE0 */ + gpio_dsi_te0:gpio_dsi_te0 { + gpios = <&gpio6 7 0>; + }; + gpio_lcd_id1:gpio_lcd_id1 { + gpios = <&gpio7 0 0>; + }; + gpio_volume1_n:gpio_volume1_n { + gpios = <&gpio7 1 0>; + }; + gpio_uart5_rxd:gpio_uart5_rxd { + gpios = <&gpio7 2 0>; + }; + gpio_uart5_txd:gpio_uart5_txd { + gpios = <&gpio7 3 0>; + }; + gpio_modem_pcm_di:gpio_modem_pcm_di { + gpios = <&gpio7 4 0>; + }; + gpio_modem_pcm_do:gpio_modem_pcm_do { + gpios = <&gpio7 5 0>; + }; + gpio_uart4_rxd:gpio_uart4_rxd { + gpios = <&gpio7 6 0>; + }; + gpio_uart4_txd:gpio_uart4_txd { + gpios = <&gpio7 7 0>; + }; + gpio_ap_wakeup_wl:gpio_ap_wakeup_wl { + gpios = <&gpio8 0 0>; + }; + gpio_mdm_pwr_en:gpio_mdm_pwr_en { + gpios = <&gpio8 1 0>; + }; + gpio_tcxo0_afc:gpio_tcxo0_afc { + gpios = <&gpio15 6 0>; + }; + gpio_rf_ssi0:gpio_rf_ssi0 { + gpios; + }; + gpio_rf_tcvr_on0:gpio_rf_tcvr_on0 { + gpios; + }; + gpio_rf_mipi_clk0:gpio_rf_mipi_clk0 { + gpios; + }; + gpio_rf_mipi_data0:gpio_rf_mipi_data0 { + gpios = <&gpio15 7 0>; + }; + gpio_flash_mask:gpio_flash_mask { + gpios = <&gpio16 0 0>; + }; + gpio_gps_blanking:gpio_gps_blanking { + gpios = <&gpio16 1 0>; + }; + gpio_rf_gpio_2:gpio_rf_gpio_2 { + gpios = <&gpio16 2 0>; + }; + gpio_rf_gpio_3:gpio_rf_gpio_3 { + gpios = <&gpio16 3 0>; + }; + gpio_rf_gpio_4:gpio_rf_gpio_4 { + gpios = <&gpio16 4 0>; + }; + gpio_rf_gpio_5:gpio_rf_gpio_5 { + gpios = <&gpio16 5 0>; + }; + gpio_rf_gpio_6:gpio_rf_gpio_6 { + gpios = <&gpio16 6 0>; + }; + gpio_rf_gpio_7:gpio_rf_gpio_7 { + gpios = <&gpio16 7 0>; + }; + gpio_rf_gpio_8:gpio_rf_gpio_8 { + gpios = <&gpio17 0 0>; + }; + gpio_rf_gpio_9:gpio_rf_gpio_9 { + gpios = <&gpio17 1 0>; + }; + gpio_rf_gpio_10:gpio_rf_gpio_10 { + gpios = <&gpio17 2 0>; + }; + gpio_rf_gpio_11:gpio_rf_gpio_11 { + gpios = <&gpio17 3 0>; + }; + gpio_rf_gpio_12:gpio_rf_gpio_12 { + gpios = <&gpio17 4 0>; + }; + gpio_rf_gpio_13:gpio_rf_gpio_13 { + gpios = <&gpio17 5 0>; + }; + gpio_rf_gpio_14:gpio_rf_gpio_14 { + gpios = <&gpio17 6 0>; + }; + gpio_rf_gpio_15:gpio_rf_gpio_15 { + gpios = <&gpio17 7 0>; + }; + gpio_rf_gpio_16:gpio_rf_gpio_16 { + gpios = <&gpio18 0 0>; + }; + gpio_rf_gpio_17:gpio_rf_gpio_17 { + gpios = <&gpio18 1 0>; + }; + gpio_rf_gpio_18:gpio_rf_gpio_18 { + gpios = <&gpio18 2 0>; + }; + gpio_rf_gpio_19:gpio_rf_gpio_19 { + gpios = <&gpio18 3 0>; + }; + gpio_rf_gpio_20:gpio_rf_gpio_20 { + gpios = <&gpio18 4 0>; + }; + gpio_rf_gpio_21:gpio_rf_gpio_21 { + gpios = <&gpio18 5 0>; + }; + gpio_rf_gpio_22:gpio_rf_gpio_22 { + gpios = <&gpio18 6 0>; + }; + gpio_rf_gpio_23:gpio_rf_gpio_23 { + gpios = <&gpio18 7 0>; + }; + gpio_rf_gpio_24:gpio_rf_gpio_24 { + gpios = <&gpio19 0 0>; + }; + gpio_rf_gpio_25:gpio_rf_gpio_25 { + gpios = <&gpio19 1 0>; + }; + gpio_rf_gpio_26:gpio_rf_gpio_26 { + gpios = <&gpio19 2 0>; + }; + gpio_rf_ssi1:gpio_rf_ssi1 { + gpios = <&gpio19 3 0>; + }; + gpio_rf_tcvr_on1:gpio_rf_tcvr_on1 { + gpios = <&gpio19 4 0>; + }; + gpio_rf_gpio_29:gpio_rf_gpio_29 { + gpios = <&gpio19 5 0>; + }; + gpio_rf_gpio_30:gpio_rf_gpio_30 { + gpios = <&gpio19 6 0>; + }; + gpio_apt_pdm0:gpio_apt_pdm0 { + gpios = <&gpio19 7 0>; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi new file mode 100644 index 000000000000..28806df214d7 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -0,0 +1,684 @@ +/* + * pinctrl dts fils for Hislicon HiKey development board + * + */ +#include <dt-bindings/pinctrl/hisi.h> + +/ { + soc { + pmx0: pinmux@f7010000 { + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_pmx_func + &hkadc_ssi_pmx_func + &codec_clk_pmx_func + &pwm_in_pmx_func + &bl_pwm_pmx_func + >; + + boot_sel_pmx_func: boot_sel_pmx_func { + pinctrl-single,pins = < + 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ + >; + }; + + emmc_pmx_func: emmc_pmx_func { + pinctrl-single,pins = < + 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ + 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ + 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ + 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ + 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ + 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ + 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ + 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ + 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ + 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ + >; + }; + + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0xc MUX_M0 /* SD_CLK (IOMG003) */ + 0x10 MUX_M0 /* SD_CMD (IOMG004) */ + 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ + >; + }; + sd_pmx_idle: sd_pmx_idle { + pinctrl-single,pins = < + 0xc MUX_M1 /* SD_CLK (IOMG003) */ + 0x10 MUX_M1 /* SD_CMD (IOMG004) */ + 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ + >; + }; + + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ + >; + }; + sdio_pmx_idle: sdio_pmx_idle { + pinctrl-single,pins = < + 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ + >; + }; + + isp_pmx_func: isp_pmx_func { + pinctrl-single,pins = < + 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ + 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ + 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ + 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ + 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ + 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ + 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ + 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ + 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ + 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ + 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ + 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ + 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ + 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ + 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ + 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ + >; + }; + + hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { + pinctrl-single,pins = < + 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ + >; + }; + + codec_clk_pmx_func: codec_clk_pmx_func { + pinctrl-single,pins = < + 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ + >; + }; + + codec_pmx_func: codec_pmx_func { + pinctrl-single,pins = < + 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ + 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ + 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ + 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ + >; + }; + + fm_pmx_func: fm_pmx_func { + pinctrl-single,pins = < + 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ + 0x84 MUX_M1 /* FM_XFS (IOMG033) */ + 0x88 MUX_M1 /* FM_DI (IOMG034) */ + 0x8c MUX_M1 /* FM_DO (IOMG035) */ + >; + }; + + bt_pmx_func: bt_pmx_func { + pinctrl-single,pins = < + 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ + 0x94 MUX_M0 /* BT_XFS (IOMG037) */ + 0x98 MUX_M0 /* BT_DI (IOMG038) */ + 0x9c MUX_M0 /* BT_DO (IOMG039) */ + >; + }; + + pwm_in_pmx_func: pwm_in_pmx_func { + pinctrl-single,pins = < + 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ + >; + }; + + bl_pwm_pmx_func: bl_pwm_pmx_func { + pinctrl-single,pins = < + 0xbc MUX_M1 /* BL_PWM (IOMG047) */ + >; + }; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ + 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ + >; + }; + + uart1_pmx_func: uart1_pmx_func { + pinctrl-single,pins = < + 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ + 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ + 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ + 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ + 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ + 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ + 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ + 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ + 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ + 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ + 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ + 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ + 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ + >; + }; + + uart5_pmx_func: uart5_pmx_func { + pinctrl-single,pins = < + 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ + 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ + 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ + 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ + >; + }; + + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ + 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ + >; + }; + }; + + pmx1: pinmux@f7010800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_cfg_func + &hkadc_ssi_cfg_func + &codec_clk_cfg_func + &pwm_in_cfg_func + &bl_pwm_cfg_func + >; + + boot_sel_cfg_func: boot_sel_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* BOOT_SEL (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { + pinctrl-single,pins = < + 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + emmc_clk_cfg_func: emmc_clk_cfg_func { + pinctrl-single,pins = < + 0x104 0x0 /* EMMC_CLK (IOCFG065) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; + }; + + emmc_cfg_func: emmc_cfg_func { + pinctrl-single,pins = < + 0x108 0x0 /* EMMC_CMD (IOCFG066) */ + 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ + 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ + 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ + 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ + 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ + 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ + 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ + 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + + emmc_rst_cfg_func: emmc_rst_cfg_func { + pinctrl-single,pins = < + 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>; + }; + sd_clk_cfg_idle: sd_clk_cfg_idle { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; + }; + sd_cfg_idle: sd_cfg_idle { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; + }; + sdio_clk_cfg_idle: sdio_clk_cfg_idle { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + sdio_cfg_idle: sdio_cfg_idle { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + isp_cfg_func1: isp_cfg_func1 { + pinctrl-single,pins = < + 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ + 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ + 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + 0x3c 0x0 /* ISP_PWM (IOCFG015) */ + 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ + 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ + 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ + 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ + 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ + 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ + 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ + 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ + 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + isp_cfg_idle1: isp_cfg_idle1 { + pinctrl-single,pins = < + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + isp_cfg_func2: isp_cfg_func2 { + pinctrl-single,pins = < + 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + codec_clk_cfg_func: codec_clk_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + codec_clk_cfg_idle: codec_clk_cfg_idle { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + codec_cfg_func1: codec_cfg_func1 { + pinctrl-single,pins = < + 0x74 0x0 /* DMIC_CLK (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + codec_cfg_func2: codec_cfg_func2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + codec_cfg_idle2: codec_cfg_idle2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + fm_cfg_func: fm_cfg_func { + pinctrl-single,pins = < + 0x84 0x0 /* FM_XCLK (IOCFG033) */ + 0x88 0x0 /* FM_XFS (IOCFG034) */ + 0x8c 0x0 /* FM_DI (IOCFG035) */ + 0x90 0x0 /* FM_DO (IOCFG036) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + bt_cfg_func: bt_cfg_func { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + bt_cfg_idle: bt_cfg_idle { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + pwm_in_cfg_func: pwm_in_cfg_func { + pinctrl-single,pins = < + 0xbc 0x0 /* PWM_IN (IOCFG047) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + bl_pwm_cfg_func: bl_pwm_cfg_func { + pinctrl-single,pins = < + 0xc0 0x0 /* BL_PWM (IOCFG048) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart0_cfg_func1: uart0_cfg_func1 { + pinctrl-single,pins = < + 0xc4 0x0 /* UART0_RXD (IOCFG049) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart0_cfg_func2: uart0_cfg_func2 { + pinctrl-single,pins = < + 0xc8 0x0 /* UART0_TXD (IOCFG050) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; + }; + + uart1_cfg_func1: uart1_cfg_func1 { + pinctrl-single,pins = < + 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ + 0xd4 0x0 /* UART1_RXD (IOCFG053) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart1_cfg_func2: uart1_cfg_func2 { + pinctrl-single,pins = < + 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ + 0xd8 0x0 /* UART1_TXD (IOCFG054) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ + 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ + 0xe4 0x0 /* UART2_RXD (IOCFG057) */ + 0xe8 0x0 /* UART2_TXD (IOCFG058) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ + 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ + 0x198 0x0 /* UART3_RXD (IOCFG102) */ + 0x19c 0x0 /* UART3_TXD (IOCFG103) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ + 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ + 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ + 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ + 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0xec 0x0 /* I2C0_SCL (IOCFG059) */ + 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ + 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ + 0x100 0x0 /* I2C2_SDA (IOCFG064) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + }; + + pmx2: pinmux@f8001800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &rstout_n_cfg_func + >; + + rstout_n_cfg_func: rstout_n_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* RSTOUT_N (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { + pinctrl-single,pins = < + 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + sysclk0_en_cfg_func: sysclk0_en_cfg_func { + pinctrl-single,pins = < + 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + jtag_tdo_cfg_func: jtag_tdo_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* JTAG_TDO (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; + }; + + rf_reset_cfg_func: rf_reset_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* RF_RESET0 (IOCFG028) */ + 0x74 0x0 /* RF_RESET1 (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + }; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34d71dd86781..e6dac77be183 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -37,11 +37,11 @@ CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_FSL_LS2085A=y CONFIG_ARCH_HISI=y CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_QCOM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_QCOM=y CONFIG_ARCH_SPRD=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y @@ -50,7 +50,6 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_XGENE=y -CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y @@ -70,7 +69,20 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_BPF_JIT=y -# CONFIG_WIRELESS is not set +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_DEBUG_MENU=y +CONFIG_RFKILL=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_RFKILL_GPIO=y CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y # CONFIG_TEGRA_AHB is not set @@ -97,7 +109,9 @@ CONFIG_NET_XGENE=y CONFIG_SKY2=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -# CONFIG_WLAN is not set +CONFIG_WL_TI=y +CONFIG_WL18XX=y +CONFIG_WLCORE_SDIO=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_SERIO_SERPORT is not set @@ -116,16 +130,22 @@ CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MSM8916=y CONFIG_GPIO_PL061=y CONFIG_GPIO_XGENE=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y # CONFIG_HWMON is not set +CONFIG_MFD_HI655X_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_HI655X=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -141,14 +161,16 @@ CONFIG_USB_STORAGE=y CONFIG_USB_ISP1760=y CONFIG_USB_ULPI=y CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=64 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_K3=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y @@ -159,13 +181,12 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_COMMON_CLK_QCOM=y CONFIG_MSM_GCC_8916=y +CONFIG_MAILBOX=y +CONFIG_HI6220_MBOX=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PHY_XGENE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y CONFIG_QUOTA=y diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 4563343b6420..c1c340cc5e31 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -110,11 +110,11 @@ static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", }; static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", }; static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { - { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, + { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_rst_clk", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, { HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, - { HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, }, + { HI6220_MMC1_CLK, "mmc1_clk", "mmc1_rst_clk", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, }, { HI6220_MMC1_CIUCLK, "mmc1_ciuclk", "mmc1_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, }, - { HI6220_MMC2_CLK, "mmc2_clk", "mmc2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, }, + { HI6220_MMC2_CLK, "mmc2_clk", "mmc2_rst_clk", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, }, { HI6220_MMC2_CIUCLK, "mmc2_ciuclk", "mmc2_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, }, { HI6220_USBOTG_HCLK, "usbotg_hclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 4, 0, }, { HI6220_CLK_PICOPHY, "clk_picophy", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 5, 0, }, @@ -145,6 +145,12 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, }, }; +static struct hisi_gate_clock hi6220_reset_clks[] __initdata = { + { 0, "mmc0_rst_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x304, 0, 0, }, + { 0, "mmc1_rst_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x304, 1, 0, }, + { 0, "mmc2_rst_clk", "mmc2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x304, 2, 0, }, +}; + static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = { { HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, { HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, @@ -184,6 +190,9 @@ static void __init hi6220_clk_sys_init(struct device_node *np) if (!clk_data) return; + hisi_clk_register_gate(hi6220_reset_clks, + ARRAY_SIZE(hi6220_reset_clks), clk_data); + hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index bbec5009cdc2..41fb7fac1337 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -71,4 +71,12 @@ config BCM2835_MBOX the services of the Videocore. Say Y here if you want to use the BCM2835 Mailbox. +config HI6220_MBOX + tristate "Hi6220 Mailbox" + depends on ARCH_HISI + help + An implementation of the hi6220 mailbox. It is used to send message + between application processors and MCU. Say Y here if you want to build + the Hi6220 mailbox controller driver. + endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 8e6d82218a09..4ba9f5fe5f7d 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_PCC) += pcc.o obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o + +obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o diff --git a/drivers/mailbox/hi6220-mailbox.c b/drivers/mailbox/hi6220-mailbox.c new file mode 100644 index 000000000000..8f63d0d42277 --- /dev/null +++ b/drivers/mailbox/hi6220-mailbox.c @@ -0,0 +1,519 @@ +/* + * Hisilicon's Hi6220 mailbox driver + * + * RX channel's message queue is based on the code written in + * drivers/mailbox/omap-mailbox.c. + * + * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 Linaro Limited. + * + * Author: Leo Yan <leo.yan@linaro.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/device.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kfifo.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/slab.h> + +#define HI6220_MBOX_CHAN_MAX 32 +#define HI6220_MBOX_CHAN_NUM 2 +#define HI6220_MBOX_CHAN_SLOT_SIZE 64 + +#define HI6220_MBOX_RX 0x0 +#define HI6220_MBOX_TX 0x1 + +/* Mailbox message length: 32 bytes */ +#define HI6220_MBOX_MSG_LEN 32 + +/* Mailbox kfifo size */ +#define HI6220_MBOX_MSG_FIFO_SIZE 512 + +/* Status & Mode Register */ +#define HI6220_MBOX_MODE_REG 0x0 + +#define HI6220_MBOX_STATUS_MASK (0xF << 4) +#define HI6220_MBOX_STATUS_IDLE (0x1 << 4) +#define HI6220_MBOX_STATUS_TX (0x2 << 4) +#define HI6220_MBOX_STATUS_RX (0x4 << 4) +#define HI6220_MBOX_STATUS_ACK (0x8 << 4) +#define HI6220_MBOX_ACK_CONFIG_MASK (0x1 << 0) +#define HI6220_MBOX_ACK_AUTOMATIC (0x1 << 0) +#define HI6220_MBOX_ACK_IRQ (0x0 << 0) + +/* Data Registers */ +#define HI6220_MBOX_DATA_REG(i) (0x4 + (i << 2)) + +/* ACPU Interrupt Register */ +#define HI6220_MBOX_ACPU_INT_RAW_REG 0x400 +#define HI6220_MBOX_ACPU_INT_MSK_REG 0x404 +#define HI6220_MBOX_ACPU_INT_STAT_REG 0x408 +#define HI6220_MBOX_ACPU_INT_CLR_REG 0x40c +#define HI6220_MBOX_ACPU_INT_ENA_REG 0x500 +#define HI6220_MBOX_ACPU_INT_DIS_REG 0x504 + +/* MCU Interrupt Register */ +#define HI6220_MBOX_MCU_INT_RAW_REG 0x420 + +/* Core Id */ +#define HI6220_CORE_ACPU 0x0 +#define HI6220_CORE_MCU 0x2 + +struct hi6220_mbox_queue { + struct kfifo fifo; + struct work_struct work; + struct mbox_chan *chan; + bool full; +}; + +struct hi6220_mbox_chan { + + /* + * Description for channel's hardware info: + * - direction; + * - peer core id for communication; + * - local irq vector or number; + * - remoted irq vector or number for peer core; + */ + unsigned int dir; + unsigned int peer_core; + unsigned int remote_irq; + unsigned int local_irq; + + /* + * Slot address is cached value derived from index + * within buffer for every channel + */ + void __iomem *slot; + + /* For rx's fifo operations */ + struct hi6220_mbox_queue *mq; + + struct hi6220_mbox *parent; +}; + +struct hi6220_mbox { + struct device *dev; + + spinlock_t lock; + + int irq; + + /* flag of enabling tx's irq mode */ + bool tx_irq_mode; + + /* region for ipc event */ + void __iomem *ipc; + + /* region for share mem */ + void __iomem *buf; + + unsigned int chan_num; + struct hi6220_mbox_chan *mchan; + + void *irq_map_chan[HI6220_MBOX_CHAN_MAX]; + struct mbox_chan *chan; + struct mbox_controller controller; +}; + +static void hi6220_mbox_set_status(struct hi6220_mbox_chan *mchan, u32 val) +{ + u32 status; + + status = readl(mchan->slot + HI6220_MBOX_MODE_REG); + status &= ~HI6220_MBOX_STATUS_MASK; + status |= val; + writel(status, mchan->slot + HI6220_MBOX_MODE_REG); +} + +static void hi6220_mbox_set_mode(struct hi6220_mbox_chan *mchan, u32 val) +{ + u32 mode; + + mode = readl(mchan->slot + HI6220_MBOX_MODE_REG); + mode &= ~HI6220_MBOX_ACK_CONFIG_MASK; + mode |= val; + writel(mode, mchan->slot + HI6220_MBOX_MODE_REG); +} + +static bool hi6220_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + u32 status; + + /* Only set idle state for polling mode */ + BUG_ON(mbox->tx_irq_mode); + + status = readl(mchan->slot + HI6220_MBOX_MODE_REG); + status = status & HI6220_MBOX_STATUS_MASK; + return (status == HI6220_MBOX_STATUS_IDLE); +} + +static int hi6220_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + int irq = mchan->remote_irq; + u32 *buf = msg; + unsigned long flags; + int i; + + hi6220_mbox_set_status(mchan, HI6220_MBOX_STATUS_TX); + + if (mbox->tx_irq_mode) + hi6220_mbox_set_mode(mchan, HI6220_MBOX_ACK_IRQ); + else + hi6220_mbox_set_mode(mchan, HI6220_MBOX_ACK_AUTOMATIC); + + for (i = 0; i < (HI6220_MBOX_MSG_LEN >> 2); i++) + writel(buf[i], mchan->slot + HI6220_MBOX_DATA_REG(i)); + + /* trigger remote request */ + spin_lock_irqsave(&mbox->lock, flags); + writel(1 << irq, mbox->ipc + HI6220_MBOX_MCU_INT_RAW_REG); + spin_unlock_irqrestore(&mbox->lock, flags); + return 0; +} + +static void hi6220_mbox_rx_work(struct work_struct *work) +{ + struct hi6220_mbox_queue *mq = + container_of(work, struct hi6220_mbox_queue, work); + struct mbox_chan *chan = mq->chan; + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + int irq = mchan->local_irq, len; + u32 msg[HI6220_MBOX_MSG_LEN >> 2]; + + while (kfifo_len(&mq->fifo) >= sizeof(msg)) { + len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + WARN_ON(len != sizeof(msg)); + + mbox_chan_received_data(chan, (void *)msg); + spin_lock_irq(&mbox->lock); + if (mq->full) { + mq->full = false; + writel(1 << irq, + mbox->ipc + HI6220_MBOX_ACPU_INT_ENA_REG); + } + spin_unlock_irq(&mbox->lock); + } +} + +static void hi6220_mbox_tx_interrupt(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + int irq = mchan->local_irq; + + spin_lock(&mbox->lock); + writel(1 << irq, mbox->ipc + HI6220_MBOX_ACPU_INT_CLR_REG); + spin_unlock(&mbox->lock); + + hi6220_mbox_set_status(mchan, HI6220_MBOX_STATUS_IDLE); + mbox_chan_txdone(chan, 0); +} + +static void hi6220_mbox_rx_interrupt(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox_queue *mq = mchan->mq; + struct hi6220_mbox *mbox = mchan->parent; + int irq = mchan->local_irq; + int msg[HI6220_MBOX_MSG_LEN >> 2]; + int i, len; + + if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { + spin_lock(&mbox->lock); + writel(1 << irq, mbox->ipc + HI6220_MBOX_ACPU_INT_DIS_REG); + mq->full = true; + spin_unlock(&mbox->lock); + goto nomem; + } + + for (i = 0; i < (HI6220_MBOX_MSG_LEN >> 2); i++) + msg[i] = readl(mchan->slot + HI6220_MBOX_DATA_REG(i)); + + /* clear IRQ source */ + spin_lock(&mbox->lock); + writel(1 << irq, mbox->ipc + HI6220_MBOX_ACPU_INT_CLR_REG); + spin_unlock(&mbox->lock); + + hi6220_mbox_set_status(mchan, HI6220_MBOX_STATUS_IDLE); + + len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + WARN_ON(len != sizeof(msg)); + +nomem: + schedule_work(&mq->work); +} + +static irqreturn_t hi6220_mbox_interrupt(int irq, void *p) +{ + struct hi6220_mbox *mbox = p; + struct hi6220_mbox_chan *mchan; + struct mbox_chan *chan; + unsigned int state; + unsigned int intr_bit; + + state = readl(mbox->ipc + HI6220_MBOX_ACPU_INT_STAT_REG); + if (!state) { + dev_warn(mbox->dev, "%s: spurious interrupt\n", + __func__); + return IRQ_HANDLED; + } + + while (state) { + intr_bit = __ffs(state); + state &= (state - 1); + + chan = mbox->irq_map_chan[intr_bit]; + if (!chan) { + dev_warn(mbox->dev, "%s: unexpected irq vector %d\n", + __func__, intr_bit); + continue; + } + + mchan = chan->con_priv; + if (mchan->dir == HI6220_MBOX_TX) + hi6220_mbox_tx_interrupt(chan); + else + hi6220_mbox_rx_interrupt(chan); + } + + return IRQ_HANDLED; +} + +static struct hi6220_mbox_queue *hi6220_mbox_queue_alloc( + struct mbox_chan *chan, + void (*work)(struct work_struct *)) +{ + struct hi6220_mbox_queue *mq; + + mq = kzalloc(sizeof(struct hi6220_mbox_queue), GFP_KERNEL); + if (!mq) + return NULL; + + if (kfifo_alloc(&mq->fifo, HI6220_MBOX_MSG_FIFO_SIZE, GFP_KERNEL)) + goto error; + + mq->chan = chan; + INIT_WORK(&mq->work, work); + return mq; + +error: + kfree(mq); + return NULL; +} + +static void hi6220_mbox_queue_free(struct hi6220_mbox_queue *mq) +{ + kfifo_free(&mq->fifo); + kfree(mq); +} + +static int hi6220_mbox_startup(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + unsigned int irq = mchan->local_irq; + struct hi6220_mbox_queue *mq; + unsigned long flags; + + mq = hi6220_mbox_queue_alloc(chan, hi6220_mbox_rx_work); + if (!mq) + return -ENOMEM; + mchan->mq = mq; + mbox->irq_map_chan[irq] = (void *)chan; + + /* enable interrupt */ + spin_lock_irqsave(&mbox->lock, flags); + writel(1 << irq, mbox->ipc + HI6220_MBOX_ACPU_INT_ENA_REG); + spin_unlock_irqrestore(&mbox->lock, flags); + return 0; +} + +static void hi6220_mbox_shutdown(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + unsigned int irq = mchan->local_irq; + unsigned long flags; + + /* disable interrupt */ + spin_lock_irqsave(&mbox->lock, flags); + writel(1 << irq, mbox->ipc + HI6220_MBOX_ACPU_INT_DIS_REG); + spin_unlock_irqrestore(&mbox->lock, flags); + + mbox->irq_map_chan[irq] = NULL; + flush_work(&mchan->mq->work); + hi6220_mbox_queue_free(mchan->mq); +} + +static struct mbox_chan_ops hi6220_mbox_chan_ops = { + .send_data = hi6220_mbox_send_data, + .startup = hi6220_mbox_startup, + .shutdown = hi6220_mbox_shutdown, + .last_tx_done = hi6220_mbox_last_tx_done, +}; + +static void hi6220_mbox_init_hw(struct hi6220_mbox *mbox) +{ + struct hi6220_mbox_chan init_data[HI6220_MBOX_CHAN_NUM] = { + { HI6220_MBOX_RX, HI6220_CORE_MCU, 1, 10 }, + { HI6220_MBOX_TX, HI6220_CORE_MCU, 0, 11 }, + }; + struct hi6220_mbox_chan *mchan = mbox->mchan; + int i; + + for (i = 0; i < HI6220_MBOX_CHAN_NUM; i++) { + memcpy(&mchan[i], &init_data[i], sizeof(*mchan)); + mchan[i].slot = mbox->buf + HI6220_MBOX_CHAN_SLOT_SIZE * i; + mchan[i].parent = mbox; + } + + /* mask and clear all interrupt vectors */ + writel(0x0, mbox->ipc + HI6220_MBOX_ACPU_INT_MSK_REG); + writel(~0x0, mbox->ipc + HI6220_MBOX_ACPU_INT_CLR_REG); + + /* use interrupt for tx's ack */ + mbox->tx_irq_mode = true; +} + +static const struct of_device_id hi6220_mbox_of_match[] = { + { .compatible = "hisilicon,hi6220-mbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, hi6220_mbox_of_match); + +static int hi6220_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hi6220_mbox *mbox; + struct resource *res; + int i, err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->dev = dev; + mbox->chan_num = HI6220_MBOX_CHAN_NUM; + mbox->mchan = devm_kzalloc(dev, + mbox->chan_num * sizeof(*mbox->mchan), GFP_KERNEL); + if (!mbox->mchan) + return -ENOMEM; + + mbox->chan = devm_kzalloc(dev, + mbox->chan_num * sizeof(*mbox->chan), GFP_KERNEL); + if (!mbox->chan) + return -ENOMEM; + + mbox->irq = platform_get_irq(pdev, 0); + if (mbox->irq < 0) + return mbox->irq; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->ipc = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->ipc)) { + dev_err(dev, "ioremap ipc failed\n"); + return PTR_ERR(mbox->ipc); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mbox->buf = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->buf)) { + dev_err(dev, "ioremap buffer failed\n"); + return PTR_ERR(mbox->buf); + } + + err = devm_request_irq(dev, mbox->irq, hi6220_mbox_interrupt, 0, + dev_name(dev), mbox); + if (err) { + dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", + err); + return -ENODEV; + } + + /* init hardware parameters */ + hi6220_mbox_init_hw(mbox); + + spin_lock_init(&mbox->lock); + + for (i = 0; i < mbox->chan_num; i++) { + mbox->chan[i].con_priv = &mbox->mchan[i]; + mbox->irq_map_chan[i] = NULL; + } + + mbox->controller.dev = dev; + mbox->controller.chans = &mbox->chan[0]; + mbox->controller.num_chans = mbox->chan_num; + mbox->controller.ops = &hi6220_mbox_chan_ops; + + if (mbox->tx_irq_mode) + mbox->controller.txdone_irq = true; + else { + mbox->controller.txdone_poll = true; + mbox->controller.txpoll_period = 5; + } + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + return 0; +} + +static int hi6220_mbox_remove(struct platform_device *pdev) +{ + struct hi6220_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + return 0; +} + +static struct platform_driver hi6220_mbox_driver = { + .driver = { + .name = "hi6220-mbox", + .owner = THIS_MODULE, + .of_match_table = hi6220_mbox_of_match, + }, + .probe = hi6220_mbox_probe, + .remove = hi6220_mbox_remove, +}; + +static int __init hi6220_mbox_init(void) +{ + return platform_driver_register(&hi6220_mbox_driver); +} +core_initcall(hi6220_mbox_init); + +static void __exit hi6220_mbox_exit(void) +{ + platform_driver_unregister(&hi6220_mbox_driver); +} +module_exit(hi6220_mbox_exit); + +MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>"); +MODULE_DESCRIPTION("Hi6220 mailbox driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 99d63675f073..d320def0fdd7 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -273,6 +273,15 @@ config MFD_HI6421_PMIC menus in order to enable them. We communicate with the Hi6421 via memory-mapped I/O. +config MFD_HI655X_PMIC + tristate "HiSilicon Hi655X series PMU/Codec IC" + depends on ARCH_HISI + depends on OF + select MFD_CORE + select REGMAP_MMIO + help + Select this option to enable Hisilicon hi655x series pmic driver. + config HTC_EGPIO bool "HTC EGPIO support" depends on GPIOLIB && ARM diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index a59e3fcc8626..11ec427e6f70 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -185,6 +185,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o +obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o obj-$(CONFIG_MFD_DLN2) += dln2.o obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c new file mode 100644 index 000000000000..caeca4e3c5cd --- /dev/null +++ b/drivers/mfd/hi655x-pmic.c @@ -0,0 +1,358 @@ +/* + * Device driver for PMIC DRIVER in HI655X IC + * + * Copyright (c) 2015 Hisilicon Co. Ltd + * + * Fei Wang <w.f@huawei.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/types.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/hardirq.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/of_platform.h> +#include <linux/irqdomain.h> +#include <linux/mfd/hi655x-pmic.h> +#include <linux/regmap.h> + + +static const struct of_device_id of_hi655x_pmic_child_match_tbl[] = { + { .compatible = "hisilicon,hi655x-regulator-pmic", }, + { .compatible = "hisilicon,hi655x-powerkey", }, + { .compatible = "hisilicon,hi655x-usbvbus", }, + { .compatible = "hisilicon,hi655x-coul", }, + { .compatible = "hisilicon,hi655x-pmu-rtc", }, + {}, +}; + +static const struct of_device_id of_hi655x_pmic_match_tbl[] = { + { .compatible = "hisilicon,hi655x-pmic-driver", }, + {}, +}; + +static unsigned int hi655x_pmic_get_version(struct hi655x_pmic *pmic) +{ + u32 val; + + regmap_read(pmic->regmap, + HI655X_REG_TO_BUS_ADDR(HI655X_VER_REG), &val); + + return val; +} + +static irqreturn_t hi655x_pmic_irq_handler(int irq, void *data) +{ + struct hi655x_pmic *pmic = (struct hi655x_pmic *)data; + u32 pending; + u32 ret = IRQ_NONE; + unsigned long offset; + int i; + + for (i = 0; i < HI655X_IRQ_ARRAY; i++) { + regmap_read(pmic->regmap, + HI655X_REG_TO_BUS_ADDR(i + HI655X_IRQ_STAT_BASE), + &pending); + if (pending != 0) + pr_debug("pending[%d]=0x%x\n\r", i, pending); + + /* clear pmic-sub-interrupt */ + regmap_write(pmic->regmap, + HI655X_REG_TO_BUS_ADDR(i + HI655X_IRQ_STAT_BASE), + pending); + + if (pending) { + for_each_set_bit(offset, (unsigned long *)&pending, + HI655X_BITS) + generic_handle_irq(pmic->irqs[offset + + i * HI655X_BITS]); + ret = IRQ_HANDLED; + } + } + return ret; +} + + +static void hi655x_pmic_irq_mask(struct irq_data *d) +{ + + u32 data, offset; + unsigned long pmic_spin_flag = 0; + struct hi655x_pmic *pmic = irq_data_get_irq_chip_data(d); + + offset = ((irqd_to_hwirq(d) >> 3) + HI655X_IRQ_MASK_BASE); + spin_lock_irqsave(&pmic->ssi_hw_lock, pmic_spin_flag); + regmap_read(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), &data); + data |= (1 << (irqd_to_hwirq(d) & 0x07)); + regmap_write(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), data); + spin_unlock_irqrestore(&pmic->ssi_hw_lock, pmic_spin_flag); +} + +static void hi655x_pmic_irq_unmask(struct irq_data *d) +{ + u32 data, offset; + unsigned long pmic_spin_flag = 0; + struct hi655x_pmic *pmic = irq_data_get_irq_chip_data(d); + + offset = ((irqd_to_hwirq(d) >> 3) + HI655X_IRQ_MASK_BASE); + spin_lock_irqsave(&pmic->ssi_hw_lock, pmic_spin_flag); + regmap_read(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), &data); + data &= ~(1 << (irqd_to_hwirq(d) & 0x07)); + regmap_write(pmic->regmap, HI655X_REG_TO_BUS_ADDR(offset), data); + spin_unlock_irqrestore(&pmic->ssi_hw_lock, pmic_spin_flag); +} + + +static struct irq_chip hi655x_pmic_irqchip = { + .name = "hisi-hi655x-pmic-irqchip", + .irq_mask = hi655x_pmic_irq_mask, + .irq_unmask = hi655x_pmic_irq_unmask, +}; + +static int hi655x_pmic_irq_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct hi655x_pmic *pmic = d->host_data; + + irq_set_chip_and_handler_name(virq, &hi655x_pmic_irqchip, + handle_simple_irq, "hisi-hi655x-pmic-irqchip"); + irq_set_chip_data(virq, pmic); + irq_set_irq_type(virq, IRQ_TYPE_NONE); + + return 0; +} + +static struct irq_domain_ops hi655x_domain_ops = { + .map = hi655x_pmic_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static inline void hi655x_pmic_clear_int(struct hi655x_pmic *pmic) +{ + int addr; + + for (addr = HI655X_IRQ_STAT_BASE; addr < (HI655X_IRQ_STAT_BASE + + HI655X_IRQ_ARRAY); addr++) { + regmap_write(pmic->regmap, + HI655X_REG_TO_BUS_ADDR(addr), HI655X_IRQ_CLR); + } +} + +static inline void hi655x_pmic_mask_int(struct hi655x_pmic *pmic) +{ + int addr; + + for (addr = HI655X_IRQ_MASK_BASE; addr < (HI655X_IRQ_MASK_BASE + + HI655X_IRQ_ARRAY); addr++) { + regmap_write(pmic->regmap, + HI655X_REG_TO_BUS_ADDR(addr), HI655X_IRQ_MASK); + } +} + + + +static struct regmap_config hi655x_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 8, + .max_register = HI655X_REG_TO_BUS_ADDR(0xFF), +}; + + +static int hi655x_pmic_probe(struct platform_device *pdev) +{ + int i = 0; + int ret = 0; + u32 virq = 0; + int pmu_on = 1; + enum of_gpio_flags gpio_flags; + + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct hi655x_pmic *pmic = NULL; + struct device_node *gpio_np = NULL; + void __iomem *base; + + pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); + + /* + * init spin lock + */ + spin_lock_init(&pmic->ssi_hw_lock); + + /* + * get resources + */ + pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!pmic->res) { + dev_err(dev, "platform_get_resource err\n"); + return -ENOENT; + } + if (!devm_request_mem_region(dev, pmic->res->start, + resource_size(pmic->res), pdev->name)) { + dev_err(dev, "cannot claim register memory\n"); + return -ENOMEM; + } + base = ioremap(pmic->res->start, resource_size(pmic->res)); + if (!base) { + dev_err(dev, "cannot map register memory\n"); + return -ENOMEM; + } + pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base, + &hi655x_regmap_config); + + /* + * confirm pmu is exist&effective + */ + + pmic->ver = hi655x_pmic_get_version(pmic); + if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) { + dev_warn(dev, "it is wrong pmu version\n"); + pmu_on = 0; + } + + regmap_write(pmic->regmap, HI655X_REG_TO_BUS_ADDR(0x1b5), 0xff); + + gpio_np = of_parse_phandle(np, "pmu_irq_gpio", 0); + if (!gpio_np) { + dev_err(dev, "can't parse property\n"); + return -ENOENT; + } + pmic->gpio = of_get_gpio_flags(gpio_np, 0, &gpio_flags); + if (pmic->gpio < 0) { + dev_err(dev, "failed to of_get_gpio_flags %d\n", pmic->gpio); + return pmic->gpio; + } + if (!gpio_is_valid(pmic->gpio)) { + dev_err(dev, "it is invalid gpio %d\n", pmic->gpio); + return -EINVAL; + } + ret = gpio_request_one(pmic->gpio, GPIOF_IN, "hi655x_pmic_irq"); + if (ret < 0) { + dev_err(dev, "failed to request gpio %d ret = %d\n", + pmic->gpio, ret); + return ret; + } + pmic->irq = gpio_to_irq(pmic->gpio); + + /* + * clear PMIC sub-interrupt + */ + hi655x_pmic_clear_int(pmic); + + /* + * mask PMIC sub-interrupt + */ + hi655x_pmic_mask_int(pmic); + + /* + * register irq domain + */ + pmic->domain = irq_domain_add_simple(np, + HI655X_NR_IRQ, 0, &hi655x_domain_ops, pmic); + if (!pmic->domain) { + dev_err(dev, "failed irq domain add simple!\n"); + ret = -ENODEV; + goto irq_domain_add_simple; + } + + /* + * here call map function + */ + for (i = 0; i < HI655X_NR_IRQ; i++) { + virq = irq_create_mapping(pmic->domain, i); + if (0 == virq) { + dev_err(dev, "Failed mapping hwirq\n"); + ret = -ENOSPC; + goto irq_create_mapping; + } + pmic->irqs[i] = virq; + } + + /* + * We must make sure the GPIO status which is high. + */ + if (pmu_on) { + ret = request_threaded_irq(pmic->irq, hi655x_pmic_irq_handler, + NULL, IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND, + "hi655x-pmic-irq", pmic); + if (ret < 0) { + dev_err(dev, "could not claim pmic %d\n", ret); + ret = -ENODEV; + goto request_threaded_irq; + } + } + + pmic->dev = dev; + + /* + * bind pmic to device + */ + platform_set_drvdata(pdev, pmic); + + /* + * populate sub nodes + */ + of_platform_populate(np, of_hi655x_pmic_child_match_tbl, NULL, dev); + return 0; +irq_domain_add_simple: +irq_create_mapping: +request_threaded_irq: + free_irq(pmic->irq, pmic); + gpio_free(pmic->gpio); + return ret; +} + +static int hi655x_pmic_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hi655x_pmic *pmic = platform_get_drvdata(pdev); + + free_irq(pmic->irq, pmic); + gpio_free(pmic->gpio); + devm_release_mem_region(dev, pmic->res->start, + resource_size(pmic->res)); + devm_kfree(dev, pmic); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct platform_driver hi655x_pmic_driver = { + .driver = { + .name = "hisi,hi655x-pmic", + .owner = THIS_MODULE, + .of_match_table = of_hi655x_pmic_match_tbl, + }, + .probe = hi655x_pmic_probe, + .remove = hi655x_pmic_remove, +}; +module_platform_driver(hi655x_pmic_driver); + +MODULE_AUTHOR("Fei Wang <w.f@huawei.com>"); +MODULE_DESCRIPTION("Hisi hi655x pmic driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 93b5ce8e516b..fb2f17e1f730 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -535,6 +535,14 @@ config UID_CPUTIME help Per UID based cpu time statistics exported to /proc/uid_cputime +config HI6220_SYSCFG + bool "Hisilicon HI6220 System Configuration driver" + depends on ARCH_HISI + default y + help + Hisilicon HI6220 uses some registers to configure some chip hosts to + work or not, e.g. disable the UART hosts reset and let's them work. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 24483a6caa6b..0618dc379ece 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -58,3 +58,4 @@ obj-$(CONFIG_ECHO) += echo/ obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o obj-$(CONFIG_CXL_BASE) += cxl/ obj-$(CONFIG_UID_CPUTIME) += uid_cputime.o +obj-$(CONFIG_HI6220_SYSCFG) += hi6220-sysconfig.o diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c new file mode 100644 index 000000000000..db82b8a6ca43 --- /dev/null +++ b/drivers/misc/hi6220-sysconfig.c @@ -0,0 +1,85 @@ +/* + * For Hisilicon Hi6220 SoC, the reset of some hosts (e.g. UART) should be disabled + * before using them, this driver will handle the host chip reset disable. + * + * Copyright (C) 2015 Hisilicon Ltd. + * Author: Bintian Wang <bintian.wang@huawei.com> + * + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define reset_offset 0x334 +#define pclk_offset 0x230 +#define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base) + +static int __init hi6220_sysconf(void) +{ + static void __iomem *base = NULL, *base1 = NULL; + struct device_node *node, *node1; + unsigned char ret; + + node = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220-sysctrl"); + if (!node) + return -ENOENT; + + base = of_iomap(node, 0); + if (base == NULL) { + printk(KERN_ERR "hi6220: sysctrl reg iomap failed!\n"); + return -ENOMEM; + } + + node1 = of_find_compatible_node(NULL, NULL, "hisilicon,hi655x-pmic-driver"); + if (!node1) + return -ENOENT; + + base1 = of_iomap(node1, 0); + if (base1 == NULL) { + printk(KERN_ERR "hi6220: pmic reg iomap failed!\n"); + return -ENOMEM; + } + + /*Disable UART1 reset and set pclk*/ + writel(BIT(5), base + reset_offset); + writel(BIT(5), base + pclk_offset); + + /*Disable UART2 reset and set pclk*/ + writel(BIT(6), base + reset_offset); + writel(BIT(6), base + pclk_offset); + + /*Disable UART3 reset and set pclk*/ + writel(BIT(7), base + reset_offset); + writel(BIT(7), base + pclk_offset); + + /*Disable UART4 reset and set pclk*/ + writel(BIT(8), base + reset_offset); + writel(BIT(8), base + pclk_offset); + + /*unreset microSD*/ + writel(readl(base+0x304) | 0x6, base + 0x304); + + /*enable clk for BT/WIFI*/ + ret = *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c); + ret |= 0x40; + *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c) = ret; + + iounmap(base); + iounmap(base1); + + return 0; +} +postcore_initcall(hi6220_sysconf); + +#ifdef CONFIG_ARM64 +#ifdef CONFIG_SPARSE_IRQ +#define NR_IRQS_LEGACY_HI6220 16 + +int __init arch_probe_nr_irqs(void) +{ + return NR_IRQS_LEGACY_HI6220; +} + +#endif +#endif diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h index a1b6040e6491..2690f4dab246 100644 --- a/drivers/net/wireless/ti/wlcore/wlcore.h +++ b/drivers/net/wireless/ti/wlcore/wlcore.h @@ -318,9 +318,9 @@ struct wl1271 { bool watchdog_recovery; /* Reg domain last configuration */ - u32 reg_ch_conf_last[2]; + u32 reg_ch_conf_last[2] __aligned(8); /* Reg domain pending configuration */ - u32 reg_ch_conf_pending[2]; + u32 reg_ch_conf_pending[2] __aligned(8); /* Pointer that holds DMA-friendly block for the mailbox */ void *mbox; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 64bccff557be..b5af2c676c78 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -261,6 +261,22 @@ config REGULATOR_HI6421 21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All of them come with support to either ECO (idle) or sleep mode. +config REGULATOR_HI655X + tristate "Hisilicon HI655X PMIC regulators support" + depends on ARCH_HISI + depends on MFD_HI655X_PMIC && OF + help + This driver provides support for the voltage regulators of the + Hisilicon Hi655x PMIC device. + +config REGULATOR_HI6220 + tristate "Hisilicon Hi6220 MTCMOS regulator support" + depends on ARCH_HISI + default ARCH_HISI + help + This driver provides support for the mtcmos regulators on the + Hisilicon Hi6220 chip. + config REGULATOR_ISL9305 tristate "Intersil ISL9305 regulator" depends on I2C diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 0f8174913c17..0590e8f724c8 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -34,6 +34,8 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o +obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o +obj-$(CONFIG_REGULATOR_HI6220) += hi6220-mtcmos.o obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o diff --git a/drivers/regulator/hi6220-mtcmos.c b/drivers/regulator/hi6220-mtcmos.c new file mode 100644 index 000000000000..4e84843687bd --- /dev/null +++ b/drivers/regulator/hi6220-mtcmos.c @@ -0,0 +1,281 @@ +/* + * Device driver for MTCMOS DRIVER in hi6220 SOC + * + * Copyright (c) 2015 Hisilicon Co. Ltd + * + * Fei Wang <w.f@huawei.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <linux/slab.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> +#include <linux/delay.h> +#include <linux/time.h> + +enum { + HI6220_MTCMOS1, + HI6220_MTCMOS2, + HI6220_RG_MAX, +}; + +struct hi6220_mtcmos_ctrl_regs { + unsigned int enable_reg; + unsigned int disable_reg; + unsigned int status_reg; +}; + +struct hi6220_mtcmos_ctrl_data { + int shift; + unsigned int mask; +}; + +struct hi6220_mtcmos_info { + struct regulator_desc rdesc; + struct hi6220_mtcmos_ctrl_regs ctrl_regs; + struct hi6220_mtcmos_ctrl_data ctrl_data; +}; + +struct hi6220_mtcmos { + struct regulator_dev *rdev[HI6220_RG_MAX]; + void __iomem *sc_on_regs; + int mtcmos_steady_time; + spinlock_t mtcmos_spin_lock; +}; + +static int hi6220_mtcmos_is_on(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned int ret; + unsigned long mtcmos_spin_flag = 0; + + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + ret = readl(mtcmos->sc_on_regs + regs); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + + ret &= (mask << shift); + return !!ret; +} + +int hi6220_mtcmos_on(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned long mtcmos_spin_flag = 0; + + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + writel(mask << shift, mtcmos->sc_on_regs + regs); + udelay(mtcmos->mtcmos_steady_time); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + + return 0; +} + +int hi6220_mtcmos_off(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned long mtcmos_spin_flag = 0; + + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + writel(mask << shift, mtcmos->sc_on_regs + regs); + udelay(mtcmos->mtcmos_steady_time); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, + mtcmos_spin_flag); + + return 0; +} + +static int hi6220_regulator_mtcmos_is_enabled(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, + ctrl_data->mask, ctrl_data->shift); + return ret; +} + +static int hi6220_regulator_mtcmos_enabled(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + ret = hi6220_mtcmos_on(mtcmos, ctrl_regs->enable_reg, + ctrl_data->mask, ctrl_data->shift); + if (0 == hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, + ctrl_data->mask, ctrl_data->shift)) { + return -1; + } + return ret; +} + +static int hi6220_regulator_mtcmos_disabled(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + ret = hi6220_mtcmos_off(mtcmos, ctrl_regs->disable_reg, + ctrl_data->mask, ctrl_data->shift); + + return ret; +} + +static struct regulator_ops hi6220_mtcmos_mtcmos_rops = { + .is_enabled = hi6220_regulator_mtcmos_is_enabled, + .enable = hi6220_regulator_mtcmos_enabled, + .disable = hi6220_regulator_mtcmos_disabled, +}; + +#define HI6220_MTCMOS(vreg) \ +{ \ + .rdesc = { \ + .name = #vreg, \ + .ops = &hi6220_mtcmos_mtcmos_rops, \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + }, \ +} + +static struct hi6220_mtcmos_info hi6220_mtcmos_info[] = { + HI6220_MTCMOS(MTCMOS1), + HI6220_MTCMOS(MTCMOS2), +}; + +static struct of_regulator_match hi6220_mtcmos_matches[] = { + { .name = "mtcmos1", + .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS1], }, + { .name = "mtcmos2", + .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS2], }, +}; + +static int hi6220_mtcmos_probe(struct platform_device *pdev) +{ + int ret; + struct hi6220_mtcmos *mtcmos; + const __be32 *sc_on_regs = NULL; + void __iomem *regs; + struct device *dev; + struct device_node *np, *child; + int count, i; + struct regulator_config config = { }; + struct regulator_init_data *init_data; + struct hi6220_mtcmos_info *sreg; + + dev = &pdev->dev; + np = dev->of_node; + mtcmos = devm_kzalloc(dev, + sizeof(struct hi6220_mtcmos), GFP_KERNEL); + if (!mtcmos) + return -ENOMEM; + + spin_lock_init((spinlock_t *)&mtcmos->mtcmos_spin_lock); + sc_on_regs = of_get_property(np, "hisilicon,mtcmos-sc-on-base", NULL); + if (sc_on_regs) { + regs = ioremap(be32_to_cpu(*sc_on_regs), 0x1000); + mtcmos->sc_on_regs = regs; + } + ret = of_property_read_u32(np, "hisilicon,mtcmos-steady-us", + &mtcmos->mtcmos_steady_time); + + count = of_regulator_match(&pdev->dev, np, + hi6220_mtcmos_matches, + ARRAY_SIZE(hi6220_mtcmos_matches)); + + for (i = 0; i < HI6220_RG_MAX; i++) { + init_data = hi6220_mtcmos_matches[i].init_data; + if (!init_data) + continue; + sreg = hi6220_mtcmos_matches[i].driver_data; + config.dev = &pdev->dev; + config.init_data = init_data; + config.driver_data = sreg; + config.of_node = hi6220_mtcmos_matches[i].of_node; + child = config.of_node; + + ret = of_property_read_u32_array(child, "hisilicon,ctrl-regs", + (unsigned int *)(&sreg->ctrl_regs), 0x3); + ret = of_property_read_u32_array(child, "hisilicon,ctrl-data", + (unsigned int *)(&sreg->ctrl_data), 0x2); + + mtcmos->rdev[i] = regulator_register(&sreg->rdesc, &config); + if (IS_ERR(mtcmos->rdev[i])) { + ret = PTR_ERR(mtcmos->rdev[i]); + dev_err(&pdev->dev, "failed to register mtcmos %s\n", + sreg->rdesc.name); + while (--i >= 0) + regulator_unregister(mtcmos->rdev[i]); + + return ret; + } + } + + platform_set_drvdata(pdev, mtcmos); + + return 0; +} + +static const struct of_device_id of_hi6220_mtcmos_match_tbl[] = { + { .compatible = "hisilicon,hi6220-mtcmos-driver", }, + {} +}; + +static struct platform_driver mtcmos_driver = { + .driver = { + .name = "hisi_hi6220_mtcmos", + .owner = THIS_MODULE, + .of_match_table = of_hi6220_mtcmos_match_tbl, + }, + .probe = hi6220_mtcmos_probe, +}; + +static int __init hi6220_mtcmos_init(void) +{ + return platform_driver_register(&mtcmos_driver); +} + +static void __exit hi6220_mtcmos_exit(void) +{ + platform_driver_unregister(&mtcmos_driver); +} + +fs_initcall(hi6220_mtcmos_init); +module_exit(hi6220_mtcmos_exit); + +MODULE_AUTHOR("Fei Wang <w.f@huawei.com>"); +MODULE_DESCRIPTION("Hi6220 mtcmo interface driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/regulator/hi655x-regulator.c b/drivers/regulator/hi655x-regulator.c new file mode 100644 index 000000000000..3423a8428401 --- /dev/null +++ b/drivers/regulator/hi655x-regulator.c @@ -0,0 +1,517 @@ +/* + * Device driver for regulators in HI655X IC + * + * Copyright (c) 2015 Hisilicon. + * + * Fei Wang <w.f@huawei.com> + * + * this regulator's probe function will be called lots of times,, + * because of there are lots of regulator nodes in dtb. + * so,that's say, the driver must be inited before the regulator nodes + * registor to system. + * + * Makefile have proved my guess, please refor to the makefile. + * when the code is rebuild i hope we can build pmu sub_system. + * init order can not base on compile + */ +#include <linux/slab.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> +#include <linux/delay.h> +#include <linux/time.h> +#include <linux/regulator/hi655x-regulator.h> +#include <linux/mfd/hi655x-pmic.h> +#include <linux/regmap.h> + +#define REG_VALUE_SETBITS(reg_value, pos, bits, bits_value) \ + (reg_value = (reg_value & \ + ~((((unsigned int)1 << bits) - 1) << pos)) | \ + ((unsigned int)(bits_value & \ + (((unsigned int)1 << bits) - 1)) << pos)) + +#define REG_VALUE_GETBITS(reg_value, pos, bits) \ + ((reg_value >> pos) & (((unsigned int)1 << bits) - 1)) + +static int hi655x_regulator_pmic_is_enabled(struct regulator_dev *rdev) +{ + int ret = 0; + unsigned int value = 0; + + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + /* + * regulator is all set,but the pmu is only subset. + * maybe this "buck"/"ldo"/"lvs" is not contrl by a core. + * and in regulator have a "status" member ("okey" or "disable"). + */ + regmap_read(rdev->regmap, ctrl_regs->status_reg, &value); + ret = (int)REG_VALUE_GETBITS(value, ctrl_data->shift, + ctrl_data->mask); + + return ret; +} + +static int hi655x_regulator_pmic_enable(struct regulator_dev *rdev) +{ + int ret = 0; + unsigned char value_u8 = 0; + unsigned int value_u32 = 0; + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + REG_VALUE_SETBITS(value_u32, ctrl_data->shift, ctrl_data->mask, 0x1); + value_u8 = (unsigned char)value_u32; + regmap_write(rdev->regmap, ctrl_regs->enable_reg, value_u8); + udelay(sreg->off_on_delay); + + return ret; +} + +static int hi655x_regulator_pmic_disable(struct regulator_dev *rdev) +{ + int ret = 0; + int flag = 1; + unsigned char value_u8 = 0; + unsigned int value_u32 = 0; + + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + /* + * regulator is all set,but the pmu is only subset. + * maybe this "buck"/"ldo"/"lvs" is not contrl by a core. + * and in regulator have a "status" member (okey or disable). + * maybe we can del some regulator which is not contrl by core. + */ + if (sreg->type == PMIC_BOOST_TYPE) + flag = 0; + + /* + * for flag init value = 1; + */ + + REG_VALUE_SETBITS(value_u32, ctrl_data->shift, ctrl_data->mask, flag); + value_u8 = (unsigned char)value_u32; + regmap_write(rdev->regmap, ctrl_regs->disable_reg, value_u8); + return ret; +} + +static int hi655x_regulator_pmic_list_voltage_linear(struct regulator_dev *rdev, + unsigned int selector) +{ + + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + /* + * regulator is all set,but the pmu is only subset. + * maybe this "buck"/"ldo"/"lvs" is not contrl by a core. + * and in regulator have a "status" member (okey or disable). + * maybe we can del some regulator which is not contrl by core. + * we will return min_uV + */ + if (sreg->type == PMIC_LVS_TYPE) + return 900000; + + if (selector >= sreg->vol_numb) { + pr_err("selector err %s %d\n", __func__, __LINE__); + return -1; + } + + return sreg->vset_table[selector]; +} + +static int hi655x_regulator_pmic_get_voltage(struct regulator_dev *rdev) +{ + int index = 0; + unsigned int value = 0; + + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + struct hi655x_regulator_vset_regs *vset_regs = &(sreg->vset_regs); + struct hi655x_regulator_vset_data *vset_data = &(sreg->vset_data); + + if (sreg->type == PMIC_LVS_TYPE) + return 900000; + + regmap_read(rdev->regmap, vset_regs->vset_reg, &value); + index = (unsigned int)REG_VALUE_GETBITS(value, + vset_data->shift, vset_data->mask); + + return sreg->vset_table[index]; +} + +static int hi655x_regulator_pmic_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, unsigned *selector) +{ + int i = 0; + int ret = 0; + int vol = 0; + unsigned int value = 0; + + struct hi655x_regulator *sreg = rdev_get_drvdata(rdev); + struct hi655x_regulator_vset_regs *vset_regs = &(sreg->vset_regs); + struct hi655x_regulator_vset_data *vset_data = &(sreg->vset_data); + + if (sreg->type == PMIC_LVS_TYPE) + return 0; + /* + * search the matched vol and get its index + */ + for (i = 0; i < sreg->vol_numb; i++) { + vol = sreg->vset_table[i]; + + if ((vol >= min_uV) && (vol <= max_uV)) + break; + } + + if (i == sreg->vol_numb) + return -1; + + + regmap_read(rdev->regmap, vset_regs->vset_reg, &value); + REG_VALUE_SETBITS(value, vset_data->shift, vset_data->mask, i); + regmap_write(rdev->regmap, vset_regs->vset_reg, value); + *selector = i; + + return ret; +} + +static unsigned int hi655x_regulator_pmic_get_mode( + struct regulator_dev *rdev) +{ + return REGULATOR_MODE_NORMAL; +} + +static int hi655x_regulator_pmic_set_mode(struct regulator_dev *rdev, + unsigned int mode) + +{ + return 0; +} + +static unsigned int hi655x_regulator_pmic_get_optimum_mode( + struct regulator_dev *rdev, int input_uV, int output_uV, int load_uA) + +{ + return REGULATOR_MODE_NORMAL; +} + +static struct regulator_ops hi655x_regulator_pmic_rops = { + .is_enabled = hi655x_regulator_pmic_is_enabled, + .enable = hi655x_regulator_pmic_enable, + .disable = hi655x_regulator_pmic_disable, + .list_voltage = hi655x_regulator_pmic_list_voltage_linear, + .get_voltage = hi655x_regulator_pmic_get_voltage, + .set_voltage = hi655x_regulator_pmic_set_voltage, + .get_mode = hi655x_regulator_pmic_get_mode, + .set_mode = hi655x_regulator_pmic_set_mode, + .get_optimum_mode = hi655x_regulator_pmic_get_optimum_mode, +}; + +static int hi655x_regualtor_pmic_dt_parse(struct hi655x_regulator *sreg, + struct platform_device *pdev) +{ + return 0; +} + +static const struct hi655x_regulator hi655x_regulator_pmic = { + .rdesc = { + .ops = &hi655x_regulator_pmic_rops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, + .dt_parse = hi655x_regualtor_pmic_dt_parse, +}; + + +static const struct of_device_id of_hi655x_regulator_match_tbl[] = { + { + .compatible = "hisilicon,hi655x-regulator-pmic", + .data = &hi655x_regulator_pmic, + }, + { /* end */ } +}; + +static struct regulator_init_data *hi655x_of_get_regulator_init_data( + struct device *dev, struct device_node *np) +{ + struct regulator_init_data *init_data = NULL; + const __be32 *num_consumer_supplies = NULL; + struct regulator_consumer_supply *consumer_supplies = NULL; + int consumer_id = 0; + + init_data = devm_kzalloc(dev, sizeof(*init_data), GFP_KERNEL); + if (!init_data) + return NULL; + + num_consumer_supplies = of_get_property(np, + "hisilicon,num_consumer_supplies", NULL); + + if ((NULL == num_consumer_supplies) || (0 == *num_consumer_supplies)) { + dev_warn(dev, "%s no consumer_supplies\n", __func__); + return init_data; + } + + init_data->num_consumer_supplies = be32_to_cpu(*num_consumer_supplies); + init_data->consumer_supplies = (struct regulator_consumer_supply *) + devm_kzalloc(dev, init_data->num_consumer_supplies * + sizeof(struct regulator_consumer_supply), GFP_KERNEL); + + if (NULL == init_data->consumer_supplies) { + dev_err(dev, "%s devm_kzalloc consumer_supplies err\n", + __func__); + return NULL; + } + + consumer_supplies = init_data->consumer_supplies; + + for (consumer_id = 0; consumer_id < init_data->num_consumer_supplies; + consumer_id++, consumer_supplies++) { + int ret = of_property_read_string_index(np, + "hisilicon,consumer-supplies", + consumer_id, &consumer_supplies->supply); + + if (ret) { + dev_err(dev, + "%s %s of_property_read_string_index consumer-supplies err\n", + __func__, np->name); + } + } + + return init_data; +} + +static int hi655x_of_get_regulator_constraint( + struct regulation_constraints *constraints, struct device_node *np) +{ + const __be32 *min_uV, *max_uV; + unsigned int *valid_modes_mask; + unsigned int *valid_ops_mask; + unsigned int *initial_mode; + + if (!np) + return -1; + + if (!constraints) + return -1; + + (constraints)->name = of_get_property(np, "regulator-name", NULL); + + min_uV = of_get_property(np, "regulator-min-microvolt", NULL); + if (min_uV) { + (constraints)->min_uV = be32_to_cpu(*min_uV); + (constraints)->min_uA = be32_to_cpu(*min_uV); + } + + max_uV = of_get_property(np, "regulator-max-microvolt", NULL); + if (max_uV) { + (constraints)->max_uV = be32_to_cpu(*max_uV); + (constraints)->max_uA = be32_to_cpu(*max_uV); + } + + valid_modes_mask = (unsigned int *)of_get_property(np, + "hisilicon,valid-modes-mask", NULL); + + if (valid_modes_mask) + (constraints)->valid_modes_mask = + be32_to_cpu(*valid_modes_mask); + + valid_ops_mask = (unsigned int *)of_get_property(np, + "hisilicon,valid-ops-mask", NULL); + if (valid_ops_mask) + (constraints)->valid_ops_mask = + be32_to_cpu(*valid_ops_mask); + + initial_mode = (unsigned int *)of_get_property(np, + "hisilicon,initial-mode", NULL); + if (initial_mode) + (constraints)->initial_mode = be32_to_cpu(*initial_mode); + + (constraints)->always_on = !!(of_find_property(np, + "regulator-always-on", NULL)); + + (constraints)->boot_on = !!(of_find_property(np, + "regulator-boot-on", NULL)); + return 0; + +} + +static int hi655x_of_get_regulator_sreg(struct hi655x_regulator *sreg, + struct device *dev, struct device_node *np) +{ + int *vol_numb; + unsigned int *off_on_delay; + enum hi655x_regulator_type *regulator_type; + const char *status = NULL; + unsigned int *vset_table = NULL; + int *regulator_id; + + status = of_get_property(np, "hisilicon,regulator-status", NULL); + if (status) + sreg->status = !(strcmp(status, "okey")); + + regulator_type = (enum hi655x_regulator_type *)of_get_property(np, + "hisilicon,regulator-type", NULL); + + if (regulator_type) + sreg->type = be32_to_cpu(*regulator_type); + + off_on_delay = (unsigned int *)of_get_property(np, + "hisilicon,off-on-delay", NULL); + if (off_on_delay) + sreg->off_on_delay = be32_to_cpu(*off_on_delay); + + (void)of_property_read_u32_array(np, "hisilicon,ctrl-regs", + (unsigned int *)(&sreg->ctrl_regs), 0x3); + + (void)of_property_read_u32_array(np, "hisilicon,ctrl-data", + (unsigned int *)(&sreg->ctrl_data), 0x2); + + (void)of_property_read_u32_array(np, "hisilicon,vset-regs", + (unsigned int *)(&sreg->vset_regs), 0x1); + + (void)of_property_read_u32_array(np, "hisilicon,vset-data", + (unsigned int *)(&sreg->vset_data), 0x2); + + vol_numb = (int *)of_get_property(np, "hisilicon,regulator-n-vol", + NULL); + if (vol_numb) + sreg->vol_numb = be32_to_cpu(*vol_numb); + + regulator_id = (int *)of_get_property(np, + "hisilicon, hisi-scharger-regulator-id", NULL); + + if (regulator_id) + sreg->regulator_id = be32_to_cpu(*regulator_id); + + vset_table = devm_kzalloc(dev, sreg->vol_numb * sizeof(int), + GFP_KERNEL); + if (!vset_table) + return -1; + + (void)of_property_read_u32_array(np, + "hisilicon,vset-table", (unsigned int *)vset_table, + sreg->vol_numb); + sreg->vset_table = vset_table; + + return 0; + +} + +static int hi655x_regulator_probe(struct platform_device *pdev) +{ + + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct hi655x_pmic *pmic; + struct regulator_dev *rdev = NULL; + struct regulator_desc *rdesc = NULL; + struct hi655x_regulator *sreg = NULL; + struct regulator_init_data *initdata = NULL; + const struct of_device_id *match = NULL; + const struct hi655x_regulator *template = NULL; + struct regulator_config config = { }; + + pmic = dev_get_drvdata(dev->parent); + + /* + * build hi655x_regulator device + */ + + /* to check which type of regulator this is */ + match = of_match_device(of_hi655x_regulator_match_tbl, &pdev->dev); + + if (NULL == match) { + dev_err(dev, "of match hi655x regulator fail!\n\r"); + return -EINVAL; + } + /*tempdev is regulator device*/ + template = match->data; + + /* + *initdata mem will release auto; + *this is kernel 3.10 import. + */ + + /*just for getting "std regulator node" value-key about constraint*/ + initdata = hi655x_of_get_regulator_init_data(dev, np); + if (!initdata) { + dev_err(dev, "get regulator init data error !\n"); + return -EINVAL; + } + + ret = hi655x_of_get_regulator_constraint(&initdata->constraints, np); + if (!!ret) { + dev_err(dev, "get regulator constraint error !\n"); + return -EINVAL; + } + + /* TODO:hi655x regulator supports two modes */ + sreg = kmemdup(template, sizeof(*sreg), GFP_KERNEL); + if (!sreg) + return -ENOMEM; + + if (0 != hi655x_of_get_regulator_sreg(sreg, dev, np)) { + kfree(sreg); + return -EINVAL; + } + + rdesc = &sreg->rdesc; + rdesc->n_voltages = sreg->vol_numb; + rdesc->name = initdata->constraints.name; + rdesc->id = sreg->regulator_id; + rdesc->min_uV = initdata->constraints.min_uV; + + /*just for skeleton for future*/ + /* to parse device tree data for regulator specific */ + config.dev = &pdev->dev; + config.init_data = initdata; + config.driver_data = sreg; + config.regmap = pmic->regmap; + config.of_node = pdev->dev.of_node; + /* register regulator */ + rdev = regulator_register(rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "regulator failed to register %s\n", rdesc->name); + ret = PTR_ERR(rdev); + return -EINVAL; + } + + platform_set_drvdata(pdev, rdev); + regulator_has_full_constraints(); + + return ret; +} + +static int hi655x_regulator_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver hi655x_regulator_driver = { + .driver = { + .name = "hi655x_regulator", + .owner = THIS_MODULE, + .of_match_table = of_hi655x_regulator_match_tbl, + }, + .probe = hi655x_regulator_probe, + .remove = hi655x_regulator_remove, +}; +module_platform_driver(hi655x_regulator_driver); + +MODULE_AUTHOR("Fei Wang <w.f@huawei.com>"); +MODULE_DESCRIPTION("Hisi hi655x regulator driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h new file mode 100644 index 000000000000..38f1ea879ea1 --- /dev/null +++ b/include/dt-bindings/pinctrl/hisi.h @@ -0,0 +1,59 @@ +/* + * This header provides constants for hisilicon pinctrl bindings. + * + * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_HISI_H +#define _DT_BINDINGS_PINCTRL_HISI_H + +/* iomg bit definition */ +#define MUX_M0 0 +#define MUX_M1 1 +#define MUX_M2 2 +#define MUX_M3 3 +#define MUX_M4 4 +#define MUX_M5 5 +#define MUX_M6 6 +#define MUX_M7 7 + +/* iocg bit definition */ +#define PULL_MASK (3) +#define PULL_DIS (0) +#define PULL_UP (1 << 0) +#define PULL_DOWN (1 << 1) + +/* drive strength definition */ +#define DRIVE_MASK (7 << 4) +#define DRIVE1_02MA (0 << 4) +#define DRIVE1_04MA (1 << 4) +#define DRIVE1_08MA (2 << 4) +#define DRIVE1_10MA (3 << 4) +#define DRIVE2_02MA (0 << 4) +#define DRIVE2_04MA (1 << 4) +#define DRIVE2_08MA (2 << 4) +#define DRIVE2_10MA (3 << 4) +#define DRIVE3_04MA (0 << 4) +#define DRIVE3_08MA (1 << 4) +#define DRIVE3_12MA (2 << 4) +#define DRIVE3_16MA (3 << 4) +#define DRIVE3_20MA (4 << 4) +#define DRIVE3_24MA (5 << 4) +#define DRIVE3_32MA (6 << 4) +#define DRIVE3_40MA (7 << 4) +#define DRIVE4_02MA (0 << 4) +#define DRIVE4_04MA (2 << 4) +#define DRIVE4_08MA (4 << 4) +#define DRIVE4_10MA (6 << 4) + +#endif diff --git a/include/linux/mfd/hi655x-pmic.h b/include/linux/mfd/hi655x-pmic.h new file mode 100644 index 000000000000..e66246cd2f6d --- /dev/null +++ b/include/linux/mfd/hi655x-pmic.h @@ -0,0 +1,56 @@ +/* + * Header file for device driver Hi655X PMIC + * + * Copyright (C) 2015 Hisilicon Co. Ltd. + * + * Fei Wang <w.f@huawei.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#ifndef __HI655X_PMIC_H +#define __HI655X_PMIC_H + +/* Hi655x registers are mapped to memory bus in 4 bytes stride */ +#define HI655X_REG_TO_BUS_ADDR(x) ((x) << 2) + +#define HI655X_BITS (8) + +/*numb of sub-interrupt*/ +#define HI655X_NR_IRQ (32) + +#define HI655X_IRQ_STAT_BASE (0x003) +#define HI655X_IRQ_MASK_BASE (0x007) +#define HI655X_IRQ_ARRAY (4) +#define HI655X_IRQ_MASK (0xFF) +#define HI655X_IRQ_CLR (0xFF) +#define HI655X_VER_REG (0x000) + +#define PMU_VER_START 0x10 +#define PMU_VER_END 0x38 + +struct hi655x_pmic { + struct resource *res; + struct device *dev; + struct regmap *regmap; + spinlock_t ssi_hw_lock; + struct clk *clk; + struct irq_domain *domain; + int irq; + int gpio; + unsigned int irqs[HI655X_NR_IRQ]; + unsigned int ver; +}; +#endif diff --git a/include/linux/regulator/hi655x-regulator.h b/include/linux/regulator/hi655x-regulator.h new file mode 100644 index 000000000000..387b35212ea2 --- /dev/null +++ b/include/linux/regulator/hi655x-regulator.h @@ -0,0 +1,69 @@ +/* + * Device driver for regulators in HI655X IC + * + * Copyright (c) 2015 Hisilicon. + * + * Fei Wang <w.f@huawei.com> + * + * this regulator's probe function will be called lots of times,, + * because of there are lots of regulator nodes in dtb. + * so,that's say, the driver must be inited before the regulator nodes + * registor to system. + * + * Makefile have proved my guess, please refor to the makefile. + * when the code is rebuild i hope we can build pmu sub_system. + * init order can not base on compile + */ + +#ifndef __HISI_HI655X_REGULATOR_H__ +#define __HISI_HI655X_REGULATOR_H__ + +enum hi655x_regulator_type { + PMIC_BUCK_TYPE = 0, + PMIC_LDO_TYPE = 1, + PMIC_LVS_TYPE = 2, + PMIC_BOOST_TYPE = 3, + MTCMOS_SC_ON_TYPE = 4, + MTCMOS_ACPU_ON_TYPE = 5, + SCHARGE_TYPE = 6, +}; + +struct hi655x_regulator_ctrl_regs { + unsigned int enable_reg; + unsigned int disable_reg; + unsigned int status_reg; +}; + +struct hi655x_regulator_vset_regs { + unsigned int vset_reg; +}; + +struct hi655x_regulator_ctrl_data { + int shift; + unsigned int mask; +}; + +struct hi655x_regulator_vset_data { + int shift; + unsigned int mask; +}; + +struct hi655x_regulator { + int status; /*this property in child node*/ + unsigned int off_on_delay; /*this property in parent node*/ + enum hi655x_regulator_type type; /*this property in child node*/ + int regulator_id; + + /*this property must be unify which is in child node*/ + struct hi655x_regulator_ctrl_regs ctrl_regs; + struct hi655x_regulator_ctrl_data ctrl_data; + + struct hi655x_regulator_vset_regs vset_regs; + struct hi655x_regulator_vset_data vset_data; + unsigned int vol_numb; + unsigned int *vset_table; + struct regulator_desc rdesc; + int (*dt_parse)(struct hi655x_regulator*, struct platform_device*); +}; + +#endif |