path: root/arch/arm64/boot/dts/qcom/atoll.dtsi

/* Copyright (c) 2019, The Linux Foundation.All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-atoll.h>
#include <dt-bindings/clock/qcom,dispcc-atoll.h>
#include <dt-bindings/clock/qcom,gcc-atoll.h>
#include <dt-bindings/clock/qcom,gpucc-atoll.h>
#include <dt-bindings/clock/qcom,npucc-atoll.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-atoll.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>

/ {
	model = "Qualcomm Technologies, Inc. ATOLL";
	compatible = "qcom,atoll";
	qcom,msm-name = "ATOLL";
	qcom,msm-id = <407 0x0>;
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x100000>;
				      cache-level = <3>;
				};
			};

			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_0: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_100: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};


		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_200: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_200: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_200: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_300: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_300: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_300: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_400: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_400: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_400: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			i-cache-size = <0x8000>;
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_500: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_500: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_500: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			i-cache-size = <0x10000>;
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x48000>;
			};

			L1_I_600: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_600: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_600: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_600: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_600: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			i-cache-size = <0x10000>;
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x48000>;
			};

			L1_I_700: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_700: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_700: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_700: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_700: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

			};

			cluster1 {
				core0 {
					cpu = <&CPU6>;
				};

				core1 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_region: hyp_region@80000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x80000000 0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_mem@80700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x80700000 0x0 0x140000>;
		};

		sec_apps_mem: sec_apps_region@808ff000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x808ff000 0x0 0x1000>;
		};

		smem_region: smem@80900000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x80900000 0x0 0x200000>;
		};

		removed_region: removed_region@80b00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x80b00000 0 0x3900000>;
		};

		pil_camera_mem: camera_region@8e000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8e000000 0 0x500000>;
		};

		pil_modem_mem: modem_region@86000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x86000000 0 0x8000000>;
		};

		pil_video_mem: pil_video_region@8ea00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8ea00000 0 0x500000>;
		};

		pil_cdsp_mem: cdsp_regions@8ef00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8ef00000 0 0x1e00000>;
		};

		pil_adsp_mem: pil_adsp_region@90d00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x90d00000 0 0x2800000>;
		};

		wlan_fw_mem: wlan_fw_region@93500000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x93500000 0 0x200000>;
		};

		npu_mem: npu_region@8e500000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8e500000 0 0x500000>;
		};

		pil_ipa_fw_mem: ipa_fw_region@93700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x93700000 0 0x10000>;
		};

		pil_ipa_gsi_mem: ipa_gsi_region@93710000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x93710000 0 0x5000>;
		};

		pil_gpu_mem: gpu_region@93715000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x93715000 0 0x2000>;
		};

		qseecom_mem: qseecom_region@9e000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x9e000000 0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions@0x9f400000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x9f400000 0 0xc00000>;
		};
		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x2000000>;
			linux,cma-default;
		};
	};

	chosen {
		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
	};

	soc: soc { };

};

&soc {

	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
			<0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&intc>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 0xf08>,
			     <GIC_PPI 2 0xf08>,
			     <GIC_PPI 3 0xf08>,
			     <GIC_PPI 0 0xf08>;
		clock-frequency = <19200000>;
	};

	timer@17c20000{
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		ranges = <0x0 0x146aa000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 32>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 12>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 200>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 200>;
		};
	};

	restart@c264000 {
		compatible = "qcom,pshold";
		reg = <0xc264000 0x4>,
		      <0x1fd3000 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	wdog: qcom,wdt@17c10000{
		compatible = "qcom,msm-watchdog";
		reg = <0x17c10000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 0 IRQ_TYPE_NONE>,
				<GIC_SPI 1 IRQ_TYPE_NONE>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9360>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
		qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100
				       0x10100 0x10100 0x25900 0x25900>;
	};

	qcom,chd_sliver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x18000058 0x18010058
				      0x18020058 0x18030058
				      0x18040058 0x18050058>;
		qcom,config-arr = <0x18000060 0x18010060
				   0x18020060 0x18030060
				   0x18040060 0x18050060>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x18060058 0x18070058>;
		qcom,config-arr = <0x18060060 0x18070060>;
	};

	qcom,ghd {
		compatible = "qcom,gladiator-hang-detect-v3";
		qcom,threshold-arr = <0x17e0041C>;
		qcom,config-reg = <0x17e00434>;
	};

	kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "l1-l2-faultirq",
				  "l3-scu-faultirq";
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x200000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
		qcom,guard-memory;
	};

	qcom,llcc@9200000 {
		compatible = "qcom,llcc-core", "syscon", "simple-mfd";
		reg = <0x9200000 0x450000>;
		reg-names = "llcc_base";
		qcom,llcc-banks-off = <0x0>;
		qcom,llcc-broadcast-off = <0x400000>;

		llcc: qcom,atoll-llcc {
			compatible = "qcom,atoll-llcc";
			#cache-cells = <1>;
			max-slices = <32>;
			cap-based-alloc-and-pwr-collapse;
		};

		qcom,llcc-erp {
			compatible = "qcom,llcc-erp";
		};

		qcom,llcc-amon {
			compatible = "qcom,llcc-amon";
		};

		LLCC_1: llcc_1_dcache {
			qcom,dump-size = <0x6c000>;
		};
	};

	cpuss_dump {
		compatible = "qcom,cpuss-dump";

		qcom,l1_i_cache0 {
			qcom,dump-node = <&L1_I_0>;
			qcom,dump-id = <0x60>;
		};

		qcom,l1_i_cache100 {
			qcom,dump-node = <&L1_I_100>;
			qcom,dump-id = <0x61>;
		};

		qcom,l1_i_cache200 {
			qcom,dump-node = <&L1_I_200>;
			qcom,dump-id = <0x62>;
		};

		qcom,l1_i_cache300 {
			qcom,dump-node = <&L1_I_300>;
			qcom,dump-id = <0x63>;
		};

		qcom,l1_i_cache400 {
			qcom,dump-node = <&L1_I_400>;
			qcom,dump-id = <0x64>;
		};

		qcom,l1_i_cache500 {
			qcom,dump-node = <&L1_I_500>;
			qcom,dump-id = <0x65>;
		};

		qcom,l1_i_cache600 {
			qcom,dump-node = <&L1_I_600>;
			qcom,dump-id = <0x66>;
		};

		qcom,l1_i_cache700 {
			qcom,dump-node = <&L1_I_700>;
			qcom,dump-id = <0x67>;
		};

		qcom,l1_d_cache0 {
			qcom,dump-node = <&L1_D_0>;
			qcom,dump-id = <0x80>;
		};

		qcom,l1_d_cache100 {
			qcom,dump-node = <&L1_D_100>;
			qcom,dump-id = <0x81>;
		};

		qcom,l1_d_cache200 {
			qcom,dump-node = <&L1_D_200>;
			qcom,dump-id = <0x82>;
		};

		qcom,l1_d_cache300 {
			qcom,dump-node = <&L1_D_300>;
			qcom,dump-id = <0x83>;
		};

		qcom,l1_d_cache400 {
			qcom,dump-node = <&L1_D_400>;
			qcom,dump-id = <0x84>;
		};

		qcom,l1_d_cache500 {
			qcom,dump-node = <&L1_D_500>;
			qcom,dump-id = <0x85>;
		};

		qcom,l1_d_cache600 {
			qcom,dump-node = <&L1_D_600>;
			qcom,dump-id = <0x86>;
		};

		qcom,l1_d_cache700 {
			qcom,dump-node = <&L1_D_700>;
			qcom,dump-id = <0x87>;
		};

		qcom,l1_i_tlb_dump600 {
			qcom,dump-node = <&L1_ITLB_600>;
			qcom,dump-id = <0x26>;
		};

		qcom,l1_i_tlb_dump700 {
			qcom,dump-node = <&L1_ITLB_700>;
			qcom,dump-id = <0x27>;
		};

		qcom,l1_d_tlb_dump600 {
			qcom,dump-node = <&L1_DTLB_600>;
			qcom,dump-id = <0x46>;
		};

		qcom,l1_d_tlb_dump700 {
			qcom,dump-node = <&L1_DTLB_700>;
			qcom,dump-id = <0x47>;
		};

		qcom,l2_cache_dump600 {
			qcom,dump-node = <&L2_600>;
			qcom,dump-id = <0xc6>;
		};

		qcom,l2_cache_dump700 {
			qcom,dump-node = <&L2_700>;
			qcom,dump-id = <0xc7>;
		};

		qcom,l2_tlb_dump0 {
			qcom,dump-node = <&L2_TLB_0>;
			qcom,dump-id = <0x120>;
		};

		qcom,l2_tlb_dump100 {
			qcom,dump-node = <&L2_TLB_100>;
			qcom,dump-id = <0x121>;
		};

		qcom,l2_tlb_dump200 {
			qcom,dump-node = <&L2_TLB_200>;
			qcom,dump-id = <0x122>;
		};

		qcom,l2_tlb_dump300 {
			qcom,dump-node = <&L2_TLB_300>;
			qcom,dump-id = <0x123>;
		};

		qcom,l2_tlb_dump400 {
			qcom,dump-node = <&L2_TLB_400>;
			qcom,dump-id = <0x124>;
		};

		qcom,l2_tlb_dump500 {
			qcom,dump-node = <&L2_TLB_500>;
			qcom,dump-id = <0x125>;
		};

		qcom,l2_tlb_dump600 {
			qcom,dump-node = <&L2_TLB_600>;
			qcom,dump-id = <0x126>;
		};

		qcom,l2_tlb_dump700 {
			qcom,dump-node = <&L2_TLB_700>;
			qcom,dump-id = <0x127>;
		};
	};

	clock_rpmh: qcom,rpmh {
		compatible = "qcom,dummycc";
		clock-output-names = "rpm_clocks";
		#clock-cells = <1>;
	};

	clock_aop: qcom,aopclk {
		compatible = "qcom,dummycc";
		clock-output-names = "aop_clocks";
		#clock-cells = <1>;
	};

	clock_gcc: qcom,gcc {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_camcc: qcom,camcc {
		compatible = "qcom,dummycc";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_dispcc: qcom,dispcc {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_gpucc: qcom,gpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_npucc: qcom,npucc {
		compatible = "qcom,dummycc";
		clock-output-names = "npucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_videocc: qcom,videocc {
		compatible = "qcom,dummycc";
		clock-output-names = "videocc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	tcsr_mutex_block: syscon@01F40000 {
		compatible = "syscon";
		reg = <0x01F40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	apcs_glb: mailbox@17C00000 {
		compatible = "qcom,atoll-apcs-hmss-global";
		reg = <0x17C00000 0x10000>;

		#mbox-cells = <1>;
	};

	apcs_glb2: mailbox@17C00010 {
		compatible = "qcom,atoll-apcs-hmss-ipc2";
		reg = <0x17C00010 0x4>;

		#mbox-cells = <1>;
	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_modem: modem {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apcs_glb 12>;
			mbox-names = "mpss_smem";
			interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 2>;
			};

			qcom,modem_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_cdsp>;
			};
		};

		glink_adsp: adsp {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&apcs_glb 8>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,apr_tal_rpmsg {
				qcom,glink-channels = "apr_audio_svc";
				qcom,intents = <0x200 20>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,adsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_cdsp>;
			};
		};

		glink_cdsp: cdsp {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&apcs_glb 4>;
			mbox-names = "cdsp_smem";
			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-latency-us = <44>;
					qcom,qos-maxhold-ms = <20>;
					#cooling-cells = <2>;
				};

				msm_hvx_rm: qcom,msm_hvx_rm {
					compatible = "qcom,msm-hvx-rm";
					#cooling-cells = <2>;
				};
			};

			qcom,cdsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_npu>,
						    <&glink_adsp>;
			};
		};

		glink_npu: npu {
			transport = "smem";
			qcom,remote-pid = <10>;
			mboxes = <&apcs_glb2 4>;
			mbox-names = "npu_smem";
			interrupts = <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;

			label = "npu";
			qcom,glink-label = "npu";

			qcom,npu_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,npu_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_cdsp>;
			};
		};

		glink_spi_xprt_wdsp: wdsp {
			transport = "spi";
			tx-descriptors = <0x12000 0x12004>;
			rx-descriptors = <0x1200c 0x12010>;

			label = "wdsp";
			qcom,glink-label = "wdsp";

			qcom,wdsp_ctrl {
				qcom,glink-channels = "g_glink_ctrl";
				qcom,intents = <0x400 1>;
			};

			qcom,wdsp_ild {
				qcom,glink-channels =
					"g_glink_persistent_data_ild";
			};

			qcom,wdsp_nild {
				qcom,glink-channels =
					"g_glink_persistent_data_nild";
			};

			qcom,wdsp_data {
				qcom,glink-channels = "g_glink_audio_data";
				qcom,intents = <0x1000 2>;
			};

			qcom,diag_data {
				qcom,glink-channels = "DIAG_DATA";
				qcom,intents = <0x4000 2>;
			};

			qcom,diag_ctrl {
				qcom,glink-channels = "DIAG_CTRL";
				qcom,intents = <0x4000 1>;
			};

			qcom,diag_cmd {
				qcom,glink-channels = "DIAG_CMD";
				qcom,intents = <0x4000 1 >;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
			qcom,entry-name = "wlan";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 10>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 6>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-npu {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupts = <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb2 6>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <10>;

		npu_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		npu_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qmp_aop: qcom,qmp-aop@c300000 {
		compatible = "qcom,qmp-mbox";
		reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x1>;
		interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

		label = "aop";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	spmi_bus: qcom,spmi@c440000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc440000 0x1100>,
			<0xc600000 0x2000000>,
			<0xe600000 0x100000>,
			<0xe700000 0xa0000>,
			<0xc40a000 0x26000>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
		qcom,ee = <0>;
		qcom,channel = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-controller;
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
		qcom,ipa-platform-type-msm;
		qcom,ipa-advertise-sg-support;
		qcom,ipa-napi-enable;
	};

	ipa_hw: qcom,ipa@1e00000 {
		compatible = "qcom,ipa";
		reg = <0x1e00000 0x34000>,
			<0x1e04000 0x2c000>;
		reg-names = "ipa-base", "gsi-base";
		interrupts = <0 311 0>, <0 432 0>;
		interrupt-names = "ipa-irq", "gsi-irq";
		qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
		qcom,ipa-hw-mode = <0>;
		qcom,ee = <0>;
		qcom,use-ipa-tethering-bridge;
		qcom,modem-cfg-emb-pipe-flt;
		qcom,ipa-wdi2;
		qcom,ipa-wdi2_over_gsi;
		qcom,ipa-fltrt-not-hashable;
		qcom,ipa-endp-delay-wa;
		qcom,use-64-bit-dma-mask;
		qcom,arm-smmu;
		qcom,smmu-fast-map;
		qcom,use-ipa-pm;
		qcom,bandwidth-vote-for-ipa;
		qcom,msm-bus,name = "ipa";
		qcom,msm-bus,num-cases = <5>;
		qcom,msm-bus,num-paths = <4>;
		qcom,msm-bus,vectors-KBps =
		/* No vote */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
		/* SVS2 */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 30>,
		/* SVS */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 109>,
		/* NOMINAL */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0  206000 4000000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 491>,
		/* TURBO */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 491>;
		qcom,bus-vector-names =
			"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
		qcom,throughput-threshold = <310 600 1000>;
		qcom,scaling-exceptions = <>;

		/* smp2p information */
		qcom,smp2p_map_ipa_1_out {
			compatible = "qcom,smp2p-map-ipa-1-out";
			qcom,smem-states = <&smp2p_ipa_1_out 0>;
			qcom,smem-state-names = "ipa-smp2p-out";
		};

		qcom,smp2p_map_ipa_1_in {
			compatible = "qcom,smp2p-map-ipa-1-in";
			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
			interrupt-names = "ipa-smp2p-in";
		};
	};

	ipa_smmu_ap: ipa_smmu_ap {
		compatible = "qcom,ipa-smmu-ap-cb";
		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x0440 0x0>;
		qcom,iova-mapping = <0x20000000 0x40000000>;
		/* modem tables in IMEM */
		qcom,additional-mapping = <0x146A8000 0x146A8000 0x2000>;
	};

	ipa_smmu_wlan: ipa_smmu_wlan {
		compatible = "qcom,ipa-smmu-wlan-cb";
		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x0441 0x0>;
		/* ipa-uc ram */
		qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>;
	};

	ipa_smmu_uc: ipa_smmu_uc {
		compatible = "qcom,ipa-smmu-uc-cb";
		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x0442 0x0>;
		qcom,iova-mapping = <0x40400000 0x1fc00000>;
	};

	qcom,ipa_fws {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <0xf>;
		qcom,firmware-name = "ipa_fws";
		qcom,pil-force-shutdown;
		memory-region = <&pil_ipa_fw_mem>;
	};
};

#include "atoll-gdsc.dtsi"
#include "atoll-ion.dtsi"
#include "msm-arm-smmu-sdmatoll.dtsi"

&ufs_phy_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&bps_gdsc {
	status = "ok";
};

&ipe_0_gdsc {
	status = "ok";
};

&ife_0_gdsc {
	status = "ok";
};

&ife_1_gdsc {
	status = "ok";
};

&titan_top_gdsc {
	status = "ok";
};

&mdss_core_gdsc {
	status = "ok";
};

&gpu_cx_gdsc {
	status = "ok";
};

&gpu_gx_gdsc {
	status = "ok";
};

&vcodec0_gdsc {
	status = "ok";
};

&venus_gdsc {
	status = "ok";
};

&npu_core_gdsc {
	status = "ok";
};

#include "atoll-pinctrl.dtsi"
#include "atoll-pm.dtsi"
#include "atoll-stub-regulator.dtsi"