diff options
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 845eb7a6bf92..ccdaf3f17a47 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1294,3 +1294,59 @@ drive-strength = <6>; bias-disable; }; + +&camss { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* The port index denotes CSIPHY id i.e. csiphy2 */ + port@2 { + reg = <2>; + csiphy2_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx412_ep>; + }; + + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci_i2c2 { + camera@1a { + compatible = "sony,imx412"; + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "xvclk"; + clock-frequency = <24000000>; + + power-domains = <&camcc TITAN_TOP_GDSC>; + dovdd-supply = <&vreg_s4a_1p8>; + avdd-supply = <&vreg_l7f_1p8>; + dvdd-supply = <&vreg_l9a_1p2>; + + status = "okay"; + port { + imx412_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy2_ep>; + }; + }; + }; +}; |