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| author | Linux Build Service Account <lnxbuild@localhost> | 2018-10-11 01:19:38 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-10-11 01:19:38 -0700 |
| commit | 59f53f2609aed26598d0f6960f06b0664b833a3c (patch) | |
| tree | 2bd1d6e21e3ae45c379824b500629c43292f7801 | |
| parent | 28e84708d893922cc171e95ae5a912233cb4385c (diff) | |
| parent | 3472f139d09a62ac3563bb93230cf139401956e6 (diff) | |
Merge "ARM: dts: msm: Add pin control settings for UFS reset on sdm670" into kernel.lnx.4.9.r18-relLA.UM.6.8.r3-02300-SDM710.0
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi | 46 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm670.dtsi | 4 |
2 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi index ee1a59379841..04614292bad8 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi @@ -21,6 +21,52 @@ #interrupt-cells = <2>; interrupt-parent = <&pdc>; + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + /* QUPv3 South SE mappings */ /* SE 0 pin mappings */ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 47cb70b91f41..9e579af426d0 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1941,6 +1941,10 @@ qcom,pm-qos-cpu-group-latency-us = <70 70>; qcom,pm-qos-default-cpu = <0>; + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + resets = <&clock_gcc GCC_UFS_PHY_BCR>; reset-names = "core_reset"; |