diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2019-12-03 23:31:09 -0800 |
|---|---|---|
| committer | Linux Build Service Account <lnxbuild@localhost> | 2019-12-03 23:31:09 -0800 |
| commit | 736bd6d87b4278dbc189ee62c2159de0576628d6 (patch) | |
| tree | f2c01e01b7f029dce156728bd337ca730ac0149f | |
| parent | 8be73471cca22ba5666dbee507600bbe0c08e7ec (diff) | |
| parent | 0c4f6840fff1742995fb3d64d274db2e8bcfbb8a (diff) | |
Merge 0c4f6840fff1742995fb3d64d274db2e8bcfbb8a on remote branchLV.AU.0.1.0-02000-gen3meta.0
Change-Id: Iee2fe538ff5ecba980dc5b12c999973ff75121ff
100 files changed, 11505 insertions, 168 deletions
diff --git a/AndroidKernel.mk b/AndroidKernel.mk index a1d51ed8edaa..1ba0b65f2adc 100644 --- a/AndroidKernel.mk +++ b/AndroidKernel.mk @@ -76,7 +76,11 @@ KERNEL_GCC_NOANDROID_CHK := $(shell (echo "int main() {return 0;}" | $(KERNEL_CR real_cc := ifeq ($(KERNEL_LLVM_SUPPORT),true) -real_cc := REAL_CC=$(KERNEL_LLVM_BIN) CLANG_TRIPLE=aarch64-linux-gnu- + ifeq ($(KERNEL_ARCH), arm64) + real_cc := REAL_CC=$(KERNEL_LLVM_BIN) CLANG_TRIPLE=aarch64-linux-gnu- + else + real_cc := REAL_CC=$(KERNEL_LLVM_BIN) CLANG_TRIPLE=arm-linux-gnueabihf + endif else ifeq ($(strip $(KERNEL_GCC_NOANDROID_CHK)),0) KERNEL_CFLAGS := KCFLAGS=-mno-android diff --git a/Documentation/arm/msm/msm_smp2p.txt b/Documentation/arm/msm/msm_smp2p.txt new file mode 100644 index 000000000000..d20443a41ba4 --- /dev/null +++ b/Documentation/arm/msm/msm_smp2p.txt @@ -0,0 +1,476 @@ +Introduction +============ +The Shared Memory Point to Point (SMP2P) protocol facilitates communication of +a single 32-bit value between two processors. Each value has a single writer +(the local side) and a single reader (the remote side). Values are uniquely +identified in the system by the directed edge (local processor ID to remote +processor ID) and a string identifier. + +Version and feature negotiation has been included in the design to allow for +phased upgrades of all processors. + +Software Architecture Description +================================= +The data and interrupt coupling between processors is shown in Fig. 1. Each +processor is responsible for creating the outgoing SMEM items and each item is +writable by the local processor and readable by the remote processor. By using +two separate SMEM items that are single-reader and single-writer, SMP2P does +not require any remote locking mechanisms. + +The client API uses the Linux GPIO and interrupt framework to expose a virtual +GPIO and a virtual interrupt controller for each entry. + + ================= + | | + -----write------>|SMEM item A->B |-----read------ + | | | | + | ================= | + | | + | v + GPIO API => ------------ ======= Interrupt line ======> ------------ + Processor A Processor B + Interrupt <= ------------ <====== Interrupt line ======= ------------ + API ^ | + | | + | | + | ================= | + | | | | + ------read-------|SMEM item A<-B |<-----write---- + | | + ================= + + Fig 1 + + +Design +====== +Each SMEM item contains a header that is used to identify and manage the edge +along with an array of actual entries. The overall structure is captured in +Fig 2 and the details of the header and entries are covered later in this +section. The memory format of all shared structures is little-endian. + + ----------------------------------------------- + | SMEM item A->B | + | | + | ----------------------------------------- | + | |31 24| 16| 8| 0| | + | |----------|---------|----------|---------| | + | | Identifier Constant(Magic Number) | | + | |----------|---------|----------|---------| | + | | Feature Flags |Version | | + | | |Number | | + | |----------|---------|----------|---------| | + | | Remote Proc ID |Local Proc ID | | + | |----------|---------|----------|---------| | + | | Entries Valid | Entries Total | | + | |-----------------------------------------| | + | | + | | + | ----------------------------------------- | + | | Entry 0 | | + | | ---------------------------------- | | + | | | Identifier String | | | + | | |---------------------------------| | | + | | | Data | | | + | | |---------------------------------| | | + | |---------------------------------------| | + | ----------------------------------------- | + | | Entry 1 | | + | | ---------------------------------- | | + | | | Identifier String | | | + | | |---------------------------------| | | + | | | Data | | | + | | |---------------------------------| | | + | |---------------------------------------| | + | - | + | - | + | - | + | ----------------------------------------- | + | | Entry N | | + | | ---------------------------------- | | + | | | Identifier String | | | + | | |---------------------------------| | | + | | | Data | | | + | | |---------------------------------| | | + | |---------------------------------------| | + ----------------------------------------------- + + Fig 2 + + +The header of each SMEM item contains metadata that describes the processors +using the edge, the version information, and the entry count. The constant +identifier is used as a magic number to enable extraction of the items from a +memory dump. The size of each entry depends upon the version, but the number +of total entries (and hence the size of each SMEM item) is configurable with a +suggested value of 16. + +The number of valid entries is used to indicate how many of the Entries Total +are currently used and are current valid. + + --------------------------------------------------------------------------- + |Field Size Description Valid Values | + --------------------------------------------------------------------------- + | Identifier 4 Bytes Value used to identify | + | Constant structure in memory. Must be set to $SMP | + | Useful for debugging. (0x504D5324) | + --------------------------------------------------------------------------- + | Local 2 Bytes Writing processor ID. Refer Processor ID Table 3| + | Processor | + | ID | + --------------------------------------------------------------------------- + | Remote 2 Bytes Reading processor ID. Refer Processor ID Table 3| + | Processor | + | ID | + --------------------------------------------------------------------------- + | Version 1 Bytes Refer to Version | + | Number Feature Negotiation Must be set to 1. | + | section. | + --------------------------------------------------------------------------- + | Feature 3 Bytes Refer to Version | + | flags and Feature Negotiation | + | section for details. | + | bit 0 SSR_ACK Feature Supported when set to 1 | + | bits 1:31 Reserved Must be set to 0. | + --------------------------------------------------------------------------- + | Entries 2 Bytes Total number of Must be 0 or greater. | + | Total entries. | + --------------------------------------------------------------------------- + | Entries 2 Bytes Number of valid Must be between 0 | + | Valid entries. and Entries Total. | + --------------------------------------------------------------------------- + | Flags 4 Bytes | + | bit 0 RESTART_DONE Toggle for every restart | + | bit 1 RESTART_ACK Toggle to ACK remote | + | RESTART_DONE | + | bits 2:31 Reserved Must be set to 0. | + --------------------------------------------------------------------------- + Table 1 - SMEM Item Header + +The content of each SMEM entries is described in Table 2 and consists of a +string identifier and a 32-bit data value. The string identifier must be +unique for each SMEM item. The data value is opaque to SMP2P giving the client +complete flexibility as to its usage. + + ----------------------- --------------------- ----------------------------- + | Field | Size | Description | Valid Values | + ------------|----------|---------------------|----------------------------- + | | | | | + | Identifier | 16 Bytes | Null Terminated | NON-NULL for | + | String | | ASCII string. | valid entries. | + | | | | | + ------------|----------|---------------------|----------------------------- + | Data | 4 Bytes | Data | Any (client defined) | + ------------ ---------- --------------------- ----------------------------- + Table 2 - Entry Format + + +The processor IDs in the system are fixed and new processors IDs will be +added to the end of the list (Table 3). + + ------------------------------------------------- + | Processor Name | ID value | + ------------------------------------------------- + | Application processor | 0 | + ------------------------------------------------- + | Modem processor | 1 | + ------------------------------------------------- + | Audio processor | 2 | + ------------------------------------------------- + | Sensor processor | 3 | + ------------------------------------------------- + | Wireless processor | 4 | + ------------------------------------------------- + | Modem Fw | 5 | + ------------------------------------------------- + | Power processor | 6 | + ------------------------------------------------- + | TrustZone processor | 7 | + ------------------------------------------------- + | NUM PROCESSORS | 8 | + ------------------------------------------------- + Table 3 - Processor IDs + +SMEM Item +--------- +The responsibility of creating an SMEM item is with the local processor that is +initiating outbound traffic. After creating the item, the local and remote +processors negotiate the version and feature flags for the item to ensure +compatibility. + +Table 4 lists the SMEM item base identifiers. To get the SMEM item ID for a +particular edge, the remote processor ID (Table 3) is added to the base item ID +for the local processor (Table 4). For example, the Apps ==> Modem (id 1) SMEM +Item ID will be 427 + 1 = 428. + + --------------------------------------------------- + | Description | SMEM ID value | + --------------------------------------------------- + | Apps SMP2P SMEM Item base | 427 | + --------------------------------------------------- + | Modem SMP2P SMEM Item base | 435 | + --------------------------------------------------- + | Audio SMP2P SMEM Item base | 443 | + --------------------------------------------------- + | Sensors SMP2P SMEM Item base | 481 | + --------------------------------------------------- + | Wireless SMP2P SMEM Item base | 451 | + --------------------------------------------------- + | Power SMP2P SMEM Item base | 459 | + --------------------------------------------------- + | TrustZone SMP2P SMEM Item base | 489 | + --------------------------------------------------- + Table 4 - SMEM Items Base IDs + + +Version and Feature Negotiation +------------------------------- +To enable upgrading without breaking the system and to enable graceful feature +fall-back support, SMP2P supports a version number and feature flags. The +combination of the version number and feature flags enable: + 1) SMP2P software updates to be rolled out to each processor separately. + 2) Individual features to be enabled or disabled per connection or edge. + +The version number represents any change in SMP2P that breaks compatibility +between processors. Examples would be a change in the shared data structures +or changes to fundamental behavior. Each implementation of SMP2P must be able +to support a minimum of the current version and the previous version. + +The feature flags represent any changes in SMP2P that are optional and +backwards compatible. Endpoints will negotiate the supported flag when the +SMEM items are created and they cannot be changed after negotiation has been +completed. + + +Negotiation Algorithm +---------------------- +While creating the SMEM item the following algorithm shall be used. + + if remote endpoint's SMEM Item exists + Read remote version number and flags + Local version number must be lower of + - remote version number + - highest supported local version number + Flags value is bitwise AND of + - remote feature flags + - locally supported flags + Create SMEM item and populate negotiated number and flags + Interrupt remote processor + if version and flags match, negotiation is complete, else wait + for remote interrupt below. + Else + Create SMEM item and populate it with highest supported version and any + requested feature flag. + Interrupt remote processor. + Wait for Interrupt below. + +Upon receiving the interrupt from remote processor and negotiation is not +complete, check the version number and feature flags: + if equal, negotiation is complete. + if remote number is less than local number, and remote number is + supported: + Set local version number to remote version number + Bitwise AND local flags with remote flags + Interrupt remote processor + Negotiation is complete + if remote number is not supported, then negotiation has failed + Set version number to 0xFF and report failure in kernel log. + if remote number is more than local number: + Wait for remote endpoint to process our interrupt and negotiate down. + + +Creating an SMEM Entry +---------------------- +Each new SMEM entry used in data transfer must be created at the end of the +entry array in the SMEM item and cannot be deleted until the system is +rebooted. The following sequence is be followed: + 1) Compare Entries Valid and Entries Total to verify if there is room in the + entry array for this request (if not, return error code to client). + 2) Populate the Identifier of new entry and do a write memory barrier. + 3) Update Entries Valid and Entries Total and do a write memory barrier. + 4) Interrupt remote endpoint. + + +Entry Write +----------- +An entry write is achieved by the following sequence of operations: + 1) Update data field in the entry and do a write memory barrier. + 2) Interrupt remote endpoint. + + +Entry Read / Receiving Interrupts +--------------------------------- +An interrupt will be received from the remote system for one or more of the following events: + 1) Initialization + 2) Entry change + 3) New Entry + +As long as the SMEM item initialization is complete, then each interrupt should +trigger SMP2P to: + 1) Compare valid entry data value to cached value and notify client if it + has changed. + 2) Compare Entries Valid to cached value. If changed, initialize new entries. + +Security +======== +Since the implementation resides in the kernel and does not expose interfaces +to userspace, no security issues are anticipated. The usage of separate SMEM +items allows for future security enhancements in SMEM. + +Performance +=========== +No performance issues are anticipated as the signaling rate is expected to be +low and is performed in interrupt context which minimizes latency. + +Interfaces +================ +SMP2P is only supported in the kernel and interfaces with clients through the +GPIO and interrupt subsystems. + +To map an entry to the client, the client must add two nodes to the Device +Tree: + 1) A node that matches "qcom,smp2pgpio" to create the entry + 2) A node that matches the client driver to provide the GPIO pin mapping + +The details of the device tree entries for the GPIO interface are contained in +the file Documentation/devicetree/bindings/gpio/gpio-smp2p.txt. + + /* SMP2P Test Driver for inbound entry. */ + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P Test Client for inbound entry. */ + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>, + <&smp2pgpio_smp2p_7_in 1 0>, + . . . + <&smp2pgpio_smp2p_7_in 31 0>; + }; + + /* SMP2P Test Driver for outbound entries */ + smp2pgpio_smp2p_345_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P Test Client for outbound entry. */ + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>, + <&smp2pgpio_smp2p_7_out 1 0>, + . . . + <&smp2pgpio_smp2p_7_out 31 0>; + +The client can use a match entry for "qcom,smp2pgpio_test_smp2p_7_in" to +retrieve the Device Tree configuration node. Once that node has been +retrieved, the client can call of_get_gpio() to get the virtual GPIO pin and +also use gpio_to_irq() to map the GPIO pin to a virtual interrupt. After that +point, the standard GPIO and Interrupt APIs can be used to manipulate the SMP2P +entries and receive notifications of changes. Examples of typical function +calls are shown below: + of_get_gpio() + gpio_get_value() + gpio_set_value() + gpio_to_irq() + request_irq() + free_irq() + +Please reference the unit test code for example usage. + +Subsystem Restart +================= +SMP2P is unaffected by SubSystem Restart (SSR) on the high-level OS side and is +actually used as an underlying communication mechanism for SSR. On the +peripheral system that is being restarted, SMP2P will zero out all existing +state entries upon reboot as part of the SMP2P initialization process and if the +SSR_ACK feature is enabled, then it waits for an acknowledgment as outlined in +the following subsections. + +SSR_ACK Feature - Reboot Use Case (Non-HLOS Only) +------------------------------------------------- +If a remote system boots up after an SSR and sees that the remote and local +version numbers and feature flags are equal, then it zeros out entry values. If +the SSR_ACK feature is enabled, it will wait for an acknowledgment from the other +processor that it has seen the zero entry before completing the negotiation +sequence. + + if remote and local version numbers and feature flags are equal + Zero out all entry values + if SSR_ACK feature is enabled + Set local RESTART_DONE flag to inverse of the remote RESTART_ACK + Send interrupt to remote system + Wait for interrupt and for remote RESTART_ACK to be equal to local + RESTART_DONE + Continue with normal negotiation sequence + +Interrupt Use Case +------------------ +For every interrupt triggered by a remote change, SMP2P will notify the client +of a change in state. In addition, if the SSR_ACK feature is enabled, the SSR +handshaking will also be handled. + + if SSR_ACK feature is enabled + if remote RESTART_DONE != local RESTART_ACK + Notify client of entry change (will be * -> 0 transition) + Toggle local RESTART_ACK + Send interrupt to remote system + else + Notify client of entry change as usual + else + Notify client of entry change as usual + +Debug +===== +The state values and names for all entries accessible by the Apps are +accessible through debugfs nodes for general debug purposes. + +Debugfs entries for triggering unit-tests are also exported. + +Internal logging will be performed using the IPC Logging module to enable +post-mortem analysis. + +Testing +======= +On-target unit testing will be done to verify internal functionality and the +GPIO/IRQ API's. + +Driver parameters +================= +One module parameter will be provided to change the verbosity of internal logging. + +Config options +============== +Configuration of interrupts will be done using Device Tree per the format in +Documentation/devicetree/bindings/arm/msm/smp2p.txt. By default, the testing +components will be enabled since it does not affect performance and has a +minimal impact on kernel size. However, customers can disable the testing +component for size optimization. + + CONFIG_MSM_SMP2P - enables SMP2P + CONFIG_MSM_SMP2P_TEST - enables unit test support + +Dependencies +=========== +Requires SMEM for creating the SMEM items. + +User Space utilities +==================== +No userspace utilities are planned. + +Known issues +============ +None. diff --git a/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt b/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt new file mode 100644 index 000000000000..ef40b72cacf1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt @@ -0,0 +1,28 @@ +Qualcomm Technologies, Inc. BAM Data Multiplexer Driver + +Required properties: +- compatible : should be "qcom,bam_dmux" +- reg : the location and size of the BAM hardware +- interrupts : the BAM hardware to apps processor interrupt line + +Optional properties: +-qcom,satellite-mode: the hardware needs to be configured in satellite mode +-qcom,rx-ring-size: the size of the receive ring buffer pool, default is 32 +-qcom,max-rx-mtu: the maximum receive MTU that can be negotiated, in bytes. + Default is 2048. Other possible values are 4096, 8192, and 16384. +-qcom,no-cpu-affinity: boolean value indicating that workqueue CPU affinity + is not required. +-qcom,fast-shutdown: boolean value to support fast shutdown time. + +Example: + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + qcom,satellite-mode; + qcom,rx-ring-size = <64>; + qcom,max-rx-mtu = <8192>; + qcom,no-cpu-affinity; + qcom,fast-shutdown; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt b/Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt new file mode 100644 index 000000000000..56fa470eddfe --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt @@ -0,0 +1,49 @@ +* MSM Sleep status + +MSM Sleep status device is used to check the power collapsed status of a +offlined core. The core that initiates the hotplug would wait on the +sleep status device before CPU_DEAD notifications are sent out. Some hardware +devices require that the offlined core is power collapsed before turning off +the resources that are used by the offlined core. + +The required properties of core sleep status node are: +- compatible: qcom,cpu-sleep-status + +The required properties of sleep status node are: +- reg: physical address of the sleep status register for the cpus +- qcom,cpu-sleep-status-mask - The bit mask within the status register that + indicates the Core's sleep state. + +Example: + qcom,cpu-sleep-status { + compatible = "qcom,cpu-sleep-status"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + + qcom,sleep-status = <&cpu0_slp_sts>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo"; + + qcom,sleep-status = <&cpu1_slp_sts>; + }; + }; + + cpu0_slp_sts: cpu-sleep-status@9981058 { + reg = <0x9981058 0x100>; + qcom,sleep-status-mask = <0xc00000>; + }; + + cpu1_slp_sts: cpu-sleep-status@9991058 { + reg = <0x9991058 0x100>; + qcom,sleep-status-mask = <0xc00000>; + } diff --git a/Documentation/devicetree/bindings/arm/msm/ipc-spinlock.txt b/Documentation/devicetree/bindings/arm/msm/ipc-spinlock.txt new file mode 100644 index 000000000000..db3f26835af9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/ipc-spinlock.txt @@ -0,0 +1,27 @@ +Qualcomm Technologies, Inc. Interprocessor Communication Spinlock + +--Dedicated Hardware Implementation-- +Required properties: +- compatible : should be "qcom,ipc-spinlock-sfpb" +- reg : the location and size of the spinlock hardware +- qcom,num-locks : the number of locks supported + +Example: + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x1000>; + qcom,num-locks = <32>; + }; + +--LDREX Implementation-- +Required properties: +- compatible : should be "qcom,ipc-spinlock-ldrex" +- reg : the location and size of the shared lock memory + +Example: + + qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt b/Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt new file mode 100644 index 000000000000..9fc20315674d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt @@ -0,0 +1,22 @@ +* JTAG-FUSE + +The jtag-fuse entry specifies the memory mapped addresses for the fuse +registers. The jtag-fuse driver uses these to provide api(s) that can be used +by jtag save and restore driver(s) to query whether the Hardware they manage +is functionally disabled or not and take corresponding steps. + +Required Properties: +compatible: component name used for driver matching, should be one of the + following: + "qcom,jtag-fuse" for jtag fuse device + "qcom,jtag-fuse-v2" for jtag fuse v2 device + "qcom,jtag-fuse-v3" for jtag fuse v3 device +reg: physical base address and length of the register set +reg-names: should be "fuse-base" + +Example: + jtag_fuse: jtagfuse@fc4be024 { + compatible = "qcom,jtag-fuse"; + reg = <0xfc4be024 0x8>; + reg-names = "fuse-base"; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/mpm.txt b/Documentation/devicetree/bindings/arm/msm/mpm.txt new file mode 100644 index 000000000000..c3535cb65400 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/mpm.txt @@ -0,0 +1,77 @@ +* MSM Sleep Power Manager (mpm-v2) + +The MPM acts a sleep power manager to shutdown the clock source and put the +device into a retention mode to save power. The MPM is also responsible for +waking up and bringing up the resources from sleep. The MPM driver configures +interrupts monitored by the MPM hardware before entering sleep through a +RPM interface. + +The required nodes for the MPM driver are: + +- compatible: "qcom, mpm-v2" +- reg: Specifies the base physical address(s) and the size of the MPM + registers. The MPM driver access two memory regions for confifure the + virtual MPM driver on the RPM. The first region is the memory space + shared with the virtual MPM driver. The second region is the address + to the register that triggers a interrupt to the RPM. +- reg-names: "vmpm" - string to identify the shared memory space region + "ipc" - string to identify the register that triggers a interrupt +- clocks: clock identifers used by clock driver while looking up mpm clocks. +- clock-names: name of the clock used by mpm driver. +- qcom,ipc-bit-offset: The bit to set in the ipc register that triggers a interrupt + to the RPM +- qcom,gic-parent: phandle to the gic interrupt controller +- qcom,gic-map: Provides a mapping of how a GIC interrupt is connect to a MPM. The + mapping is presented in tuples. Each tuple represents a MPM pin and + which GIC interrupt is routed to it. Since MPM monitors interrupts + only during system wide low power mode, system interrupts originating + from other processors can be ignored and assigned an MPM pin mapping + of 0xff. +- qcom,gpio-parent: phandle to the GPIO interrupt controller +- qcom,gpio-map: Provides a mapping of how a GPIO interrupt is connect to a MPM. The + mapping is presented in tuples. Each tuple represents a MPM pin and + which GIC interrupt is routed to it. Since MPM monitors interrupts + only during system wide low power mode, system interrupts originating + from other processors can be ignored and assigned an MPM pin mapping + of 0xff. + +Optional Properties: + +- qcom,num-mpm-irqs : Specifies the number of mpm interrupts supported on a + target. If the property isn't present, 64 interrupts are + considered for the target by default. + +Example: + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K*/ + <0xfa006000 0x1000>; /* MSM_APCS_GCC_BASE 4K*/ + reg-names = "vmpm", "ipc" + interrupts = <0 171 1>; + clocks = <&clock_rpm clk_xo_lpm_clk>; + clock-names = "xo"; + + qcom,ipc-bit-offset = <0>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <25 132>, + <27 111>, + <0xff 48>, + <0xff 51>, + <0xff 52>, + <0xff 53>, + <0xff 54>, + <0xff 55>; + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <1 46>, + <2 150>, + <4 103>, + <5 104>, + <6 105>, + <7 106>, + <8 107>, + <53 37>, + <54 24>, + <55 14>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index c72bd4ee7736..2989e2084d46 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -22,6 +22,8 @@ restart@fc4ab000 { * Compatible strings: SoCs: +- MDM9607 + compatible = "qcom,mdm9607" - APQ8016 compatible = "qcom,apq8016" @@ -248,3 +250,4 @@ compatible = "qcom,atoll-ab-atp" compatible = "qcom,atoll-ab-qrd" compatible = "qcom,qcs610-iot" compatible = "qcom,qcs410-iot" +compatible = "qcom,mdm9607-mtp" diff --git a/Documentation/devicetree/bindings/arm/msm/msm_ipc_router.txt b/Documentation/devicetree/bindings/arm/msm/msm_ipc_router.txt new file mode 100644 index 000000000000..256905c874d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/msm_ipc_router.txt @@ -0,0 +1,16 @@ +Qualcomm Technologies, Inc. IPC Router + +Required properties: +-compatible: should be "qcom,ipc_router" +-qcom,node-id: unique ID to identify the node in network + +Optional properties: +-qcom,default-peripheral: String property to indicate the default peripheral + to communicate + +Example: + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + qcom,default-peripheral = "modem"; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_ipc_router_smd_xprt.txt b/Documentation/devicetree/bindings/arm/msm/msm_ipc_router_smd_xprt.txt new file mode 100644 index 000000000000..1d74447ddd97 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/msm_ipc_router_smd_xprt.txt @@ -0,0 +1,34 @@ +Qualcomm Technologies, Inc. IPC Router SMD Transport + +Required properties: +-compatible: should be "qcom,ipc_router_smd_xprt" +-qcom,ch-name: the SMD channel name used by the SMD transport +-qcom,xprt-remote: string that defines the edge of the transport (PIL Name) +-qcom,xprt-linkid: unique integer to identify the tier to which the link + belongs to in the network and is used to avoid the + routing loops while forwarding the broadcast messages +-qcom,xprt-version: unique version ID used by SMD transport header + +Optional properties: +-qcom,fragmented-data: Indicate the SMD transport supports fragmented data +-qcom,disable-pil-loading: Disable PIL Loading of the remote subsystem + +Example: + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_smd_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "modem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + qcom,disable-pil-loading; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_smd_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "adsp"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt new file mode 100644 index 000000000000..de66152d650e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt @@ -0,0 +1,448 @@ +MSM thermal driver (MSM_THERMAL) + +MSM_THERMAL is a kernel platform driver which regulates thermal conditions +on the device during kernel boot. The goal of MSM_THERMAL is to prevent the +temperature of the system from exceeding a thermal limit at which it cannot +operate. Examples are CPU junction thermal limit, or POP memory thermal limit. +The MSM_THERMAL driver polls the TSENS sensor hardware during boot, and +reduces the maximum CPU frequency allowed in steps, to limit power/thermal +output when a threshold temperature is crossed. It restores the maximum CPU +frequency allowed in the same stepwise fashion when the threshold temperature +(with hysteresis gap) is cleared. + +The devicetree representation of the MSM_THERMAL block should be: + +Required properties + +- compatible: "qcom,msm-thermal" +- qcom,sensor-id: The id of the TSENS sensor polled for temperature. + Typically the sensor closest to CPU0. +- qcom,poll-ms: Sampling interval to read sensor, in ms. +- qcom,limit-temp: Threshold temperature to start stepping CPU down, in degC. +- qcom,temp-hysteresis: Degrees C below threshold temperature to step CPU up. +- qcom,freq-step: Number of frequency steps to take on each CPU mitigation. + +Optional properties + +- reg: Physical address for uio mapping +- qcom,core-limit-temp: Threshold temperature to start shutting down cores + in degC +- qcom,core-temp-hysteresis: Degrees C below which the cores will be brought + online in sequence. +- qcom,hotplug-temp: Threshold temperature to start shutting down cores + in degC. This will be used when polling based + core control is disabled. The difference between hotplug-temp + and core-limit-temp is that core-limit-temp is used during + early boot prior to thermal_sys being available for hotplug. +- qcom,hotplug-temp-hysteresis: Degrees C below which thermal will not force the + cores to be offlined. Cores can be brought online if needed. +- qcom,freq-mitigation-temp: Threshold temperature to mitigate + the CPU max frequency in degC. This will be + used when polling based frequency control is disabled. + The difference between freq-mitigation-temp + and limit-temp is that limit-temp is used during + early boot prior to thermal_sys being available for registering + temperature thresholds. Also, this emergency frequency + mitigation is a single step frequency mitigation to a predefined value + as opposed to the step by step frequency mitigation during boot-up. +- qcom,freq-mitigation-temp-hysteresis: Degrees C below which thermal will not mitigate the + cpu max frequency. +- qcom,freq-mitigation-value: The frequency value (in kHz) to which the thermal + should mitigate the CPU, when the freq-mitigation-temp + threshold is reached. +- qcom,vdd-restriction-temp: When temperature is below this threshold, will + enable vdd restriction which will set higher voltage on + key voltage rails, in degC. +- qcom,vdd-restriction-temp-hysteresis: When temperature is above this threshold + will disable vdd restriction on key rails, in degC. +- qcom,pmic-sw-mode-temp: Threshold temperature to disable auto mode on the + rail, in degC. If this property exists, + qcom,pmic-sw-mode-temp-hysteresis and + qcom,pmic-sw-mode-regs need to exist, otherwise return error. +- qcom,pmic-sw-mode-temp-hysteresis: Degree below threshold temperature to + enable auto mode on the rail, in degC. If this property exists, + qcom,pmic-sw-mode-temp and qcom,pmic-sw-mode-regs need to + exist, otherwise return error. +- qcom,pmic-sw-mode-regs: Array of the regulator names that will want to + disable/enable automode based on the threshold. If this + property exists, qcom,pmic-sw-mode-temp and + qcom,pmic-sw-mode-temp-hysteresis need to exist, otherwise + return error. Also, if this property is defined, will have to + define <consumer_supply_name>-supply = <&phandle_of_regulator> +- <consumer_supply_name>-supply = <&phandle_of_regulator>: consumer_supply_name + is the name that's defined in thermal driver. + phandle_of_regulator is defined by reuglator device tree. +- qcom,online-hotplug-core: This property should be defined in targets where + KTM should online cores, which are hotplugged due to + thermal condition. +- qcom,synchronous-cluster-id: This property specifies an array of synchronous cluster-ID's. + This property will be used by KTM to optimize the synchronous + cluster frequency update. +- qcom,synchronous-cluster-map: This property specifies an array of cluster-ID, + number of cpus in that cluster and their corresponding cpu + phandles. This property should be defined in targets where + the kernel topology module is not present. + In the older kernel version, where the kernel topology module is + not available, KTM gets the mapping information from this property. +- qcom,disable-vdd-mx: If this property is defined, the feature VDD MX + restriction will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-vdd-rstr: If this property is defined, the feature VDD + restriction will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-sensor-info: If this property is defined, the feature sensor + alias info will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-ocr: If this property is defined, the feature optimum current + request will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-psm: If this property is defined, the feature PMIC software + mode will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-gfx-phase-ctrl: If this property is defined, the feature graphics + phase control will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,disable-cx-phase-ctrl: If this property is defined, the feature + cx phase control will be disabled. All other properties + corresponding to this feature will be ignored. +- qcom,therm-ddr-lm-info: If this optional property is defined, it enables + DDR frequency restriction feature. It expects array of + sensor id to be monitored, high threshold and low threshold + for that sensor respectively. + +Optional child nodes +- qcom,pmic-opt-curr-temp: Threshold temperature for requesting optimum current (request + dual phase) for rails with PMIC, in degC. If this property exists, + then the properties, qcom,pmic-opt-curr-temp-hysteresis and + qcom,pmic-opt-curr-regs should also be defined to enable this + feature. +- qcom,pmic-opt-curr-temp-hysteresis: Degree below the threshold to disable the optimum + current request for a rail, in degC. If this property exists, + then the properties, qcom,pmic-opt-curr-temp and + qcom,pmic-opt-curr-regs should also be defined to enable + this feature. +- qcom,pmic-opt-curr-regs: Name of the rails for which the optimum current should be + requested. If this property exists, then the properties, + qcom,pmic-opt-curr-temp and qcom,pmic-opt-curr-temp-hysteresis + should also be defined to enable this feature. +- qcom,pmic-opt-curr-sensor-id: Sensor, which needs to be monitored for requesting OCR + when qcom,pmic-opt-curr-temp threshold is reached. + It is an optional property, if it is configured, msm_thermal will + monitor only this sensor, otherwise it will monitor all TSENS for + this feature. If this property exists, then the properties, + qcom,pmic-opt-curr-temp, qcom,pmic-opt-curr-temp-hysteresis and + qcom,pmic-opt-curr-regs should also be defined to enable this feature. +- qcom,<vdd restriction child node name>: Define the name of the child node. + If this property exisits, qcom,vdd-rstr-reg, qcom,levels + need to exist. qcom,min-level is optional if qcom,freq-req + exists, otherwise it's required. +- qcom,vdd-rstr-reg: Name of the rail +- qcom,levels: Array of the level values. Unit is corner voltage for voltage request + or kHz for frequency request. +- qcom,min-level: Request this level as minimum level when disabling voltage + restriction. Unit is corner voltage for voltage request. + This will not be required if qcom,freq-req exists. +- qcom,freq-req: Flag to determine if we should restrict frequency on this rail + instead of voltage. +- qcom,max-freq-level: Request this frequency as scaling maximum level when + enabling vdd restriction feature for a rail. This is + an optional property which is only applicable to the rail + with "qcom,freq-req" property set. +- qcom,cx-phase-hot-crit-temp: Threshold temperature for sending the 'HOT_CRITICAL' + temperature band to RPM, in degC. This will aid RPM + in deciding the number of phases required for CX rail. + If this property exists, then the property, + qcom,cx-phase-hot-crit-temp-hyst should also be defined to + enable this feature. +- qcom,cx-phase-hot-crit-temp-hyst: Degree below the threshold to send the 'WARM' + temperature band to RPM, in degC. This will aid RPM + in deciding the number of phases required for CX. + If this property exists, then the property, + qcom,cx-phase-hot-crit-temp should also be defined to enable + this feature. +- qcom,cx-phase-resource-key: The key name to be used for sending the CX + temperature band message to RPM. This property should + be defined along with the other properties required for + CX phase selection feature. +- qcom,gfx-phase-hot-crit-temp: Threshold temperature for sending the 'HOT_CRITICAL' + temperature band to RPM, in degC. This will aid RPM in + deciding the number of phases required for GFX rail. + If this property exists, then the properties, + qcom,gfx-phase-hot-crit-temp-hyst and qcom,gfx-sensor-id + should also be defined to enable this feature. +- qcom,gfx-phase-hot-crit-temp-hyst: Degree below the threshold to clear the 'HOT_CRITICAL' + band and send the 'WARM' temperature band to RPM, in degC. + This will aid RPM in deciding the number of phases required + for GFX rail. If this property exists, then the properties, + qcom,gfx-phase-hot-crit-temp and qcom,gfx-sensor-id + should also be defined to enable this feature. +- qcom,gfx-phase-warm-temp: Threshold temperature for sending the 'WARM' temperature + band to RPM, in degC. This will aid RPM in deciding the + number of phases required for GFX rail. If this property + exists, then the properties, qcom,gfx-sensor-id and + qcom,gfx-phase-warm-temp-hyst should also be defined to + enable this feature. +- qcom,gfx-phase-warm-temp-hyst: Degree below the threshold to clear the 'WARM' + band and send the 'NORMAL' temperature band to RPM, in degC. + This will aid RPM in deciding the number of phases required + for GFX rail. If this property exists, then the property, + qcom,gfx-sensor-id and qcom,gfx-phase-warm-temp should also + be defined to enable this feature. +-qcom,gfx-sensor-id: The ID of the TSENS sensor, which is closest to graphics + processor, monitoring the GPU temperature. If this property + exists, then the property, qcom,gfx-phase-hot-crit-temp and + qcom,gfx-phase-hot-crit-temp-hyst or/and qcom,gfx-phase-warm-temp + and qcom,gfx-phase-warm-temp-hyst should also be defined to + enable this feature. +- qcom,gfx-phase-resource-key: The key name to be used for sending the GFX temperature + band message to RPM. This property should be defined along + with the other properties required for GFX phase selection + feature. +- qcom,rpm-phase-resource-type: The RPM resource type name to be used for sending + temperature bands for CX and GFX phase selection. This + property should be defined along with the other properties + required for CX and GFX phase selection feature. +- qcom,rpm-phase-resource-id: The RPM resource ID to be used for sending temperature + bands for CX and GFX phase selection. This property should + be defined along with the other properties required for CX + and GFX phase selection feature. +- qcom,mx-restriction-temp: Threshold temperature below which the module votes for + higher data retention voltage of MX and CX supply. If and only if this + property exists, then the property qcom,mx-restriction-temp-hysteresis, + qcom,mx-retention-min should also be present. Also, if this + property is defined, will have to define vdd-mx-supply = + <&phandle_of_regulator> +- qcom,mx-restriction-temp-hysteresis: Degree above the threshold to remove MX and CX vote. + If this property exists, then the property qcom,mx-restriction-temp, + qcom,mx-retention-min should also be present.Also, if this + property is defined, will have to define vdd-mx-supply = + <&phandle_of_regulator> +- qcom,mx-retention-min: Minimum data retention voltage to be applied to MX rail if + the low threshold is crossed. If this property exists, then the + property qcom,mx-restriction-temp and + qcom,mx-restriction-temp-hysteresis should also be present. + Also, if this property is defined, will have to define + vdd-mx-supply = <&phandle_of_regulator> +- qcom,cx-retention-min: Minimum data retention voltage to be applied to CX rail if the low + threshold is crossed. If this property exists, then the property + qcom,mx-restriction-temp and qcom,mx-restriction-temp-hysteresis + should also be present. Also, if this property is defined, will + have to define vdd-cx-supply = <&phandle_of_regulator>. +- qcom,mx-restriction-sensor_id: sensor id, which needs to be monitored for requesting MX/CX + retention voltage. If this optional property is defined, msm_thermal + will monitor only this sensor, otherwise by default it will monitor + all TSENS for this feature. If this property exists, then the properties, + qcom,mx-restriction-temp, qcom,mx-restriction-temp-hysteresis and + qcom,mx-retention-min should also be defined to enable this feature. +- qcom,therm-reset-temp: Degree above which the KTM will initiate a secure watchdog reset. + When this property is defined, KTM will monitor all the tsens from + boot time and will initiate a secure watchdog reset if any of the + tsens temperature reaches this threshold. This reset helps in + generating more informative crash dumps opposed to the crash dump + generated by the hardware reset. + +Example: + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + reg = <0x70000 0x1000>; + qcom,sensor-id = <0>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,therm-reset-temp = <115>; + qcom,core-limit-temp = <90>; + qcom,core-temp-hysteresis = <10>; + qcom,hotplug-temp = <110>; + qcom,hotplug-temp-hysteresis = <20>; + qcom,freq-mitigation-temp = <110>; + qcom,freq-mitigation-temp-hysteresis = <20>; + qcom,freq-mitigation-value = <960000>; + qcom,rpm-phase-resource-type = "misc"; + qcom,rpm-phase-resource-id = <0>; + qcom,cx-phase-resource-key = "tmpc"; + qcom,cx-phase-hot-crit-temp = <75>; + qcom,cx-phase-hot-crit-temp-hyst = <15>; + qcom,gfx-phase-warm-temp = <60>; + qcom,gfx-phase-warm-temp-hyst = <10>; + qcom,gfx-phase-hot-crit-temp = <85>; + qcom,gfx-phase-hot-crit-temp-hyst = <15>; + qcom,gfx-sensor-id = <4>; + qcom,gfx-phase-resource-key = "tmpg"; + qcom,pmic-sw-mode-temp = <90>; + qcom,pmic-sw-mode-temp-hysteresis = <80>; + qcom,pmic-sw-mode-regs = "vdd-dig"; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + vdd-dig-supply=<&pm8841_s2_floor_corner> + qcom,mx-restriction-temp = <5>; + qcom,mx-restriction-temp-hysteresis = <10>; + qcom,mx-retention-min = <710000>; + qcom,mx-restriction-sensor_id = <2>; + vdd-mx-supply = <&pma8084_s1>; + qcom,cx-retention-min = <RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS>; + vdd-cx-supply = <&pmd9635_s5_level>; + qcom,online-hotplug-core; + qcom,therm-ddr-lm-info = <1 90 75>; + qcom,synchronous-cluster-id = <0 1>; /* Indicates cluster 0 and 1 are synchronous */ + qcom,synchronous-cluster-map = <0 2 &CPU0 &CPU1>, + <1 2 &CPU2 &CPU3>; + /* <cluster-ID, number of cores in cluster, cpu phandles>. + ** In the above case, the cluster with ID 0 & 1 has 2 cores + ** and their phandles are mentioned. + */ + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <1881600 1958400 2265600>; + qcom,freq-req; + qcom,max-freq-level = <1958400>; + }; + }; + + + +The sensor information node is an optional node that holds information +about thermal sensors on a target. The information includes sensor type, +sensor name, sensor alias and sensor scaling factor. The parent node +name is qcom,sensor-information. It has a list of optional child +nodes, each representing a sensor. The child node is named as +qcom,sensor-information-<id>. The id takes values sequentially +from 0 to N-1 where N is the number of sensors. This id doesn't +relate to zone id or sensor id. + +The devicetree representation of sensor information node should be: + +1.0 Required properties: + +- compatible: "qcom,sensor-information" + +1.1 Optional nodes: + +qcom,sensor-information-<id> + +The below properties belong to the child node qcom,sensor-information-<id>. +Following are the required and optional properties of a child node. + +1.1.a Required properties: + +- qcom,sensor-type: Type of a sensor. A sensor can be of type tsens, + alarm or adc. + tsens: Sensors that are on MSM die. + alarm: Sensors that are on PMIC die. + adc: Sensors that are usually thermistors + placed out of the die. +- qcom,sensor-name: Name of a sensor as defined by low level sensor driver. + +1.1.b Optional properties: + +- qcom,alias-name: Alias name for a sensor. The alias name corresponds + to a device such as gpu/pop-mem whose temperature + is relative to the sensor temperature defined in the + child node. This node can not be used for providing + alias name for cpu devices. Thermal driver assigns the + cpu device alias, based on the sensor defined in the + cpu mitigation profile. +- qcom,scaling-factor: The unit that needs to be multiplied to the + sensor temperature to get temperature unit in + degree centigrade. If this property is not + present, a default scaling factor of 1 is assigned + to a sensor. + +Example: + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + }; + + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + }; + + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + }; + + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + }; + + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + }; + + sensor_information5: qcom,sensor-information-5 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor5"; + }; + + sensor_information6: qcom,sensor-information-6 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor6"; + qcom,alias-name = "cpu7"; + } + + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "alarm"; + qcom,sensor-name = "pm8994_tz"; + qcom,scaling-factor = <1000>; + }; + + }; + +=============================================================================== +Mitigation Profile: +=============================================================================== +Thermal driver allows users to specify various mitigation profiles and +associate a profile to a device. The device should have a phandle, to associate +itself with a mitigation profile, using a "qcom,limits-info" property. +This profile can specify whether to mitigate the device during various +limiting conditions. + +Required Node: +- qcom,limit_info-#: This is a mitigation profile node. A profile should + normally have a sensor(s) to monitor and a list + of properties enabling or disabling a mitigation. + +Required properties: + +- qcom,temperature-sensor: Array of phandle(s) to the temperature sensor(s) that + need(s) to be used for monitoring the device associated + with this mitigation profile. Right now the first + sensor will be used for KTM CPU monitoring. Alias + name of multiple sensors monitoring a same device will + be differentiated by appending an index like, "cpu0_0" + and "cpu0_1". A single sensor monitoring multiple + devices will have an alias name like "cpu0-cpu1-cpu2". + +Optional properties: + +- qcom,boot-frequency-mitigate: Enable thermal frequency mitigation + during boot. +- qcom,emergency-frequency-mitigate: Enable emergency frequency mitigation. +- qcom,hotplug-mitigation-enable: Enable hotplug mitigation. This enables + hotplug mitigation both during boot and emergency + condition. + +Example: + mitigation_profile7: qcom,limit_info-7 { + qcom,temperature-sensor = + <&sensor_information6 &sensor_information8>; + qcom,boot-frequency-mitigate; + qcom,emergency-frequency-mitigate; + qcom,hotplug-mitigation-enable; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/rdbg-smp2p.txt b/Documentation/devicetree/bindings/arm/msm/rdbg-smp2p.txt index 3965ec54dacf..6cb0776ca356 100644 --- a/Documentation/devicetree/bindings/arm/msm/rdbg-smp2p.txt +++ b/Documentation/devicetree/bindings/arm/msm/rdbg-smp2p.txt @@ -13,3 +13,19 @@ Example: qcom,smp2p_interrupt_rdbg_2_in { compatible = "qcom,smp2p-interrupt-rdbg-2-in"; }; + +Required properties: +-compatible : Should be one of + To communicate with modem + qcom,smp2pgpio_client_rdbg_2_in (inbound) + qcom,smp2pgpio_client_rdbg_2_out (outbound) + To communicate with modem + qcom,smp2pgpio_client_rdbg_1_in (inbound) + qcom,smp2pgpio_client_rdbg_1_out (outbound) +-gpios : the relevant gpio pins of the entry. + +Example: + qcom,smp2pgpio_client_rdbg_2_in { + compatible = "qcom,smp2pgpio_client_rdbg_2_in"; + gpios = <&smp2pgpio_rdbg_2_in 0 0>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/rpm-log.txt b/Documentation/devicetree/bindings/arm/msm/rpm-log.txt new file mode 100644 index 000000000000..298dd1859b5b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/rpm-log.txt @@ -0,0 +1,61 @@ +* RPM Log + +RPM maintains Ulog in the RPM RAM. A device tree node is added +that will hold the address of the RPM RAM region from where +Ulog is read. The physical address from the RPM RAM region +contains a header where various parameters to read the log are +defined. These parameter's offsets in the header are also stored +as a part of the device tree node. + +The required properties for rpm-log are: + +- compatible: "qcom,rpm-log" +- reg: Specifies the base physical address and the size of the RPM + registers from where ulog is read. + Second register(optional) specifies the offset of the rpm + log start address pointer. If the second register is available, + the offset value read is added to the first register address + to read the ulog message. +- qcom,rpm-addr-phys: RPM reads physical address of the RPM RAM region + differently when compared to Apps. Physical address of + the RPM RAM region is at an offset when seen from Apps. + This property specifies the offset which will get added + to the physical address of RPM RAM to make it + accessible to the Apps. +- qcom,offset-version: Offset from the start of the phys_addr_base where version + information is stored. +- qcom,offset-page-buffer-addr: Offset from the start of the phys_addr_base + where raw log start address is stored. Raw log + start address is the start of raw log in the + RPM address space as it should be seen from rpm. +- qcom,offset-log-len: Offset from the start of the phy_addr_base where log + length is stored. +- qcom,offset-log-len-mask: Offset from the start of the phy_addr_base where + log length mask is stored. +- qcom,offset-page-indices: Offset from the start of the phy_addr_base where + index to the writer is stored. + +Example 1: +qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x2000>; + qcom,offset-rpm-addr = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; +}; + +Example 2: +qcom,rpm-log@fc000000 { + compatible = "qcom,rpm-log"; + reg = <0xfc000000 0x2000>, + <0xfc190018 0x4>; + qcom,offset-rpm-addr = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; +}; diff --git a/Documentation/devicetree/bindings/arm/msm/rpm-rbcpr-stats.txt b/Documentation/devicetree/bindings/arm/msm/rpm-rbcpr-stats.txt new file mode 100644 index 000000000000..9b69037a179a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/rpm-rbcpr-stats.txt @@ -0,0 +1,26 @@ +* RPM RBCPR + +The RBCPR(Rapid Bridge Core Power Reduction) is module on RPM that controls +the voltage level on the chip based on feedback received through various +sensors on the chip that allow compensation of the chip process variation, +temperature etc. +RPM maintains RBCPR (Rapid Bridge Core Power Reduction) related stats in +data memory. This module allows users to read those stats. + +The required properties for rpm-stats are: + +- compatible: "qcom,rpmrbcpr-stats" +- reg: Pointer to the start of the RPM Data Memory. The size of the memory + is inclusive of the entire RPM data memory. +- qcom,start_offset: The offset at which the RBCPR stats are maintained. The + driver module reads this parameter to get another offset + that contain the rbcpr stats. + + +Example: + +qcom,rpm-rbcpr-stats@fc000000 { + compatible = "qcom,rpmrbcpr-stats"; + reg = <0xfc000000 0x1a0000>; + qcom,start-offset = <0x190010>; +}; diff --git a/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt b/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt index d82d521b60f0..eb780dd3681f 100644 --- a/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt +++ b/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt @@ -17,3 +17,15 @@ qcom,smp2p_sleepstate { interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; + + + +Required properties: +-compatible : should be "qcom,smp2pgpio_sleepstate_3_out"; +-gpios : the relevant gpio pins of the entry. + +Example: + qcom,smp2pgpio-sleepstate-3-out { + compatible = "qcom,smp2pgpio_sleepstate_3_out"; + gpios = <&smp2pgpio_sleepstate_3_out 0 0>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/smdpkt.txt b/Documentation/devicetree/bindings/arm/msm/smdpkt.txt new file mode 100644 index 000000000000..684088828364 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/smdpkt.txt @@ -0,0 +1,42 @@ +Qualcomm Technologies, Inc. Shared Memory Packet Driver (smdpkt) + +[Root level node] +Required properties: +-compatible : should be "qcom,smdpkt" + +[Second level nodes] +qcom,smdpkt-port-names +Required properties: +-qcom,smdpkt-remote : the remote subsystem name +-qcom,smdpkt-port-name : the smd channel name +-qcom,smdpkt-dev-name : the smdpkt device name + +Example: + + qcom,smdpkt { + compatible = "qcom,smdpkt"; + + qcom,smdpkt-data5-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-dev-name = "smdcntl0"; + }; + + qcom,smdpkt-data6-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA6_CNTL"; + qcom,smdpkt-dev-name = "smdcntl1"; + }; + + qcom,smdpkt-cxm-qmi-port-8064 { + qcom,smdpkt-remote = "wcnss"; + qcom,smdpkt-port-name = "CXM_QMI_PORT_8064"; + qcom,smdpkt-dev-name = "smd_cxm_qmi"; + }; + + qcom,smdpkt-loopback { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "LOOPBACK"; + qcom,smdpkt-dev-name = "smd_pkt_loopback"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/smdtty.txt b/Documentation/devicetree/bindings/arm/msm/smdtty.txt new file mode 100644 index 000000000000..cedd36560049 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/smdtty.txt @@ -0,0 +1,39 @@ +Qualcomm Technologies, Inc. Shared Memory TTY Driver (smdtty) + +[Root level node] +Required properties: +-compatible : should be "qcom,smdtty" + +[Second level nodes] +qcom,smdtty-port-names +Required properties: +-qcom,smdtty-remote: the remote subsystem name +-qcom,smdtty-port-name : the smd channel name + +Optional properties: +-qcom,smdtty-dev-name : the smdtty device name + +Required alias: +- The index into TTY subsystem is specified via an alias with the following format + 'smd{n}' where n is the tty device index. + +Example: + aliases { + smd1 = &smdtty_apps_fm; + smd36 = &smdtty_loopback; + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_apps_fm: qcom,smdtty-apps-fm { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_FM"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; diff --git a/Documentation/devicetree/bindings/coresight/coresight.txt b/Documentation/devicetree/bindings/coresight/coresight.txt new file mode 100644 index 000000000000..242560041a26 --- /dev/null +++ b/Documentation/devicetree/bindings/coresight/coresight.txt @@ -0,0 +1,435 @@ +* CoreSight Components + +CoreSight components are compliant with the ARM CoreSight architecture +specification and can be connected in various topologies to suite a particular +SoCs tracing needs. These trace components can generally be classified as sinks, +links and sources. Trace data produced by one or more sources flows through the +intermediate links connecting the source to the currently selected sink. Each +CoreSight component device should use these properties to describe its hardware +characteristcs. + +Required properties: + +- compatible : name of the component used for driver matching, should be one of + the following: + "arm,coresight-tmc" for coresight tmc-etr or tmc-etf device, + "arm,coresight-tpiu" for coresight tpiu device, + "qcom,coresight-replicator" for coresight replicator device, + "arm,coresight-funnel" for coresight funnel devices, + "qcom,coresight-tpda" for coresight tpda device, + "qcom,coresight-tpdm" for coresight tpdm device, + "qcom,coresight-dbgui" for coresight dbgui device + "arm,coresight-stm" for coresight stm trace device, + "arm,coresight-etm" for coresight etm trace devices, + "arm,coresight-etmv4" for coresight etmv4 trace devices, + "qcom,coresight-csr" for coresight csr device, + "arm,coresight-cti" for coresight cti devices, + "qcom,coresight-hwevent" for coresight hardware event devices + "arm,coresight-fuse" for coresight fuse v1 device, + "arm,coresight-fuse-v2" for coresight fuse v2 device, + "arm,coresight-fuse-v3" for coresight fuse v3 device, + "qcom,coresight-remote-etm" for coresight remote processor etm trace device, + "qcom,coresight-qpdi" for coresight qpdi device +- reg : physical base address and length of the register set(s) of the component. + Not required for the following compatible string: + - "qcom,coresight-remote-etm" +- reg-names : names corresponding to each reg property value. + Not required for the following compatible string: + - "qcom,coresight-remote-etm" + The reg-names that need to be used with corresponding compatible string + for a coresight device are: + - for coresight tmc-etr or tmc-etf device: + compatible : should be "arm,coresight-tmc" + reg-names : should be: + "tmc-base" - physical base address of tmc configuration + registers + "bam-base" - physical base address of tmc-etr bam registers + - for coresight tpiu device: + compatible : should be "arm,coresight-tpiu" + reg-names : should be: + "tpiu-base" - physical base address of tpiu registers + - for coresight replicator device + compatible : should be "qcom,coresight-replicator" + reg-names : should be: + "replicator-base" - physical base address of replicator + registers + - for coresight funnel devices + compatible : should be "arm,coresight-funnel" + reg-names : should be: + "funnel-base" - physical base address of funnel registers + - for coresight tpda trace device + compatible : should be "qcom,coresight-tpda" + reg-names : should be: + "tpda-base" - physical base address of tpda registers + - for coresight tpdm trace device + compatible : should be "qcom,coresight-tpdm" + reg-names : should be: + "tpdm-base" - physical base address of tpdm registers + - for coresight dbgui device: + compatible : should be "qcom,coresight-dbgui" + reg-names : should be: + "dbgui-base" - physical base address of dbgui registers + - for coresight stm trace device + compatible : should be "arm,coresight-stm" + reg-names : should be: + "stm-base" - physical base address of stm configuration + registers + "stm-data-base" - physical base address of stm data registers + - for coresight etm trace devices + compatible : should be "arm,coresight-etm" + reg-names : should be: + "etm-base" - physical base address of etm registers + - for coresight etmv4 trace devices + compatible : should be "arm,coresight-etmv4" + reg-names : should be: + "etm-base" - physical base address of etmv4 registers + - for coresight csr device: + compatible : should be "qcom,coresight-csr" + reg-names : should be: + "csr-base" - physical base address of csr registers + - for coresight cti devices: + compatible : should be "arm,coresight-cti" + reg-names : should be: + "cti<num>-base" - physical base address of cti registers + - for coresight hardware event devices: + compatible : should be "qcom,coresight-hwevent" + reg-names : should be: + "<ss-mux>" - physical base address of hardware event mux + control registers where <ss-mux> is subsystem mux it + represents + - for coresight fuse device: + compatible : should be "arm,coresight-fuse" + reg-names : should be: + "fuse-base" - physical base address of fuse registers + "nidnt-fuse-base" - physical base address of nidnt fuse registers + "qpdi-fuse-base" - physical base address of qpdi fuse registers + - for coresight qpdi device: + compatible : should be "qcom,coresight-qpdi" + reg-names : should be: + "qpdi-base" - physical base address of qpdi registers +- coresight-id : unique integer identifier for the component +- coresight-name : unique descriptive name of the component +- coresight-nr-inports : number of input ports on the component + +Optional properties: + +- coresight-outports : list of output port numbers of this component +- coresight-child-list : list of phandles pointing to the children of this + component +- coresight-child-ports : list of input port numbers of the children +- coresight-default-sink : represents the default compile time CoreSight sink +- coresight-ctis : list of ctis that this component interacts with +- qcom,cti-save : boolean, indicating cti context needs to be saved and restored +- qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti + registers to be saved and restored +- qcom,cti-gpio-trigin : cti trigger input driven by gpio +- qcom,cti-gpio-trigout : cti trigger output sent to gpio +- qcom,pc-save : program counter save implemented +- qcom,blk-size : block size for tmc-etr to usb transfers +- qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer +- qcom,round-robin : indicates if per core etms are allowed round-robin access + by the funnel +- qcom,write-64bit : only 64bit data writes supported by stm +- qcom,data-barrier : barrier required for every stm data write to channel space +- <supply-name>-supply: phandle to the regulator device tree node. The required + <supply-name> is "vdd" for SD card and "vdd-io" for SD + I/O supply. Used for tpiu component +- qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should + be specified in pairs (min, max) with units + being uV. Here <supply> can be "vdd" for SD card + vdd supply or "vdd-io" for SD I/O vdd supply. +- qcom,<supply>-current-level : specifies current load levels for vdd supply. + Should be specified in pairs (lpm, hpm) with + units being uA. Here <supply> can be "vdd" for + SD card vdd supply or "vdd-io" for SD I/O vdd + supply. +- qcom,hwevent-clks : list of clocks required by hardware event driver +- qcom,hwevent-regs : list of regulators required by hardware event driver +- qcom,byte-cntr-absent : specifies if the byte counter feature is absent on + the device. Only relevant in case of tmc-etr device. +- interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is + spi/ppi, b is the interrupt number and c is the mask, +- interrupt-names : a list of strings that map in order to the list of + interrupts specified in the 'interrupts' property. +- qcom,sg-enable : indicates whether scatter gather feature is supported for TMC + ETR configuration. +- qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped. + Used for TMC component +- qcom,nidntsw : boolean, indicating NIDnT software debug or trace support + present. Used for tpiu component +- qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present. + Used for tpiu component + qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of + these may specified for tpiu component +- qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used + for tpiu component +- qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used + for tpiu component +- qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used + for tpiu component +- qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used + for tpiu component +- nidnt-gpio : specifies gpio for NIDnT hardware detection +- nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection +- pinctrl-names : names corresponding to the numbered pinctrl. The allowed + names are subset of the following: cti-trigin-pctrl, + cti-trigout-pctrl. Used for cti component +- pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer + to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt". +- qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled + for the ETM whose CPU is being powered down. The port + state is restored when CPU is powered up. Used for + funnel component. +- qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before + powering down CPU. Used for TMC component. +- qcom,bc-elem-size : specifies the BC element size supported by each monitor + connected to the aggregator on each port. Should be specified + in pairs (port, bc element size). +- qcom,tc-elem-size : specifies the TC element size supported by each monitor + connected to the aggregator on each port. Should be specified + in pairs (port, tc element size). +- qcom,dsb-elem-size : specifies the DSB element size supported by each monitor + connected to the aggregator on each port. Should be specified + in pairs (port, dsb element size). +- qcom,cmb-elem-size : specifies the CMB element size supported by each monitor + connected to the aggregator on each port. Should be specified + in pairs (port, cmb element size). +- qcom,clk-enable: specifies whether additional clock bit needs to be set for + M4M TPDM. +- qcom,tpda-atid : specifies the ATID for TPDA. +- qcom,inst-id : QMI instance id for remote ETMs. +- qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be + set in ETM stall control register. +- coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true +- coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device +- qcom,dbgui-addr-offset : indicates the offset of dbgui address registers +- qcom,dbgui-data-offset : indicates the offset of dbgui data registers +- qcom,dbgui-size : indicates the size of dbgui address and data registers +- qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver +- qcom,cpuss-debug-cgc: debug clock gating phandle for etm + reg : the clock gating register for each cluster + cluster : indicate the cluster number + +coresight-outports, coresight-child-list and coresight-child-ports lists will +be of the same length and will have a one to one correspondence among the +elements at the same list index. + +coresight-default-sink must be specified for one of the sink devices that is +intended to be made the default sink. Other sink devices must not have this +specified. Not specifying this property on any of the sinks is invalid. + +Examples: + +1. Sinks + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + interrupts = <0 166 0>; + interrupt-names = "byte-cntr-irq"; + + qcom,byte-cntr-absent; + qcom,memory-size = <0x100000>; + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-default-sink; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + qcom,nidnt; + qcom,nidnthw; + nidnt-gpio = <38>; + nidnt-gpio-polarity = <1>; + + vdd-supply = <&pm8941_l21>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + }; + +2. Links + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + tpda_lmh: tpda@fbb91000 { + compatible = "qcom,coresight-tpda"; + reg = <0xfbb91000x1000>; + reg-names = "tpda-base"; + + coresight-id = <7>; + coresight-name = "coresight-tpda-lmh"; + coresight-nr-inports = <32>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_rpm clk_qdss_clk>, + <&clock_rpm clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + +3. Sources + tpdm_lmh: tpdm@fbb90000 { + compatible = "qcom,coresight-tpdm"; + reg = <0xfbb90000x1000>; + reg-names = "tpdm-base"; + + coresight-id = <8>; + coresight-name = "coresight-tpdm-lmh"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&tpda_lmh>; + coresight-child-ports = <0>; + + clocks = <&clock_rpm clk_qdss_clk>, + <&clock_rpm clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + dbgui: dbgui@86d000 { + compatible = "qcom,coresight-dbgui"; + reg = <0x86d000 0x1000>; + reg-names = "dbgui-base"; + + coresight-id = <11>; + coresight-name = "coresight-dbgui"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in3>; + coresight-child-ports = <2>; + + qcom,dbgui-addr-offset = <0x30>; + qcom,dbgui-data-offset = <0xB0>; + qcom,dbgui-size = <32>; + + clocks = <&clock_rpm clk_qdss_clk>, + <&clock_rpm clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <9>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc33c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <0>; + coresight-etm-cpu = <&CPU0>; + qcom,cpuss-debug-cgc = <&CGC_0>; + + qcom,pc-save; + qcom,round-robin; + + #address-cells = <1>; + #size-cells = <1>; + CGC_0: cluster-cgc { + reg = <0xb011088 0x4>; + cluster = <1>; + }; + }; + +4. Miscellaneous + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + + qcom,cti-gpio-trigout = <1>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fdf30018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfdf30018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>, + <0xfc401600 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux"; + + coresight-id = <29>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + qcom,hwevent-regs = "gdsc_ufs"; + }; + + fuse: fuse@fc4be024 { + compatible = "arm,coresight-fuse"; + reg = <0xfc4be024 0x8> + <0x58040 0x4>; + reg-names = "fuse-base", "nidnt-fuse-base"; + + coresight-id = <30>; + coresight-name = "coresight-fuse"; + coresight-nr-inports = <0>; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-smp2p.txt b/Documentation/devicetree/bindings/gpio/gpio-smp2p.txt new file mode 100644 index 000000000000..f32f20f9847a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-smp2p.txt @@ -0,0 +1,93 @@ +Qualcomm Technologies, Inc. SMSM Point-to-Point (SMP2P) GPIO Driver + +Used to map an SMP2P entry and remote processor ID to a virtual GPIO controller +and virtual interrupt controller. + +Required properties: +-compatible : should be "qcom,smp2pgpio"; +-qcom,entry-name : name of the SMP2P entry +-qcom,remote-pid : the SMP2P remote processor ID (see smp2p_private_api.h) +-gpio-controller : specifies that this is a GPIO controller +-#gpio-cells : number of GPIO cells (should always be <2>) +-interrupt-controller : specifies that this is an interrupt controller +-#interrupt-cells : number of interrupt cells (should always be <2>) + +Optional properties: +-qcom,is-inbound : specifies that this is an inbound entry (default is outbound) + +Comments: +All device tree entries must be unique. Therefore to prevent naming collisions +between clients, it is recommended that the DT nodes should be named using the +format: + smp2pgpio_<ENTRY_NAME>_<REMOTE PID>_<in|out> + +Unit test devices ("smp2p" entries): +-compatible : should be one of + "qcom,smp2pgpio_test_smp2p_1_out" + "qcom,smp2pgpio_test_smp2p_1_in" + "qcom,smp2pgpio_test_smp2p_2_out" + "qcom,smp2pgpio_test_smp2p_2_in" + "qcom,smp2pgpio_test_smp2p_3_out" + "qcom,smp2pgpio_test_smp2p_3_in" + "qcom,smp2pgpio_test_smp2p_4_out" + "qcom,smp2pgpio_test_smp2p_4_in" + "qcom,smp2pgpio_test_smp2p_7_out" + "qcom,smp2pgpio_test_smp2p_7_in" + "qcom,smp2pgpio_test_smp2p_15_out" + "qcom,smp2pgpio_test_smp2p_15_in" +-gpios : the relevant gpio pins of the entry + +Example: + /* Maps inbound "smp2p" entry on remote PID 7 to GPIO controller. */ + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* + * Maps inbound "smp2p" entry on remote PID 7 to client driver + * "qcom,smp2pgpio_test_smp2p_7_in". + * + * Note: If all 32-pins are used by this client, then you + * can just list pin 0 here as a shortcut. + */ + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>, /* pin 0 */ + <&smp2pgpio_smp2p_7_in 1 0>, + . . . + <&smp2pgpio_smp2p_7_in 31 0>; /* pin 31 */ + }; + + + /* Maps outbound "smp2p" entry on remote PID 7 to GPIO controller. */ + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* + * Maps outbound "smp2p" entry on remote PID 7 to client driver + * "qcom,smp2pgpio_test_smp2p_7_out". + * + * Note: If all 32-pins are used by this client, then you + * can just list pin 0 here as a shortcut. + */ + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>, /* pin 0 */ + <&smp2pgpio_smp2p_7_out 1 0>, + . . . + <&smp2pgpio_smp2p_7_out 31 0>; /* pin 31 */ + }; diff --git a/Documentation/devicetree/bindings/gpio/qpnp-pin.txt b/Documentation/devicetree/bindings/gpio/qpnp-pin.txt new file mode 100644 index 000000000000..21976425bbc9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/qpnp-pin.txt @@ -0,0 +1,224 @@ +* msm-qpnp-pin + +msm-qpnp-pin is a GPIO chip driver for the MSM SPMI implementation. +It creates a spmi_device for every spmi-dev-container block of device_nodes. +These device_nodes contained within specify the PMIC pin number associated +with each gpio chip. The driver will map these to Linux GPIO numbers. + +[PMIC GPIO Device Declarations] + +-Root Node- + +Required properties : + - spmi-dev-container : Used to specify the following child nodes as part of the + same SPMI device. + - gpio-controller : Specify as gpio-controller. All child nodes will belong to + this gpio_chip. + - #gpio-cells: We encode a PMIC pin number and a 32-bit flag field to + specify the gpio configuration. This must be set to '2'. + - #address-cells: Specify one address field. This must be set to '1'. + - #size-cells: Specify one size-cell. This must be set to '1'. + - compatible = "qcom,qpnp-pin" : Specify driver matching for this driver. + - label: String giving the name for the gpio_chip device. This name + should be unique on the system and portray the specifics of the device. + +-Child Nodes- + +Required properties : + - reg : Specify the spmi offset and size for this pin device. + - qcom,pin-num : Specify the PMIC pin number for this device. + +Optional configuration properties : + - qcom,mode: indicates whether the pin should be input, output, or + both for gpios. mpp pins also support bidirectional, + analog in, analog out and current sink. + QPNP_PIN_MODE_DIG_IN = 0, (GPIO/MPP) + QPNP_PIN_MODE_DIG_OUT = 1, (GPIO/MPP) + QPNP_PIN_MODE_DIG_IN_OUT = 2, (GPIO/MPP) + QPNP_PIN_MODE_ANA_PASS_THRU = 3, (GPIO_LV/GPIO_MV) + QPNP_PIN_MODE_BIDIR = 3, (MPP) + QPNP_PIN_MODE_AIN = 4, (MPP) + QPNP_PIN_MODE_AOUT = 5, (MPP) + QPNP_PIN_MODE_SINK = 6 (MPP) + + - qcom,output-type: indicates gpio should be configured as CMOS or open + drain. + QPNP_PIN_OUT_BUF_CMOS = 0, (GPIO) + QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS = 1, (GPIO) + QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS = 2 (GPIO) + QPNP_PIN_OUT_BUF_NO_DRIVE = 3, (GPIO_LV/GPIO_MV) + + - qcom,invert: Invert the signal of the gpio line - + QPNP_PIN_INVERT_DISABLE = 0 (GPIO/MPP) + QPNP_PIN_INVERT_ENABLE = 1 (GPIO/MPP) + + - qcom,pull: This parameter should be programmed to different values + depending on whether it's GPIO or MPP. + For GPIO, it indicates whether a pull up or pull down + should be applied. If a pullup is required the + current strength needs to be specified. + Current values of 30uA, 1.5uA, 31.5uA, 1.5uA with 30uA + boost are supported. This value should be one of + the QPNP_PIN_GPIO_PULL_*. Note that the hardware ignores + this configuration if the GPIO is not set to input or + output open-drain mode. + QPNP_PIN_PULL_UP_30 = 0, (GPIO) + QPNP_PIN_PULL_UP_1P5 = 1, (GPIO) + QPNP_PIN_PULL_UP_31P5 = 2, (GPIO) + QPNP_PIN_PULL_UP_1P5_30 = 3, (GPIO) + QPNP_PIN_PULL_DN = 4, (GPIO) + QPNP_PIN_PULL_NO = 5 (GPIO) + + For MPP, it indicates whether a pullup should be + applied for bidirectitional mode only. The hardware + ignores the configuration when operating in other modes. + This value should be one of the QPNP_PIN_MPP_PULL_*. + + QPNP_PIN_MPP_PULL_UP_0P6KOHM = 0, (MPP) + QPNP_PIN_MPP_PULL_UP_OPEN = 1 (MPP) + QPNP_PIN_MPP_PULL_UP_10KOHM = 2, (MPP) + QPNP_PIN_MPP_PULL_UP_30KOHM = 3, (MPP) + + - qcom,vin-sel: specifies the voltage level when the output is set to 1. + For an input gpio specifies the voltage level at which + the input is interpreted as a logical 1. + QPNP_PIN_VIN0 = 0, (GPIO/MPP/GPIO_LV/GPIO_MV) + QPNP_PIN_VIN1 = 1, (GPIO/MPP/GPIO_MV) + QPNP_PIN_VIN2 = 2, (GPIO/MPP) + QPNP_PIN_VIN3 = 3, (GPIO/MPP) + QPNP_PIN_VIN4 = 4, (GPIO/MPP) + QPNP_PIN_VIN5 = 5, (GPIO/MPP) + QPNP_PIN_VIN6 = 6, (GPIO/MPP) + QPNP_PIN_VIN7 = 7 (GPIO/MPP) + + - qcom,out-strength: the amount of current supplied for an output gpio. + QPNP_PIN_OUT_STRENGTH_LOW = 1 (GPIO) + QPNP_PIN_OUT_STRENGTH_MED = 2, (GPIO) + QPNP_PIN_OUT_STRENGTH_HIGH = 3, (GPIO) + + - qcom,dtest-sel Route the pin internally to a DTEST line. + QPNP_PIN_DIG_IN_CTL_DTEST1 = 1 (GPIO/MPP) + QPNP_PIN_DIG_IN_CTL_DTEST2 = 2, (GPIO/MPP) + QPNP_PIN_DIG_IN_CTL_DTEST3 = 3, (GPIO/MPP) + QPNP_PIN_DIG_IN_CTL_DTEST4 = 4, (GPIO/MPP) + + - qcom,src-sel: select a function for the pin. Certain pins + can be paired (shorted) with each other. Some gpio pins + can act as alternate functions. + In the context of gpio, this acts as a source select. + For mpps, this is an enable select. + QPNP_PIN_SEL_FUNC_CONSTANT = 0, (GPIO/MPP) + QPNP_PIN_SEL_FUNC_PAIRED = 1, (GPIO/MPP) + QPNP_PIN_SEL_FUNC_1 = 2, (GPIO/MPP) + QPNP_PIN_SEL_FUNC_2 = 3, (GPIO/MPP) + QPNP_PIN_SEL_DTEST1 = 4, (GPIO/MPP) + QPNP_PIN_SEL_DTEST2 = 5, (GPIO/MPP) + QPNP_PIN_SEL_DTEST3 = 6, (GPIO/MPP) + QPNP_PIN_SEL_DTEST4 = 7 (GPIO/MPP) + + Below are the source-select values for GPIO_LV/MV. + QPNP_PIN_LV_MV_SEL_FUNC_CONSTANT = 0, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_FUNC_PAIRED = 1, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_FUNC_1 = 2, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_FUNC_2 = 3, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_FUNC_3 = 4, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_FUNC_4 = 5, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_DTEST1 = 6 (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_DTEST2 = 7, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_DTEST3 = 8, (GPIO_LV/GPIO_MV) + QPNP_PIN_LV_MV_SEL_DTEST4 = 9, (GPIO_LV/GPIO_MV) + + - qcom,master-en: 1 = Enable features within the + pin block based on configurations. (GPIO/MPP) + 0 = Completely disable the block and + let the pin float with high impedance + regardless of other settings. (GPIO/MPP) + - qcom,aout-ref: set the analog output reference. + + QPNP_PIN_AOUT_1V25 = 0, (MPP) + QPNP_PIN_AOUT_0V625 = 1, (MPP) + QPNP_PIN_AOUT_0V3125 = 2, (MPP) + QPNP_PIN_AOUT_MPP = 3, (MPP) + QPNP_PIN_AOUT_ABUS1 = 4, (MPP) + QPNP_PIN_AOUT_ABUS2 = 5, (MPP) + QPNP_PIN_AOUT_ABUS3 = 6, (MPP) + QPNP_PIN_AOUT_ABUS4 = 7 (MPP) + + - qcom,ain-route: Set the destination for analog input. + QPNP_PIN_AIN_AMUX_CH5 = 0, (MPP) + QPNP_PIN_AIN_AMUX_CH6 = 1, (MPP) + QPNP_PIN_AIN_AMUX_CH7 = 2, (MPP) + QPNP_PIN_AIN_AMUX_CH8 = 3, (MPP) + QPNP_PIN_AIN_AMUX_ABUS1 = 4, (MPP) + QPNP_PIN_AIN_AMUX_ABUS2 = 5, (MPP) + QPNP_PIN_AIN_AMUX_ABUS3 = 6, (MPP) + QPNP_PIN_AIN_AMUX_ABUS4 = 7 (MPP) + + - qcom,cs-out: Set the the amount of output to sync in mA. + QPNP_PIN_CS_OUT_5MA = 0, (MPP) + QPNP_PIN_CS_OUT_10MA = 1, (MPP) + QPNP_PIN_CS_OUT_15MA = 2, (MPP) + QPNP_PIN_CS_OUT_20MA = 3, (MPP) + QPNP_PIN_CS_OUT_25MA = 4, (MPP) + QPNP_PIN_CS_OUT_30MA = 5, (MPP) + QPNP_PIN_CS_OUT_35MA = 6, (MPP) + QPNP_PIN_CS_OUT_40MA = 7 (MPP) + + - qcom,apass-sel: Set the ATEST channel to route the signal + QPNP_PIN_APASS_SEL_ATEST1 = 0, (GPIO_LV/GPIO_MV) + QPNP_PIN_APASS_SEL_ATEST2 = 1, (GPIO_LV/GPIO_MV) + QPNP_PIN_APASS_SEL_ATEST3 = 2, (GPIO_LV/GPIO_MV) + QPNP_PIN_APASS_SEL_ATEST4 = 3, (GPIO_LV/GPIO_MV) + +*Note: If any of the configuration properties are not specified, then the + qpnp-pin driver will not modify that respective configuration in + hardware. + +[PMIC GPIO clients] + +Required properties : + - gpios : Contains 3 fields of the form <&gpio_controller pmic_pin_num flags> + +[Example] + +qpnp: qcom,spmi@fc4c0000 { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8941@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pm8941_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <62>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <20>; + qcom,source_sel = <2>; + qcom,pull = <5>; + }; + }; + + qcom,testgpio@1000 { + compatible = "qcom,qpnp-testgpio"; + reg = <0x1000 0x1000>; + gpios = <&pm8941_gpios 62 0x0 &pm8941_gpios 20 0x1>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt b/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt new file mode 100644 index 000000000000..62ba54bac512 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt @@ -0,0 +1,197 @@ +Qualcomm Technologies, Inc. QPNP PMIC Voltage ADC Arbiter + +QPNP PMIC Voltage ADC (VADC) provides interface to clients to read +Voltage. A 15 bit ADC is used for Voltage measurements. There are multiple +peripherals to the VADC and the scope of the driver is to provide interface +for the USR peripheral of the VADC. + +VADC node + +Required properties: +- compatible : should be "qcom,qpnp-vadc" for Voltage ADC device driver and + "qcom,qpnp-vadc-hc" for VADC_HC voltage ADC device driver. +- reg : offset and length of the PMIC Aribter register map. +- address-cells : Must be one. +- size-cells : Must be zero. +- interrupts : The USR bank peripheral VADC interrupt. +- interrupt-names : Should contain "eoc-int-en-set" for EOC, + "high-thr-en-set" for high threshold interrupts and + "low-thr-en-set" for low threshold interrupts. High and low threshold + interrupts are to be enabled if VADC_USR needs to support recurring measurement. +- qcom,adc-bit-resolution : Bit resolution of the ADC. +- qcom,adc-vdd-reference : Voltage reference used by the ADC. + +Channel nodes +NOTE: Atleast one Channel node is required. + +Optional properties: +- qcom,vadc-poll-eoc: Use polling instead of interrupts for End of Conversion completion. +- qcom,pmic-revid : Phandle pointing to the revision peripheral node. Use it to query the + PMIC type and revision for applying the appropriate temperature + compensation parameters. +-qcom,vadc-meas-int-mode : Enable VADC_USR to handle requests to perform recurring measurements + for any one supported channel along with supporting single conversion + requests. +- qcom,vadc-recalib-check: Add this property to check if recalibration required due to inaccuracy. +- qcom,vadc-thermal-node : If present a thermal node is created and the channel is registered as + part of the thermal sysfs which allows clients to use the thermal framework + to set temperature thresholds and receive notification when the temperature + crosses a set threshold, read temperature and enable/set trip types supported + by the thermal framework. +- hkadc_ldo-supply : Add this property if VADC needs to perform a Software Vote for the HKADC. +- hkadc_ok-supply : Add this property if the VADC needs to perform a Software vote for the HKADC VREG_OK. +- qcom,cal-val : Add this property for VADC_HC voltage ADC device to select from the following + unsigned int. If the property is not present the default calibration value of + using the timer value is chosen. + 0 : The calibration values used for measurement are from a timer. + 1 : Forces a fresh measurement for calibration values at the same time + measurement is taken. + +Client required property: +- qcom,<consumer name>-vadc : The phandle to the corresponding vadc device. + The consumer name passed to the driver when calling + qpnp_get_vadc() is used to associate the client + with the corresponding device. + +Required properties: +- label : Channel name used for sysfs entry. +- reg : AMUX channel number. +- qcom,decimation : Sampling rate to use for the individual channel measurement. + Select from following unsigned int for Voltage ADC device. + 0 : 512 + 1 : 1K + 2 : 2K + 3 : 4K + Select from following unsigned int for VADC_HC voltage ADC device. + 0 : 256 + 1 : 512 + 2 : 1024 +- qcom,pre-div-channel-scaling : Pre-div used for the channel before the signal + is being measured. Some of the AMUX channels + support dividing the signal from a predetermined + ratio. The configuration for this node is to know + the pre-determined ratio and use it for post scaling. + Select from the following unsigned int. + 0 : {1, 1} + 1 : {1, 3} + 2 : {1, 4} + 3 : {1, 6} + 4 : {1, 20} + 5 : {1, 8} + 6 : {10, 81} + 7 : {1, 10} +- qcom,calibration-type : Reference voltage to use for channel calibration. + Channel calibration is dependendent on the channel. + Certain channels like XO_THERM, BATT_THERM use ratiometric + calibration. Most other channels fall under absolute calibration. + Select from the following strings. + "absolute" : Uses the 625mv and 1.25V reference channels. + "ratiometric" : Uses the reference Voltage/GND for calibration. +- qcom,scale-function : Scaling function used to convert raw ADC code to units specific to + a given channel. + Select from the following unsigned int. + 0 : Default scaling to convert raw adc code to voltage. + 1 : Conversion to temperature based on btm parameters. + 2 : Returns result in degC for 100k pull-up. + 3 : Returns current across 0.1 ohm resistor. + 4 : Returns XO thermistor voltage in degree's Centigrade. + 5 : Returns result in degC for 150k pull-up. + 9 : Conversion to temperature based on -15~55 allowable + battery charging tempeature setting for btm parameters. +- qcom,hw-settle-time : Settling period for the channel before ADC read. + Select from the following unsigned int. + 0 : 0us + 1 : 100us + 2 : 200us + 3 : 300us + 4 : 400us + 5 : 500us + 6 : 600us + 7 : 700us + 8 : 800us + 9 : 900us + 0xa : 1ms + 0xb : 2ms + 0xc : 4ms + 0xd : 6ms + 0xe : 8ms + 0xf : 10ms +- qcom,fast-avg-setup : Average number of samples to be used for measurement. Fast averaging + provides the option to obtain a single measurement from the ADC that + is an average of multiple samples. The value selected is 2^(value) + Select from the following unsigned int for Voltage ADC device. + 0 : 1 + 1 : 2 + 2 : 4 + 3 : 8 + 4 : 16 + 5 : 32 + 6 : 64 + 7 : 128 + 8 : 256 + Select from the following unsigned int for VADC_HC ADC device. + 0 : 1 + 1 : 2 + 2 : 4 + 3 : 8 + 4 : 16 + +Example: + /* Main Node */ + qcom,vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + /* Channel Node */ + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + +Client device example: +/* Add to the clients node that needs the VADC channel A/D */ +client_node { + qcom,client-vadc = <&pm8941_vadc>; +}; + +/* Clients have an option of measuring an analog signal through an MPP. + MPP block is not part of the VADC block but is an individual PMIC + block that has an option to support clients to configure an MPP as + an analog input which can be routed through one of the VADC pre-mux + inputs. Here is an example of how to configure an MPP as an analog + input */ + +/* Configure MPP4 as an Analog input to AMUX8 and read from channel 0x23 */ +/* MPP DT configuration in the platform DT file*/ + mpp@a300 { /* MPP 4 */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; + +/* VADC Channel configuration */ + chan@23 { + label = "mpp4_div3"; + reg = <0x23>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; diff --git a/Documentation/devicetree/bindings/net/can/k61-can.txt b/Documentation/devicetree/bindings/net/can/k61-can.txt new file mode 100644 index 000000000000..57e85817a0a5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/k61-can.txt @@ -0,0 +1,27 @@ +* Kinetis K61 CAN * + +This driver implements SPI slave protocol for Freescale K61 CAN controller. + +Required properties: + - compatible: Should be "fsl,k61". + - reg: Should contain SPI chip select. + - interrupt-parent: Should specify interrupt controller for the interrupt. + - interrupts: Should contain IRQ line for the CAN controller. + - reset-gpio: Reference to the GPIO connected to the reset input. + - pinctrl-names : Names corresponding to the numbered pinctrl states. + - pinctrl-0 : This explains the active state of the GPIO line. + - pinctrl-1 : This explains the suspend state of the GPIO line. + + +Example: + + can-controller@0 { + compatible = "fsl,k61"; + reg = <0>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <25 0>; + reset-gpio = <&tlmm_pinmux 11 0x1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&can_rst_on>; + pinctrl-1 = <&can_rst_off>; + }; diff --git a/Documentation/devicetree/bindings/net/msm-emac.txt b/Documentation/devicetree/bindings/net/msm-emac.txt new file mode 100644 index 000000000000..f4c09e8f6cd8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/msm-emac.txt @@ -0,0 +1,197 @@ +Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Controller + +This network controller consists of two devices: a MAC and an +internal PHY (SGMII/RGMII). Each device is represented by a device tree node. +A phandle connects the MAC node to its corresponding internal phy node. +Another phandle points to the external PHY node. + +Required properties: + +MAC node: +- compatible : Should be "qcom,mdm9607-emac" for mdm9607 based EMAC driver + Should be "qcom,emac" for other targets based EMAC driver +- reg : Offset and length of the register regions for the device +- reg-names : Register region names referenced in 'reg' above. + Required register resource entries are: + "emac" : EMAC controller register block. + "emac_csr" : EMAC wrapper register block. + Optional register resource entries are: + "emac_1588" : EMAC 1588 (PTP) register block. + Required if 'qcom,emac-tstamp-en' is present. +- interrupts : Interrupt number used by this controller +- interrupt-names : Interrupt resource names referenced in 'interrupts' above. + Required interrupt resource entries are: + "emac_core0_irq" : EMAC core0 interrupt. + "emac_core1_irq" : EMAC core1 interrupt. + "emac_core2_irq" : EMAC core2 interrupt. + "emac_core3_irq" : EMAC core3 interrupt. + Optional interrupt resource entries are: + "emac_wol_irq" : EMAC Wake-On-LAN (WOL) interrupt. + Required if WOL is supported. +- phy-mode: String, operation mode of the PHY interface. See ethernet.txt in the + same directory. +- internal-phy : phandle to the internal PHY node +- phy-handle : phandle the the external PHY node + +Internal PHY node: +- compatible : Should be "qcom,mdm9607-emac-sgmii" for mdm9607. + Should be "qcom,qdf2432-emac-sgmii" for QDF2432 + Should be "qcom,fsm9900-emac-sgmii" for FSM9900 +- reg : Offset and length of the register region(s) for the device +- reg-names : Register region names referenced in 'reg' above. + "emac_sgmii" : EMAC SGMII PHY register block. + Required if 'phy-mode' is "sgmii". +- interrupts : Interrupt number used by this controller +- interrupt-names : Interrupt resource names referenced in 'interrupts' above. + "emac_sgmii_irq" : EMAC SGMII interrupt. + Required if 'phy-mode' is "sgmii". + +The external phy child node: +- reg : The phy address + +Optional properties: + +MAC node: +- qcom,emac-tstamp-en : Enables the PTP (1588) timestamping feature. + Include this only if PTP (1588) timestamping + feature is needed. If included, "emac_1588" register + base should be specified. +- mac-address : The 6-byte MAC address. If present, it is the default + MAC address. +- qcom,no-external-phy : Indicates there is no external PHY connected to EMAC. + Include this only if the EMAC is directly connected to + the peer end without EPHY. +- qcom,emac-ptp-grandmaster : Enable the PTP (1588) grandmaster mode. + Include this only if PTP (1588) is configured as + grandmaster. +- qcom,emac-ptp-frac-ns-adj : The vector table to adjust the fractional ns per + RTC clock cycle. + Include this only if there is accuracy loss of + fractional ns per RTC clock cycle. For individual + table entry, the first field indicates the RTC + reference clock rate. The second field indicates + the number of adjustment in 2 ^ -26 ns. +- tstamp-eble : Enables the PTP (1588) timestamping feature in ACPI mode. +- <supply-name>-supply: phandle to the regulator device tree node + Required "supply-name" are "emac_vreg*" +- qcom,vdd-voltage-level: This property must be a list of five integer + values (max voltage value for supply 1/2/3/4/5) where each value + represents a voltage in microvolts. + + +Example: + +FSM9900: + +soc { + #address-cells = <1>; + #size-cells = <1>; + + emac0: ethernet@feb20000 { + compatible = "qcom,fsm9900-emac"; + reg-names = "emac", "emac_csr", "emac_1588"; + reg = <0xfeb20000 0x10000>, + <0xfeb36000 0x1000>, + <0xfeb3c000 0x4000>, + interrupts = <0 76 0>, <0 77 0>, <0 78 0>, <0 79 0>; + interrupt-names = "emac_core0_irq", "emac_core1_irq", + "emac_core2_irq", "emac_core3_irq"; + + clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, + <&gcc 6>, <&gcc 7>; + clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", + "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; + + internal-phy = <&emac_sgmii>; + + phy-handle = <&phy0>; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_a>; + }; + + emac_sgmii: ethernet@feb38000 { + compatible = "qcom,fsm9900-emac-sgmii"; + reg-names = "emac_sgmii"; + reg = <0xfeb38000 0x1000>; + interrupts = <80>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,fsm9900-pinctrl"; + + mdio_pins_a: mdio { + state { + pins = "gpio123", "gpio124"; + function = "mdio"; + }; + }; + }; + + +MDM9607: + + emac0: qcom,emac@7c40000 { + compatible = "qcom,mdm9607-emac"; + reg-names = "emac", "emac_csr", "emac_1588"; + reg = <0x7c40000 0x10000>, + <0x7c56000 0x1000>, + <0x7c5c000 0x4000>; + + #address-cells = <0>; + interrupt-parent = <&emac0>; + #interrupt-cells = <1>; + interrupts = <0 1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 76 0 + 1 &tlmm_pinmux 30 0x8>; + interrupt-names = "emac_core0_irq", "emac_wol_irq"; + + emac_vreg1-supply = <&mdm9607_l1>; + emac_vreg2-supply = <&mdm9607_l3>; + emac_vreg3-supply = <&mdm9607_l5>; + emac_vreg4-supply = <&mdm9607_l11>; + emac_vreg5-supply = <&emac_lan_vreg>; + qcom,vdd-voltage-level = <1250000 1800000 2850000 1800000 0>; + clocks = <&clock_gcc clk_gcc_emac_0_axi_clk>, + <&clock_gcc clk_gcc_emac_0_ahb_clk>, + <&clock_gcc clk_gcc_emac_0_125m_clk>, + <&clock_gcc clk_gcc_emac_0_sys_25m_clk>, + <&clock_gcc clk_gcc_emac_0_tx_clk>, + <&clock_gcc clk_gcc_emac_0_rx_clk>, + <&clock_gcc clk_gcc_emac_0_sys_clk>; + clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", + "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; + + internal-phy = <&emac_sgmii>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + + pinctrl-names = "emac_mdio_active", "emac_mdio_sleep", + "emac_ephy_active", "emac_ephy_sleep"; + pinctrl-0 = <&emac0_mdio_active>; + pinctrl-1 = <&emac0_mdio_sleep>; + pinctrl-2 = <&emac0_ephy_active>; + pinctrl-3 = <&emac0_ephy_sleep>; + qcom,emac-tstamp-en; + qcom,emac-ptp-frac-ns-adj = <125000000 1>; + status = "disable"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + emac_sgmii: ethernet@7c58000 { + compatible = "qcom,mdm9607-emac-sgmii"; + reg-names = "emac_sgmii"; + reg = <0x7c58000 0x400>; + interrupt-names = "emac_sgmii_irq"; + interrupts = <0 80 0>; + }; diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt new file mode 100644 index 000000000000..30db91aef956 --- /dev/null +++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt @@ -0,0 +1,140 @@ +Qualcomm Technologies, Inc. MSS QDSP6v5 Peripheral Image Loader + +pil-qdsp6v5-mss is a peripheral image loader (PIL) driver. It is used for +loading QDSP6v5 (Hexagon) firmware images for modem subsystems into memory and +preparing the subsystem's processor to execute code. It's also responsible for +shutting down the processor when it's not needed. + +Required properties: +- compatible: Must be "qcom,pil-q6v5-mss" or "qcom,pil-q6v55-mss" or + "pil-q6v56-mss". +- reg: Pairs of physical base addresses and region sizes of + memory mapped registers. +- reg-names: Names of the bases for the above registers. "qdsp6_base", + "rmb_base", "restart_reg" or "restart_reg_sec"(optional + for secure mode) are expected. + If "halt_base" is in same 4K pages this register then + this will be defined else "halt_q6", "halt_modem", + "halt_nc" is required. +- interrupts: The modem watchdog interrupt +- vdd_cx-supply: Reference to the regulator that supplies the vdd_cx domain. +- vdd_cx-voltage: Voltage corner/level(max) for cx rail. +- vdd_mx-supply: Reference to the regulator that supplies the memory rail. +- vdd_mx-uV: Voltage setting for the mx rail. +- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp" + +Optional properties: +- vdd_mss-supply: Reference to the regulator that supplies the processor. + This may be a shared regulator that is already voted + on in the PIL proxy voting code (and also managed by the + modem on its own), hence we mark it as as optional. +- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail. +- qcom,vdd_pll: Voltage to be set for the PLL's rail. +- reg-names: "cxrail_bhs_reg" - control register for modem power + domain. +- clocks: Array of <clock_controller_phandle clock_reference> listing + all the clocks that are accesed by this subsystem. +- qcom,proxy-clock-names: Names of the clocks that need to be turned on/off during + proxy voting/unvoting. +- qcom,active-clock-names: Names of the clocks that need to be turned on for the + subsystem to run. Turned off when the subsystem is shutdown. +- clock-names: Names of all the clocks that are accessed by the subsystem. +- qcom,is-not-loadable: Boolean- Present if the image does not need to + be loaded. +- qcom,pil-self-auth: Boolean- True if authentication is required. +- qcom,mem-protect-id: Virtual ID used by PIL to call into TZ/HYP to protect/unprotect + subsystem related memory. +- qcom,gpio-err-fatal: GPIO used by the modem to indicate error fatal to the apps. +- qcom,gpio-err-ready: GPIO used by the modem to indicate error ready to the apps. +- qcom,gpio-proxy-unvote: GPIO used by the modem to trigger proxy unvoting in + the apps. +- qcom,gpio-force-stop: GPIO used by the apps to force the modem to shutdown. +- qcom,gpio-stop-ack: GPIO used by the modem to ack force stop or a graceful stop + to the apps. +- qcom,gpio-ramdump-disable: GPIO used by the modem to inform the apps that ramdump + collection should be disabled. +- qcom,gpio-shutdown-ack: GPIO used by the modem to indicate that it has done the + necessary cleanup and that the apps can move forward with + the shutdown sequence. +- qcom,restart-group: List of subsystems that will need to restart together. +- qcom,mba-image-is-not-elf: Boolean- Present if MBA image doesn't use the ELF + format. +- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL + service. +- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem. +- qcom,override-acc: Boolean- Present if we need to override the default ACC settings +- qcom,ahb-clk-vote: Boolean- Present if we need to remove the vote for the mss_cfg_ahb + clock after the modem boots up +- qcom,pnoc-clk-vote: Boolean- Present if the modem needs the PNOC bus to be + clocked before it boots up +- qcom,qdsp6v56-1-3: Boolean- Present if the qdsp version is v56 1.3 +- qcom,qdsp6v56-1-5: Boolean- Present if the qdsp version is v56 1.5 +- qcom,edge: GLINK logical name of the remote subsystem +- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown + on behalf of the subsystem driver. +- qcom,pil-mss-memsetup: Boolean - True if TZ need to be informed of modem start address and size. +- qcom,pas-id: pas_id of the subsystem. +- qcom,qdsp6v56-1-8: Boolean- Present if the qdsp version is v56 1.8 +- qcom,qdsp6v56-1-8-inrush-current: Boolean- Present if the qdsp version is V56 1.8 and has in-rush + current issue. +- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1 +- qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2 +- qcom,qdsp6v62-1-4: Boolean- Present if the qdsp version is v62 1.4 +- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5 +- qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory + wordline clamp, and compiler memory clamp during MSS restart. +- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10 +- qcom,override-acc-1: Override the default ACC settings with this value if present. + +One child node to represent the MBA image may be specified, when the MBA image +needs to be loaded in a specifically carved out memory region. + +Required properties: +- compatible: Must be "qcom,pil-mba-mem" +- memory-region: A phandle that points to a reserved memory where the MBA image will be loaded. + +Example: + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg"; + interrupts = <0 24 1>; + vdd_mss-supply = <&pm8841_s3>; + vdd_cx-supply = <&pm8841_s2>; + vdd_cx-voltage = <7>; + vdd_mx-supply = <&pm8841_s1>; + vdd_mx-uV = <105000>; + + clocks = <&clock_rpm clk_xo_pil_mss_clk>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>; + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; + + qcom,is-not-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + qcom,mba-image-is-not-elf; + qcom,override-acc; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + qcom,ssctl-instance-id = <12>; + qcom,sysmon-id = <0>; + + qcom,mba-mem@0 { + compatible = "qcom,pil-mba-mem"; + memory-region = <&peripheral_mem>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.txt new file mode 100644 index 000000000000..7d48334b194a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.txt @@ -0,0 +1,191 @@ +Qualcomm Technologies, Inc. MDM9607 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MDM9607 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,mdm9607-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +- qcom,tlmm-emmc-boot-select: + Usage: optional + Value type: <u32> + Definition: selects the bit-field position to set. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio79, + sdc1_clk, + sdc1_cmd, + sdc1_data, + sdc2_clk, + sdc2_cmd, + sdc2_data, + qdsd_clk, + qdsd_cmd, + qdsd_data0, + qdsd_data1, + qdsd_data2, + qdsd_data3 + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_spi3, blsp_uart3, qdss_tracedata_a, bimc_dte1, blsp_i2c3, + qdss_traceclk_a, bimc_dte0, qdss_cti_trig_in_a1, blsp_spi2, + blsp_uart2, blsp_uim2, blsp_i2c2, qdss_tracectl_a, sensor_int2, + blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, sensor_int3, sensor_en, + blsp_i2c5, ebi2_a, qdss_tracedata_b, sensor_rst, blsp2_spi, + blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c1, gcc_gp1_clk_b, blsp_spi4, blsp_uart4, + rcm_marker1, blsp_i2c4, qdss_cti_trig_out_a1, rcm_marker2, + qdss_cti_trig_out_a0, blsp_spi6, blsp_uart6, pri_mi2s_ws_a, + ebi2_lcd_te_b, blsp1_spi, backlight_en_b, pri_mi2s_data0_a, + pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, pri_mi2s_sck_a, + ebi2_lcd_cs_n_b, touch_rst, pri_mi2s_mclk_a, pwr_nav_enabled_a, + ts_int, sd_write, pwr_crypto_enabled_a, codec_rst, adsp_ext, + atest_combodac_to_gpio_native, uim2_data, gmac_mdio, gcc_gp1_clk_a, + uim2_clk, gcc_gp2_clk_a, eth_irq, uim2_reset, gcc_gp3_clk_a, + eth_rst, uim2_present, prng_rosc, uim1_data, uim1_clk, + uim1_reset, uim1_present, gcc_plltest, uim_batt, coex_uart, + codec_int, qdss_cti_trig_in_a0, atest_bbrx1, cri_trng0, atest_bbrx0, + cri_trng, qdss_cti_trig_in_b0, atest_gpsadc_dtest0_native, + qdss_cti_trig_out_b0, qdss_tracectl_b, qdss_traceclk_b, pa_indicator, + modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a, + gsm0_tx, qdss_cti_trig_in_b1, cri_trng1, qdss_cti_trig_out_b1, + ssbi1, atest_gpsadc_dtest1_native, ssbi2, atest_char3, atest_char2, + atest_char1, atest_char0, atest_char, ebi0_wrcdc, ldo_update, + gcc_tlmm, ldo_en, dbg_out, atest_tsens, lcd_rst, wlan_en1, + nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, pbs0, sec_mi2s, + pwr_modem_enabled_a, pbs1, pwr_modem_enabled_b, pbs2, pwr_nav_enabled_b, + pwr_crypto_enabled_b, gpio + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@01010000 { + compatible = "qcom,mdm9607-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + qcom,tlmm-emmc-boot-select = <0x1>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/power/smb358-charger.txt b/Documentation/devicetree/bindings/power/smb358-charger.txt new file mode 100644 index 000000000000..55c2ced3f877 --- /dev/null +++ b/Documentation/devicetree/bindings/power/smb358-charger.txt @@ -0,0 +1,106 @@ +Summit smb358 battery charger + +SMB358 is a single-cell battery charger. It can charge +the battery and power the system via the USB/AC adapter input. + +The smb358 interface is via I2C bus. + +Required Properties: +- compatible Must be "qcom,smb358-charger". +- reg The device 7-bit I2C address. +- interrupt-parent parent of interrupt. +- interrupts This indicates the IRQ number of the GPIO + connected to the STAT pin. +- qcom,irq-gpio GPIO which receives interrupts from STAT output. +- qcom,bms-psy-name This is a string and it points to the bms + power supply name. +- qcom,float-voltage-mv Float Voltage in mV - the maximum voltage up to which + the battery is charged. Supported range 3500mV to 4500mV + +Optional Properties: + +- qcom,fastchg-current-max-ma Fast Charging current in mA. Supported range is + from 200mA to 2000mA. +- qcom,chg-valid-gpio GPIO which indicates the charger presence. + This GPIO is connected to the SYSOK pin. +- qcom,chg-autonomous-mode This is a bool property and it indicates that the + charger is configured for autonomous operation and + does not require any software configuration. +- qcom,disable-apsd This is a bool property which disables automatic + power source detection (APSD). If this is set + charger detection is done by DCIN UV irq. +- qcom,charger-disabled This is a bool property which disables charging. +- qcom,using-pmic-therm This property indicates thermal pin connected to pmic or smb. +- qcom,vcc-i2c-supply Power source required to power up i2c bus. +- qcom,bms-controlled-charging This property indicates integrating with VMBMS, charger + driver and BMS communicates with each other via power_supply + framework. Property "qcom,iterm-disabled" also needs defined + if using this feature to make sure that the charger doesn't + terminate charging on its own. +- qcom,iterm-ma Specifies the termination current to indicate end-of-charge. + Possible values in mA - 30, 40, 60, 80, 100, 125, 150, 200. +- qcom,iterm-disabled Disables the termination current feature. This is a bool + property. +- qcom,recharge-mv Recharge threshold in mV - the offset from the float-volatge + as which the charger restarts charging. Possible + values are 50mV to 300mV. +- qcom,recharge-disabled Boolean value which disables the auto-recharge. +- qcom,chg-inhibit-disabled This is a bool property which disables charger inhibit. + Charger inhibit option prevents battery charging upon insertion + of the charger when battery voltage is above the programmed inhibit + threshold. +- qcom,chg-adc_tm phandle to the corresponding VADC device to read the ADC channels. +- qcom,cold-bat-decidegc Cold battery temperature in decidegC. +- qcom,hot-bat-decidegc Hot battery temperature in decidegC. +- qcom,bat-present-decidegc This is a property indicating battery present temperature, if + higher than it, battery should exist. Default value is negative, + if this property is 200, it stands for -200 decidegC. +- qcom,warm-bat-decidegc: Warm battery temperature in decidegC. After hitting this threshold, + "qcom,warm-bat-ma" defines maximum charging current and + "qcom,warm-bat-mv" defines maximum target voltage. +- qcom,cool-bat-decidegc: Cool battery temperature in decidegC. After hitting this threshold, + "qcom,cool-bat-ma" defines maximum charging current and + "qcom,cool-bat-mv" defines maximum target voltage. +- qcom,warm-bat-ma: Maximum warm battery charge current in milli-amps. +- qcom,cool-bat-ma: Maximum cool battery charge current in milli-amps. +- qcom,warm-bat-mv: Maximum warm battery target voltage in milli-volts. +- qcom,cool-bat-mv: Maximum cool battery target voltage in milli-volts. +- qcom,chg-vadc Corresponding VADC device's phandle. +- qcom,skip-usb-suspend-for-fake-battery: A boolean property to skip suspending USB path for fake + battery. If this property is not present then 'qcom,batt-id-vref-uv' and + 'qcom,batt-id-rpullup-kohm' should be present. +- qcom,batt-id-vref-uv The reference voltage on the battery-ID line + specified in micro-volts. +- qcom,batt-id-rpullup-kohm The pull-up resistor connected on the battery-ID + (vref) line. +- qcom,using-vbat-sns Bool property to indicate that VBAT sense can be + done by PMIC. + +Example: + i2c@f9967000 { + smb358-charger@1b { + compatible = "qcom,smb358-charger"; + reg = <0x1b>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x0>; + qcom,irq-gpio = <&msmgpio 17 0x00>; + qcom,vcc-i2c-supply = <&pm8226_lvs1>; + qcom,float-voltage-mv = <4350>; + qcom,disable-apsd; + qcom,chg-inhibit-disabled; + qcom,bms-controlled-charging; + qcom,fastchg-current-max-ma = <1500>; + qcom,bms-psy-name = "bms"; + qcom,chg-vadc = <&pm8226_vadc>; + qcom,chg-adc_tm = <&pm8226_adc_tm>; + qcom,hot-bat-decidegc = <500>; + qcom,cold-bat-decidegc = <0>; + qcom,bat-present-decidegc = <200>; + qcom,warm-bat-decidegc = <450>; + qcom,cool-bat-decidegc = <100>; + qcom,warm-bat-ma = <350>; + qcom,cool-bat-ma = <350>; + qcom,warm-bat-mv = <4200>; + qcom,cool-bat-mv = <4200>; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-regulator.txt new file mode 100644 index 000000000000..a75001d36f4e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qpnp-regulator.txt @@ -0,0 +1,158 @@ +Qualcomm Technologies, Inc. QPNP Regulators + +qpnp-regulator is a regulator driver which supports regulators inside of PMICs +that utilize the MSM SPMI implementation. + +Required properties: +- compatible: Must be "qcom,qpnp-regulator" +- reg: Specifies the SPMI address and size for this regulator device + Note, this is the only property which can be used within a + subnode of a node which has specified spmi-dev-container. +- regulator-name: A string used as a descriptive name for regulator outputs +- parent-supply: phandle to the parent supply/regulator node + +Required structure: +- A qcom,qpnp-regulator node must be a child of an SPMI node that has specified + the spmi-slave-container property + +Optional properties: +- interrupts: List of interrupts used by the regulator. +- interrupt-names: List of strings defining the names of the + interrupts in the 'interrupts' property 1-to-1. + Supported values are "ocp" for voltage switch + type regulators. If an OCP interrupt is + specified, then the voltage switch will be + toggled off and back on when OCP triggers in + order to handle high in-rush current. +- qcom,system-load: Load in uA present on regulator that is not + captured by any consumer request +- qcom,enable-time: Time in us to delay after enabling the regulator +- qcom,auto-mode-enable: 1 = Enable automatic hardware selection of + regulator mode (HPM vs LPM); not available on + boost type regulators + 0 = Disable auto mode selection +- qcom,bypass-mode-enable: 1 = Enable bypass mode for an LDO type regulator + so that it acts like a switch and simply outputs + its input voltage + 0 = Do not enable bypass mode +- qcom,ocp-enable: 1 = Allow over current protection (OCP) to be + enabled for voltage switch type regulators so + that they latch off automatically when over + current is detected. OCP is enabled when in + HPM or auto mode. + 0 = Disable OCP +- qcom,ocp-max-retries: Maximum number of times to try toggling a voltage + switch off and back on as a result of + consecutive over current events. +- qcom,ocp-retry-delay: Time to delay in milliseconds between each + voltage switch toggle after an over current + event takes place. +- qcom,pull-down-enable: 1 = Enable output pull down resistor when the + regulator is disabled + 0 = Disable pull down resistor +- qcom,soft-start-enable: 1 = Enable soft start for LDO and voltage switch + type regulators so that output voltage slowly + ramps up when the regulator is enabled + 0 = Disable soft start +- qcom,boost-current-limit: This property sets the current limit of boost + type regulators; supported values are: + 0 = 300 mA + 1 = 600 mA + 2 = 900 mA + 3 = 1200 mA + 4 = 1500 mA + 5 = 1800 mA + 6 = 2100 mA + 7 = 2400 mA +- qcom,pin-ctrl-enable: Bit mask specifying which hardware pins should be + used to enable the regulator, if any; supported + bits are: + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal +- qcom,pin-ctrl-hpm: Bit mask specifying which hardware pins should be + used to force the regulator into high power + mode, if any; supported bits are: + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal + BIT(4) = follow PMIC awake state +- qcom,vs-soft-start-strength: This property sets the soft start strength for + voltage switch type regulators; supported values + are: + 0 = 0.05 uA + 1 = 0.25 uA + 2 = 0.55 uA + 3 = 0.75 uA +- qcom,hpm-enable: 1 = Enable high power mode (HPM), also referred + to as NPM. HPM consumes more ground current + than LPM, but it can source significantly higher + load current. HPM is not available on boost + type regulators. For voltage switch type + regulators, HPM implies that over current + protection and soft start are active all the + time. This configuration can be overwritten + by changing the regulator's mode dynamically. + 0 = Do not enable HPM +- qcom,force-type: Override the type and subtype register values. Useful for some + regulators that have invalid types advertised by the hardware. + The format is two unsigned integers of the form <type subtype>. +- spmi-dev-container: Specifies that all the device nodes specified + within this node should have their resources coalesced into a + single spmi_device. This is used to specify all SPMI peripherals + that logically make up a single regulator device. + +Note, if a given optional qcom,* binding is not present, then the qpnp-regulator +driver will leave that feature in the default hardware state. + +All properties specified within the core regulator framework can also be used. +These bindings can be found in regulator.txt. + +Example: + qcom,spmi@fc4c0000 { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8941@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8941_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8941_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,pull-down-enable = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index 5cb44feee8a7..f0d4ba2af719 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -433,6 +433,11 @@ Required properties: Optional properties: - qcom,lpi-gpios : This boolean property is added if GPIOs are under LPI TLMM. +- qcom,chip-wakeup-reg : This lists registers related to control interrupt mask + for respective LPI TLMM GPIOs. +- qcom,chip-wakeup-maskbit : This gives info on maskbit for given list of registers. +- qcom,chip-wakeup-default-val : This gives info on default value to be updated + for given chip regs. * msm-dai-slim @@ -2256,3 +2261,88 @@ Example: asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; }; +* MDM9607 ASoC Machine driver + +Required properties: +- compatible : "qcom,mdm9607-audio-tomtom" for tomtom codec + "qcom,mdm9607-audio-tapan" for tapan codec +- qcom,model : The user-visible name of this sound card. +- qcom,audio-routing : A list of the connections between audio components. +Each entry is a pair of strings, the first being the connection's sink, +the second being the connection's source. +- qcom,codec-mclk-clk-freq : Master clock value given to codec. Some WCD9XXX +codec can run at different mclk values. Mclk value can be 9.6MHz or 12.288MHz. +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order given + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". + +Optional Properties: +- qcom,mi2s-interface-mode: This property contains mi2s interface modes master/ slave. + Entry is a pair of strings, the first being for primary mi2s + and the second for secondary mi2s and so on +- qcom,auxpcm-interface-mode: This property contains auxpcm interface modes master/ slave. + Entry is a pair of strings, the first being for primary auxpcm + and the second for secondary auxpcm and so on + +Example: + +sound-9330 { + compatible = "qcom,mdm9607-audio-tomtom"; + qcom,model = "mdm9607-tomtom-i2s-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3"; + + qcom,tomtom-mclk-clk-freq = <12288000>; + qcom,mi2s-interface-mode = "pri_mi2s_master", "sec_mi2s_master"; + qcom,auxpcm-interface-mode = "pri_pcm_master", "sec_pcm_master"; + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", + "msm-pcm-hostless", "msm-pcm-afe", + "msm-pcm-routing", "msm-pcm-dtmf", "msm-voice-host-pcm"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-mi2s.0", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + }; diff --git a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt new file mode 100644 index 000000000000..e4938359c545 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt @@ -0,0 +1,171 @@ +Qualcomm Technologies, Inc. QPNP PMIC thermal monitor ADC driver (VADC_TM) + +QPNP PMIC thermal monitoring (TM) provides interface to thermal clients +to set temperature thresholds and receive notification when the thresholds +are crossed. A 15 bit ADC is used for measurements. The driver is part +of the sysfs thermal framework that provides support to read the trip +points, set threshold for the trip points and enable the trip points. +Separate kernel api's are provided to usb_id and batt_therm +to set thresholds and receive threshold notifications. + +VADC_TM node + +Required properties: +- compatible : should be "qcom,qpnp-adc-tm" for thermal ADC driver. +- reg : offset and length of the PMIC Aribter register map. +- address-cells : Must be one. +- size-cells : Must be zero. +- interrupts : The thermal ADC bank peripheral interrupts for eoc, high and low interrupts. +- interrupt-names : Should be "eoc-int-en-set", "high-thr-en-set" and "low-thr-en-set". +- qcom,adc-bit-resolution : Bit resolution of the ADC. +- qcom,adc-vdd-reference : Voltage reference used by the ADC. + +Optional properties: +- qcom,thermal-node : If present a thermal node is created and the channel is registered as + part of the thermal sysfs which allows clients to use the thermal framework + to set temperature thresholds and receive notification when the temperature + crosses a set threshold, read temperature and enable/set trip types supported + by the thermal framework. +- qcom,meas-interval-timer-idx: If present select from the following timer index to choose + a preset configurable measurement interval timer value. The driver defaults + to timer 2 with a measurement interval of 1 second if the property is not present. + 0 : Select Timer 1 for a measurement polling interval of 3.9 milliseconds. + 1 : Select Timer 2 for a measurement polling interval of 1 second. + 2 : Select Timer 3 for a measurement polling interval of 4 seconds. +- qcom,adc-tm-recalib-check: Add this property to check if recalibration required due to inaccuracy. +- hkadc_ldo-supply : Add this property if VADC needs to perform a Software Vote for the HKADC. +- hkadc_ok-supply : Add this property if the VADC needs to perform a Software vote for the HKADC VREG_OK. + +Client required property: +- qcom,<consumer name>-adc_tm : The phandle to the corresponding adc_tm device. + The consumer name passed to the driver when calling + qpnp_get_adc_tm() is used to associate the client + with the corresponding device. + +Channel nodes +NOTE: Atleast one Channel node is required. + +Required properties: +- label : Channel name used for sysfs entry. +- reg : AMUX channel number. +- qcom,decimation : Sampling rate to use for the individual channel measurement. + Select from the following unsigned int. + 0 : 512 + 1 : 1K + 2 : 2K + 3 : 4K +- qcom,pre-div-channel-scaling : Pre-div used for the channel before the signal is being measured. + Select from the following unsigned int for the corresponding + numerator/denominator pre-div ratio. + 0 : pre-div ratio of {1, 1} + 1 : pre-div ratio of {1, 3} + 2 : pre-div ratio of {1, 4} + 3 : pre-div ratio of {1, 6} + 4 : pre-div ratio of {1, 20} + 5 : pre-div ratio of {1, 8} + 6 : pre-div ratio of {10, 81} + 7 : pre-div ratio of {1, 10} +- qcom,calibration-type : Reference voltage to use for channel calibration. + Channel calibration is dependendent on the channel. + Certain channels like XO_THERM, BATT_THERM use ratiometric + calibration. Most other channels fall under absolute calibration. + Select from the following strings. + "absolute" : Uses the 625mv and 1.25V reference channels. + "ratiometric" : Uses the reference Voltage/GND for calibration. +- qcom,scale-function : Reverse scaling function used to convert raw ADC code to units specific to + a given channel. + Select from the following unsigned int. + 0 : Scaling to convert voltage in uV to raw adc code. + 1 : Scaling to convert decidegC to raw adc code. + 2 : Scaling for converting USB_ID reverse scaling. + 3 : Scaling to convert milldegC to raw ADC code. + 4 : Scaling to convert smb_batt_therm values to raw ADC code. + 5 : Scaling to perform reverse calibration for absolute voltage from uV + to raw ADC code. + 6 : Scaling to convert qrd skuh battery decidegC to raw ADC code. +- qcom,hw-settle-time : Settling period for the channel before ADC read. + Select from the following unsigned int. + 0 : 0us + 1 : 100us + 2 : 200us + 3 : 300us + 4 : 400us + 5 : 500us + 6 : 600us + 7 : 700us + 8 : 800us + 9 : 900us + 0xa : 1ms + 0xb : 2ms + 0xc : 4ms + 0xd : 6ms + 0xe : 8ms + 0xf : 10ms +- qcom,fast-avg-setup : Average number of samples to be used for measurement. Fast averaging + provides the option to obtain a single measurement from the ADC that + is an average of multiple samples. The value selected is 2^(value) + Select from + 0 : 1 + 1 : 2 + 2 : 4 + 3 : 8 + 4 : 16 + 5 : 32 + 6 : 64 + 7 : 128 + 8 : 256 +- qcom,btm-channel-number : Depending on the PMIC version, a max of upto 8 BTM channels. + The BTM channel numbers are statically allocated to the + corresponding channel node. +- qcom,adc_tm-vadc : phandle to the corresponding VADC device to read the ADC channels. + +Client device example: +/* Add to the clients node that needs the ADC_TM channel A/D */ +client_node { + qcom,client-adc_tm = <&pm8941_adc_tm>; +}; + +Example: + /* Main Node */ + qcom,vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,adc_tm-vadc = <&pm8941_vadc>; + + /* Channel Node to be registered as part of thermal sysfs */ + chan@b5 { + label = "pa_therm1"; + reg = <0xb5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + /* Channel Node */ + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x78>; + }; + }; diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt index dcb4bda84f2b..46e31626a4ea 100644 --- a/Documentation/devicetree/bindings/thermal/tsens.txt +++ b/Documentation/devicetree/bindings/thermal/tsens.txt @@ -22,6 +22,7 @@ Required properties: should be "qcom,msm8937-tsens" for 8937 TSENS driver. should be "qcom,qcs405-tsens" for QCS405 TSENS driver. should be "qcom,sm6150-tsens" for 6150 TSENS driver. + should be "qcom,mdm9607-tsens" for 9607 TSENS driver. The compatible property is used to identify the respective controller to use for the corresponding SoC. diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt new file mode 100644 index 000000000000..8ed5b97202ab --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt @@ -0,0 +1,84 @@ +* Qualcomm Technologies, Inc. MSM UART + +Required properties: +- compatible : + - "qcom,msm-uart", and one of "qcom,msm-hsuart" or + "qcom,msm-lsuart". +- reg : offset and length of the register set for the device + for the hsuart operating in compatible mode, there should be a + second pair describing the gsbi registers. +- interrupts : should contain the uart interrupt. + +There are two different UART blocks used in MSM devices, +"qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is +able to handle both of these, and matches against the "qcom,msm-uart" +as the compatibility. + +The registers for the "qcom,msm-hsuart" device need to specify both +register blocks, even for the common driver. + +Example: + + uart@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <195>; + }; + +* Qualcomm Technologies, Inc. MSM HSUART + +Required properties: +- compatible : one of: + - "qcom,msm-lsuart-v14" +- reg : offset and length of the register set for the device. +- interrupts : should contain the uart interrupt. + +Optional properties: +- qcom,config-gpio : Set this value if UART GPIOs need to be configured by driver. +set 4 if 4-wire UART used (for Tx, Rx, CTS, RFR GPIOs). +Set 1 if 2-wire UART used (for Tx, Rx GPIOs). +- qcom,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" in +Documentation/devicetree/bindings/gpio/gpio.txt. +"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs +need to configured. +qcom,use-pm : If present, this property will cause the device to prevent system +suspend as long as the port remains open. +- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for below properties: + - qcom,msm_bus,name + - qcom,msm_bus,num_cases + - qcom,msm_bus,active_only + - qcom,msm_bus,num_paths + - qcom,msm_bus,vectors + +Aliases: +An alias may optionally be used to bind the serial device to a tty device +(ttyHSLx) with a given line number. Aliases are of the form serial<n> where <n> +is an integer representing the line number to use. On systems with multiple +serial devices present it is recommended that an alias be defined for each such +device. + +Example: + aliases { + serial0 = &uart0; // This device will be called ttyHSL0 + }; + + uart0: serial@19c400000 { + compatible = "qcom,msm-lsuart-v14" + reg = <0x19c40000 0x1000">; + interrupts = <195>; + + qcom,config-gpio = <4>; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; + qcom,use-pm; + + qcom,msm-bus,name = "serial_uart0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + }; diff --git a/Documentation/devicetree/bindings/usb/msm-ehci-hsic.txt b/Documentation/devicetree/bindings/usb/msm-ehci-hsic.txt new file mode 100644 index 000000000000..e5304f8852f9 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/msm-ehci-hsic.txt @@ -0,0 +1,216 @@ +MSM HSIC EHCI controller + +Required properties : +- compatible : should be "qcom,hsic-host" +- regs : offset and length of the register set in the memory map +- interrupts: IRQ lines used by this controller +- interrupt-names : Required interrupt resource entries are: + "core_irq" : Interrupt for HSIC core +- <supply-name>-supply: handle to the regulator device tree node + Required "supply-name" is either "hsic_vdd_dig" or "HSIC_VDDCX" and + optionally - "HSIC_GDSC". + +Optional properties : +- interrupt-parent - This must provide reference to the current + device node. +- #address-cells - Should provide a value of 0. +- interrupts - Should be <0 1 2> and it is an index to the + interrupt-map. +- #interrupt-cells - should provide a value of 1. +- #interrupt-mask - should provide a value of 0xffffffff. +- interrupt-map - Must create mapping for the number of interrupts + that are defined in above interrupts property. + For HSIC device node, it should define 3 mappings for + core_irq, async_irq and wakeup in the format + mentioned in below example node of HSIC. + +- interrupt-names : Optional interrupt resource entries are: + "async_irq" : Interrupt from HSIC for asynchronous events in HSIC LPM. + "wakeup" : Wakeup interrupt from HSIC during suspend (or XO shutdown). +- pinctrl-names : This should be defined if a target uses pinctrl framework. + See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt. + It should specify the names of the configs that pinctrl can install in driver + Following are the pinctrl configs that can be installed + "hsic_ehci_active" : Active configuration of pins, this should specify active + config defined in pin groups of used gpio's from strobe, data and + resume. + "hsic_ehci_sleep" : Disabled configuration of pins, this should specify sleep + config defined in pin groups of used gpio's from strobe, data and + resume. +- hsic,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" + in Documentation/devicetree/bindings/gpio/gpio.txt. + If pinctrl is being used we need to define only gpio's which drives signals + using gpiolib api's like resume gpio in dt, the node name in such cases should + be msm_gpio as defined in pinctrl-dtsi. For gpio's only installing active and + sleep configs it is not required to specify the gpio in dt file. + Optional "gpio-name" can be "strobe", "data" and "resume". +- hsic,resume-gpio : if present then periperal connected to hsic controller + cannot wakeup from XO shutdown using in-band hsic resume. Use resume + gpio to wakeup peripheral +- qcom,phy-sof-workaround : If present then HSIC PHY has h/w BUGs related to + SOFs. All the relevant software workarounds are required for the same during + suspend, reset and resume. +- qcom,phy-susp-sof-workaround : If present then HSIC PHY has h/w BUG related to + SOFs while entering SUSPEND. Relevant software workaround is required for the same + during SUSPEND. +- qcom,phy-reset-sof-workaround : If present then HSIC PHY has h/w BUG related to + SOFs during RESET. +- qcom,pool-64-bit-align: If present then the pool's memory will be aligned + to 64 bits +- qcom,enable_hbm: if present host bus manager is enabled. +- qcom,disable-park-mode: if present park mode is enabled. Park mode enables executing + up to 3 usb packets from each QH. +- hsic,consider-ipa-handshake: If present then hsic low power mode is + depend on suitable handshake with the IPA peer. +- qcom,ahb-async-bridge-bypass: if present AHB ASYNC bridge will be bypassed such that + the bridge on the slave AHB is always used. +- hsic,log2-itc: itc (interrupt threshold control) defines rate at which usb + controller will issue interrupts. It represents max interrupt interval + measured in micro frames. In high speed USB, each micro frame is 125us. + Valid values are from zero to six. Zero is default. Higher ITC value will + result in higher interrupt latency and can impact overall data latency. + + log2-itc - Max interrupt threshold + -------- ----------------------- + 0 (2^0 = 1) 1 micro frame interrupt threshold aka 125us interrupt threshold + 1 (2^1 = 2) 2 micro frame interrupt threshold aka 250us interrupt threshold + 2 (2^2 = 4) 4 micro frame interrupt threshold aka 500us interrupt threshold + 3 (2^3 = 8) 8 micro frame interrupt threshold aka 1ms interrupt threshold + 4 (2^4 = 16) 16 micro frame interrupt threshold aka 2ms interrupt threshold + 5 (2^5 = 32) 32 micro frame interrupt threshold aka 4ms interrupt threshold + 6 (2^6 = 64) 64 micro frame interrupt threshold aka 8ms interrupt threshold + +- hsic,disable-cerr: CERR is 2bit down error counter that keeps track of number + of consecutive errors detected on single usb transaction. When set to non + zero value, hw decrements the count and updates qTD when transaction fails. + If counter reaches zero, hw marks the qTD inactive and triggers the interrupt. + When CERR is programmed to zero, hw ignores transaction failures. ECHI stack + programs the CERR to 3 by default. When this flag is true, CERR is set to + zero and transaction errors are ignored. + +- hsic,reset-delay: If present then add the given delay time (ms) between + the reset and enumeration. Since some devices might take more than 100ms + for initialization when receiving the bus reset, add delay to avoid the + problem that enmueration is before device initialization done. +- hsic,vdd-voltage-level: This property must be a list of three integer + values (no, min, max) where each value represents either a voltage in + microvolts or a value corresponding to voltage corner +- qcom,disable-internal-clk-gating: If present then internal clock gating in + controller is disabled. Internal clock gating is enabled by default in hw. + +- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for + below optional properties: + - qcom,msm_bus,name + - qcom,msm_bus,num_cases + - qcom,msm_bus,num_paths + - qcom,msm_bus,vectors + + +Example MSM HSIC EHCI controller device node : + hsic_host: hsic@f9a15000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a15000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msm_gpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + hsic_vdd_dig-supply = <&pm8841_s2_corner>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + /* If pinctrl is used and resume gpio is present */ + pinctrl-names = "hsic_ehci_active","hsic_ehci_sleep"; + pinctrl-0 = <&hsic_act &resume_act>; + pinctrl-1 = <&hsic_sus &resume_act>; + hsic,resume-gpio = <&msm_gpio 80 0x00>; + /* else (pinctrl is not present) */ + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,resume-gpio = <&msmgpio 80 0x00>; + /* End */ + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + hsic,consider-ipa-handshake; + hsic,vdd-voltage-level = <1 5 7>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + +SMSC HSIC HUB + +Required properties : +- compatible : should be "qcom,hsic-smsc-hub" +- smsc,model-id : should be <3502>/<3503>/<4604> depending on hub model. It + will be 0 for standalone HSIC controller configuration. +- smsc,reset-gpio: this output gpio is used to assert/de-assert the hub reset +- Sub node for "MSM HSIC EHCI controller". + Sub node has the required properties mentioned above. + +Optional properties : +- pinctrl-names : This should be defined if a target uses pinctrl framework. + See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt. + It should specify the names of the configs that pinctrl can install in driver + Following are the pinctrl configs that can be installed + "smsc_active" : Active configuration of pins, this should specify active + config defined in pin groups of used gpio's from reset, refclk, xo-clk + and int. + "smsc_sleep" : Disabled configuration of pins, this should specify the sleep + config defined in pin groups of used gpio's from reset, refclk, xo-clk + and int. + If pinctrl is being used we need to only define gpio's which drives signals + using gpiolib api's like reset and xo-clk gpio in dt, the node name in such + cases should be msm_gpio as defined in pinctrl-dtsi. For gpio's only + installing active and sleep configs it is not required to specify the gpio + in dt file. +- smsc,int-gpio: this input gpio indicate HUB suspend status and signal remote + wakeup interrupt +- smsc,refclk-gpio: this gpio is used to supply the reference clock +- smsc,xo-clk-gpio: this output gpio is used to control the external XO clock + which is supplied to the hub as a reference clock +- hub-vbus-supply: this regulator is used to supply the power to + downstream ports +- hub-int-supply: this regulator is used to bias the interrupt gpio +- ext-hub-vddio-supply: this regulator is used to supply the power to one of + the hub's VDD. + +Example SMSC HSIC HUB : + hsic_hub { + compatible = "qcom,hsic-smsc-hub"; + smsc,model-id = <4604>; + ranges; + /* If pinctrl is used with all gpio_present */ + pinctrl-names = "smsc_active","smsc_sleep"; + pinctrl-0 = <&reset_act &refclk_act &int_act>; + pinctrl-1 = <&reset_sus &refclk_sus &int_sus>; + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + /* If target does not use pinctrl */ + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + smsc,refclk-gpio = <&pm8941_gpios 16 0x00>; + smsc,int-gpio = <&msmgpio 50 0x00>; + /* End if */ + hub-int-supply = <&pm8941_l10>; + hub-vbus-supply = <&pm8941_mvs1>; + + hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + interrupts = <0 136 0>; + interrupt-names = "core_irq"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/msm-hsic-peripheral.txt b/Documentation/devicetree/bindings/usb/msm-hsic-peripheral.txt new file mode 100644 index 000000000000..449fef0fa161 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/msm-hsic-peripheral.txt @@ -0,0 +1,37 @@ +USB HSIC Peripheral: + +This describes device tree node for the USB HSIC Peripheral. This works with +usage of USB Device controller to enable USB HSIC Device mode functionality. + +Required properties: +- compatible: should be "qcom,hsic-peripheral" +- regs : offset and length of the register set in the memory map +- interrupts: IRQ lines used by this controller +- <supply-name>-supply: handle to the regulator device tree node + Required "supply-name" is "vdd" and optional "GDSC". +- qcom,vdd-voltage-level: This property must be a list of three integer + values (no, min, max) where each value represents either a voltage in + microvolts or a value corresponding to voltage corner. + +Optional properties : +- qcom,usb-id-core: USB Core Index to be used to bind with gadget driver. +- qcom,hsic-tlmm-init-seq: HSIC TLMM PADS initialization sequence with + reg, value pairs. +- reg : offset and length of the register set in the memory map. + This is required if 'qcom,hsic-tlmm-init-seq' is specified. +- qcom,hsic-disable-on-boot: If present then HSIC is suspended on bootup + and user can enable this using sysfs if HSIC host is present. +Example USB HSIC device node : + hsic: hsic@f9a15000 { + compatible = "qcom,hsic-peripheral"; + reg = <0xf9a15000 0x352>, + <0x01112000 0xc>; + interrupts = <0 136 0>; + qcom,usb-id-core = <1>; + vdd-supply = <&pmd9635_l2>; + GDSC-supply = <&gdsc_usb_hsic>; + qcom,vdd-voltage-level = <0 1200000 1200000>; + qcom,hsic-tlmm-init-seq = + <0x8 0x5 0x4 0x5 0x0 0x1>; + qcom,hsic-disable-on-boot; + }; diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt index dd3e52eb0ec7..0af16141e6ed 100644 --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt @@ -109,3 +109,234 @@ Example HSUSB OTG controller device node: qcom,phy-init-sequence = < -1 0x63 >; qcom,vdd-levels = <1 5 7>; }; +OTG: + +Required properties : +- compatible : should be "qcom,hsusb-otg" +- regs : Array of offset and length of the register sets in the memory map +- reg-names : indicates various iomem resources passed by name. The possible + strings in this field are: + "core": USB controller register space. (Required) + "tcsr": TCSR register for routing USB Controller signals to + either picoPHY0 or picoPHY1. (Optional) + "phy_csr": PHY Wrapper CSR register space. Provides register level + interface through AHB2PHY for performing PHY related operations + like retention and HV interrupts management. +- interrupts: IRQ line +- interrupt-names: OTG interrupt name(s) referenced in interrupts above + HSUSB OTG expects "core_irq" which is IRQ line from CORE and + "async_irq" from HSPHY for asynchronous wakeup events in LPM. + optional ones are described in next section. +- qcom,hsusb-otg-phy-type: PHY type can be one of + 1 - Chipidea PHY (obsolete) + 2 - Synopsis Pico PHY + 3 - Synopsis Femto PHY + 4 - QUSB ULPI PHY +- qcom,hsusb-otg-mode: Operational mode. Can be one of + 1 - Peripheral only mode + 2 - Host only mode + 3 - OTG mode + Based on the mode, OTG driver registers platform devices for + gadget and host. +- qcom,hsusb-otg-otg-control: OTG control (VBUS and ID notifications) + can be one of + 1 - PHY control + 2 - PMIC control + 3 - User control (via debugfs) +- <supply-name>-supply: handle to the regulator device tree node + Required "supply-name" is "HSUSB_VDDCX" (when voting for VDDCX) or + "hsusb_vdd_dig" (when voting for VDDCX Corner voltage), + "HSUSB_1p8-supply" and "HSUSB_3p3-supply". +- qcom,vdd-voltage-level: This property must be a list of three integer + values (none, min, max) where each value represents either a voltage + in microvolts or a value corresponding to voltage corner. If usb core + supports svs, min value will have absolute SVS or SVS corner otherwise + min value will have absolute nominal or nominal corner. +- clocks: a list of phandles to the USB clocks. Usage is as per + Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. + + Required clocks: + "core_clk": USB core clock that is required for data transfers. + "iface_clk": USB core clock that is required for register access. + + Optional clocks: + "sleep_clk": PHY sleep clock. Required for interrupts. + "phy_reset_clk": PHY blocks asynchronous reset clock. Required + for the USB block reset. It is a reset only clock. + "phy_por_clk": Reset only clock for asserting/de-asserting + PHY POR signal. Required for overriding PHY parameters. + "phy_csr_clk": Required for accessing PHY CSR registers through + AHB2PHY interface. + "phy_ref_clk": Required when PHY have referance clock, + "xo": XO clock. The source clock that is used as a reference clock + to the PHY. + "bimc_clk", "snoc_clk", "pcnoc_clk": bus voting clocks. Used to + keep buses at a nominal frequency during USB peripheral + mode for achieving max throughput. +- qcom,max-nominal-sysclk-rate: Indicates maximum nominal frequency for which + system clock should be voted whenever streaming mode is enabled. + +Optional properties : +- interrupt-names : Optional interrupt resource entries are: + "pmic_id_irq" : Interrupt from PMIC for external ID pin notification. + "phy_irq" : Interrupt from PHY. Used for ID detection. +- qcom,hsusb-otg-disable-reset: If present then core is RESET only during + init, otherwise core is RESET for every cable disconnect as well +- qcom,hsusb-otg-pnoc-errata-fix: If present then workaround for PNOC + performance issue is applied which requires changing the mem-type + attribute via VMIDMT. +- qcom,hsusb-otg-default-mode: The default USB mode after boot-up. + Applicable only when OTG is controlled by user. Can be one of + 0 - None. Low power mode + 1 - Peripheral + 2 - Host +- qcom,hsusb-otg-phy-init-seq: PHY configuration sequence. val, reg pairs + terminate with -1 +- qcom,hsusb-otg-power-budget: VBUS power budget in mA + 0 will be treated as 500mA +- qcom,hsusb-otg-pclk-src-name: The source of pclk +- Refer to "Documentation/devicetree/bindings/arm/msm/msm-bus.txt" for + below optional properties: + - qcom,msm-bus,name + - qcom,msm-bus,num_cases - There are three valid cases for this: NONE, MAX + and MIN bandwidth votes. Minimum two cases must be defined for + both NONE and MAX votes. If MIN vote is different from NONE VOTE + then specify third case for MIN VOTE. If explicit NOC clock rates + are not specified then MAX value should be large enough to get + desired BUS frequencies. In case explicit NOC clock rates are + specified, peripheral mode bus bandwidth vote should be defined + to vote for arbitrated bandwidth so that 60MHz frequency is met. + + - qcom,msm-bus,num_paths + - qcom,msm-bus,vectors +- qcom,hsusb-otg-lpm-on-dev-suspend: If present then USB enter to + low power mode upon receiving bus suspend. +- qcom,hsusb-otg-clk-always-on-workaround: If present then USB core clocks + remain active upon receiving bus suspend and USB cable is connected. + Used for allowing USB to respond for remote wakup. +- qcom,hsusb-otg-delay-lpm: If present then USB core will wait one second + after disconnect before entering low power mode. +- <supply-name>-supply: handle to the regulator device tree node. + Optional "supply-name" is "vbus_otg" to supply vbus in host mode. +- qcom,dp-manual-pullup: If present, vbus is not routed to USB controller/phy + and controller driver therefore enables pull-up explicitly before + starting controller using usbcmd run/stop bit. +- qcom,usb2-enable-hsphy2: If present then USB2 controller is connected to 2nd + HSPHY. +- qcom,hsusb-log2-itc: value of 2^(log2_itc-1) will be used as the + interrupt threshold (ITC), when log2_itc is between 1 to 7. +- qcom,hsusb-l1-supported: If present, the device supports l1 (Link power + management). +- qcom,no-selective-suspend: If present selective suspend is disabled on hub ports. +- qcom,hsusb-otg-mpm-dpsehv-int: If present, indicates mpm interrupt to be + configured for detection of dp line transition during VDD minimization. +- qcom,hsusb-otg-mpm-dmsehv-int: If present, indicates mpm interrupt to be + configured for detection of dm line transition during VDD minimization. +- pinctrl-names : This should be defined if a target uses gpio and pinctrl framework. + See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt. + It should specify the names of the configs that pinctrl can install in driver + Following are the pinctrl config that can be installed + "hsusb_active" : Active configuration of pins, this should specify active + config of vddmin gpio (if used) defined in their pin groups. + "hsusb_sleep" : Disabled configuration of pins, this should specify sleep + config of vddmin gpio (if used) defined in their pin groups. +- qcom,hsusb-otg-vddmin-gpio = If present, indicates a gpio that will be used + to supply voltage to the D+ line during VDD minimization and peripheral + bus suspend. If not exists, then VDD minimization will not be allowed + during peripheral bus suspend. +- qcom,ahb-async-bridge-bypass: If present, indicates that enable AHB2AHB By Pass + mode with device controller for better throughput. With this mode, USB Core + runs using PNOC clock and synchronous to it. Hence it is must to have proper + "qcom,msm-bus,vectors" to have high bus frequency. User shouldn't try to + enable this feature without proper bus voting. When this feature is enabled, + it is required to do HW reset during cable disconnect for host mode functionality + working and hence need to disable qcom,hsusb-otg-disable-reset. With this feature + enabled, USB HW has to vote for maximum PNOC frequency as USB HW cannot tolerate + changes in PNOC frequency which results in USB functionality failure. +- qcom,disable-retention-with-vdd-min: If present don't allow phy retention but allow + vdd min. +- qcom,usbin-vadc: Corresponding vadc device's phandle to read usbin voltage using VADC. + This will be used to get value of usb power supply's VOLTAGE_NOW property. +- qcom,usbid-gpio: This corresponds to gpio which is used for USB ID detection. +- qcom,hub-reset-gpio: This corresponds to gpio which is used for HUB reset. +- qcom,sw-sel-gpio: This corresponds to gpio which is used for switch select routing + of D+/D- between the USB HUB and type B USB jack for peripheral mode. +- qcom,bus-clk-rate: If present, indicates nominal bus frequency to be voted for + bimc/snoc/pcnoc clock with usb cable connected. If AHB2AHB bypass is enabled, + pcnoc value should be defined to very large number so that PNOC runs at max + frequency. If 'qcom,default-mode-svs' is also set then two set of frequencies + must be specified for SVS and NOM modes which user can change using sysfs node. +- qcom,phy-dvdd-always-on: If present PHY DVDD is supplied by a always-on + regulator unlike vddcx/vddmx. PHY can keep D+ pull-up and D+/D- + pull-down resistors during peripheral and host bus suspend without + any re-work. +- qcom,emulation: Indicates that we are running on emulation platform. +- qcom,boost-sysclk-with-streaming: If present, enable controller specific + streaming feature. Also this flag can bump up usb system clock to max in streaming + mode. This flag enables streaming mode for all compositions and is different from + streaming-func property defined in android device node. Please refer Doumentation/ + devicetree/bindings/usb/android-dev.txt for details about "streaming-func" property. +- qcom,axi-prefetch-enable: If present, AXI64 interface will be used for transferring data + to/from DDR by controller. +- qcom,enable-sdp-typec-current-limit: Indicates whether type-c current for SDP CHARGER to + be limited. +- qcom,enable-phy-id-pullup: If present, PHY can keep D+ pull-up resistor on USB ID line + during cable disconnect. +- qcom,max-svs-sysclk-rate: Indicates system clock frequency voted by driver in + non-perf mode. In perf mode driver uses qcom,max-nominal-sysclk-rate. +- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, + which is used as a vote by driver to get max performance in perf mode. +- qcom,default-mode-svs: Indicates USB system clock should run at SVS frequency. + User can bump it up using 'perf_mode' sysfs attribute for gadget. +- qcom,vbus-low-as-hostmode: If present, specifies USB_VBUS to switch to host mode + if USB_VBUS is low or device mode if USB_VBUS is high. +- qcom,usbeth-reset-gpio: If present then an external usb-to-eth is connected to + the USB host controller and its RESET_N signal is connected to this + usbeth-reset-gpio GPIO. It should be driven LOW to RESET the usb-to-eth. + +Example HSUSB OTG controller device node : + usb@f9690000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9690000 0x400>; + reg-names = "core"; + interrupts = <134>; + interrupt-names = "core_irq"; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <1>; + qcom,hsusb-otg-disable-reset; + qcom,hsusb-otg-pnoc-errata-fix; + qcom,hsusb-otg-default-mode = <2>; + qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>; + qcom,hsusb-otg-power-budget = <500>; + qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk"; + qcom,hsusb-otg-lpm-on-dev-suspend; + qcom,hsusb-otg-clk-always-on-workaround; + hsusb_vdd_dig-supply = <&pm8226_s1_corner>; + HSUSB_1p8-supply = <&pm8226_l10>; + HSUSB_3p3-supply = <&pm8226_l20>; + qcom,vdd-voltage-level = <1 5 7>; + qcom,dp-manual-pullup; + qcom,hsusb-otg-mpm-dpsehv-int = <49>; + qcom,hsusb-otg-mpm-dmsehv-int = <58>; + qcom,max-nominal-sysclk-rate = <133330000>; + qcom,max-svs-sysclk-rate = <100000000>; + qcom,pm-qos-latency = <59>; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num_cases = <2>; + qcom,msm-bus,num_paths = <1>; + qcom,msm-bus,vectors = + <87 512 0 0>, + <87 512 60000000 960000000>; + pinctrl-names = "hsusb_active","hsusb_sleep"; + pinctrl-0 = <&vddmin_act>; + pinctrl-0 = <&vddmin_sus>; + qcom,hsusb-otg-vddmin-gpio = <&pm8019_mpps 6 0>; + qcom,disable-retention-with-vdd-min; + qcom,usbin-vadc = <&pm8226_vadc>; + qcom,usbid-gpio = <&msm_gpio 110 0>; + }; diff --git a/arch/arm/Makefile b/arch/arm/Makefile index db67a793d867..e9b84ea6a0d6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -13,6 +13,10 @@ # Ensure linker flags are correct LDFLAGS := +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +export DTC_FLAGS := -@ +endif + LDFLAGS_vmlinux :=-p --no-undefined -X --pic-veneer ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 2fa123e315cc..52e8c50aeee0 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -34,10 +34,10 @@ targets := Image zImage xipImage bootpImage uImage DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES)) ifneq ($(DTB_NAMES),) DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES)) +DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST)) else -DTB_LIST := $(dtb-y) +DTB_OBJS := $(shell find $(obj)/dts/ -name \*.dtb) endif -DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST)) ifeq ($(CONFIG_XIP_KERNEL),y) diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 96a62a55a663..d89e21252c37 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -73,6 +73,45 @@ config ARCH_QCS403 This enables support for the QCS403 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. +config ARCH_TRINKET + bool "Enable Support for TRINKET" + select CPU_V7 + select CLKDEV_LOOKUP + select HAVE_CLK + select HAVE_CLK_PREPARE + select PM_OPP + select SOC_BUS + select MSM_IRQ + select THERMAL_WRITABLE_TRIPS + select ARM_GIC_V3 + select ARM_AMBA + select SPARSE_IRQ + select MULTI_IRQ_HANDLER + select HAVE_ARM_ARCH_TIMER + select MAY_HAVE_SPARSE_IRQ + select COMMON_CLK + select QCOM_GDSC + select PINCTRL_MSM + select USE_PINCTRL_IRQ + select MSM_PM if PM + select QMI_ENCDEC + select CPU_FREQ + select PM_DEVFREQ + select MSM_DEVFREQ_DEVBW + select DEVFREQ_SIMPLE_DEV + select DEVFREQ_GOV_MSM_BW_HWMON + select MSM_BIMC_BWMON + select MSM_QDSP6V2_CODECS + select MSM_AUDIO_QDSP6V2 if SND_SOC + select MSM_RPM_SMD + select PCI + select MSM_JTAG_MM if CORESIGHT_ETM + select MSM_RPM_LOG + select MSM_RPM_STATS_LOG + help + This enables support for the TRINKET chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + config ARCH_MSM8X60 bool "Enable support for MSM8X60" select ARCH_SUPPORTS_BIG_ENDIAN diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index ab38dbb3e972..92d71e8c97b3 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_USE_OF) += board-dt.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_ARCH_QCS405) += board-qcs405.o obj-$(CONFIG_ARCH_QCS403) += board-qcs403.o +obj-$(CONFIG_ARCH_TRINKET) += board-trinket.o obj-$(CONFIG_ARCH_SDXPRAIRIE) += board-sdxprairie.o obj-$(CONFIG_ARCH_MDM9607) += board-mdm9607.o diff --git a/arch/arm/mach-qcom/board-trinket.c b/arch/arm/mach-qcom/board-trinket.c new file mode 100644 index 000000000000..be86457aaf86 --- /dev/null +++ b/arch/arm/mach-qcom/board-trinket.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <asm/mach/map.h> +#include <asm/mach/arch.h> +#include "board-dt.h" + +static const char *trinket_dt_match[] __initconst = { + "qcom,trinket", + NULL +}; + +static void __init trinket_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(TRINKET, + "Qualcomm Technologies, Inc. TRINKET (Flattened Device Tree)") + .init_machine = trinket_init, + .dt_compat = trinket_dt_match, +MACHINE_END diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d557d69effab..e65f24490c20 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -258,9 +258,12 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) atoll-wcd937x-idp-overlay.dtbo\ atoll-usbc-idp-overlay.dtbo\ atoll-rumi-overlay.dtbo\ - atollp-idp-overlay.dtbo \ - atollp-atp-overlay.dtbo \ - atollp-qrd-overlay.dtbo + atollp-idp-overlay.dtbo\ + atollp-atp-overlay.dtbo\ + atollp-qrd-overlay.dtbo\ + atoll-ab-idp-overlay.dtbo\ + atoll-ab-atp-overlay.dtbo\ + atoll-ab-qrd-overlay.dtbo atoll-idp-overlay.dtbo-base := atoll.dtb atoll-atp-overlay.dtbo-base := atoll.dtb @@ -271,6 +274,9 @@ atoll-usbc-idp-overlay.dtbo-base := atoll.dtb atollp-idp-overlay.dtbo-base := atollp.dtb atollp-atp-overlay.dtbo-base := atollp.dtb atollp-qrd-overlay.dtbo-base := atollp.dtb +atoll-ab-idp-overlay.dtbo-base := atoll-ab.dtb +atoll-ab-atp-overlay.dtbo-base := atoll-ab.dtb +atoll-ab-qrd-overlay.dtbo-base := atoll-ab.dtb else dtb-$(CONFIG_ARCH_ATOLL) += atoll-idp.dtb\ atoll-atp.dtb\ @@ -280,7 +286,10 @@ dtb-$(CONFIG_ARCH_ATOLL) += atoll-idp.dtb\ atoll-rumi.dtb\ atollp-idp.dtb\ atollp-atp.dtb\ - atollp-qrd.dtb + atollp-qrd.dtb\ + atoll-ab-idp.dtb\ + atoll-ab-atp.dtb\ + atoll-ab-qrd.dtb endif dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ @@ -318,6 +327,8 @@ dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ sa515m-v2-ccard-pcie-ep.dtb \ sa515m-v2-ccard-usb-ep.dtb +dtb-$(CONFIG_ARCH_MDM9607) += mdm9607-mtp.dtb + ifeq ($(CONFIG_ARM64),y) always := $(dtb-y) subdir-y := $(dts-dirs) @@ -328,6 +339,14 @@ targets += $(addprefix ../, $(dtb-y)) $(obj)/../%.dtb: $(src)/%.dts FORCE $(call if_changed_dep,dtc) +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +$(obj)/%.dtbo:$(src)/../../../../arm64/boot/dts/qcom/%.dts FORCE + $(call if_changed_dep,dtc) + $(call if_changed,dtbo_verify) + +dtbs: $(addprefix $(obj)/,$(dtb-y)) $(addprefix $(obj)/,$(dtbo-y)) +else dtbs: $(addprefix $(obj)/../,$(dtb-y)) endif +endif clean-files := *.dtb *.dtbo diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-atp-overlay.dts b/arch/arm64/boot/dts/qcom/atoll-ab-atp-overlay.dts new file mode 100644 index 000000000000..b03dbf33da52 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-atp-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "atoll-atp.dtsi" +#include "atoll-audio-overlay.dtsi" + +/ { + model = "ATP"; + compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp", "qcom,atp"; + qcom,msm-id = <443 0x0>; + qcom,board-id = <33 0>; +}; + +&dsi_rm69299_visionox_amoled_vid_display { + qcom,dsi-display-active; +}; + +&tx_swr_gpios { + qcom,chip-wakeup-reg = <0x01FFB000>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-atp.dts b/arch/arm64/boot/dts/qcom/atoll-ab-atp.dts new file mode 100644 index 000000000000..8d4b52be8241 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-atp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "atoll-ab.dtsi" +#include "atoll-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 ATP"; + compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", + "qcom,idp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-idp-overlay.dts b/arch/arm64/boot/dts/qcom/atoll-ab-idp-overlay.dts new file mode 100644 index 000000000000..73636c747758 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-idp-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "atoll-idp.dtsi" +#include "atoll-audio-overlay.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp"; + qcom,msm-id = <443 0x0>; + qcom,board-id = <34 0>; +}; + +&dsi_rm69299_visionox_amoled_vid_display { + qcom,dsi-display-active; +}; + +&tx_swr_gpios { + qcom,chip-wakeup-reg = <0x01FFB000>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-idp.dts b/arch/arm64/boot/dts/qcom/atoll-ab-idp.dts new file mode 100644 index 000000000000..2a516b66b4e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-idp.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "atoll-ab.dtsi" +#include "atoll-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 IDP"; + compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp"; + qcom,board-id = <34 0>; +}; + +&dsi_rm69299_visionox_amoled_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/atoll-ab-qrd-overlay.dts new file mode 100644 index 000000000000..d486994846de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-qrd-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "atoll-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,atoll-ab-qrd", "qcom,atoll-ab", "qcom,qrd"; + qcom,msm-id = <443 0x0>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab-qrd.dts b/arch/arm64/boot/dts/qcom/atoll-ab-qrd.dts new file mode 100644 index 000000000000..48952e8f4044 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab-qrd.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "atoll-ab.dtsi" +#include "atoll-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 QRD"; + compatible = "qcom,atoll-ab-qrd", "qcom,atoll-ab", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + +&tx_swr_gpios { + qcom,chip-wakeup-reg = <0x01FFB000>; + qcom,chip-wakeup-maskbit = <0>; + qcom,chip-wakeup-default-val = <0x1>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab.dts b/arch/arm64/boot/dts/qcom/atoll-ab.dts new file mode 100644 index 000000000000..f018f4fa60a9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "atoll-ab.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL-AB SoC"; + compatible = "qcom,atoll"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ab.dtsi b/arch/arm64/boot/dts/qcom/atoll-ab.dtsi new file mode 100644 index 000000000000..0ee4b4760cd6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-ab.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2019, The Linux Foundation.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "atoll.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL-AB"; + qcom,msm-name = "ATOLL-AB"; + qcom,msm-id = <443 0x0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll.dtsi b/arch/arm64/boot/dts/qcom/atoll.dtsi index e0be4eac56d7..5fb6158e364e 100644 --- a/arch/arm64/boot/dts/qcom/atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll.dtsi @@ -1539,6 +1539,10 @@ qcom,pas-id = <23>; qcom,firmware-name = "npu"; memory-region = <&pil_npu_mem>; + + /* Outputs to npu */ + qcom,smem-states = <&npu_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; }; qcom,turing@8300000 { diff --git a/arch/arm64/boot/dts/qcom/mdm9607-bus.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-bus.dtsi new file mode 100644 index 000000000000..50bb021e9fea --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-bus.dtsi @@ -0,0 +1,678 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/msm/msm-bus-ids.h> + +&soc { + /* Version = 1 */ + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x401000 0x58000>, + <0x500000 0x15080>; + reg-names = "bimc-base", "pcnoc-base"; + + /*Buses*/ + + fab_bimc: fab-bimc { + cell-id = <MSM_BUS_FAB_BIMC>; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <154>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_bimc_msmbus_clk>, + <&clock_gcc clk_bimc_msmbus_a_clk>; + + coresight-id = <203>; + coresight-name = "coresight-bimc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <3>; + }; + + fab_pcnoc: fab-pcnoc { + cell-id = <MSM_BUS_FAB_PERIPH_NOC>; + label = "fab-pcnoc"; + qcom,fab-dev; + qcom,base-name = "pcnoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_pcnoc_msmbus_clk>, + <&clock_gcc clk_pcnoc_msmbus_a_clk>; + + coresight-id = <201>; + coresight-name = "coresight-pcnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in2>; + coresight-child-ports = <0>; + }; + + /*Masters*/ + + mas_apps_proc: mas-apps-proc { + cell-id = <MSM_BUS_MASTER_AMPSS_M0>; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_bimc_pcnoc &slv_ebi>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>; + }; + + mas_pcnoc_bimc_1: mas-pcnoc-bimc-1 { + cell-id = <MSM_BUS_MASTER_PCNOC_BIMC_1>; + label = "mas-pcnoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_BIMC_1>; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = <MSM_BUS_MASTER_TCU_0>; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi>; + qcom,prio-lvl = <2>; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>; + }; + + mas_qdss_bam: mas-qdss-bam { + cell-id = <MSM_BUS_MASTER_QDSS_BAM>; + label = "mas-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&qdss_int>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>; + qcom,blacklist = <&pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0 + &pcnoc_s_4 &pcnoc_s_5 &pcnoc_s_3 &slv_tcu>; + }; + + mas_bimc_pcnoc: mas-bimc-pcnoc { + cell-id = <MSM_BUS_MASTER_BIMC_PCNOC>; + label = "mas-bimc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0 + &pcnoc_int_2 &slv_cats_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BIMC_PCNOC>; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = <MSM_BUS_MASTER_QDSS_ETR>; + label = "mas-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&qdss_int>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5 + &slv_crypto_0_cfg &slv_message_ram + &slv_pdm &slv_prng &slv_qdss_stm + &slv_tcu>; + }; + + mas_audio: mas-audio { + cell-id = <MSM_BUS_MASTER_AUDIO>; + label = "mas-audio"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_AUDIO>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 + &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu>; + }; + + mas_qpic: mas-qpic { + cell-id = <MSM_BUS_MASTER_QPIC>; + label = "mas-qpic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QPIC>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_4 + &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg &slv_pdm + &slv_prng &slv_usb2 >; + }; + + mas_hsic: mas-hsic { + cell-id = <MSM_BUS_MASTER_USB_HSIC>; + label = "mas-hsic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_USB_HSIC>; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = <MSM_BUS_MASTER_BLSP_1>; + label = "mas-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 + &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu >; + }; + + mas_usb_hs1: mas-usb-hs1 { + cell-id = <MSM_BUS_MASTER_USB_HS>; + label = "mas-usb-hs1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg + &slv_pdm &slv_prng &slv_usb2 + &slv_usb_phy> ; + }; + + mas_crypto: mas-crypto { + cell-id = <MSM_BUS_MASTER_CRYPTO>; + label = "mas-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_3>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg &slv_pdm + &slv_usb2 &slv_prng>; + }; + + mas_sdcc_1: mas-sdcc-1 { + cell-id = <MSM_BUS_MASTER_SDCC_1>; + label = "mas-sdcc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg &slv_pdm + &slv_usb2 &slv_prng>; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = <MSM_BUS_MASTER_SDCC_2>; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg &slv_pdm + &slv_usb2 &slv_prng>; + }; + + mas_xi_usb_hs1: mas-xi-usb-hs1 { + cell-id = <MSM_BUS_MASTER_XM_USB_HS1>; + label = "mas-xi-usb-hs1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_5 &slv_tcu &slv_crypto_0_cfg + &slv_pdm &slv_usb2 &slv_prng + &slv_usb_phy>; + }; + + mas_xi_hsic: mas-xi-hsic { + cell-id = <MSM_BUS_MASTER_XI_USB_HSIC>; + label = "mas-xi-hsic"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_XI_HSIC>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5 + &slv_tcu &slv_crypto_0_cfg + &slv_pdm &slv_usb2 &slv_prng>; + }; + + mas_sgmii: mas-sgmii { + cell-id = <MSM_BUS_MASTER_SGMII>; + label = "mas-sgmii"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <10>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SGMII>; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3 + &pcnoc_s_4 &pcnoc_s_5 &slv_tcu + &slv_crypto_0_cfg &slv_pdm + &slv_usb2 &slv_prng>; + }; + + /*Internal nodes*/ + + pcnoc_m_0: pcnoc-m-0 { + cell-id = <MSM_BUS_PNOC_M_0>; + label = "pcnoc-m-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>; + }; + + pcnoc_m_1: pcnoc-m-1 { + cell-id = <MSM_BUS_PNOC_M_1>; + label = "pcnoc-m-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>; + }; + + qdss_int: qdss-int { + cell-id = <MSM_BUS_SNOC_QDSS_INT>; + label = "qdss-int"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0 &slv_pcnoc_bimc_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>; + }; + + pcnoc_int_0: pcnoc-int-0 { + cell-id = <MSM_BUS_PNOC_INT_0>; + label = "pcnoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_imem &slv_qdss_stm>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>; + }; + + pcnoc_int_2: pcnoc-int-2 { + cell-id = <MSM_BUS_PNOC_INT_2>; + label = "pcnoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_s_1 &pcnoc_s_2 + &pcnoc_s_0 &pcnoc_s_4 + &pcnoc_s_5 &pcnoc_s_3 + &slv_tcu >; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>; + }; + + pcnoc_int_3: pcnoc-int-3 { + cell-id = <MSM_BUS_PNOC_INT_3>; + label = "pcnoc-int-3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>; + }; + + pcnoc_s_0: pcnoc-s-0 { + cell-id = <MSM_BUS_PNOC_SLV_0>; + label = "pcnoc-s-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tcsr &slv_sdcc_1 &slv_blsp_1 + &slv_sgmii>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>; + }; + + pcnoc_s_1: pcnoc-s-1 { + cell-id = <MSM_BUS_PNOC_SLV_1>; + label = "pcnoc-s-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_usb2 &slv_crypto_0_cfg + &slv_prng &slv_pdm + &slv_message_ram>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>; + }; + + pcnoc_s_2: pcnoc-s-2 { + cell-id = <MSM_BUS_PNOC_SLV_2>; + label = "pcnoc-s-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_hsic &slv_sdcc_2 &slv_audio>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>; + }; + + pcnoc_s_3: pcnoc-s-3 { + cell-id = <MSM_BUS_PNOC_SLV_3>; + label = "pcnoc-s-3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_usb_phy>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>; + }; + + pcnoc_s_4: pcnoc-s-4 { + cell-id = <MSM_BUS_PNOC_SLV_4>; + label = "pcnoc-s-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_imem_cfg &slv_pmic_arb>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>; + }; + + pcnoc_s_5: pcnoc-s-5 { + cell-id = <MSM_BUS_PNOC_SLV_5>; + label = "pcnoc-s-5"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tlmm>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>; + }; + + /*Slaves*/ + + slv_ebi:slv-ebi { + cell-id = <MSM_BUS_SLAVE_EBI_CH0>; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>; + }; + + slv_bimc_pcnoc:slv-bimc-pcnoc { + cell-id = <MSM_BUS_SLAVE_BIMC_PCNOC>; + label = "slv-bimc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_PCNOC>; + }; + + slv_pcnoc_bimc_1:slv-pcnoc-bimc-1 { + cell-id = <MSM_BUS_SLAVE_PCNOC_BIMC_1>; + label = "slv-pcnoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,connections = <&mas_pcnoc_bimc_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_BIMC_1>; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = <MSM_BUS_SLAVE_QDSS_STM>; + label = "slv-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>; + }; + + slv_cats_0:slv-cats-0 { + cell-id = <MSM_BUS_SLAVE_CATS_128>; + label = "slv-cats-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>; + }; + + slv_imem:slv-imem { + cell-id = <MSM_BUS_SLAVE_SYSTEM_IMEM>; + label = "slv-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>; + }; + + slv_tcsr:slv-tcsr { + cell-id = <MSM_BUS_SLAVE_TCSR>; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>; + }; + + slv_sdcc_1:slv-sdcc-1 { + cell-id = <MSM_BUS_SLAVE_SDCC_1>; + label = "slv-sdcc-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = <MSM_BUS_SLAVE_BLSP_1>; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>; + }; + + slv_sgmii:slv-sgmii { + cell-id = <MSM_BUS_SLAVE_SGMII>; + label = "slv-sgmii"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SGMII>; + }; + + slv_crypto_0_cfg:slv-crypto-0-cfg { + cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>; + label = "slv-crypto-0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>; + }; + + slv_message_ram:slv-message-ram { + cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>; + }; + + slv_pdm:slv-pdm { + cell-id = <MSM_BUS_SLAVE_PDM>; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PDM>; + }; + + slv_prng:slv-prng { + cell-id = <MSM_BUS_SLAVE_PRNG>; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>; + }; + + slv_usb2:slv-usb2 { + cell-id = <MSM_BUS_SLAVE_USB_HS>; + label = "slv-usb2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = <MSM_BUS_SLAVE_SDCC_2>; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>; + }; + + slv_audio:slv-audio { + cell-id = <MSM_BUS_SLAVE_AUDIO>; + label = "slv-audio"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_AUDIO>; + }; + + slv_hsic:slv-hsic { + cell-id = <MSM_BUS_SLAVE_USB_HSIC>; + label = "slv-hsic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_USB_HSIC>; + }; + + slv_usb_phy:slv-usb-phy { + cell-id = <MSM_BUS_SLAVE_USB_PHYS_CFG>; + label = "slv-usb-phy"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_USB_PHY_CFG>; + }; + + slv_tlmm:slv-tlmm { + cell-id = <MSM_BUS_SLAVE_TLMM>; + label = "slv-tlmm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>; + }; + + slv_imem_cfg:slv-imem-cfg { + cell-id = <MSM_BUS_SLAVE_IMEM_CFG>; + label = "slv-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = <MSM_BUS_SLAVE_PMIC_ARB>; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>; + }; + + slv_tcu:slv-tcu { + cell-id = <MSM_BUS_SLAVE_TCU>; + label = "slv-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCU>; + }; + + slv_qipc { + cell-id = <MSM_BUS_SLAVE_QPIC>; + label = "slv-qpic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_QPIC>; + + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-coresight.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-coresight.dtsi new file mode 100644 index 000000000000..3e79b110f1a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-coresight.dtsi @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@6026000 { + compatible = "arm,coresight-tmc"; + reg = <0x6026000 0x1000>, + <0x6084000 0x15000>; + reg-names = "tmc-base", "bam-base"; + interrupts = <0 166 0>; + interrupt-names = "byte-cntr-irq"; + + qcom,memory-size = <0x100000>; + qcom,sg-enable; + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + tpiu: tpiu@6020000 { + compatible = "arm,coresight-tpiu"; + reg = <0x6020000 0x1000>, + <0x1100000 0xb0000>; + reg-names = "tpiu-base", "nidnt-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + pinctrl-names = "sdcard", "trace", "swduart", + "swdtrc", "jtag", "spmi"; + /* NIDnT */ + pinctrl-0 = <&qdsd_clk_sdcard &qdsd_cmd_sdcard + &qdsd_data0_sdcard &qdsd_data1_sdcard + &qdsd_data2_sdcard &qdsd_data3_sdcard>; + pinctrl-1 = <&qdsd_clk_trace &qdsd_cmd_trace + &qdsd_data0_trace &qdsd_data1_trace + &qdsd_data2_trace &qdsd_data3_trace>; + pinctrl-2 = <&qdsd_cmd_swduart &qdsd_data0_swduart + &qdsd_data1_swduart &qdsd_data2_swduart + &qdsd_data3_swduart>; + pinctrl-3 = <&qdsd_clk_swdtrc &qdsd_cmd_swdtrc + &qdsd_data0_swdtrc &qdsd_data1_swdtrc + &qdsd_data2_swdtrc &qdsd_data3_swdtrc>; + pinctrl-4 = <&qdsd_cmd_jtag &qdsd_data0_jtag + &qdsd_data1_jtag &qdsd_data2_jtag + &qdsd_data3_jtag>; + pinctrl-5 = <&qdsd_clk_spmi &qdsd_cmd_spmi + &qdsd_data0_spmi &qdsd_data3_spmi>; + + qcom,nidnthw; + qcom,nidnt-swduart; + qcom,nidnt-swdtrc; + qcom,nidnt-jtag; + qcom,nidnt-spmi; + nidnt-gpio = <26>; + nidnt-gpio-polarity = <1>; + + interrupts = <0 82 0>; + interrupt-names = "nidnt-irq"; + + vdd-supply = <&sdcard_ext_vreg>; + qcom,vdd-voltage-level = <2850000 2850000>; + qcom,vdd-current-level = <15 400000>; + + vdd-io-supply = <&mdm9607_l13>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 300000>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + replicator: replicator@6024000 { + compatible = "qcom,coresight-replicator"; + reg = <0x6024000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + tmc_etf: tmc@6025000 { + compatible = "arm,coresight-tmc"; + reg = <0x6025000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_in0: funnel@6021000 { + compatible = "arm,coresight-funnel"; + reg = <0x6021000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_in2: funnel@6068000 { + compatible = "arm,coresight-funnel"; + reg = <0x6068000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in2"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <6>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <6>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <7>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <8>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <9>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <10>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <11>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <12>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <13>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <14>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu0: cti@6043000 { + compatible = "arm,coresight-cti"; + reg = <0x6043000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + coresight-cti-cpu = <&CPU0>; + + qcom,cti-save; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_rpm_cpu0: cti@603c000 { + compatible = "arm,coresight-cti"; + reg = <0x603c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti-rpm-cpu0"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_modem_cpu0: cti@6038000 { + compatible = "arm,coresight-cti"; + reg = <0x6038000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti-modem-cpu0"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + stm: stm@6002000 { + compatible = "arm,coresight-stm"; + reg = <0x6002000 0x1000>, + <0x9280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <18>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <7>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <19>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + etm0: etm@6042000 { + compatible = "arm,coresight-etm"; + reg = <0x6042000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <20>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + coresight-etm-cpu = <&CPU0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + hwevent: hwevent@606c000 { + compatible = "qcom,coresight-hwevent"; + reg = <0x606c000 0x148>, + <0x606cfb0 0x4>, + <0x78640cc 0x4>, + <0x78240cc 0x4>, + <0x7885010 0x4>, + <0x200c004 0x4>, + <0x78d90a0 0x4>; + reg-names = "wrapper-mux", "wrapper-lockaccess", + "wrapper-sdcc2", "wrapper-sdcc1", + "blsp-mux", "spmi-mux" ,"usb-mux"; + + coresight-id = <21>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-id = <22>; + coresight-name = "coresight-rpm-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <0>; + + qcom,inst-id = <4>; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-id = <23>; + coresight-name = "coresight-modem-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <2>; + + qcom,inst-id = <2>; + }; + + fuse: fuse@a601c { + compatible = "arm,coresight-fuse-v2"; + reg = <0xa601c 0x8>; + reg-names = "fuse-base"; + + coresight-id = <24>; + coresight-name = "coresight-fuse"; + coresight-nr-inports = <0>; + }; + + dbgui: dbgui@606d000 { + compatible = "qcom,coresight-dbgui"; + reg = <0x606d000 0x1000>; + reg-names = "dbgui-base"; + + coresight-id = <25>; + coresight-name = "coresight-dbgui"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in2>; + coresight-child-ports = <1>; + + qcom,dbgui-addr-offset = <0x30>; + qcom,dbgui-data-offset = <0xB0>; + qcom,dbgui-size = <32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-display.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-display.dtsi new file mode 100644 index 000000000000..588aa29dbbdc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-display.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + mdss_qpic: qcom,msm_qpic@7980000 { + compatible = "qcom,mdss_qpic"; + reg = <0x7980000 0x24000>; + reg-names = "qpic_base"; + interrupts = <0 251 0>; + + qcom,msm-bus,name = "mdss_qpic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 800000>; + + vdd-supply = <&mdm9607_l11>; + + clock-names = "core_clk", "core_a_clk"; + clocks = <&clock_gcc clk_qpic_clk>, + <&clock_gcc clk_qpic_a_clk>; + + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-ion.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-ion.dtsi new file mode 100644 index 000000000000..ff375d07bfc4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-ion.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015,2017, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + reg = <28>; + memory-region = <&audio_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-mtp.dts b/arch/arm64/boot/dts/qcom/mdm9607-mtp.dts new file mode 100644 index 000000000000..10482d33c9ff --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-mtp.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "mdm9607-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MDM 9607 MTP"; + compatible = "qcom,mdm9607-mtp", "qcom,mdm9607", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-mtp.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-mtp.dtsi new file mode 100644 index 000000000000..fe6101021130 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-mtp.dtsi @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mdm9607.dtsi" +#include "mdm9607-pinctrl.dtsi" +#include "mdm9607-display.dtsi" +#include "qpic-panel-ili-hvga.dtsi" + +/ { + bluetooth: bt_qca6174 { + compatible = "qca,qca6174"; + qca,bt-reset-gpio = <&pm8019_gpios 2 0>; /* BT_EN */ + qca,bt-vdd-pa-supply = <&rome_vreg>; + qca,bt-vdd-io-supply = <&mdm9607_l11>; + qca,bt-vdd-xtal-supply = <&mdm9607_l2>; + qca,bt-vdd-io-voltage-level = <1800000 1800000>; + qca,bt-vdd-xtal-voltage-level = <1800000 1800000>; + }; +}; + +&soc { +}; + +&blsp1_uart5 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_sleep>; +}; + +&i2c_4 { + status = "ok"; +}; + +&spi_1 { + status = "ok"; + + can-controller@0 { + compatible = "fsl,k61"; + spi-max-frequency = <4800000>; + reg = <0>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <25 0>; + reset-gpio = <&tlmm_pinmux 11 0x1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&can_rst_on>; + pinctrl-1 = <&can_rst_off>; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; + +&qnand_1 { + status = "ok"; +}; + +&emac0 { + status = "ok"; +}; + +&pm8019_mpps { + /* MPP 2 configs for SMB358 interrupt line */ + smb_stat { + smb_stat_default: smb_stat_default { + pins = "mpp2"; + function = "digital"; + input-enable; + }; + }; + + mpp@a300 { /* MPP 4 */ + pins = "mpp4"; + function = "digital"; + output-high; + }; +}; + +&pm8019_gpios { + /* PMIC GPIO 1 for wlan power supply */ + wlan_en { + wlan_en_default_wlan_en_default { + pins = "gpio1"; + function = "normal"; + output-high; + bias-pull-up; + qcom,drive-strength = <1>; + power-source = <1>; + }; + }; + + bt_en { + bt_en_default: bt_en_default { /* BT_EN GPIO 2*/ + pins = "gpio2"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <1>; + }; + }; + + gpio@c300 { /* GPIO 4 */ + pins = "gpio4"; + function = "normal"; + output-high; + bias-pull-up; + qcom,drive-strength = <1>; + power-source = <1>; + }; + + /* ROME 32k GPIO 6 Sleep Clock */ + gpio@c500 { + pins = "gpio6"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <1>; + }; +}; + +&sdhc_1 { + vdd-io-supply = <&mdm9607_l11>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 30000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&pmx_sdc1_clk_on &pmx_sdc1_cmd_on &pmx_sdc1_data_on + &sdc1_wlan_gpio_active>; + pinctrl-1 = <&pmx_sdc1_clk_off &pmx_sdc1_cmd_off &pmx_sdc1_data_off + &sdc1_wlan_gpio_sleep>; + qcom,nonremovable; + qcom,core_3_0v_support; + status = "ok"; +}; + +&i2c_4 { + /* SMB358 charger configuration */ + smb358_otg_vreg: smb358-charger@57 { + compatible = "qcom,smb358-charger"; + regulator-name = "smb358_otg_vreg"; + reg = <0x57>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xa1 0 IRQ_TYPE_NONE>; /* PMIC MPP 2 */ + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + qcom,float-voltage-mv = <4200>; + qcom,irq-gpio = <&pm8019_mpps 2 0>; + qcom,chg-vadc = <&pm8019_vadc>; + qcom,batt-id-vref-uv = <1800000>; + qcom,batt-id-rpullup-kohm = <220>; + }; +}; + +&sdhc_2 { + vdd-supply = <&sdcard_ext_vreg>; + qcom,vdd-voltage-level = <2850000 2850000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&mdm9607_l13>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <200 50000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm_pinmux 26 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm_pinmux 26 0x1>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + status = "disabled"; +}; + +/* Display */ +&mdss_qpic { + pinctrl-names= "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_ldo_active &mdss_cs_active &mdss_te_active + &mdss_rs_active &mdss_ad_active &mdss_bl_active>; + pinctrl-1 = <&mdss_ldo_sleep &mdss_cs_sleep &mdss_te_sleep + &mdss_rs_sleep &mdss_ad_sleep &mdss_bl_sleep>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-pinctrl.dtsi new file mode 100644 index 000000000000..a3d0fdcade7d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-pinctrl.dtsi @@ -0,0 +1,1108 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm_pinmux: pinctrl@1000000 { + compatible = "qcom,mdm9607-pinctrl"; + reg = <0x1000000 0x300000>; + reg-names = "pinctrl"; + interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&wakegpio>; + #interrupt-cells = <2>; + qcom,tlmm-emmc-boot-select = <0x1>; + + uart_console_sleep: uart_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart5"; + }; + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart5_active: blsp1_uart5_active { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart5_sleep: blsp1_uart5_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi1 { + + spi1_default: spi1_default { + /* active state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", "gpio7"; + drive-strength = <12>; /* 12 MA */ + bias-disable = <0>; /* No PULL */ + }; + }; + + + spi1_sleep: spi1_sleep { + /* suspended state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio4", "gpio5", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + + spi1_cs0_active: cs0_active { + /* CS */ + mux { + pins = "gpio6"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + spi1_cs0_sleep: cs0_sleep { + /* CS */ + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + /* SDC pin type */ + + pmx_sdc1_cmd { + pmx_sdc1_cmd_on: pmx_sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + pmx_sdc1_cmd_off: pmx_sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc1_clk { + pmx_sdc1_clk_on: pmx_sdc1_clk_on { + config { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + }; + + pmx_sdc1_clk_off: pmx_sdc1_clk_off { + config { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_sdc1_data { + pmx_sdc1_data_on: pmx_sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + pmx_sdc1_data_off: pmx_sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + sdc1_wlan_gpio { + sdc1_wlan_gpio_active: sdc1_wlan_gpio_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + config { + pins = "gpio38"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc1_wlan_gpio_sleep: sdc1_wlan_gpio_sleep { + mux { + pins = "gpio38"; + function = "gpio"; + }; + config { + pins = "gpio38"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + /* active state */ + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + /* suspended state */ + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + bmi160_int1_default: bmi160_int1_default { + mux { + pins = "gpio78"; + function = "gpio"; + }; + config { + pins = "gpio78"; + drive-strength = <16>; /* 16 mA */ + bias-pull-down; /* pull down */ + }; + }; + + bmi160_int2_default: bmi160_int2_default { + mux { + pins = "gpio79"; + function = "gpio"; + }; + config { + pins = "gpio79"; + drive-strength = <16>; /* 16 mA */ + bias-pull-down; /* pull down */ + }; + }; + + codec_reset { + codec_reset_active: codec_reset_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + codec_reset_sleep: codec_reset_sleep { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + + pmx_pri_mi2s { + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio20"; + function = "pri_mi2s_ws_a"; + }; + config { + pins = "gpio20"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio23"; + function = "pri_mi2s_sck_a"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + pri_mi2s_dout_active: pri_mi2s_dout_active { + mux { + pins = "gpio22"; + function = "pri_mi2s_data1_a"; + }; + config { + pins = "gpio22"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio20"; + function = "pri_mi2s_ws_a"; + }; + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio23"; + function = "pri_mi2s_sck_a"; + }; + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + pri_mi2s_dout_sleep: pri_mi2s_dout_sleep { + mux { + pins = "gpio22"; + function = "pri_mi2s_data1_a"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_pri_mi2s_din { + pri_mi2s_din_active: pri_mi2s_din_active { + mux { + pins = "gpio21"; + function = "pri_mi2s_data0_a"; + }; + config { + pins = "gpio21"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + }; + }; + + pri_mi2s_din_sleep: pri_mi2s_din_sleep { + mux { + pins = "gpio21"; + function = "pri_mi2s_data0_a"; + }; + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sec_mi2s { + sec_mi2s_ws_active: sec_mi2s_ws_active { + mux { + pins = "gpio79"; + function = "sec_mi2s"; + }; + config { + pins = "gpio79"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + sec_mi2s_sck_active: sec_mi2s_sck_active { + mux { + pins = "gpio78"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + sec_mi2s_dout_active: sec_mi2s_dout_active { + mux { + pins = "gpio77"; + function = "sec_mi2s"; + }; + config { + pins = "gpio77"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { + mux { + pins = "gpio79"; + function = "sec_mi2s"; + }; + config { + pins = "gpio79"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { + mux { + pins = "gpio78"; + function = "sec_mi2s"; + }; + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sec_mi2s_dout_sleep: sec_mi2s_dout_sleep { + mux { + pins = "gpio77"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sec_mi2s_din { + sec_mi2s_din_active: sec_mi2s_din_active { + mux { + pins = "gpio76"; + function = "sec_mi2s"; + }; + config { + pins = "gpio76"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + }; + }; + + sec_mi2s_din_sleep: sec_mi2s_din_sleep { + mux { + pins = "gpio76"; + function = "sec_mi2s"; + }; + config { + pins = "gpio76"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_qdsd_clk { + qdsd_clk_sdcard: clk_sdcard { + config { + pins = "qdsd_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + qdsd_clk_trace: clk_trace { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_clk_swdtrc: clk_swdtrc { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_clk_spmi: clk_spmi { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_cmd { + qdsd_cmd_sdcard: cmd_sdcard { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_cmd_trace: cmd_trace { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_cmd_swduart: cmd_uart { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_cmd_swdtrc: cmd_swdtrc { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_cmd_jtag: cmd_jtag { + config { + pins = "qdsd_cmd"; + bias-disable; /* NO pull */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_cmd_spmi: cmd_spmi { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <10>; /* 10 MA */ + }; + }; + }; + + pmx_qdsd_data0 { + qdsd_data0_sdcard: data0_sdcard { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data0_trace: data0_trace { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data0_swduart: data0_uart { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data0_swdtrc: data0_swdtrc { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data0_jtag: data0_jtag { + config { + pins = "qdsd_data0"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data0_spmi: data0_spmi { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data1 { + qdsd_data1_sdcard: data1_sdcard { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data1_trace: data1_trace { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data1_swduart: data1_uart { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data1_swdtrc: data1_swdtrc { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data1_jtag: data1_jtag { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data2 { + qdsd_data2_sdcard: data2_sdcard { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data2_trace: data2_trace { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data2_swduart: data2_uart { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data2_swdtrc: data2_swdtrc { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data2_jtag: data2_jtag { + config { + pins = "qdsd_data2"; + bias-pull-up; /* pull up */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_qdsd_data3 { + qdsd_data3_sdcard: data3_sdcard { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data3_trace: data3_trace { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + qdsd_data3_swduart: data3_uart { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data3_swdtrc: data3_swdtrc { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data3_jtag: data3_jtag { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + qdsd_data3_spmi: data3_spmi { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_sdc2_clk { + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + drive-strength = <16>; /* 16 MA */ + bias-disable; /* NO pull */ + }; + }; + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_cmd { + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_data { + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + sdhc2_cd_pin { + sdc2_cd_on: cd_on { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sdc2_cd_off: cd_off { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + emac0 { + emac0_mdio_active: emac0_mdio_active { + /* active state */ + mux { + /* MDC MDIO */ + pins = "gpio27", "gpio28"; + function = "gmac_mdio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <16>; /* 16 MA */ + bias-pull-up; + }; + }; + + emac0_mdio_sleep: emac0_mdio_sleep { + /* suspended state */ + mux { + /* MDC MDIO */ + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + emac0_ephy_active: emac0_ephy_active { + /* active state */ + mux { + /* EPHY RST */ + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <16>; /* 16 MA */ + bias-pull-up; + output-high; + }; + }; + + emac0_ephy_sleep: emac0_ephy_sleep { + /* suspended state */ + mux { + /* EPHY RST */ + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + output-low; + }; + }; + }; + + mdss_cs_active: mdss_cs_active { + mux { + pins = "gpio23"; + function = "ebi2_lcd_cs_n_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_cs_sleep:mdss_cs_sleep { + mux { + pins = "gpio23"; + function = "ebi2_lcd_cs_n_b"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_te_active:mdss_te_active { + mux { + pins = "gpio20"; + function = "ebi2_lcd_te_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_te_sleep:mdss_te_sleep { + mux { + pins = "gpio20"; + function = "ebi2_lcd_te_b"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_rs_active:mdss_rs_active { + mux { + pins = "gpio74"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio74"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_rs_sleep:mdss_rs_sleep { + mux { + pins = "gpio74"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio74"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_ad_active:mdss_ad_active { + mux { + pins = "gpio22"; + function = "ebi2_a_d_8_b"; + }; + + config { + pins = "gpio22"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_ad_sleep:mdss_ad_sleep { + mux { + pins = "gpio22"; + function = "ebi2_a_d_8_b"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_bl_active:mdss_bl_active { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + output-high; + }; + }; + + mdss_bl_sleep:mdss_bl_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + }; + }; + + mdss_ldo_active:mdss_ldo_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <10>;/*10mA*/ + bias-disable;/*NOpull*/ + output-high; + }; + }; + + mdss_ldo_sleep:mdss_ldo_sleep { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>;/*2mA*/ + bias-disable;/*NOpull*/ + output-low; + }; + }; + pinctrl_pps: ppsgrp { + mux { + pins = "gpio53"; + function = "nav_tsync_out_a"; + }; + + config { + pins = "gpio53"; + bias-pull-down; + }; + }; + + can_reset { + can_rst_on: rst_on { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + can_rst_off: rst_off { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + output-high; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-pm.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-pm.dtsi new file mode 100644 index 000000000000..d5e91875090b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-pm.dtsi @@ -0,0 +1,153 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/msm/pm.h> + +&soc { + qcom,spm@b009000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb009000 0x1000>; + qcom,name = "cpu0"; + qcom,cpu = <&CPU0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x1>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0xe>; + qcom,mode0 { + qcom,label = "qcom,saw2-spm-cmd-wfi"; + qcom,sequence = [04 03 04 0f]; + qcom,spm_en; + }; + qcom,mode1 { + qcom,label = "qcom,saw2-spm-cmd-spc"; + qcom,sequence = [1f 34 04 44 24 54 03 + 54 44 04 24 34 0f]; + qcom,spm_en; + qcom,pc_mode; + }; + qcom,mode2 { + qcom,label = "qcom,saw2-spm-cmd-pc"; + qcom,sequence = [1f 34 04 44 14 24 54 03 + 54 44 14 04 04 24 04 34 0f]; + qcom,spm_en; + qcom,pc_mode; + qcom,slp_cmd_mode; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0{ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "system"; + qcom,default-level=<0>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "l2-active"; + qcom,latency-us = <270>; + qcom,ss-power = <455>; + qcom,energy-overhead = <270621>; + qcom,time-overhead = <500>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "l2-pc"; + qcom,latency-us = <285>; + qcom,ss-power = <442>; + qcom,energy-overhead = <306621>; + qcom,time-overhead = <540>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cpu-level@0{ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,latency-us = <1>; + qcom,ss-power = <473>; + qcom,energy-overhead = <100000>; + qcom,time-overhead = <25>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + qcom,spm-cpu-mode ="standalone_pc"; + qcom,latency-us = <240>; + qcom,ss-power = <467>; + qcom,energy-overhead = <202781>; + qcom,time-overhead = <420>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cpu-level@2 { + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,latency-us = <270>; + qcom,ss-power = <455>; + qcom,energy-overhead = <270621>; + qcom,time-overhead = <500>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + }; + }; + }; + + qcom,pm@8600664 { + compatible = "qcom,pm"; + reg = <0x8600664 0x40>; + clocks = <&clock_cpu clk_a7ssmux>; + clock-names = "cpu0_clk"; + qcom,use-sync-timer; + qcom,synced-clocks; + qcom,tz-flushes-cache; + }; + + qcom,cpu-sleep-status@b088008{ + compatible = "qcom,cpu-sleep-status"; + reg = <0xb088008 0x100>; + qcom,cpu-alias-addr = <0x10000>; + qcom,sleep-status-mask= <0x80000>; + }; + + qcom,rpm-stats@29dba0 { + compatible = "qcom,rpm-stats"; + reg = <0x29dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-master-stats@60150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x60150 0x2030>; + qcom,masters = "APSS", "MPSS", "PRONTO"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-regulator.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-regulator.dtsi new file mode 100644 index 000000000000..7ffaecf74cc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-regulator.dtsi @@ -0,0 +1,413 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_requests { + rpm-regulator-smpa2 { + status = "okay"; + mdm9607_s2: regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s2"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + qcom,init-voltage = <750000>; + status = "okay"; + }; + }; + + /* CX supply */ + rpm-regulator-smpa3 { + status = "okay"; + mdm9607_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + mdm9607_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + mdm9607_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + mdm9607_s3_level_so: regulator-s3-level-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s3_level_so"; + qcom,set = <2>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + mdm9607_s4: regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_s4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + mdm9607_l1: regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l1"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1250000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + mdm9607_l2: regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + mdm9607_l3: regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + mdm9607_l4: regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l4"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + mdm9607_l5: regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + mdm9607_l6: regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l6"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + mdm9607_l7: regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + mdm9607_l8: regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + mdm9607_l9: regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l9"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + mdm9607_l10: regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l10"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + mdm9607_l11: regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + /* MX supply */ + rpm-regulator-ldoa12 { + status = "okay"; + mdm9607_l12_level: regulator-l12-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l12_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + mdm9607_l12_level_ao: regulator-l12-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l12_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + qcom,always-send-voltage; + }; + + mdm9607_l12_level_so: regulator-l12-level-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l12_level_so"; + qcom,set = <2>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + mdm9607_l12_floor_level: regulator-l12-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l12_floor_lebel"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + mdm9607_l13: regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + mdm9607_l14: regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "mdm9607_l14"; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2650000>; + status = "okay"; + }; + }; +}; + +&spmi_bus { + qcom,pm8019@1 { + /* APC supply */ + mdm9607_s1: spm-regulator@1400 { + compatible = "qcom,spm-regulator"; + reg = <0x1400 0x100>; + regulator-name = "mdm9607_s1"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + qcom,bypass-spm; /* TODO: Remove once SPM is up */ + }; + }; +}; + +&soc { + mem_acc_vreg_corner: regulator@1942130 { + compatible = "qcom,mem-acc-regulator"; + reg = <0x1942130 0x4>; + reg-names = "acc-sel-l1"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-sel-l1-bit-pos = <0>; + qcom,corner-acc-map = <0 1 1>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb010058 4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 20 0>; + regulator-name = "apc_corner"; + qcom,cpr-fuse-corners = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + + qcom,cpr-voltage-ceiling = <1050000 1225000 1350000>; + qcom,cpr-voltage-floor = <1050000 1050000 1150000>; + vdd-apc-supply = <&mdm9607_s1>; + + vdd-mx-supply = <&mdm9607_l12_level_ao>; + qcom,vdd-mx-vmin-method = <4>; + qcom,vdd-mx-corner-map = < RPM_SMD_REGULATOR_LEVEL_SVS + RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,vdd-mx-vmax = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <22 0 24 0 0 0 0 0>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <3>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <12500>; + + qcom,cpr-fuse-row = <65 0>; + qcom,cpr-fuse-target-quot = <24 12 0>; + qcom,cpr-fuse-ro-sel = <42 39 36>; + qcom,cpr-fuse-bp-cpr-disable = <54>; + qcom,cpr-fuse-init-voltage = + <66 6 6 0>, + <66 0 6 0>, + <65 45 6 0>; + qcom,cpr-fuse-revision = <65 51 3 0>; + qcom,cpr-init-voltage-ref = <1050000 1225000 1350000>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3 3 3>; + qcom,cpr-init-voltage-as-ceiling; + qcom,cpr-corner-frequency-map = + <1 400000000>, + <2 800000000>, + <3 998400000>, + <4 1094400000>, + <5 1190400000>, + <6 1248000000>, + <7 1305600000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 0 1 2 7>; + qcom,cpr-quot-adjust-scaling-factor-max = <1400>; + qcom,disable-closed-loop-in-pc; + qcom,cpr-cpus = <&CPU0>; + qcom,cpr-enable; + }; + +/* Miscellaneous regulators */ + sdcard_ext_vreg: sdcard_ext_vreg { + compatible = "regulator-fixed"; + regulator-name = "sdcard_ext_vreg"; + startup-delay-us = <250>; + enable-active-high; + gpio = <&pm8019_gpios 4 0>; + }; + + /* Rome 3.3V supply */ + rome_vreg: rome_vreg { + compatible = "regulator-fixed"; + regulator-name = "rome_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8019_gpios 3 0>; + }; + + emac_lan_vreg: emac_lan_vreg { + compatible = "regulator-fixed"; + regulator-name = "emac_lan_vreg"; + startup-delay-us = <250>; + enable-active-high; + gpio = <&pm8019_mpps 4 0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607-smp2p.dtsi b/arch/arm64/boot/dts/qcom/mdm9607-smp2p.dtsi new file mode 100644 index 000000000000..a0ba40d3064d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607-smp2p.dtsi @@ -0,0 +1,104 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0x0b011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <&smp2pgpio_smp2p_15_in 0 0>; + }; + + smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <&smp2pgpio_smp2p_15_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/mdm9607.dtsi b/arch/arm64/boot/dts/qcom/mdm9607.dtsi new file mode 100644 index 000000000000..cf454b9bcb22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mdm9607.dtsi @@ -0,0 +1,1888 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/mdm-clocks-9607.h> +#include <dt-bindings/clock/msm-clocks-a7.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +/ { + model = "Qualcomm Technologies, Inc. MDM 9607"; + compatible = "qcom,mdm9607"; + qcom,msm-id = <290 0x10000>, <296 0x10000>, <297 0x10000>, + <298 0x10000>, <299 0x10000>; + interrupt-parent = <&wakegic>; + + aliases { + sdhc1 = &sdhc_1;/* SDC1 for SDIO slot */ + qpic_nand1 = &qnand_1; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + modem_adsp_mem: modem_adsp_region@0 { + compatible = "removed-dma-pool"; + no-map-fixup; + reg = <0x82a00000 0x5000000>; + }; + + cnss_debug_mem: cnss_debug_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x87a00000 0x200000>; + }; + + external_image_mem: external_image_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x87c00000 0x400000>; + }; + + audio_mem: audio_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0x400000>; + size = <0x400000>; + }; + + qseecom_mem: qseecom_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0x400000>; + size = <0x0400000>; + status = "disabled"; + }; + }; + + aliases { + /* smdtty devices */ + smd7 = &smdtty_data1; + smd8 = &smdtty_data4; + smd9 = &smdtty_data2; + smd10 = &smdtty_data3; + smd11 = &smdtty_data11; + smd21 = &smdtty_data21; + smd36 = &smdtty_loopback; + /* spi device */ + spi1 = &spi_1; + i2c4 = &i2c_4; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + qcom,limits-info = <&mitigation_profile0>; + }; + }; + soc: soc { }; +}; + +#include "mdm9607-ion.dtsi" +#include "mdm9607-bus.dtsi" +#include "mdm9607-coresight.dtsi" +#include "mdm9607-pm.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-mdm9607", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 171 + IRQ_TYPE_EDGE_RISING>; + reg = <0x601d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xb011008 0x4>; + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <64>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio-mdm9607", "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xb021000 0x1000>, + <0xb022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xb023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xb024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xb025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xb026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xb027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xb028000 0x1000>; + status = "disabled"; + }; + + frame@b029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xb029000 0x1000>; + status = "disabled"; + }; + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,wakeup-enable; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x10000>; /* 64K EBI1 buffer */ + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + jtag_fuse: jtagfuse@a601c { + compatible = "qcom,jtag-fuse-v2"; + reg = <0xa601c 0x8>; + reg-names = "fuse-base"; + }; + + jtag_mm: jtagmm@6042000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x6042000 0x1000>, + <0x6040000 0x1000>; + reg-names = "etm-base", "debug-base"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + clock_gcc: qcom,gcc@1800000 { + compatible = "qcom,gcc-mdm9607"; + reg = <0x1800000 0x80000>, + <0x0b008000 0x00050>; + reg-names = "cc_base", "apcs_base"; + vdd_dig-supply = <&mdm9607_s3_level>; + vdd_stromer_dig-supply = <&mdm9607_s3_level_ao>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apcs: syscon@0b011008 { + compatible = "syscon"; + reg = <0x0b011008 0x04>; + }; + + clock_debug: qcom,debug@1874000 { + compatible = "qcom,cc-debug-mdm9607"; + reg = <0x1800000 0x80000>, + <0xb01101c 0x8>; + reg-names = "cc_base", "meas"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,clock-a7@0b010008 { + compatible = "qcom,clock-a7-mdm9607"; + reg = <0x0b010008 0x8>, + <0x000a412c 0x8>; + reg-names = "rcg-base", "efuse"; + qcom,safe-freq = < 400000000 >; + cpu-vdd-supply = <&apc_vreg_corner>; + clocks = <&clock_gcc clk_gpll0_ao_clk_src>, + <&clock_gcc clk_a7sspll>; + clock-names = "clk-1", "clk-5"; + qcom,speed4-bin-v0 = + < 0 0>, + < 400000000 1>, + < 800000000 2>, + < 998400000 3>, + < 1094400000 4>, + < 1190400000 5>, + < 1248000000 6>, + < 1305600000 7>; + qcom,a7ssmux-opp-store-vcorner = <&CPU0>; + #clock-cells = <1>; + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 366 /* 48 MHz */>, + < 732 /* 96 MHz */>, + < 915 /* 120 MHz */>, + < 1145 /* 150.15 MHz */>, + < 1831 /* 240 MHz */>, + < 2291 /* 300.3 MHZ */>; + }; + + devfreq-cpufreq { + cpubw-cpufreq { + target-dev = <&cpubw>; + cpu-to-dev-map = + < 400000 732>, + < 800000 915>, + < 998400 1145>, + < 1094400 1831>, + < 1305600 2291>; + }; + }; + + qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon2"; + reg = <0x408000 0x300>, <0x401000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + qcom,msm-cpufreq { + reg = <0 4>; + compatible = "qcom,msm-cpufreq"; + clocks = <&clock_cpu clk_a7ssmux>; + clock-names = "cpu0_clk"; + qcom,cpufreq-table = + < 400000 >, + < 800000 >, + < 998400 >, + < 1094400 >, + < 1190400 >, + < 1248000 >, + < 1305600 >; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + blsp1_uart5: serial@78b3000 { /* BLSP1 UART5 */ + compatible = "qcom,msm-uartdm-v1.4","qcom,msm-uartdm"; + reg = <0x78b3000 0x200>; + interrupts = <0 121 0>; + clocks = <&clock_gcc clk_gcc_blsp1_uart5_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x2b000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <10>; + }; + + i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 0>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 18 64 0x20000020 0x20>, + <&dma_blsp1 19 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + + wcd9xxx_tomtom_codec@0d{ + compatible = "qcom,wcd9xxx-i2c"; + reg = <0x0d>; + + qcom,cdc-reset-gpio = <&tlmm_pinmux 26 0>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&codec_reset_active>; + pinctrl-1 = <&codec_reset_sleep>; + + qcom,cdc-micbias1-ext-cap; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28>; + cdc-vdd-buck-supply = <&mdm9607_s4>; + qcom,cdc-vdd-buck-voltage = <1950000 1950000>; + qcom,cdc-vdd-buck-current = <25000>; + + cdc-vdd-tx-h-supply = <&mdm9607_l11>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&mdm9607_l11>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&mdm9607_l11>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-a-1p2v-supply = <&mdm9607_l9>; + qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>; + qcom,cdc-vdd-a-1p2v-current = <10000>; + + cdc-vddcx-1-supply = <&mdm9607_l9>; + qcom,cdc-vddcx-1-voltage = <1225000 1225000>; + qcom,cdc-vddcx-1-current = <10000>; + + cdc-vddcx-2-supply = <&mdm9607_l9>; + qcom,cdc-vddcx-2-voltage = <1225000 1225000>; + qcom,cdc-vddcx-2-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-a-1p2v", + "cdc-vddcx-1", + "cdc-vddcx-2"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + qcom,cdc-micbias4-cfilt-sel = <0x2>; + qcom,cdc-mclk-clk-rate = <12288000>; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-variant = "WCD9330"; + }; + + wcd9xxx_tapan_codec@0d{ + compatible = "qcom,wcd9xxx-i2c"; + reg = <0x0d>; + + status = "disabled"; + qcom,cdc-reset-gpio = <&tlmm_pinmux 26 0>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&codec_reset_active>; + pinctrl-1 = <&codec_reset_sleep>; + + qcom,cdc-micbias1-ext-cap; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6>, <7 8 9 10 11 12 13>, + <14 15 16 17 18 19 20>, + <21 22 23 24 25 26 27 28>; + cdc-vdd-buck-supply = <&mdm9607_s4>; + qcom,cdc-vdd-buck-voltage = <1950000 1950000>; + qcom,cdc-vdd-buck-current = <25000>; + + cdc-vdd-tx-h-supply = <&mdm9607_l11>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&mdm9607_l11>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&mdm9607_l11>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-cx-supply = <&mdm9607_l9>; + qcom,cdc-vdd-cx-voltage = <1225000 1225000>; + qcom,cdc-vdd-cx-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-cx"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + qcom,cdc-micbias4-cfilt-sel = <0x2>; + qcom,cdc-mclk-clk-rate = <12288000>; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-variant = "WCD9306"; + }; + + wcd9xxx_codec@77{ + compatible = "qcom,wcd9xxx-i2c"; + reg = <0x77>; + }; + + wcd9xxx_codec@66{ + compatible = "qcom,wcd9xxx-i2c"; + reg = <0x66>; + }; + + wcd9xxx_codec@55{ + compatible = "qcom,wcd9xxx-i2c"; + reg = <0x55>; + }; + + bmi160@68{ + compatible = "bosch,bmi160"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&bmi160_int1_default &bmi160_int2_default>; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <78 0x2002>; + bmi,init-interval = <200>; + bmi,place = <1>; + bmi,gpio_irq = <&tlmm_pinmux 78 0x2002>; + }; + }; + + blsp1_uart3: uart@78b1000 { + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78b1000 0x200>, + <0x7884000 0x2b000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 119 0 + 1 &intc 0 238 0 + 2 &tlmm_pinmux 1 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_sleep>; + pinctrl-1 = <&blsp1_uart3_active>; + qcom,msm-bus,name = "blsp1_uart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart5_hs: uart@78b3000 { /* BLSP1 UART5 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78b3000 0x200>, + <0x7884000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart5_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 121 0 + 1 &intc 0 238 0 + 2 &tlmm_pinmux 9 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <8>; + qcom,bam-rx-ep-pipe-index = <9>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart5_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart5_sleep>; + pinctrl-1 = <&blsp1_uart5_active>; + + qcom,msm-bus,name = "buart5"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + cnss_sdio: qcom,cnss-sdio { + compatible = "qcom,cnss_sdio"; + reg = <0x87a00000 0x200000>; + reg-names = "ramdump"; + subsys-name = "AR6320"; + vdd-wlan-supply = <&rome_vreg>; + vdd-wlan-dsrc-supply = <&sdcard_ext_vreg>; + vdd-wlan-io-supply = <&mdm9607_l11>; + vdd-wlan-xtal-supply = <&mdm9607_l2>; + }; + + usb_otg: usb@78d9000 { + compatible = "qcom,hsusb-otg"; + reg = <0x78d9000 0x400>, <0x6c000 0x200>; + reg-names = "core", "phy_csr"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + + hsusb_vdd_dig-supply = <&mdm9607_l9>; + HSUSB_1p8-supply = <&mdm9607_l2>; + HSUSB_3p3-supply = <&mdm9607_l4>; + qcom,vdd-voltage-level = <0 1225000 1225000>; + + qcom,hsusb-otg-phy-init-seq = + <0x44 0x80 0x38 0x81 0x24 0x82 0x13 0x83 0xffffffff>; + + qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ + qcom,hsusb-otg-mode = <3>; /* OTG mode */ + qcom,hsusb-otg-otg-control = <2>; /* PMIC control */ + qcom,usbid-gpio = <&pm8019_mpps 1 0>; + qcom,hsusb-log2-itc = <4>; + qcom,dp-manual-pullup; + qcom,boost-sysclk-with-streaming; + qcom,phy-dvdd-always-on; + qcom,hsusb-otg-lpm-on-dev-suspend; + qcom,axi-prefetch-enable; + qcom,hsusb-otg-mpm-dpsehv-int = <49>; + qcom,hsusb-otg-mpm-dmsehv-int = <58>; + qcom,hsusb-otg-delay-lpm; + qcom,enable-phy-id-pullup; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 80000 0>, + <87 512 6000 6000>; + clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>, + <&clock_gcc clk_gcc_usb_hs_system_clk>, + <&clock_gcc clk_gcc_usb2a_phy_sleep_clk>, + <&clock_gcc clk_bimc_usb_a_clk>, + <&clock_gcc clk_pcnoc_usb_a_clk>, + <&clock_gcc clk_gcc_qusb2_phy_clk>, + <&clock_gcc clk_gcc_usb2_hs_phy_only_clk>, + <&clock_gcc clk_gcc_usb_hs_phy_cfg_ahb_clk>, + <&clock_gcc clk_xo_otg_clk>; + clock-names = "iface_clk", "core_clk", "sleep_clk", + "bimc_clk", "pcnoc_clk", "phy_reset_clk", + "phy_por_clk", "phy_csr_clk", "xo"; + qcom,bus-clk-rate = <240000000 0 100000000 + 120000000 0 50000000>; + qcom,max-nominal-sysclk-rate = <133330000>; + qcom,max-svs-sysclk-rate = <69500000>; + qcom,default-mode-svs; + resets = <&clock_gcc GCC_USB_HS_BCR>, + <&clock_gcc GCC_QUSB2_PHY_BCR>, + <&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "core_reset", "phy_reset", "phy_por_reset"; + + qcom,usbbam@78c4000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x78c4000 0x15000>; + interrupt-parent = <&intc>; + interrupts = <0 135 0>; + qcom,bam-type = <1>; + qcom,usb-bam-num-pipes = <2>; + qcom,usb-bam-fifo-baseaddr = <0x08603800>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,reset-bam-on-disconnect; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6084000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x600>; + qcom,descriptor-fifo-offset = <0x600>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + }; + + hsic: hsic@7c00000 { + compatible = "qcom,hsic-peripheral"; + reg = <0x7c00000 0x352>, + <0x1100000 0x1200c>; + interrupts = <0 141 0>, <0 142 0>; + qcom,hsic-usb-core-id = <1>; + vdd-supply = <&mdm9607_l9>; + qcom,vdd-voltage-level = <0 1225000 1225000>; + qcom,hsic-tlmm-init-seq = + <0x12008 0x5 0x12004 0x5 0x12000 0x1>; + qcom,hsic-disable-on-boot; + + clocks = <&clock_gcc clk_gcc_usb_hsic_ahb_clk>, + <&clock_gcc clk_gcc_usb_hsic_system_clk>, + <&clock_gcc clk_gcc_usb_hsic_clk>, + <&clock_gcc clk_gcc_usb_hsic_io_cal_clk>, + <&clock_gcc clk_gcc_usb_hsic_io_cal_sleep_clk>; + clock-names = "iface_clk", "core_clk", "phy_clk", + "cal_clk", "cal_sleep_clk"; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 6000 6000>; + resets = <&clock_gcc GCC_USB_HS_HSIC_BCR>; + reset-names = "core_reset"; + status = "disabled"; + }; + + hsic_host: hsic_host@7c00000 { + compatible = "qcom,hsic-host"; + reg = <0x7c00000 0x352>, + <0x1100000 0x1200c>; + interrupts = <0 141 0>, <0 142 0>; + interrupt-names = "core_irq", "async_irq"; + hsic_vdd_dig-supply = <&mdm9607_l9>; + hsic,vdd-voltage-level = <0 1225000 1225000>; + qcom,hsic-tlmm-init-seq = + <0x12008 0x5 0x12004 0x5 0x12000 0x1>; + qcom,phy-susp-sof-workaround; + qcom,disable-internal-clk-gating; + + clocks = <&clock_gcc clk_gcc_usb_hsic_ahb_clk>, + <&clock_gcc clk_gcc_usb_hsic_system_clk>, + <&clock_gcc clk_gcc_usb_hsic_clk>, + <&clock_gcc clk_gcc_usb_hsic_io_cal_clk>, + <&clock_gcc clk_gcc_usb_hsic_io_cal_sleep_clk>; + clock-names = "iface_clk", "core_clk", "phy_clk", + "cal_clk", "inactivity_clk"; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 60000 800000>; + status = "disabled"; + }; + + qnand_1: nand@7980000 { + compatible = "qcom,msm-nand"; + reg = <0x07980000 0x1000>, + <0x07984000 0x1a000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 132 0>; + interrupt-names = "bam_irq"; + + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 400000>; + + clock-names = "core_clk"; + clocks = <&clock_gcc clk_qpic_clk>; + status = "disabled"; + }; + + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm"; + reg = <0x7824900 0x200>, <0x7824000 0x800>, <0x01111000 0x4>; + reg-names = "hc_mem", "core_mem", "tlmm_mem"; + + qcom,cpu-dma-latency-us = <701>; + qcom,bus-width = <4>; + gpios = <&tlmm_pinmux 16 0>, /* CLK */ + <&tlmm_pinmux 17 0>, /* CMD */ + <&tlmm_pinmux 15 0>, /* DATA0 */ + <&tlmm_pinmux 14 0>, /* DATA1 */ + <&tlmm_pinmux 13 0>, /* DATA2 */ + <&tlmm_pinmux 12 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, + <&clock_gcc clk_gcc_sdcc1_apps_clk>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 800000 800000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 + 50000000 100000000 200000000 4294967295>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_1>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 123 0 + 1 &intc 0 138 0 + 2 &tlmm_pinmux 59 0x4>; + interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq"; + + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", + "DDR50","SDR104"; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <2 250>; + + status = "disabled"; + }; + + tsens: tsens@4a8000 { + compatible = "qcom,mdm9607-tsens"; + reg = <0x4a8000 0x2000>, + <0xa4000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + interrupt-names = "tsens-upper-lower"; + qcom,sensors = <5>; + qcom,slope = <3000 3000 3000 3000 3000>; + qcom,sensor-id = <0 1 2 3 4>; + qcom,temp1-offset = <1 (-4) 4 (-3) (-4)>; + qcom,temp2-offset = <1 (-2) 8 (-5) (-4)>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm_pinmux>; + qcom,gpio-connect = <&tlmm_pinmux 75 0>; + interrupt-names = "cdc-int"; + }; + + sound-9330 { + compatible = "qcom,mdm9607-audio-tomtom"; + qcom,model = "mdm9607-tomtom-i2s-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC6", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3"; + + qcom,codec-mclk-clk-freq = <12288000>; + qcom,mi2s-interface-mode = "pri_mi2s_master", "sec_mi2s_master"; + qcom,auxpcm-interface-mode = "pri_pcm_master", "sec_pcm_master"; + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&mi2s_prim>, <&mi2s_sec>, <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + }; + + sound-9306 { + compatible = "qcom,mdm9607-audio-tapan"; + qcom,model = "mdm9607-tapan-i2s-snd-card"; + status = "disabled"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4"; + + qcom,codec-mclk-clk-freq = <12288000>; + qcom,mi2s-interface-mode = "pri_mi2s_master", "sec_mi2s_master"; + qcom,auxpcm-interface-mode = "pri_pcm_master", "sec_pcm_master"; + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&mi2s_prim>, <&mi2s_sec>, <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,scm-mp-enabled; + memory-region = <&audio_mem>; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 2.8"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&pri_mi2s_ws_active + &pri_mi2s_sck_active + &pri_mi2s_dout_active + &pri_mi2s_din_active>; + pinctrl-1 = <&pri_mi2s_ws_sleep + &pri_mi2s_sck_sleep + &pri_mi2s_dout_sleep + &pri_mi2s_din_sleep>; + }; + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <4>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-mitigation-temp = <105>; + qcom,freq-mitigation-temp-hysteresis = <15>; + qcom,freq-mitigation-value = <800000>; + qcom,disable-cx-phase-ctrl; + qcom,disable-gfx-phase-ctrl; + qcom,disable-psm; + qcom,disable-ocr; + qcom,mx-restriction-temp = <10>; + qcom,mx-restriction-temp-hysteresis = <5>; + qcom,mx-retention-min = + <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS>; + vdd-mx-supply = <&mdm9607_l12_floor_level>; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + vdd-dig-supply = <&mdm9607_s3_floor_level>; + qcom,therm-ddr-lm-info = <2 78 70>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + }; + + msm_thermal_freq: qcom,vdd-apps-rstr { + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <998400>; + qcom,freq-req; + }; + }; + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + }; + + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + }; + + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + }; + + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + }; + + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + }; + + sensor_information5: qcom,sensor-information-5 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm0"; + }; + + sensor_information6: qcom,sensor-information-6 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm1"; + }; + + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "xo_therm"; + }; + + sensor_information8: qcom,sensor-information-8 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "xo_therm_amux"; + }; + }; + + mitigation_profile0: qcom,limit_info-0 { + qcom,temperature-sensor = <&sensor_information4>; + qcom,boot-frequency-mitigate; + qcom,emergency-frequency-mitigate; + }; + + qcom,ipc-spinlock@1905000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1905000 0x8000>; + qcom,num-locks = <8>; + }; + + sfpb_mutex_block: syscon@190500 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + sfpb_mutex: hwlock { + compatible = "qcom,sfpb-mutex"; + syscon = <&sfpb_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + smem_mem: smem_region@87d00000 { + reg = <0x87d00000 0x100000>; + no-map; + }; + + qcom,smem@87d00000 { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&sfpb_mutex 3>; + }; + + qcom,smd { + compatible = "qcom,smd"; + + modem { + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 0 12>; + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + }; + + rpm { + qcom,smd-edge = <15>; + qcom,ipc = <&apcs 0 0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + label = "rpm"; + + rpm_requests: rpm_requests@0 { + compatible = "qcom,rpm-smd"; + qcom,smd-channels = "rpm_requests"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + }; + }; + + }; + + qcom,smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 0 13>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0x0b011008 0x4>; + qcom,smem = <435>, <428>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + qcom,ipc = <&apcs 0 14>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + #address-cells = <1>; + #size-cells = <0>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + reg = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_data1: qcom,smdtty-data1 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA1"; + }; + + smdtty_data2: qcom,smdtty-data2 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA2"; + }; + + smdtty_data3: qcom,smdtty-data3 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA3"; + }; + + smdtty_data4: qcom,smdtty-data4 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA4"; + }; + + smdtty_data11: qcom,smdtty-data11 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA11"; + }; + + smdtty_data21: qcom,smdtty-data21 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA21"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; + + qcom,smdpkt { + compatible = "qcom,smdpkt"; + + qcom,smdpkt-data5-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-dev-name = "smdcntl0"; + }; + + qcom,smdpkt-data22 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA22"; + qcom,smdpkt-dev-name = "smd22"; + }; + + qcom,smdpkt-data40-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA40_CNTL"; + qcom,smdpkt-dev-name = "smdcntl8"; + }; + + qcom,smdpkt-apr-apps2 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "apr_apps2"; + qcom,smdpkt-dev-name = "apr_apps2"; + }; + + qcom,smdpkt-loopback { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "LOOPBACK"; + qcom,smdpkt-dev-name = "smd_pkt_loopback"; + }; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_smd_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "modem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + qcom,disable-pil-loading; + }; + + apps_modem { + #address-cells = <1>; + #size-cells = <0>; + + apps_modem: apps@1 { + reg = <1>; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,bam_dmux@4044000 { + compatible = "qcom,bam_dmux"; + reg = <0x4044000 0x19000>; + interrupts = <0 29 1>; + qcom,rx-ring-size = <32>; + qcom,max-rx-mtu = <4096>; + qcom,fast-shutdown; + + qcom,smem-states = <&apps_modem 0>, <&apps_modem 32>; + qcom,smem-state-names = "pwrctrl", "pwrctrlack"; + }; + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0xa00>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <0 190 0>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + spi_1: spi@78b6000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b6000 0x600>, + <0x7884000 0x2b000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 0>, <0 238 0>; + spi-max-frequency = <19200000>; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi1_default &spi1_cs0_active>; + pinctrl-1 = <&spi1_sleep &spi1_cs0_sleep>; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + clock-names = "iface_clk", "core_clk"; + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + status = "disabled"; + }; + + qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x04080000 0x100>, + <0x0194f000 0x010>, + <0x01950000 0x008>, + <0x01951000 0x008>, + <0x04020000 0x040>, + <0x0183e000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", + "rmb_base", "restart_reg"; + + interrupts = <0 24 1>; + vdd_cx-supply = <&mdm9607_s3_level>; + vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_mx-supply = <&mdm9607_l12_level>; + vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_pll-supply = <&mdm9607_l3>; + qcom,vdd_pll = <1800000>; + + clocks = <&clock_gcc clk_xo_pil_mss_clk>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>; + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; + + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,override-acc-1 = <0x80800000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v56-1-8-inrush-current; + + memory-region = <&modem_adsp_mem>; + }; + + sdhc_2: sdhci@07864900 { + compatible = "qcom,sdhci-msm"; + reg = <0x07864900 0x200>, <0x07864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 800000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc2_apps_clk>; + clock-names = "iface_clk", "core_clk"; + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <2 250>; + + status = "disabled"; + }; + + qrng: rng@0x22000 { + compatible = "qcom,msm-rng"; + reg = <0x22000 0x140>; + qcom,msm-rng-iface-clk; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, + <1 618 0 800>; + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; + clock-names = "iface_clk"; + }; + + qcom_crypto: qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 393600 800000>; + clocks = <&clock_gcc clk_crypto_clk_src>, + <&clock_gcc clk_gcc_crypto_clk>, + <&clock_gcc clk_gcc_crypto_ahb_clk>, + <&clock_gcc clk_gcc_crypto_axi_clk>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <100000000>; + }; + + qcom_qcedev: qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 3936000 393600>; + clocks = <&clock_gcc clk_crypto_clk_src>, + <&clock_gcc clk_gcc_crypto_clk>, + <&clock_gcc clk_gcc_crypto_ahb_clk>, + <&clock_gcc clk_gcc_crypto_axi_clk>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom_seecom: qseecom@87a80000 { + compatible = "qcom,qseecom"; + reg = <0x87a80000 0x100000>; + reg-names = "secapp-region"; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <47 512 0 0>, + <47 512 0 0>, + <47 512 120000 1200000>, + <47 512 393600 3936000>; + clocks = <&clock_gcc clk_crypto_clk_src>, + <&clock_gcc clk_gcc_crypto_clk>, + <&clock_gcc clk_gcc_crypto_ahb_clk>, + <&clock_gcc clk_gcc_crypto_axi_clk>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + status = "disabled"; + }; + + qcom_tzlog: tz-log@8600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + status = "disabled"; + }; + + emac0: qcom,emac@7c40000 { + compatible = "qcom,mdm9607-emac"; + reg-names = "emac", "emac_csr", "emac_1588"; + reg = <0x7c40000 0x10000>, + <0x7c56000 0x1000>, + <0x7c5c000 0x4000>; + + #address-cells = <0>; + interrupt-parent = <&emac0>; + #interrupt-cells = <1>; + interrupts = <0 1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 76 0 + 1 &tlmm_pinmux 30 0x8>; + interrupt-names = "emac_core0_irq", "emac_wol_irq"; + + emac_vreg1-supply = <&mdm9607_l1>; + emac_vreg2-supply = <&mdm9607_l3>; + emac_vreg3-supply = <&mdm9607_l5>; + emac_vreg4-supply = <&mdm9607_l11>; + emac_vreg5-supply = <&emac_lan_vreg>; + qcom,vdd-voltage-level = <1250000 1800000 2850000 1800000 0>; + clocks = <&clock_gcc clk_gcc_emac_0_axi_clk>, + <&clock_gcc clk_gcc_emac_0_ahb_clk>, + <&clock_gcc clk_gcc_emac_0_125m_clk>, + <&clock_gcc clk_gcc_emac_0_sys_25m_clk>, + <&clock_gcc clk_gcc_emac_0_tx_clk>, + <&clock_gcc clk_gcc_emac_0_rx_clk>, + <&clock_gcc clk_gcc_emac_0_sys_clk>; + clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", + "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; + + internal-phy = <&emac_sgmii>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + + pinctrl-names = "emac_mdio_active", "emac_mdio_sleep", + "emac_ephy_active", "emac_ephy_sleep"; + pinctrl-0 = <&emac0_mdio_active>; + pinctrl-1 = <&emac0_mdio_sleep>; + pinctrl-2 = <&emac0_ephy_active>; + pinctrl-3 = <&emac0_ephy_sleep>; + qcom,emac-tstamp-en; + qcom,emac-ptp-frac-ns-adj = <125000000 1>; + status = "disable"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + emac_sgmii: ethernet@7c58000 { + compatible = "qcom,mdm9607-emac-sgmii"; + reg-names = "emac_sgmii"; + reg = <0x7c58000 0x400>; + interrupt-names = "emac_sgmii_irq"; + interrupts = <0 80 0>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&tlmm_pinmux 53 0>; + status = "okay"; + }; +}; + +#include "pm8019-rpm-regulator.dtsi" +#include "pm8019.dtsi" +#include "mdm9607-regulator.dtsi" + +/* MPP pin 1 config for USB ID interrupt line */ +&pm8019_mpps { + mpp@a000 { + pins = "mpp1"; + function = "digital"; + input-enable; + }; +}; + +&usb_otg { + vbus_otg-supply = <&smb358_otg_vreg>; +}; + +&pm8019_vadc { + vbat_sns { + label = "vbat_sns"; + reg = <VADC_VBAT_SNS>; + qcom,pre-scaling = <1 3>; + }; + + vph_pwr { + label = "vph_pwr"; + reg = <VADC_VSYS>; + qcom,pre-scaling = <1 3>; + }; + + batt_id_therm { + label = "batt_id_therm"; + reg = <VADC_LR_MUX2_BAT_ID>; + qcom,ratiometric; + qcom,pre-scaling = <1 1>; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + label = "pa_therm1"; + reg = <VADC_LR_MUX4_AMUX_THM1>; + qcom,ratiometric; + qcom,pre-scaling = <1 1>; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + label = "pa_therm2"; + reg = <VADC_LR_MUX5_AMUX_THM2>; + qqcom,ratiometric; + qcom,pre-scaling = <1 1>; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + label = "xo_therm"; + reg = <VADC_LR_MUX3_XO_THERM>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + xo_therm_amux { + label = "xo_therm_amux"; + reg = <VADC_LR_MUX3_BUF_XO_THERM>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/pm8019-rpm-regulator.dtsi b/arch/arm64/boot/dts/qcom/pm8019-rpm-regulator.dtsi new file mode 100644 index 000000000000..e1c630848c43 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8019-rpm-regulator.dtsi @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_requests { + rpm-regulator-smpa1 { + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "mdm9607_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-smpa2 { + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "mdm9607_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-smpa3 { + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "mdm9607_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-smpa4 { + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-s4 { + regulator-name = "mdm9607_s4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa1 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l1 { + regulator-name = "mdm9607_l1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa2 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l2 { + regulator-name = "mdm9607_l2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l3 { + regulator-name = "mdm9607_l3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa4 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l4 { + regulator-name = "mdm9607_l4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa5 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l5 { + regulator-name = "mdm9607_l5"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa6 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l6 { + regulator-name = "mdm9607_l6"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa7 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l7 { + regulator-name = "mdm9607_l7"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa8 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l8 { + regulator-name = "mdm9607_l8"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa9 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l9 { + regulator-name = "mdm9607_l9"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa10 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l10 { + regulator-name = "mdm9607_l10"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa11 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l11 { + regulator-name = "mdm9607_l11"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa12 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l12 { + regulator-name = "mdm9607_l12"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa13 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l13 { + regulator-name = "mdm9607_l13"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; + + rpm-regulator-ldoa14 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-smd-regulator-resource"; + status = "disabled"; + + regulator-l14 { + regulator-name = "mdm9607_l14"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-smd-regulator"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8019.dtsi b/arch/arm64/boot/dts/qcom/pm8019.dtsi new file mode 100644 index 000000000000..fc18e446fd72 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8019.dtsi @@ -0,0 +1,163 @@ +/* Copyright (c) 2012-2013,2015,2019, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +&spmi_bus { + qcom,pm8019@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8019_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power_on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x2 IRQ_TYPE_NONE>; + interrupt-names = "cblpwr"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <2>; + qcom,pull-up; + linux,code = <116>; + }; + }; + + + rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8019_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8019_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8019_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x600>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8019_gpio1", "pm8019_gpio2", + "pm8019_gpio3", "pm8019_gpio4", + "pm8019_gpio5", "pm8019_gpio6"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm8019_mpps: pinctrl@a000 { + compatible = "qcom,spmi-mpp"; + reg = <0xa000 0x600>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>, + <0 0xa4 0 IRQ_TYPE_NONE>, + <0 0xa5 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8019_mpp1", "pm8019_mpp2", + "pm8019_mpp3", "pm8019_mpp4", + "pm8019_mpp5", "pm8019_mpp6"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm8019_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + die_temp { + label = "die_temp"; + reg = <VADC_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + }; + + ref_625mv { + label = "ref_625mv"; + reg = <VADC_REF_625MV>; + qcom,pre-scaling = <1 1>; + }; + + ref_1250v { + label = "ref_1250v"; + reg = <VADC_REF_1250MV>; + qqcom,pre-scaling = <1 1>; + }; + + ref_gnd { + label = "ref_gnd"; + reg = <VADC_GND_REF>; + qcom,pre-scaling = <1 1>; + }; + + ref_vdd { + label = "ref_vdd"; + reg = <VADC_VDD_VADC>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8019_adc_tm: vadc@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8019_vadc VADC_LR_MUX4_AMUX_THM1>, + <&pm8019_vadc VADC_LR_MUX5_AMUX_THM2>; + + pa_therm1 { + reg = <VADC_LR_MUX4_AMUX_THM1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = <VADC_LR_MUX5_AMUX_THM2>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + }; + }; + + qcom,pm8019@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi index 60af72f7ee2d..749301f6c5f5 100644 --- a/arch/arm64/boot/dts/qcom/qcs405.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405.dtsi @@ -63,19 +63,19 @@ reg = <0x0 0x86400000 0x0 0x1000000>; }; - adsp_fw_mem: adsp_fw_mem@87500000 { + adsp_fw_mem: adsp_fw_mem@87400000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x87400000 0x0 0x1400000>; }; - cdsp_fw_mem: cdsp_fw_mem@88f00000 { + cdsp_fw_mem: cdsp_fw_mem@88800000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x88800000 0x0 0x600000>; }; - wlan_msa_mem: wlan_msa_region@89500000 { + wlan_msa_mem: wlan_msa_region@88E00000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x88E00000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dts b/arch/arm64/boot/dts/qcom/sa8195-vm.dts index 18c12d196a0f..cf5a4c5663da 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dts +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dts @@ -29,6 +29,10 @@ status = "ok"; }; +&qupv3_se13_4uart { + status = "ok"; +}; + &usb0 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi index 7616cb35eb17..651825069474 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi @@ -284,6 +284,29 @@ status = "disabled"; }; + + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + VDD_CX_LEVEL: S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level { compatible = "qcom,stub-regulator"; @@ -291,6 +314,18 @@ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>; regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>; }; + qcom_seecom: qseecom@87a00000 { + compatible = "qcom,qseecom"; + reg = <0x87a00000 0x2100000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; sdhc_2: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; @@ -387,6 +422,31 @@ offset = <512>; }; }; + + bluetooth: bt_qca6174 { + compatible = "qca,qca6174"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qca,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qca,bt-vdd-pa-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qca,bt-chip-pwd-supply = <&vreg_conn_1p8>; + + qca,bt-vdd-vl-supply = <&pm8195_1_s5>; + qca,bt-vdd-vm-supply = <&pm8195_1_s2>; + qca,bt-vdd-vh-supply = <&pm8195_2_l7>; + + qca,bt-vdd-vl-voltage-level = <1000000 1000000>; + qca,bt-vdd-vm-voltage-level = <1370000 1370000>; + qca,bt-vdd-vh-voltage-level = <1900000 1900000>; + + qca,bt-vdd-vl-current-level = <0>; + qca,bt-vdd-vm-current-level = <0>; + qca,bt-vdd-vh-current-level = <450000>; + status = "ok"; + }; }; #include "sdmshrike-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi index 2a33ad562530..0747d6afe733 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi @@ -11,6 +11,7 @@ */ #include "sdxprairie.dtsi" +#include "sdxprairie-cpe-memory-map.dtsi" #include "sdxprairie-cdp.dtsi" &qnand_1 { diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-cdp-v1.1-cpe.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-cdp-v1.1-cpe.dtsi index f4f6843b16e4..0a8de3e8d411 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-cdp-v1.1-cpe.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-cdp-v1.1-cpe.dtsi @@ -11,6 +11,7 @@ */ #include "sdxprairie.dtsi" +#include "sdxprairie-cpe-memory-map.dtsi" #include "sdxprairie-cdp.dtsi" &qnand_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi index 8368791a5fa8..135a69cae0e6 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi @@ -479,7 +479,7 @@ }; mhi_event@6 { - mhi,num-elements = <1024>; + mhi,num-elements = <2048>; mhi,intmod = <5>; mhi,msi = <6>; mhi,chan = <101>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi index 40a4ab37f02a..204e59ac6832 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -528,6 +528,8 @@ compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "mx.lvl"; + pm8150l_s4_mmcx_sup_level-parent-supply = + <&VDD_CX_MMCX_SUPPLY_LEVEL>; VDD_MX_LEVEL: S4C_LEVEL: pm8150l_s4_level: regulator-pm8150l-s4-level { @@ -553,6 +555,17 @@ = <RPMH_REGULATOR_LEVEL_RETENTION>; }; + VDD_MX_MMCX_SUPPLY_LEVEL: regulator-pm8150l-s4-mmcx-sup-level { + regulator-name = "pm8150l_s4_mmcx_sup_level"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + mx_cdev: mx-cdev-lvl { compatible = "qcom,regulator-cooling-device"; regulator-cdev-supply = <&VDD_MX_LEVEL>; @@ -567,6 +580,8 @@ compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "mmcx.lvl"; + pm8150l_s5_level-parent-supply = <&VDD_MX_MMCX_SUPPLY_LEVEL>; + proxy-supply = <&VDD_MMCX_LEVEL>; VDD_MMCX_LEVEL: S5C_LEVEL: pm8150l_s5_level: regulator-pm8150l-s5-level { @@ -578,6 +593,11 @@ = <RPMH_REGULATOR_LEVEL_MAX>; qcom,init-voltage-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage + = <RPMH_REGULATOR_LEVEL_TURBO + RPMH_REGULATOR_LEVEL_MAX>; }; VDD_MMCX_LEVEL_AO: S5C_LEVEL_AO: @@ -619,6 +639,7 @@ qcom,resource-name = "cx.lvl"; pm8150l_s6_level-parent-supply = <&VDD_MX_LEVEL>; pm8150l_s6_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + proxy-supply = <&VDD_CX_MMCX_SUPPLY_LEVEL>; VDD_CX_LEVEL: S6C_LEVEL: pm8150l_s6_level: regulator-pm8150l-s6-level { @@ -646,6 +667,21 @@ qcom,min-dropout-voltage-level = <(-1)>; }; + VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm8150l-s6-mmcx-sup-level { + regulator-name = "pm8150l_s6_mmcx_sup_level"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_MIN_SVS>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_MIN_SVS>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage + = <RPMH_REGULATOR_LEVEL_TURBO + RPMH_REGULATOR_LEVEL_MAX>; + }; + cx_cdev: regulator-cdev { compatible = "qcom,rpmh-reg-cdev"; mboxes = <&qmp_aop 0>; diff --git a/drivers/bus/mhi/controllers/mhi_arch_qcom.c b/drivers/bus/mhi/controllers/mhi_arch_qcom.c index 63f36ed39e33..b914bcb2747d 100644 --- a/drivers/bus/mhi/controllers/mhi_arch_qcom.c +++ b/drivers/bus/mhi/controllers/mhi_arch_qcom.c @@ -328,11 +328,8 @@ static int mhi_arch_pcie_scale_bw(struct mhi_controller *mhi_cntrl, { int ret; - mhi_cntrl->lpm_disable(mhi_cntrl, mhi_cntrl->priv_data); ret = msm_pcie_set_link_bandwidth(pci_dev, link_info->target_link_speed, link_info->target_link_width); - mhi_cntrl->lpm_enable(mhi_cntrl, mhi_cntrl->priv_data); - if (ret) return ret; diff --git a/drivers/bus/mhi/controllers/mhi_qcom.c b/drivers/bus/mhi/controllers/mhi_qcom.c index 4ed779ab81df..e97e8fc5ab45 100644 --- a/drivers/bus/mhi/controllers/mhi_qcom.c +++ b/drivers/bus/mhi/controllers/mhi_qcom.c @@ -33,6 +33,7 @@ struct firmware_info { }; static const struct firmware_info firmware_table[] = { + {.dev_id = 0x307, .fw_image = "sdx60m/sbl1.mbn"}, {.dev_id = 0x306, .fw_image = "sdx55m/sbl1.mbn"}, {.dev_id = 0x305, .fw_image = "sdx50m/sbl1.mbn"}, {.dev_id = 0x304, .fw_image = "sbl.mbn", .edl_image = "edl.mbn"}, @@ -856,6 +857,7 @@ static struct pci_device_id mhi_pcie_device_id[] = { {PCI_DEVICE(MHI_PCIE_VENDOR_ID, 0x0304)}, {PCI_DEVICE(MHI_PCIE_VENDOR_ID, 0x0305)}, {PCI_DEVICE(MHI_PCIE_VENDOR_ID, 0x0306)}, + {PCI_DEVICE(MHI_PCIE_VENDOR_ID, 0x0307)}, {PCI_DEVICE(MHI_PCIE_VENDOR_ID, MHI_PCIE_DEBUG_ID)}, {0}, }; diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index 2fd7ddb08673..19630b5487f0 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -366,6 +366,8 @@ enum mhi_cmd_type { #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) +#define MHI_RSC_MIN_CREDITS (8) + enum MHI_CMD { MHI_CMD_RESET_CHAN, MHI_CMD_START_CHAN, diff --git a/drivers/bus/mhi/core/mhi_main.c b/drivers/bus/mhi/core/mhi_main.c index 91e87f07989b..bb2e402786e2 100644 --- a/drivers/bus/mhi/core/mhi_main.c +++ b/drivers/bus/mhi/core/mhi_main.c @@ -448,6 +448,8 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, struct mhi_ring *buf_ring = &mhi_chan->buf_ring; struct mhi_buf_info *buf_info; struct mhi_tre *mhi_tre; + bool ring_db = true; + int nr_tre; if (mhi_is_ring_full(mhi_cntrl, tre_ring)) return -ENOMEM; @@ -489,6 +491,15 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, mhi_tre->dword[0] = MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; + /* + * on RSC channel IPA HW has a minimum credit requirement before + * switching to DB mode + */ + nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); + read_lock_bh(&mhi_chan->lock); + if (mhi_chan->db_cfg.db_mode && nr_tre < MHI_RSC_MIN_CREDITS) + ring_db = false; + read_unlock_bh(&mhi_chan->lock); } else { mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); @@ -506,7 +517,7 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); - if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { + if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && ring_db) { read_lock_bh(&mhi_chan->lock); mhi_ring_chan_db(mhi_cntrl, mhi_chan); read_unlock_bh(&mhi_chan->lock); @@ -902,6 +913,8 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, u32 ev_code; struct mhi_result result; unsigned long flags = 0; + bool ring_db = true; + int nr_tre; ev_code = MHI_TRE_GET_EV_CODE(event); buf_ring = &mhi_chan->buf_ring; @@ -996,9 +1009,21 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); mhi_chan->db_cfg.db_mode = 1; + + /* + * on RSC channel IPA HW has a minimum credit requirement before + * switching to DB mode + */ + if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) { + nr_tre = mhi_get_no_free_descriptors(mhi_chan->mhi_dev, + DMA_FROM_DEVICE); + if (nr_tre < MHI_RSC_MIN_CREDITS) + ring_db = false; + } + read_lock_irqsave(&mhi_cntrl->pm_lock, flags); if (tre_ring->wp != tre_ring->rp && - MHI_DB_ACCESS_VALID(mhi_cntrl)) { + MHI_DB_ACCESS_VALID(mhi_cntrl) && ring_db) { mhi_ring_chan_db(mhi_cntrl, mhi_chan); } read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); @@ -1392,29 +1417,28 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, struct mhi_link_info link_info, *cur_info = &mhi_cntrl->mhi_link_info; int result, ret = 0; - mutex_lock(&mhi_cntrl->pm_mutex); - if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) { MHI_LOG("No EV access, PM_STATE:%s\n", to_mhi_pm_state_str(mhi_cntrl->pm_state)); ret = -EIO; - goto exit_bw_process; + goto exit_no_lock; } - /* - * BW change is not process during suspend since we're suspending link, - * host will process it during resume - */ - if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state)) { - ret = -EACCES; - goto exit_bw_process; - } + ret = __mhi_device_get_sync(mhi_cntrl); + if (ret) + goto exit_no_lock; + + mutex_lock(&mhi_cntrl->pm_mutex); spin_lock_bh(&mhi_event->lock); dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); if (ev_ring->rp == dev_rp) { spin_unlock_bh(&mhi_event->lock); + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + MHI_VERB("no pending event found\n"); goto exit_bw_process; } @@ -1459,13 +1483,16 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0, MHI_BW_SCALE_RESULT(result, link_info.sequence_num)); + + mhi_cntrl->wake_put(mhi_cntrl, false); read_unlock_bh(&mhi_cntrl->pm_lock); exit_bw_process: - MHI_VERB("exit er_index:%u\n", mhi_event->er_index); - mutex_unlock(&mhi_cntrl->pm_mutex); +exit_no_lock: + MHI_VERB("exit er_index:%u\n", mhi_event->er_index); + return ret; } @@ -1625,7 +1652,8 @@ irqreturn_t mhi_intvec_handlr(int irq_number, void *dev) wake_up_all(&mhi_cntrl->state_event); MHI_VERB("Exit\n"); - schedule_work(&mhi_cntrl->low_priority_worker); + if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) + schedule_work(&mhi_cntrl->low_priority_worker); return IRQ_WAKE_THREAD; } diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index 0b1c161a6448..263f702d2f98 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -154,9 +154,6 @@ enum MHI_PM_STATE __must_check mhi_tryset_pm_state( MHI_VERB("Transition to pm state from:%s to:%s\n", to_mhi_pm_state_str(cur_state), to_mhi_pm_state_str(state)); - if (MHI_REG_ACCESS_VALID(cur_state) && MHI_REG_ACCESS_VALID(state)) - mhi_timesync_log(mhi_cntrl); - mhi_cntrl->pm_state = state; return mhi_cntrl->pm_state; } @@ -451,22 +448,24 @@ int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl) static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) { int i, ret; + enum mhi_ee ee = 0; struct mhi_event *mhi_event; MHI_LOG("Processing Mission Mode Transition\n"); write_lock_irq(&mhi_cntrl->pm_lock); if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) - mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + ee = mhi_get_exec_env(mhi_cntrl); write_unlock_irq(&mhi_cntrl->pm_lock); - if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee)) + if (!MHI_IN_MISSION_MODE(ee)) return -EIO; - wake_up_all(&mhi_cntrl->state_event); - mhi_cntrl->status_cb(mhi_cntrl, mhi_cntrl->priv_data, MHI_CB_EE_MISSION_MODE); + mhi_cntrl->ee = ee; + + wake_up_all(&mhi_cntrl->state_event); /* force MHI to be in M0 state before continuing */ ret = __mhi_device_get_sync(mhi_cntrl); @@ -505,6 +504,9 @@ static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) /* setup support for time sync */ mhi_init_timesync(mhi_cntrl); + if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + mhi_timesync_log(mhi_cntrl); + MHI_LOG("Adding new devices\n"); /* add supported devices */ @@ -772,10 +774,8 @@ void mhi_low_priority_worker(struct work_struct *work) TO_MHI_EXEC_STR(mhi_cntrl->ee)); /* check low priority event rings and process events */ - list_for_each_entry(mhi_event, &mhi_cntrl->lp_ev_rings, node) { - if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) - mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); - } + list_for_each_entry(mhi_event, &mhi_cntrl->lp_ev_rings, node) + mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); } void mhi_pm_sys_err_worker(struct work_struct *work) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 5c76aa0610f9..98acec0eaaf6 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -308,6 +308,7 @@ struct fastrpc_apps { spinlock_t ctxlock; struct smq_invoke_ctx *ctxtable[FASTRPC_CTX_MAX]; bool legacy_remote_heap; + int in_hib; }; struct fastrpc_mmap { @@ -501,6 +502,7 @@ static void fastrpc_buf_free(struct fastrpc_buf *buf, int cache) { struct fastrpc_file *fl = buf == NULL ? NULL : buf->fl; int vmid; + struct fastrpc_apps *me = &gfa; if (!fl) return; @@ -524,7 +526,7 @@ static void fastrpc_buf_free(struct fastrpc_buf *buf, int cache) if (fl->sctx->smmu.cb && fl->cid != SDSP_DOMAIN_ID) buf->phys &= ~((uint64_t)fl->sctx->smmu.cb << 32); vmid = fl->apps->channel[fl->cid].vmid; - if (vmid) { + if ((vmid) && (me->in_hib == 0)) { int srcVM[2] = {VMID_HLOS, vmid}; hyp_assign_phys(buf->phys, buf_page_size(buf->size), @@ -752,7 +754,7 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) sess = fl->sctx; vmid = fl->apps->channel[fl->cid].vmid; - if (vmid && map->phys) { + if (vmid && map->phys && me->in_hib == 0) { int srcVM[2] = {VMID_HLOS, vmid}; hyp_assign_phys(map->phys, buf_page_size(map->size), @@ -2243,7 +2245,8 @@ bail: me->staticpd_flags = 0; if (mem && err) { if (mem->flags == ADSP_MMAP_REMOTE_HEAP_ADDR - && me->channel[fl->cid].rhvm.vmid) + && me->channel[fl->cid].rhvm.vmid + && me->in_hib == 0) hyp_assign_phys(mem->phys, (uint64_t)mem->size, me->channel[fl->cid].rhvm.vmid, me->channel[fl->cid].rhvm.vmcount, @@ -2412,7 +2415,7 @@ static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, uint64_t phys, err = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, TZ_PIL_CLEAR_PROTECT_MEM_SUBSYS_ID), &desc); } else if (flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { - if (me->channel[fl->cid].rhvm.vmid) { + if ((me->channel[fl->cid].rhvm.vmid) && (me->in_hib == 0)) { VERIFY(err, !hyp_assign_phys(phys, (uint64_t)size, me->channel[fl->cid].rhvm.vmid, @@ -3254,6 +3257,7 @@ static int fastrpc_channel_open(struct fastrpc_file *fl) me->channel[cid].prevssrcount = me->channel[cid].ssrcount; } + me->in_hib = 0; mutex_unlock(&me->channel[cid].smd_mutex); bail: @@ -4147,6 +4151,7 @@ static int fastrpc_restore(struct device *dev) uint32_t val; pr_info("adsprpc: restore enter\n"); + me->in_hib = 1; if (of_device_is_compatible(dev->of_node, "qcom,msm-adsprpc-mem-region")) { me->dev = dev; @@ -4244,6 +4249,7 @@ static int __init fastrpc_device_init(void) fastrpc_init(me); me->dev = NULL; me->legacy_remote_heap = 0; + me->in_hib = 0; VERIFY(err, 0 == platform_driver_register(&fastrpc_driver)); if (err) goto register_bail; diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c index e6e1eb41ad40..306987fe213d 100644 --- a/drivers/clk/qcom/gpucc-sm8150.c +++ b/drivers/clk/qcom/gpucc-sm8150.c @@ -130,6 +130,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .hid_width = 5, .parent_map = gpu_cc_parent_map_0, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_names = gpu_cc_parent_names_0, diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c index fcd8575a743f..427adf010c43 100644 --- a/drivers/devfreq/governor_bw_hwmon.c +++ b/drivers/devfreq/governor_bw_hwmon.c @@ -713,7 +713,7 @@ static int devfreq_bw_hwmon_get_freq(struct devfreq *df, struct hwmon_node *node = df->data; /* Suspend/resume sequence */ - if (!node->mon_started) { + if (node && !node->mon_started) { *freq = node->resume_freq; *node->dev_ab = node->resume_ab; return 0; diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c index e4bb1434a09d..24f17dc7eedf 100644 --- a/drivers/gpu/msm/adreno_snapshot.c +++ b/drivers/gpu/msm/adreno_snapshot.c @@ -289,13 +289,10 @@ static void snapshot_rb_ibs(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - unsigned int rptr, *rbptr; + unsigned int *rbptr, rptr = adreno_get_rptr(rb); int index, i; int parse_ibs = 0, ib_parse_start; - /* Get the current read pointers for the RB */ - adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr); - /* * Figure out the window of ringbuffer data to dump. First we need to * find where the last processed IB ws submitted. Start walking back @@ -859,6 +856,7 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot, struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); + bool gx_on = true; ib_max_objs = 0; /* Reset the list of objects */ @@ -878,20 +876,22 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot, if (gpudev->snapshot) gpudev->snapshot(adreno_dev, snapshot); - /* Dumping these buffers is useless if the GX is not on */ - if (GMU_DEV_OP_VALID(gmu_dev_ops, gx_is_on) && - !gmu_dev_ops->gx_is_on(adreno_dev)) - goto out; + if (GMU_DEV_OP_VALID(gmu_dev_ops, gx_is_on)) + gx_on = gmu_dev_ops->gx_is_on(adreno_dev); setup_fault_process(device, snapshot, context ? context->proc_priv : NULL); - adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB1_BASE, - ADRENO_REG_CP_IB1_BASE_HI, &snapshot->ib1base); - adreno_readreg(adreno_dev, ADRENO_REG_CP_IB1_BUFSZ, &snapshot->ib1size); - adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB2_BASE, - ADRENO_REG_CP_IB2_BASE_HI, &snapshot->ib2base); - adreno_readreg(adreno_dev, ADRENO_REG_CP_IB2_BUFSZ, &snapshot->ib2size); + if (gx_on) { + adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB1_BASE, + ADRENO_REG_CP_IB1_BASE_HI, &snapshot->ib1base); + adreno_readreg(adreno_dev, ADRENO_REG_CP_IB1_BUFSZ, + &snapshot->ib1size); + adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB2_BASE, + ADRENO_REG_CP_IB2_BASE_HI, &snapshot->ib2base); + adreno_readreg(adreno_dev, ADRENO_REG_CP_IB2_BUFSZ, + &snapshot->ib2size); + } snapshot->ib1dumped = false; snapshot->ib2dumped = false; @@ -980,7 +980,6 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot, KGSL_CORE_ERR("GPU snapshot froze %zdKb of GPU buffers\n", snapshot_frozen_objsize / 1024); -out: if (device->pwrctrl.ahbpath_pcl) msm_bus_scale_client_update_request(device->pwrctrl.ahbpath_pcl, KGSL_AHB_PATH_LOW); diff --git a/drivers/hid/hid-qvr.c b/drivers/hid/hid-qvr.c index b28e0128bd0e..0328bddbb459 100644 --- a/drivers/hid/hid-qvr.c +++ b/drivers/hid/hid-qvr.c @@ -105,6 +105,7 @@ struct qvr_external_sensor { static DECLARE_WAIT_QUEUE_HEAD(wq); static struct qvr_external_sensor qvr_external_sensor; +static uint8_t DEBUG_ORIENTATION; static int read_calibration_len(void) { @@ -237,7 +238,6 @@ static int control_imu_stream(bool status) return -ETIME; } - static int qvr_send_package_wrap(u8 *message, int msize, struct hid_device *hid) { struct qvr_external_sensor *sensor = &qvr_external_sensor; @@ -254,7 +254,32 @@ static int qvr_send_package_wrap(u8 *message, int msize, struct hid_device *hid) memcpy((void *)&imuData, (void *)message, sizeof(struct external_imu_format)); - + if (!sensor->ts_base) { + if (imuData.gNumerator == 1 && imuData.aNumerator == 1) + DEBUG_ORIENTATION = 1; + else + DEBUG_ORIENTATION = 0; + pr_debug("qvr msize = %d reportID=%d padding=%d\n" + "qvr version=%d numImu=%d nspip=%d pSize=%d\n" + "qvr imuID=%d sampleID=%d temp=%d\n", + msize, imuData.reportID, imuData.padding, + imuData.version, imuData.numIMUs, + imuData.numSamplesPerImuPacket, + imuData.totalPayloadSize, imuData.imuID, + imuData.sampleID, imuData.temperature); + pr_debug("qvr gts0=%llu num=%d denom=%d\n" + "qvr gx0=%d gy0=%d gz0=%d\n", + imuData.gts0, imuData.gNumerator, imuData.gDenominator, + imuData.gx0, imuData.gy0, imuData.gz0); + pr_debug("qvr ats0=%llu num=%d denom=%d\n" + "qvr ax0=%d ay0=%d az0=%d\n", + imuData.ats0, imuData.aNumerator, imuData.aDenominator, + imuData.ax0, imuData.ay0, imuData.az0); + pr_debug("qvr mts0=%llu num=%d denom=%d\n" + "mx0=%d my0=%d mz0=%d\n", + imuData.mts0, imuData.mNumerator, imuData.mDenominator, + imuData.mx0, imuData.my0, imuData.mz0); + } if (!sensor->ts_base) sensor->ts_base = ktime_to_ns(ktime_get_boottime()); if (!sensor->ts_offset) @@ -276,15 +301,28 @@ static int qvr_send_package_wrap(u8 *message, int msize, struct hid_device *hid) else data->mts = data->ats; data->gts = data->ats; - data->ax = -imuData.ax0; - data->ay = imuData.ay0; - data->az = -imuData.az0; - data->gx = -imuData.gx0; - data->gy = imuData.gy0; - data->gz = -imuData.gz0; - data->mx = -imuData.my0; - data->my = -imuData.mx0; - data->mz = -imuData.mz0; + + if (DEBUG_ORIENTATION == 1) { + data->ax = -imuData.ax0; + data->ay = imuData.ay0; + data->az = -imuData.az0; + data->gx = -imuData.gx0; + data->gy = imuData.gy0; + data->gz = -imuData.gz0; + data->mx = -imuData.my0; + data->my = -imuData.mx0; + data->mz = -imuData.mz0; + } else { + data->ax = -imuData.ay0; + data->ay = -imuData.ax0; + data->az = -imuData.az0; + data->gx = -imuData.gy0; + data->gy = -imuData.gx0; + data->gz = -imuData.gz0; + data->mx = -imuData.my0; + data->my = -imuData.mx0; + data->mz = -imuData.mz0; + } trace_qvr_recv_sensor("gyro", data->gts, data->gx, data->gy, data->gz); trace_qvr_recv_sensor("accel", data->ats, data->ax, data->ay, data->az); diff --git a/drivers/iio/imu/st_asm330lhh/st_asm330lhh_core.c b/drivers/iio/imu/st_asm330lhh/st_asm330lhh_core.c index 09281c998b49..a905476342a1 100644 --- a/drivers/iio/imu/st_asm330lhh/st_asm330lhh_core.c +++ b/drivers/iio/imu/st_asm330lhh/st_asm330lhh_core.c @@ -1219,7 +1219,8 @@ int st_asm330lhh_probe(struct device *dev, int irq, return 0; regulator_shutdown: - st_asm330lhh_regulator_power_down(hw); + if (asm330_check_regulator) + st_asm330lhh_regulator_power_down(hw); return err; } diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index eb75de68214c..19348209c063 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -27,5 +27,7 @@ obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o +ccflags-$(CONFIG_PTP_1588_CLOCK)+=-DCONFIG_PTPSUPPORT_OBJ + obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o stmmac-pci-objs:= stmmac_pci.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-pps.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-pps.c index 0ab17422bf36..c4d41a9162a4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-pps.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-pps.c @@ -127,6 +127,7 @@ int ppsout_stop(struct stmmac_priv *priv, struct pps_cfg *eth_pps_cfg) u32 val; void __iomem *ioaddr = priv->ioaddr; + val = readl_relaxed(ioaddr + MAC_PPS_CONTROL); val |= PPSCMDX(eth_pps_cfg->ppsout_ch, 0x5); val |= TRGTMODSELX(eth_pps_cfg->ppsout_ch, 0x3); val |= PPSEN0; @@ -186,6 +187,17 @@ static void ethqos_register_pps_isr(struct stmmac_priv *priv, int ch) } } +static void ethqos_unregister_pps_isr(struct stmmac_priv *priv, int ch) +{ + struct qcom_ethqos *ethqos = priv->plat->bsp_priv; + + if (ch == DWC_ETH_QOS_PPS_CH_2) { + free_irq(ethqos->pps_class_a_irq, priv); + } else if (ch == DWC_ETH_QOS_PPS_CH_3) { + free_irq(ethqos->pps_class_b_irq, priv); + } +} + int ppsout_config(struct stmmac_priv *priv, struct ifr_data_struct *req) { struct pps_cfg *eth_pps_cfg = (struct pps_cfg *)req->ptr; @@ -196,6 +208,9 @@ int ppsout_config(struct stmmac_priv *priv, struct ifr_data_struct *req) if (!eth_pps_cfg->ppsout_start) { ppsout_stop(priv, eth_pps_cfg); + if (eth_pps_cfg->ppsout_ch == DWC_ETH_QOS_PPS_CH_2 || + eth_pps_cfg->ppsout_ch == DWC_ETH_QOS_PPS_CH_3) + ethqos_unregister_pps_isr(priv, eth_pps_cfg->ppsout_ch); return 0; } @@ -247,6 +262,30 @@ int ppsout_config(struct stmmac_priv *priv, struct ifr_data_struct *req) return 0; } +int ethqos_init_pps(struct stmmac_priv *priv) +{ + u32 value; + struct ifr_data_struct req = {0}; + struct pps_cfg eth_pps_cfg = {0}; + + priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; + value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSUPDT); + priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); + priv->hw->ptp->init_systime(priv->ptpaddr, 0, 0); + priv->hw->ptp->adjust_systime(priv->ptpaddr, 0, 0, 0, 1); + + /*Configuaring PPS0 PPS output frequency to default 19.2 Mhz*/ + eth_pps_cfg.ppsout_ch = 0; + eth_pps_cfg.ptpclk_freq = 62500000; + eth_pps_cfg.ppsout_freq = 19200000; + eth_pps_cfg.ppsout_start = 1; + eth_pps_cfg.ppsout_duty = 50; + req.ptr = (void *)ð_pps_cfg; + + ppsout_config(priv, &req); + return 0; +} + int ethqos_handle_prv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct stmmac_priv *pdata = netdev_priv(dev); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index c441a4514dd1..e88a660e0679 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -167,6 +167,7 @@ extern struct emac_emb_smmu_cb_ctx emac_emb_smmu_ctx; &emac_emb_smmu_ctx.smmu_pdev->dev : priv->device) int ethqos_handle_prv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ethqos_init_pps(struct stmmac_priv *priv); extern bool phy_intr_en; int stmmac_mdio_unregister(struct net_device *ndev); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 97a4295d85cb..4f8e8a56d3af 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2529,6 +2529,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) netdev_warn(priv->dev, "PTP init failed\n"); else ret = clk_set_rate(priv->plat->clk_ptp_ref, 96000000); + ret = ethqos_init_pps(priv); } priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; @@ -2611,7 +2612,12 @@ static int stmmac_open(struct net_device *dev) goto init_error; } +#ifdef CONFIG_PTPSUPPORT_OBJ ret = stmmac_hw_setup(dev, true); +#else + ret = stmmac_hw_setup(dev, false); +#endif + if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); goto init_error; diff --git a/drivers/net/wireless/cnss_utils/cnss_utils.c b/drivers/net/wireless/cnss_utils/cnss_utils.c index 77a58c8cb6a4..31de9bfbfb16 100644 --- a/drivers/net/wireless/cnss_utils/cnss_utils.c +++ b/drivers/net/wireless/cnss_utils/cnss_utils.c @@ -12,11 +12,11 @@ #define pr_fmt(fmt) "cnss_utils: " fmt -#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/etherdevice.h> #include <linux/kernel.h> +#include <linux/module.h> #include <linux/slab.h> -#include <linux/etherdevice.h> -#include <linux/debugfs.h> #include <net/cnss_utils.h> #define CNSS_MAX_CH_NUM 45 diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f11e20b42e1f..0b7620daa21e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -223,4 +223,12 @@ config PINCTRL_SLPI This is the pinctrl, pinmux and pinconf driver for the SLPI pin controller block. +config PINCTRL_MDM9607 + tristate "QTI MDM9607 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + QTI TLMM block found in the QTI 9607 platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index b92770834ba5..4b20f24f268d 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_PINCTRL_TRINKET) += pinctrl-trinket.o obj-$(CONFIG_PINCTRL_SDXPRAIRIE) += pinctrl-sdxprairie.o obj-$(CONFIG_PINCTRL_SDMMAGPIE) += pinctrl-sdmmagpie.o obj-$(CONFIG_PINCTRL_SLPI) += pinctrl-slpi.o +obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c new file mode 100644 index 000000000000..276e50fd0455 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -0,0 +1,1128 @@ +/* + * Copyright (c) 2015, 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc mdm9607_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "SDC1_CLK"), + PINCTRL_PIN(81, "SDC1_CMD"), + PINCTRL_PIN(82, "SDC1_DATA"), + PINCTRL_PIN(83, "SDC2_CLK"), + PINCTRL_PIN(84, "SDC2_CMD"), + PINCTRL_PIN(85, "SDC2_DATA"), + PINCTRL_PIN(86, "QDSD_CLK"), + PINCTRL_PIN(87, "QDSD_CMD"), + PINCTRL_PIN(88, "QDSD_DATA0"), + PINCTRL_PIN(89, "QDSD_DATA1"), + PINCTRL_PIN(90, "QDSD_DATA2"), + PINCTRL_PIN(91, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); + +static const unsigned int sdc1_clk_pins[] = { 80 }; +static const unsigned int sdc1_cmd_pins[] = { 81 }; +static const unsigned int sdc1_data_pins[] = { 82 }; +static const unsigned int sdc2_clk_pins[] = { 83 }; +static const unsigned int sdc2_cmd_pins[] = { 84 }; +static const unsigned int sdc2_data_pins[] = { 85 }; +static const unsigned int qdsd_clk_pins[] = { 86 }; +static const unsigned int qdsd_cmd_pins[] = { 87 }; +static const unsigned int qdsd_data0_pins[] = { 88 }; +static const unsigned int qdsd_data1_pins[] = { 89 }; +static const unsigned int qdsd_data2_pins[] = { 90 }; +static const unsigned int qdsd_data3_pins[] = { 91 }; + +enum mdm9607_functions { + msm_mux_blsp_spi3, + msm_mux_gpio, + msm_mux_blsp_uart3, + msm_mux_qdss_tracedata_a, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c3, + msm_mux_qdss_traceclk_a, + msm_mux_bimc_dte0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_blsp_spi2, + msm_mux_blsp_uart2, + msm_mux_blsp_uim2, + msm_mux_blsp_i2c2, + msm_mux_qdss_tracectl_a, + msm_mux_sensor_int2, + msm_mux_blsp_spi5, + msm_mux_blsp_uart5, + msm_mux_ebi2_lcd, + msm_mux_m_voc, + msm_mux_sensor_int3, + msm_mux_sensor_en, + msm_mux_blsp_i2c5, + msm_mux_ebi2_a, + msm_mux_qdss_tracedata_b, + msm_mux_sensor_rst, + msm_mux_blsp2_spi, + msm_mux_blsp_spi1, + msm_mux_blsp_uart1, + msm_mux_blsp_uim1, + msm_mux_blsp3_spi, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_b, + msm_mux_blsp_i2c1, + msm_mux_gcc_gp1_clk_b, + msm_mux_blsp_spi4, + msm_mux_blsp_uart4, + msm_mux_rcm_marker1, + msm_mux_blsp_i2c4, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_rcm_marker2, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_blsp_spi6, + msm_mux_blsp_uart6, + msm_mux_pri_mi2s_ws_a, + msm_mux_ebi2_lcd_te_b, + msm_mux_blsp1_spi, + msm_mux_backlight_en_b, + msm_mux_pri_mi2s_data0_a, + msm_mux_pri_mi2s_data1_a, + msm_mux_blsp_i2c6, + msm_mux_ebi2_a_d_8_b, + msm_mux_pri_mi2s_sck_a, + msm_mux_ebi2_lcd_cs_n_b, + msm_mux_touch_rst, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pwr_nav_enabled_a, + msm_mux_ts_int, + msm_mux_sd_write, + msm_mux_pwr_crypto_enabled_a, + msm_mux_codec_rst, + msm_mux_adsp_ext, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_uim2_data, + msm_mux_gmac_mdio, + msm_mux_gcc_gp1_clk_a, + msm_mux_uim2_clk, + msm_mux_gcc_gp2_clk_a, + msm_mux_eth_irq, + msm_mux_uim2_reset, + msm_mux_gcc_gp3_clk_a, + msm_mux_eth_rst, + msm_mux_uim2_present, + msm_mux_prng_rosc, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_gcc_plltest, + msm_mux_uim_batt, + msm_mux_coex_uart, + msm_mux_codec_int, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_atest_bbrx1, + msm_mux_cri_trng0, + msm_mux_atest_bbrx0, + msm_mux_cri_trng, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_traceclk_b, + msm_mux_pa_indicator, + msm_mux_modem_tsync, + msm_mux_nav_tsync_out_a, + msm_mux_nav_ptp_pps_in_a, + msm_mux_ptp_pps_out_a, + msm_mux_gsm0_tx, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_cri_trng1, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_ssbi1, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_ssbi2, + msm_mux_atest_char3, + msm_mux_atest_char2, + msm_mux_atest_char1, + msm_mux_atest_char0, + msm_mux_atest_char, + msm_mux_ebi0_wrcdc, + msm_mux_ldo_update, + msm_mux_gcc_tlmm, + msm_mux_ldo_en, + msm_mux_dbg_out, + msm_mux_atest_tsens, + msm_mux_lcd_rst, + msm_mux_wlan_en1, + msm_mux_nav_tsync_out_b, + msm_mux_nav_ptp_pps_in_b, + msm_mux_ptp_pps_out_b, + msm_mux_pbs0, + msm_mux_sec_mi2s, + msm_mux_pwr_modem_enabled_a, + msm_mux_pbs1, + msm_mux_pwr_modem_enabled_b, + msm_mux_pbs2, + msm_mux_pwr_nav_enabled_b, + msm_mux_pwr_crypto_enabled_b, + msm_mux_NA, +}; + +static const char * const blsp_spi3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const blsp_uart3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const bimc_dte1_groups[] = { + "gpio1", "gpio24", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio2", "gpio3", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio2", +}; +static const char * const bimc_dte0_groups[] = { + "gpio2", "gpio15", +}; +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio6", +}; +static const char * const sensor_int2_groups[] = { + "gpio8", +}; +static const char * const blsp_spi5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio8", "gpio11", "gpio74", "gpio78", +}; +static const char * const m_voc_groups[] = { + "gpio8", "gpio78", +}; +static const char * const sensor_int3_groups[] = { + "gpio9", +}; +static const char * const sensor_en_groups[] = { + "gpio10", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio10", "gpio11", +}; +static const char * const ebi2_a_groups[] = { + "gpio10", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio46", + "gpio47", "gpio48", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio58", "gpio59", +}; +static const char * const sensor_rst_groups[] = { + "gpio11", +}; +static const char * const blsp2_spi_groups[] = { + "gpio11", "gpio13", "gpio77", +}; +static const char * const blsp_spi1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uart1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uim1_groups[] = { + "gpio12", "gpio13", +}; +static const char * const blsp3_spi_groups[] = { + "gpio12", "gpio26", "gpio76", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio12", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio14", "gpio15", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio14", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const rcm_marker1_groups[] = { + "gpio18", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", +}; +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio18", +}; +static const char * const rcm_marker2_groups[] = { + "gpio19", +}; +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const pri_mi2s_ws_a_groups[] = { + "gpio20", +}; +static const char * const ebi2_lcd_te_b_groups[] = { + "gpio20", +}; +static const char * const blsp1_spi_groups[] = { + "gpio20", "gpio21", "gpio78", +}; +static const char * const backlight_en_b_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data0_a_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data1_a_groups[] = { + "gpio22", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const ebi2_a_d_8_b_groups[] = { + "gpio22", +}; +static const char * const pri_mi2s_sck_a_groups[] = { + "gpio23", +}; +static const char * const ebi2_lcd_cs_n_b_groups[] = { + "gpio23", +}; +static const char * const touch_rst_groups[] = { + "gpio24", +}; +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio24", +}; +static const char * const pwr_nav_enabled_a_groups[] = { + "gpio24", +}; +static const char * const ts_int_groups[] = { + "gpio25", +}; +static const char * const sd_write_groups[] = { + "gpio25", +}; +static const char * const pwr_crypto_enabled_a_groups[] = { + "gpio25", +}; +static const char * const codec_rst_groups[] = { + "gpio26", +}; +static const char * const adsp_ext_groups[] = { + "gpio26", +}; +static const char * const atest_combodac_to_gpio_native_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio41", "gpio45", "gpio49", "gpio50", + "gpio51", "gpio52", "gpio54", "gpio55", "gpio57", "gpio59", +}; +static const char * const uim2_data_groups[] = { + "gpio27", +}; +static const char * const gmac_mdio_groups[] = { + "gpio27", "gpio28", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio27", +}; +static const char * const uim2_clk_groups[] = { + "gpio28", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio28", +}; +static const char * const eth_irq_groups[] = { + "gpio29", +}; +static const char * const uim2_reset_groups[] = { + "gpio29", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio29", +}; +static const char * const eth_rst_groups[] = { + "gpio30", +}; +static const char * const uim2_present_groups[] = { + "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio30", +}; +static const char * const uim1_data_groups[] = { + "gpio31", +}; +static const char * const uim1_clk_groups[] = { + "gpio32", +}; +static const char * const uim1_reset_groups[] = { + "gpio33", +}; +static const char * const uim1_present_groups[] = { + "gpio34", +}; +static const char * const gcc_plltest_groups[] = { + "gpio34", "gpio35", +}; +static const char * const uim_batt_groups[] = { + "gpio35", +}; +static const char * const coex_uart_groups[] = { + "gpio36", "gpio37", +}; +static const char * const codec_int_groups[] = { + "gpio38", +}; +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio38", +}; +static const char * const atest_bbrx1_groups[] = { + "gpio39", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const atest_bbrx0_groups[] = { + "gpio40", +}; +static const char * const cri_trng_groups[] = { + "gpio42", +}; +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio44", +}; +static const char * const atest_gpsadc_dtest0_native_groups[] = { + "gpio44", +}; +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio45", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio49", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio50", +}; +static const char * const pa_indicator_groups[] = { + "gpio51", +}; +static const char * const modem_tsync_groups[] = { + "gpio53", +}; +static const char * const nav_tsync_out_a_groups[] = { + "gpio53", +}; +static const char * const nav_ptp_pps_in_a_groups[] = { + "gpio53", +}; +static const char * const ptp_pps_out_a_groups[] = { + "gpio53", +}; +static const char * const gsm0_tx_groups[] = { + "gpio55", +}; +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio56", +}; +static const char * const cri_trng1_groups[] = { + "gpio57", +}; +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio57", +}; +static const char * const ssbi1_groups[] = { + "gpio58", +}; +static const char * const atest_gpsadc_dtest1_native_groups[] = { + "gpio58", +}; +static const char * const ssbi2_groups[] = { + "gpio59", +}; +static const char * const atest_char3_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio63", +}; +static const char * const atest_char_groups[] = { + "gpio64", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio70", +}; +static const char * const ldo_update_groups[] = { + "gpio72", +}; +static const char * const gcc_tlmm_groups[] = { + "gpio72", +}; +static const char * const ldo_en_groups[] = { + "gpio73", +}; +static const char * const dbg_out_groups[] = { + "gpio73", +}; +static const char * const atest_tsens_groups[] = { + "gpio73", +}; +static const char * const lcd_rst_groups[] = { + "gpio74", +}; +static const char * const wlan_en1_groups[] = { + "gpio75", +}; +static const char * const nav_tsync_out_b_groups[] = { + "gpio75", +}; +static const char * const nav_ptp_pps_in_b_groups[] = { + "gpio75", +}; +static const char * const ptp_pps_out_b_groups[] = { + "gpio75", +}; +static const char * const pbs0_groups[] = { + "gpio76", +}; +static const char * const sec_mi2s_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; +static const char * const pwr_modem_enabled_a_groups[] = { + "gpio76", +}; +static const char * const pbs1_groups[] = { + "gpio77", +}; +static const char * const pwr_modem_enabled_b_groups[] = { + "gpio77", +}; +static const char * const pbs2_groups[] = { + "gpio78", +}; +static const char * const pwr_nav_enabled_b_groups[] = { + "gpio78", +}; +static const char * const pwr_crypto_enabled_b_groups[] = { + "gpio79", +}; + +static const struct msm_function mdm9607_functions[] = { + FUNCTION(blsp_spi3), + FUNCTION(gpio), + FUNCTION(blsp_uart3), + FUNCTION(qdss_tracedata_a), + FUNCTION(bimc_dte1), + FUNCTION(blsp_i2c3), + FUNCTION(qdss_traceclk_a), + FUNCTION(bimc_dte0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uim2), + FUNCTION(blsp_i2c2), + FUNCTION(qdss_tracectl_a), + FUNCTION(sensor_int2), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uart5), + FUNCTION(ebi2_lcd), + FUNCTION(m_voc), + FUNCTION(sensor_int3), + FUNCTION(sensor_en), + FUNCTION(blsp_i2c5), + FUNCTION(ebi2_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(sensor_rst), + FUNCTION(blsp2_spi), + FUNCTION(blsp_spi1), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uim1), + FUNCTION(blsp3_spi), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(blsp_i2c1), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(blsp_spi4), + FUNCTION(blsp_uart4), + FUNCTION(rcm_marker1), + FUNCTION(blsp_i2c4), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(rcm_marker2), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart6), + FUNCTION(pri_mi2s_ws_a), + FUNCTION(ebi2_lcd_te_b), + FUNCTION(blsp1_spi), + FUNCTION(backlight_en_b), + FUNCTION(pri_mi2s_data0_a), + FUNCTION(pri_mi2s_data1_a), + FUNCTION(blsp_i2c6), + FUNCTION(ebi2_a_d_8_b), + FUNCTION(pri_mi2s_sck_a), + FUNCTION(ebi2_lcd_cs_n_b), + FUNCTION(touch_rst), + FUNCTION(pri_mi2s_mclk_a), + FUNCTION(pwr_nav_enabled_a), + FUNCTION(ts_int), + FUNCTION(sd_write), + FUNCTION(pwr_crypto_enabled_a), + FUNCTION(codec_rst), + FUNCTION(adsp_ext), + FUNCTION(atest_combodac_to_gpio_native), + FUNCTION(uim2_data), + FUNCTION(gmac_mdio), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(uim2_clk), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(eth_irq), + FUNCTION(uim2_reset), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(eth_rst), + FUNCTION(uim2_present), + FUNCTION(prng_rosc), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(gcc_plltest), + FUNCTION(uim_batt), + FUNCTION(coex_uart), + FUNCTION(codec_int), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(atest_bbrx1), + FUNCTION(cri_trng0), + FUNCTION(atest_bbrx0), + FUNCTION(cri_trng), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(atest_gpsadc_dtest0_native), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_traceclk_b), + FUNCTION(pa_indicator), + FUNCTION(modem_tsync), + FUNCTION(nav_tsync_out_a), + FUNCTION(nav_ptp_pps_in_a), + FUNCTION(ptp_pps_out_a), + FUNCTION(gsm0_tx), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(cri_trng1), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(ssbi1), + FUNCTION(atest_gpsadc_dtest1_native), + FUNCTION(ssbi2), + FUNCTION(atest_char3), + FUNCTION(atest_char2), + FUNCTION(atest_char1), + FUNCTION(atest_char0), + FUNCTION(atest_char), + FUNCTION(ebi0_wrcdc), + FUNCTION(ldo_update), + FUNCTION(gcc_tlmm), + FUNCTION(ldo_en), + FUNCTION(dbg_out), + FUNCTION(atest_tsens), + FUNCTION(lcd_rst), + FUNCTION(wlan_en1), + FUNCTION(nav_tsync_out_b), + FUNCTION(nav_ptp_pps_in_b), + FUNCTION(ptp_pps_out_b), + FUNCTION(pbs0), + FUNCTION(sec_mi2s), + FUNCTION(pwr_modem_enabled_a), + FUNCTION(pbs1), + FUNCTION(pwr_modem_enabled_b), + FUNCTION(pbs2), + FUNCTION(pwr_nav_enabled_b), + FUNCTION(pwr_crypto_enabled_b), +}; + +static const struct msm_pingroup mdm9607_groups[] = { + PINGROUP(0, blsp_uart3, blsp_spi3, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA), + PINGROUP(1, blsp_uart3, blsp_spi3, NA, NA, NA, NA, NA, + qdss_tracedata_a, bimc_dte1), + PINGROUP(2, blsp_uart3, blsp_i2c3, blsp_spi3, NA, NA, NA, NA, NA, + qdss_traceclk_a), + PINGROUP(3, blsp_uart3, blsp_i2c3, blsp_spi3, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA, + qdss_tracedata_a, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA, + qdss_tracedata_a, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, NA, NA, NA, NA, NA), + PINGROUP(9, blsp_spi5, blsp_uart5, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, blsp_spi5, blsp_i2c5, blsp_uart5, ebi2_a, NA, NA, + qdss_tracedata_b, NA, NA), + PINGROUP(11, blsp_spi5, blsp_i2c5, blsp_uart5, blsp2_spi, ebi2_lcd, NA, + NA, NA, NA), + PINGROUP(12, blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, + gcc_gp2_clk_b, NA, NA, NA, NA), + PINGROUP(13, blsp_spi1, blsp_uart1, blsp_uim1, blsp2_spi, + gcc_gp3_clk_b, NA, NA, NA, NA), + PINGROUP(14, blsp_spi1, blsp_uart1, blsp_i2c1, gcc_gp1_clk_b, NA, NA, + NA, NA, NA), + PINGROUP(15, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi4, blsp_uart4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi4, blsp_uart4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, blsp_uart6, pri_mi2s_ws_a, ebi2_lcd_te_b, + blsp1_spi, NA, NA, NA, qdss_tracedata_a), + PINGROUP(21, blsp_spi6, blsp_uart6, pri_mi2s_data0_a, blsp1_spi, NA, + NA, NA, NA, NA), + PINGROUP(22, blsp_spi6, blsp_uart6, pri_mi2s_data1_a, blsp_i2c6, + ebi2_a_d_8_b, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_uart6, pri_mi2s_sck_a, blsp_i2c6, + ebi2_lcd_cs_n_b, NA, NA, NA, NA), + PINGROUP(24, pri_mi2s_mclk_a, NA, pwr_nav_enabled_a, NA, NA, NA, NA, + qdss_tracedata_a, bimc_dte1), + PINGROUP(25, sd_write, NA, pwr_crypto_enabled_a, NA, NA, NA, NA, + qdss_tracedata_a, NA), + PINGROUP(26, blsp3_spi, adsp_ext, NA, qdss_tracedata_a, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(27, uim2_data, gmac_mdio, gcc_gp1_clk_a, NA, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(28, uim2_clk, gmac_mdio, gcc_gp2_clk_a, NA, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(29, uim2_reset, gcc_gp3_clk_a, NA, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(30, uim2_present, prng_rosc, NA, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(31, uim1_data, NA, NA, atest_combodac_to_gpio_native, NA, NA, + NA, NA, NA), + PINGROUP(32, uim1_clk, NA, NA, atest_combodac_to_gpio_native, NA, NA, + NA, NA, NA), + PINGROUP(33, uim1_reset, NA, NA, atest_combodac_to_gpio_native, NA, NA, + NA, NA, NA), + PINGROUP(34, uim1_present, gcc_plltest, NA, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(35, uim_batt, gcc_plltest, NA, atest_combodac_to_gpio_native, + NA, NA, NA, NA, NA), + PINGROUP(36, coex_uart, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, coex_uart, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, qdss_cti_trig_in_a0, NA, NA, NA, NA, NA), + PINGROUP(39, NA, NA, NA, qdss_tracedata_b, NA, atest_bbrx1, NA, NA, NA), + PINGROUP(40, NA, cri_trng0, NA, NA, NA, NA, qdss_tracedata_b, NA, + atest_bbrx0), + PINGROUP(41, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA), + PINGROUP(42, NA, cri_trng, NA, NA, qdss_tracedata_b, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA, NA), + PINGROUP(44, NA, NA, qdss_cti_trig_in_b0, NA, + atest_gpsadc_dtest0_native, NA, NA, NA, NA), + PINGROUP(45, NA, NA, qdss_cti_trig_out_b0, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(46, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(48, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, qdss_tracectl_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(50, NA, NA, qdss_traceclk_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(51, NA, pa_indicator, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(52, NA, NA, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(53, NA, modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, + ptp_pps_out_a, qdss_tracedata_b, NA, NA, NA), + PINGROUP(54, NA, qdss_tracedata_b, NA, atest_combodac_to_gpio_native, + NA, NA, NA, NA, NA), + PINGROUP(55, gsm0_tx, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA, NA), + PINGROUP(56, NA, NA, qdss_cti_trig_in_b1, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, cri_trng1, NA, qdss_cti_trig_out_b1, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(58, NA, ssbi1, NA, qdss_tracedata_b, NA, + atest_gpsadc_dtest1_native, NA, NA, NA), + PINGROUP(59, NA, ssbi2, NA, qdss_tracedata_b, NA, + atest_combodac_to_gpio_native, NA, NA, NA), + PINGROUP(60, atest_char3, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, atest_char2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, atest_char1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, atest_char0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, atest_char, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, ebi0_wrcdc, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, ldo_update, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ldo_en, dbg_out, NA, NA, NA, atest_tsens, NA, NA, NA), + PINGROUP(74, ebi2_lcd, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, NA, + qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(76, pbs0, sec_mi2s, blsp3_spi, pwr_modem_enabled_a, NA, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(77, pbs1, sec_mi2s, blsp2_spi, pwr_modem_enabled_b, NA, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(78, pbs2, sec_mi2s, blsp1_spi, ebi2_lcd, m_voc, + pwr_nav_enabled_b, NA, qdss_tracedata_a, NA), + PINGROUP(79, sec_mi2s, NA, pwr_crypto_enabled_b, NA, qdss_tracedata_a, + NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data mdm9607_pinctrl = { + .pins = mdm9607_pins, + .npins = ARRAY_SIZE(mdm9607_pins), + .functions = mdm9607_functions, + .nfunctions = ARRAY_SIZE(mdm9607_functions), + .groups = mdm9607_groups, + .ngroups = ARRAY_SIZE(mdm9607_groups), + .ngpios = 80, +}; + +static int mdm9607_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &mdm9607_pinctrl); +} + +static const struct of_device_id mdm9607_pinctrl_of_match[] = { + { .compatible = "qcom,mdm9607-pinctrl", }, + { }, +}; + +static struct platform_driver mdm9607_pinctrl_driver = { + .driver = { + .name = "mdm9607-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mdm9607_pinctrl_of_match, + }, + .probe = mdm9607_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init mdm9607_pinctrl_init(void) +{ + return platform_driver_register(&mdm9607_pinctrl_driver); +} +arch_initcall(mdm9607_pinctrl_init); + +static void __exit mdm9607_pinctrl_exit(void) +{ + platform_driver_unregister(&mdm9607_pinctrl_driver); +} +module_exit(mdm9607_pinctrl_exit); + +MODULE_DESCRIPTION("QTI mdm9607 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index 631d40278b81..4c17c7ebec09 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -3477,7 +3477,7 @@ static int ipa3_q6_set_ex_path_to_apps(void) /* Set the exception path to AP */ for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) { ep_idx = ipa3_get_ep_mapping(client_idx); - if (ep_idx == -1) + if (ep_idx == -1 || (ep_idx >= IPA3_MAX_NUM_PIPES)) continue; /* disable statuses for all modem controlled prod pipes */ diff --git a/drivers/power/supply/qcom/battery.c b/drivers/power/supply/qcom/battery.c index 952778b234d7..dbcf48af1ff1 100644 --- a/drivers/power/supply/qcom/battery.c +++ b/drivers/power/supply/qcom/battery.c @@ -197,6 +197,34 @@ static int cp_get_parallel_mode(struct pl_data *chip, int mode) return pval.intval; } +static int get_hvdcp3_icl_limit(struct pl_data *chip) +{ + int rc, main_icl, target_icl = -EINVAL; + union power_supply_propval pval = {0, }; + + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_REAL_TYPE, &pval); + if ((rc < 0) || (pval.intval != POWER_SUPPLY_TYPE_USB_HVDCP_3)) + return target_icl; + + /* + * For HVDCP3 adapters, limit max. ILIM as follows: + * HVDCP3_ICL: Maximum ICL of HVDCP3 adapter(from DT configuration) + * For Parallel input configurations: + * VBUS: target_icl = HVDCP3_ICL - main_ICL + * VMID: target_icl = HVDCP3_ICL + */ + target_icl = chip->chg_param->hvdcp3_max_icl_ua; + if (cp_get_parallel_mode(chip, PARALLEL_INPUT_MODE) + == POWER_SUPPLY_PL_USBIN_USBIN) { + main_icl = get_effective_result_locked(chip->usb_icl_votable); + if ((main_icl >= 0) && (main_icl < target_icl)) + target_icl -= main_icl; + } + + return target_icl; +} + /* * Adapter CC Mode: ILIM over-ridden explicitly, below takes no effect. * @@ -212,7 +240,7 @@ static int cp_get_parallel_mode(struct pl_data *chip, int mode) */ static void cp_configure_ilim(struct pl_data *chip, const char *voter, int ilim) { - int rc, fcc, main_icl, target_icl = chip->chg_param->hvdcp3_max_icl_ua; + int rc, fcc, target_icl; union power_supply_propval pval = {0, }; if (!is_usb_available(chip)) @@ -225,30 +253,8 @@ static void cp_configure_ilim(struct pl_data *chip, const char *voter, int ilim) == POWER_SUPPLY_PL_OUTPUT_VPH) return; - rc = power_supply_get_property(chip->usb_psy, - POWER_SUPPLY_PROP_REAL_TYPE, &pval); - if (rc < 0) - return; - - /* - * For HVDCP3 adapters limit max. ILIM based on DT configuration - * of HVDCP3 ICL value. - * Input VBUS: - * target_icl = HVDCP3_ICL - main_ICL - * Input VMID - * target_icl = HVDCP3_ICL - */ - if (pval.intval == POWER_SUPPLY_TYPE_USB_HVDCP_3) { - if (((cp_get_parallel_mode(chip, PARALLEL_INPUT_MODE)) - == POWER_SUPPLY_PL_USBIN_USBIN)) { - main_icl = get_effective_result_locked( - chip->usb_icl_votable); - if ((main_icl >= 0) && (main_icl < target_icl)) - target_icl -= main_icl; - } - - ilim = min(target_icl, ilim); - } + target_icl = get_hvdcp3_icl_limit(chip); + ilim = (target_icl > 0) ? min(ilim, target_icl) : ilim; rc = power_supply_get_property(chip->cp_master_psy, POWER_SUPPLY_PROP_MIN_ICL, &pval); @@ -671,14 +677,17 @@ out: static void get_fcc_stepper_params(struct pl_data *chip, int main_fcc_ua, int parallel_fcc_ua) { - int main_set_fcc_ua, total_fcc_ua; + int main_set_fcc_ua, total_fcc_ua, target_icl; + bool override; if (!chip->chg_param->fcc_step_size_ua) { pr_err("Invalid fcc stepper step size, value 0\n"); return; } - if (is_override_vote_enabled_locked(chip->fcc_main_votable)) { + total_fcc_ua = main_fcc_ua + parallel_fcc_ua; + override = is_override_vote_enabled_locked(chip->fcc_main_votable); + if (override) { /* * FCC stepper params need re-calculation in override mode * only if there is change in Main or total FCC @@ -686,48 +695,99 @@ static void get_fcc_stepper_params(struct pl_data *chip, int main_fcc_ua, main_set_fcc_ua = get_effective_result_locked( chip->fcc_main_votable); - total_fcc_ua = main_fcc_ua + parallel_fcc_ua; - if ((main_set_fcc_ua != chip->override_main_fcc_ua) || (total_fcc_ua != chip->total_fcc_ua)) { chip->override_main_fcc_ua = main_set_fcc_ua; chip->total_fcc_ua = total_fcc_ua; - parallel_fcc_ua = (total_fcc_ua - - chip->override_main_fcc_ua); } else { goto skip_fcc_step_update; } } - /* Read current FCC of main charger */ - chip->main_fcc_ua = get_effective_result(chip->fcc_main_votable); - chip->main_step_fcc_dir = (main_fcc_ua > chip->main_fcc_ua) ? - STEP_UP : STEP_DOWN; - chip->main_step_fcc_count = abs((main_fcc_ua - chip->main_fcc_ua) / - chip->chg_param->fcc_step_size_ua); - chip->main_step_fcc_residual = abs((main_fcc_ua - chip->main_fcc_ua) % - chip->chg_param->fcc_step_size_ua); - - chip->parallel_step_fcc_dir = (parallel_fcc_ua > chip->slave_fcc_ua) ? - STEP_UP : STEP_DOWN; - chip->parallel_step_fcc_count - = abs((parallel_fcc_ua - chip->slave_fcc_ua) / - chip->chg_param->fcc_step_size_ua); - chip->parallel_step_fcc_residual - = abs((parallel_fcc_ua - chip->slave_fcc_ua) % - chip->chg_param->fcc_step_size_ua); + /* + * If override vote is removed then start main FCC from the + * last overridden value. + * Clear slave_fcc if requested parallel current is 0 i.e. + * parallel is disabled. + */ + if (chip->override_main_fcc_ua && !override) { + chip->main_fcc_ua = chip->override_main_fcc_ua; + chip->override_main_fcc_ua = 0; + if (!parallel_fcc_ua) + chip->slave_fcc_ua = 0; + } else { + chip->main_fcc_ua = get_effective_result_locked( + chip->fcc_main_votable); + } + + /* Skip stepping if override vote is applied on main */ + if (override) { + chip->main_step_fcc_count = 0; + chip->main_step_fcc_residual = 0; + } else { + chip->main_step_fcc_dir = + (main_fcc_ua > chip->main_fcc_ua) ? + STEP_UP : STEP_DOWN; + chip->main_step_fcc_count = + abs(main_fcc_ua - chip->main_fcc_ua) / + chip->chg_param->fcc_step_size_ua; + chip->main_step_fcc_residual = + abs(main_fcc_ua - chip->main_fcc_ua) % + chip->chg_param->fcc_step_size_ua; + } + + /* Calculate CP_ILIM based on adapter limit and max. FCC */ + if (!parallel_fcc_ua && is_cp_available(chip) && override) { + if (!chip->cp_ilim_votable) + chip->cp_ilim_votable = find_votable("CP_ILIM"); + + target_icl = get_hvdcp3_icl_limit(chip) * 2; + total_fcc_ua -= chip->main_fcc_ua; + + /* + * CP_ILIM = parallel_fcc_ua / 2. + * Calculate parallel_fcc_ua as follows: + * parallel_fcc_ua is based minimum of total FCC + * or adapter's maximum allowed ICL limitation(if adapter + * has max. ICL limitations). + */ + parallel_fcc_ua = (target_icl > 0) ? + min(target_icl, total_fcc_ua) : total_fcc_ua; + } + /* Skip stepping if override vote is applied on CP */ + if (chip->cp_ilim_votable + && is_override_vote_enabled(chip->cp_ilim_votable)) { + chip->parallel_step_fcc_count = 0; + chip->parallel_step_fcc_residual = 0; + } else { + chip->parallel_step_fcc_dir = + (parallel_fcc_ua > chip->slave_fcc_ua) ? + STEP_UP : STEP_DOWN; + chip->parallel_step_fcc_count = + abs(parallel_fcc_ua - chip->slave_fcc_ua) / + chip->chg_param->fcc_step_size_ua; + chip->parallel_step_fcc_residual = + abs(parallel_fcc_ua - chip->slave_fcc_ua) % + chip->chg_param->fcc_step_size_ua; + } skip_fcc_step_update: if (chip->parallel_step_fcc_count || chip->parallel_step_fcc_residual || chip->main_step_fcc_count || chip->main_step_fcc_residual) chip->step_fcc = 1; - pr_debug("Main FCC Stepper parameters: main_step_direction: %d, main_step_count: %d, main_residual_fcc: %d\n", - chip->main_step_fcc_dir, chip->main_step_fcc_count, - chip->main_step_fcc_residual); - pr_debug("Parallel FCC Stepper parameters: parallel_step_direction: %d, parallel_step_count: %d, parallel_residual_fcc: %d\n", + pl_dbg(chip, PR_PARALLEL, + "Main FCC Stepper parameters: target_main_fcc: %d, current_main_fcc: %d main_step_direction: %d, main_step_count: %d, main_residual_fcc: %d override_main_fcc_ua: %d override: %d\n", + main_fcc_ua, chip->main_fcc_ua, chip->main_step_fcc_dir, + chip->main_step_fcc_count, chip->main_step_fcc_residual, + chip->override_main_fcc_ua, override); + pl_dbg(chip, PR_PARALLEL, + "Parallel FCC Stepper parameters: target_pl_fcc: %d current_pl_fcc: %d parallel_step_direction: %d, parallel_step_count: %d, parallel_residual_fcc: %d\n", + parallel_fcc_ua, chip->slave_fcc_ua, chip->parallel_step_fcc_dir, chip->parallel_step_fcc_count, chip->parallel_step_fcc_residual); + pl_dbg(chip, PR_PARALLEL, "FCC Stepper parameters: step_fcc=%d\n", + chip->step_fcc); } #define MINIMUM_PARALLEL_FCC_UA 500000 @@ -853,7 +913,7 @@ static int pl_fcc_vote_callback(struct votable *votable, void *data, { struct pl_data *chip = data; int master_fcc_ua = total_fcc_ua, slave_fcc_ua = 0; - int main_fcc_ua = 0, cp_fcc_ua = 0, fcc_thr_ua = 0, rc; + int cp_fcc_ua = 0, fcc_thr_ua = 0, rc; union power_supply_propval pval = {0, }; bool is_cc_mode = false; @@ -900,14 +960,14 @@ static int pl_fcc_vote_callback(struct votable *votable, void *data, (4 * pval.intval); } - if (chip->fcc_main_votable) - main_fcc_ua = - get_effective_result_locked(chip->fcc_main_votable); - - if (main_fcc_ua < 0) - main_fcc_ua = 0; - - cp_fcc_ua = total_fcc_ua - main_fcc_ua; + /* + * CP charger current = Total FCC - Main charger's FCC. + * Main charger FCC is userspace's override vote on main. + */ + cp_fcc_ua = total_fcc_ua - chip->chg_param->forced_main_fcc; + pl_dbg(chip, PR_PARALLEL, + "cp_fcc_ua=%d total_fcc_ua=%d forced_main_fcc=%d\n", + cp_fcc_ua, total_fcc_ua, chip->chg_param->forced_main_fcc); if (cp_fcc_ua > 0) { if (chip->cp_slave_psy && chip->cp_slave_disable_votable) { /* @@ -1482,13 +1542,6 @@ static int pl_disable_vote_callback(struct votable *votable, if (chip->step_fcc) { vote(chip->pl_awake_votable, FCC_STEPPER_VOTER, true, 0); - /* - * Configure ILIM above min ILIM of CP to - * ensure CP is not disabled due to ILIM vote. - * Later FCC stepper will take to ILIM to - * target value. - */ - cp_configure_ilim(chip, FCC_VOTER, 0); schedule_delayed_work(&chip->fcc_stepper_work, 0); } @@ -1781,6 +1834,10 @@ static void handle_usb_change(struct pl_data *chip) vote(chip->pl_disable_votable, PL_TAPER_EARLY_BAD_VOTER, false, 0); vote(chip->pl_disable_votable, ICL_LIMIT_VOTER, false, 0); + chip->override_main_fcc_ua = 0; + chip->total_fcc_ua = 0; + chip->slave_fcc_ua = 0; + chip->main_fcc_ua = 0; } } diff --git a/drivers/power/supply/qcom/battery.h b/drivers/power/supply/qcom/battery.h index 886ddc9c9084..0ff716a3d97b 100644 --- a/drivers/power/supply/qcom/battery.h +++ b/drivers/power/supply/qcom/battery.h @@ -18,6 +18,7 @@ struct charger_param { u32 fcc_step_size_ua; u32 smb_version; u32 hvdcp3_max_icl_ua; + u32 forced_main_fcc; }; int qcom_batt_init(struct charger_param *param); diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index a4615384d70e..0013e3ec6123 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -1310,6 +1310,9 @@ static int smb5_usb_main_set_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_FORCE_MAIN_FCC: vote_override(chg->fcc_main_votable, CC_MODE_VOTER, (val->intval < 0) ? false : true, val->intval); + if (val->intval >= 0) + chg->chg_param.forced_main_fcc = val->intval; + /* Main FCC updated re-calculate FCC */ rerun_election(chg->fcc_votable); break; @@ -1554,6 +1557,7 @@ static enum power_supply_property smb5_batt_props[] = { POWER_SUPPLY_PROP_FCC_STEPPER_ENABLE, }; +#define DEBUG_ACCESSORY_TEMP_DECIDEGC 250 static int smb5_batt_get_prop(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -1634,7 +1638,11 @@ static int smb5_batt_get_prop(struct power_supply *psy, rc = smblib_get_prop_batt_iterm(chg, val); break; case POWER_SUPPLY_PROP_TEMP: - rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_TEMP, val); + if (chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_DEBUG_ACCESSORY) + val->intval = DEBUG_ACCESSORY_TEMP_DECIDEGC; + else + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_TEMP, val); break; case POWER_SUPPLY_PROP_TECHNOLOGY: val->intval = POWER_SUPPLY_TECHNOLOGY_LION; diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index 6b17af244718..7454512b4278 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -48,6 +48,7 @@ && (!chg->typec_legacy || chg->typec_legacy_use_rp_icl)) static void update_sw_icl_max(struct smb_charger *chg, int pst); +static int smblib_get_prop_typec_mode(struct smb_charger *chg); int smblib_read(struct smb_charger *chg, u16 addr, u8 *val) { @@ -1187,6 +1188,7 @@ static void smblib_uusb_removal(struct smb_charger *chg) chg->usb_icl_delta_ua = 0; chg->pulse_cnt = 0; chg->uusb_apsd_rerun_done = false; + chg->chg_param.forced_main_fcc = 0; /* write back the default FLOAT charger configuration */ rc = smblib_masked_write(chg, USBIN_OPTIONS_2_CFG_REG, @@ -1352,6 +1354,11 @@ int smblib_set_icl_current(struct smb_charger *chg, int icl_ua) /* suspend if 25mA or less is requested */ bool suspend = (icl_ua <= USBIN_25MA); + /* Do not configure ICL from SW for DAM cables */ + if (smblib_get_prop_typec_mode(chg) == + POWER_SUPPLY_TYPEC_SINK_DEBUG_ACCESSORY) + return 0; + if (chg->connector_type == POWER_SUPPLY_CONNECTOR_TYPEC) { rc = smblib_masked_write(chg, USB_CMD_PULLDOWN_REG, EN_PULLDOWN_USB_IN_BIT, @@ -3501,6 +3508,10 @@ static int smblib_get_prop_ufp_mode(struct smb_charger *chg) return POWER_SUPPLY_TYPEC_SOURCE_HIGH; case SNK_RP_SHORT_BIT: return POWER_SUPPLY_TYPEC_NON_COMPLIANT; + case SNK_DAM_500MA_BIT: + case SNK_DAM_1500MA_BIT: + case SNK_DAM_3000MA_BIT: + return POWER_SUPPLY_TYPEC_SINK_DEBUG_ACCESSORY; default: break; } @@ -5713,6 +5724,7 @@ static void typec_src_removal(struct smb_charger *chg) chg->voltage_min_uv = MICRO_5V; chg->voltage_max_uv = MICRO_5V; chg->usbin_forced_max_uv = 0; + chg->chg_param.forced_main_fcc = 0; /* Reset CC mode votes */ vote(chg->fcc_main_votable, MAIN_FCC_VOTER, false, 0); diff --git a/drivers/power/supply/qcom/smb5-reg.h b/drivers/power/supply/qcom/smb5-reg.h index dd23b2c55474..444841d67c82 100644 --- a/drivers/power/supply/qcom/smb5-reg.h +++ b/drivers/power/supply/qcom/smb5-reg.h @@ -340,7 +340,10 @@ enum { * TYPEC Peripheral Registers * ********************************/ #define TYPE_C_SNK_STATUS_REG (TYPEC_BASE + 0x06) -#define DETECTED_SRC_TYPE_MASK GENMASK(3, 0) +#define DETECTED_SRC_TYPE_MASK GENMASK(6, 0) +#define SNK_DAM_500MA_BIT BIT(6) +#define SNK_DAM_1500MA_BIT BIT(5) +#define SNK_DAM_3000MA_BIT BIT(4) #define SNK_RP_STD_BIT BIT(3) #define SNK_RP_1P5_BIT BIT(2) #define SNK_RP_3P0_BIT BIT(1) diff --git a/drivers/soc/qcom/service-notifier.c b/drivers/soc/qcom/service-notifier.c index a96c662df8dd..43016be0e1c1 100644 --- a/drivers/soc/qcom/service-notifier.c +++ b/drivers/soc/qcom/service-notifier.c @@ -59,7 +59,7 @@ #define QMI_STATE_MIN_VAL QMI_SERVREG_NOTIF_SERVICE_STATE_ENUM_TYPE_MIN_VAL_V01 #define QMI_STATE_MAX_VAL QMI_SERVREG_NOTIF_SERVICE_STATE_ENUM_TYPE_MAX_VAL_V01 -#define SERVER_TIMEOUT 500 +#define SERVER_TIMEOUT 3000 #define MAX_STRING_LEN 100 /* diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index 0dc9a5cd0686..54b23ee0a2be 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -178,6 +178,7 @@ struct msm_geni_serial_port { bool manual_flow; struct msm_geni_serial_ver_info ver_info; u32 cur_tx_remaining; + bool startup_in_progress; }; static const struct uart_ops msm_geni_serial_pops; @@ -1087,6 +1088,9 @@ static void start_rx_sequencer(struct uart_port *uport) int ret; u32 geni_se_param = UART_PARAM_RFR_OPEN; + if (port->startup_in_progress) + return; + geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS); if (geni_status & S_GENI_CMD_ACTIVE) { if (port->xfer_mode == SE_DMA && !port->rx_dma) { @@ -1847,6 +1851,8 @@ static int msm_geni_serial_startup(struct uart_port *uport) scnprintf(msm_port->name, sizeof(msm_port->name), "msm_serial_geni%d", uport->line); + msm_port->startup_in_progress = true; + if (likely(!uart_console(uport))) { ret = msm_geni_serial_power_on(&msm_port->uport); if (ret) { @@ -1896,6 +1902,8 @@ static int msm_geni_serial_startup(struct uart_port *uport) exit_startup: if (likely(!uart_console(uport))) msm_geni_serial_power_off(&msm_port->uport); + msm_port->startup_in_progress = false; + return ret; } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 38e1fa0b58a6..63685c0125d1 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2807,6 +2807,9 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, int chain; req = next_request(&dep->started_list); + if (req->trb->ctrl & DWC3_TRB_CTRL_HWO) + return 0; + length = req->request.length; chain = req->num_pending_sgs > 0; if (chain) { diff --git a/include/linux/dma-removed.h b/include/linux/dma-removed.h index a6a3caee6175..930dff3a4227 100644 --- a/include/linux/dma-removed.h +++ b/include/linux/dma-removed.h @@ -1,17 +1,15 @@ /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef __LINUX_DMA_REMOVED_H diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 66929d24c576..eeb98fd14c10 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2948,18 +2948,22 @@ void note_task_waking(struct task_struct *p, u64 wallclock); static inline bool task_placement_boost_enabled(struct task_struct *p) { - if (task_sched_boost(p)) - return sched_boost_policy() != SCHED_BOOST_NONE; + if (likely(sched_boost_policy() == SCHED_BOOST_NONE)) + return false; - return false; + return task_sched_boost(p); } - static inline enum sched_boost_policy task_boost_policy(struct task_struct *p) { - enum sched_boost_policy policy = task_sched_boost(p) ? - sched_boost_policy() : - SCHED_BOOST_NONE; + enum sched_boost_policy policy = sched_boost_policy(); + + if (likely(policy == SCHED_BOOST_NONE)) + return SCHED_BOOST_NONE; + + if (!task_sched_boost(p)) + return SCHED_BOOST_NONE; + if (policy == SCHED_BOOST_ON_BIG) { /* * Filter out tasks less than min task util threshold diff --git a/kernel/sched/tune.c b/kernel/sched/tune.c index 0124f9b03b84..51862ccdb719 100644 --- a/kernel/sched/tune.c +++ b/kernel/sched/tune.c @@ -184,9 +184,18 @@ void restore_cgroup_boost_settings(void) bool task_sched_boost(struct task_struct *p) { - struct schedtune *st = task_schedtune(p); + struct schedtune *st; + bool enabled; + + if (unlikely(!schedtune_initialized)) + return false; + + rcu_read_lock(); + st = task_schedtune(p); + enabled = st->sched_boost_enabled; + rcu_read_unlock(); - return st->sched_boost_enabled; + return enabled; } static u64 |