diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2020-05-25 11:27:46 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2020-05-25 11:52:17 +0800 |
| commit | 55d9939eb0c9d9d5e6a6a8fff8c56982f9f4fb21 (patch) | |
| tree | 1d0004ed5dae928d5e44bc63127b1748142c6463 | |
| parent | f290e661d30cbcbf5e1275d6c183299c66cf9d0d (diff) | |
soc: qcom: msm-spm: fix SPM start address setuplinaro-m3-2020_05_25
We are running into an issue with plug-off the last cpu in a cluster,
where L2 of the cluster will be power collapsed. It's caused by a bug
in function msm_spm_drv_set_start_addr().
As 'qcom,lpm-wa-skip-l2-spm' DT property indicates, we need to skip
programming L2 SPM enable bit as TZ is doing that as a workaround for
SDI fix. This is being well handled by lpm_wa_get_skip_l2_spm() check
in set_l2_mode() and the 'set_spm_enable' argument in
msm_spm_dev_set_low_power_mode(). However, the buggy
msm_spm_drv_set_start_addr() overwrites the whole setup with 'ctl',
where only the start address bits should be configured.
The 3.10 kernel does the right thing, configuring start address bits
with mask, so that SPM enable bit gets preserved. Let's fix the bug
by doing the same.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | drivers/soc/qcom/msm-spm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/soc/qcom/msm-spm.c b/drivers/soc/qcom/msm-spm.c index cad99d7ce355..79132b570ca4 100644 --- a/drivers/soc/qcom/msm-spm.c +++ b/drivers/soc/qcom/msm-spm.c @@ -179,7 +179,10 @@ static inline uint32_t msm_spm_drv_get_num_spm_entry( static inline void msm_spm_drv_set_start_addr( struct msm_spm_driver_data *dev, uint32_t ctl) { - dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] = ctl; + u32 addr_mask = 0x7f << 4; + + dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] &= ~addr_mask; + dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] |= ctl & addr_mask; } static inline bool msm_spm_pmic_arb_present(struct msm_spm_driver_data *dev) |