diff options
Diffstat (limited to 'meta-linaro-toolchain/recipes-core/glibc/glibc-linaro-2.20/eglibc-ppc8xx-cache-line-workaround.patch')
| -rw-r--r-- | meta-linaro-toolchain/recipes-core/glibc/glibc-linaro-2.20/eglibc-ppc8xx-cache-line-workaround.patch | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/meta-linaro-toolchain/recipes-core/glibc/glibc-linaro-2.20/eglibc-ppc8xx-cache-line-workaround.patch b/meta-linaro-toolchain/recipes-core/glibc/glibc-linaro-2.20/eglibc-ppc8xx-cache-line-workaround.patch deleted file mode 100644 index bb83d6d3..00000000 --- a/meta-linaro-toolchain/recipes-core/glibc/glibc-linaro-2.20/eglibc-ppc8xx-cache-line-workaround.patch +++ /dev/null @@ -1,68 +0,0 @@ -2007-06-13 Nathan Sidwell <nathan@codesourcery.com> - Mark Shinwell <shinwell@codesourcery.com> - - * sysdeps/unix/sysv/linux/powerpc/libc-start.c - (__libc_start_main): Detect 8xx parts and clear - __cache_line_size if detected. - * sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c - (DL_PLATFORM_AUXV): Likewise. - -Upstream-Status: Pending - -Index: git/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c -=================================================================== ---- git.orig/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c 2014-08-27 18:49:23.996070587 +0000 -+++ git/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c 2014-08-27 18:49:27.332070587 +0000 -@@ -24,9 +24,21 @@ - /* Scan the Aux Vector for the "Data Cache Block Size" entry. If found - verify that the static extern __cache_line_size is defined by checking - for not NULL. If it is defined then assign the cache block size -- value to __cache_line_size. */ -+ value to __cache_line_size. This is used by memset to -+ optimize setting to zero. We have to detect 8xx processors, which -+ have buggy dcbz implementations that cannot report page faults -+ correctly. That requires reading SPR, which is a privileged -+ operation. Fortunately 2.2.18 and later emulates PowerPC mfspr -+ reads from the PVR register. */ - #define DL_PLATFORM_AUXV \ - case AT_DCACHEBSIZE: \ -+ if (__LINUX_KERNEL_VERSION >= 0x020218) \ -+ { \ -+ unsigned pvr = 0; \ -+ asm ("mfspr %0, 287" : "=r" (pvr)); \ -+ if ((pvr & 0xffff0000) == 0x00500000) \ -+ break; \ -+ } \ - __cache_line_size = av->a_un.a_val; \ - break; - -Index: git/sysdeps/unix/sysv/linux/powerpc/libc-start.c -=================================================================== ---- git.orig/sysdeps/unix/sysv/linux/powerpc/libc-start.c 2014-08-27 18:49:23.996070587 +0000 -+++ git/sysdeps/unix/sysv/linux/powerpc/libc-start.c 2014-08-27 18:49:27.332070587 +0000 -@@ -68,11 +68,24 @@ - rtld_fini = NULL; - } - -- /* Initialize the __cache_line_size variable from the aux vector. */ -+ /* Initialize the __cache_line_size variable from the aux vector. -+ This is used by memset to optimize setting to zero. We have to -+ detect 8xx processors, which have buggy dcbz implementations that -+ cannot report page faults correctly. That requires reading SPR, -+ which is a privileged operation. Fortunately 2.2.18 and later -+ emulates PowerPC mfspr reads from the PVR register. */ - for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av) - switch (av->a_type) - { - case AT_DCACHEBSIZE: -+ if (__LINUX_KERNEL_VERSION >= 0x020218) -+ { -+ unsigned pvr = 0; -+ -+ asm ("mfspr %0, 287" : "=r" (pvr) :); -+ if ((pvr & 0xffff0000) == 0x00500000) -+ break; -+ } - __cache_line_size = av->a_un.a_val; - break; - } |