diff options
author | Koen Kooi <koen.kooi@linaro.org> | 2015-02-21 17:43:30 +0800 |
---|---|---|
committer | Koen Kooi <koen.kooi@linaro.org> | 2015-02-21 17:43:36 +0800 |
commit | b995735712b99d451c71e74199eeb181f0470da2 (patch) | |
tree | ebe026e6a3f4eec93dd296c1b1b92eeebf0db575 /meta-linaro-toolchain/recipes-devtools | |
parent | ae52ff9077050176bad1b5f12d28e90fbb87ad1b (diff) |
Revert "gcc-linaro-4.9: update to 2015.02 release"
This reverts commit 9ee5bfef065b1b93b5e1a2a222b4340c047f9d47.
Change-Id: Iaa902560304676f9551d9ea3d93ee177ca9bf812
Diffstat (limited to 'meta-linaro-toolchain/recipes-devtools')
11 files changed, 238 insertions, 538 deletions
diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9.inc b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9.inc index 758d1f44..d939a65c 100644 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9.inc +++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9.inc @@ -1,7 +1,7 @@ require recipes-devtools/gcc/gcc-4.9.inc PV = "linaro-${BASEPV}" -MMYY = "15.02" +MMYY = "15.01" RELEASE = "20${MMYY}" PR = "r${RELEASE}" BINV = "4.9.3" @@ -42,6 +42,7 @@ SRC_URI = "https://releases.linaro.org/${MMYY}/components/toolchain/gcc-linaro/$ file://0032-libtool.patch \ file://0033-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch \ file://0034-Use-the-multilib-config-files-from-B-instead-of-usin.patch \ + file://0037-gcc-4.8-PR56797.patch \ file://0040-fix-g++-sysroot.patch \ file://0041-libtool-avoid-libdir.patch \ file://0043-cpp.patch \ @@ -51,22 +52,19 @@ SRC_URI = "https://releases.linaro.org/${MMYY}/components/toolchain/gcc-linaro/$ file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \ file://0050-Revert-Use-dbx_reg_number-for-spanning-registers.patch \ file://0051-eabispe.patch \ - file://0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch \ + file://0052-Fix-GCC-targeting-E500-SPE-errors-with-the-_Decimal64-type.patch;apply=no \ file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \ file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \ - file://0055-dwarf-reg-processing-helper.patch \ - file://0056-define-default-cfa-register-mapping.patch \ - file://0057-aarch64-config.patch;apply=no \ + file://0055-PR-rtl-optimization-61801.patch;apply=no \ + file://0056-top-level-reorder_gcc-bug-61144.patch \ file://0058-gcc-r212171.patch \ file://0059-gcc-PR-rtl-optimization-63348.patch \ - file://0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch \ - file://0061-target-gcc-includedir.patch \ file://AArch64-Define-BE-loader-name-default-be.patch \ file://use-lib-for-aarch64.patch \ " -SRC_URI[md5sum] = "d88bac1e939278e2f859728121bac8f3" -SRC_URI[sha256sum] = "400db5574749e2c8e9460ffcb7b0ab4128d7f689fb7ea2d84b51cbf2dd94fd92" +SRC_URI[md5sum] = "5c1ae710e0445d5a6a840803f9ca7f84" +SRC_URI[sha256sum] = "169fb4d8ccf0ca975dbe137e2f5147d25087acf426174d5e8f38124b9df93505" S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}-${RELEASE}" B = "${WORKDIR}/gcc-${PV}-${RELEASE}/build.${HOST_SYS}.${TARGET_SYS}" diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0037-gcc-4.8-PR56797.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0037-gcc-4.8-PR56797.patch new file mode 100644 index 00000000..b5d7b864 --- /dev/null +++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0037-gcc-4.8-PR56797.patch @@ -0,0 +1,66 @@ +Upstream-Status: Backport +Signed-off-by: Khem Raj <raj.khem@gmail.com> + +From patchwork Fri Apr 19 09:34:49 2013 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [ARM] Fix PR56797 +Date: Thu, 18 Apr 2013 23:34:49 -0000 +From: Greta Yorsh <Greta.Yorsh@arm.com> +X-Patchwork-Id: 237891 +Message-Id: <000801ce3ce1$23fbdd60$6bf39820$@yorsh@arm.com> +To: "GCC Patches" <gcc-patches@gcc.gnu.org> +Cc: <raj.khem@gmail.com>, "Richard Earnshaw" <Richard.Earnshaw@arm.com>, + "Ramana Radhakrishnan" <Ramana.Radhakrishnan@arm.com> + +Fix PR56797 +http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56797 + +The problem is that peephole optimizer thinks it can generate an ldm, but +the pattern for ldm no longer matches, because after r188738 it requires +that if one of the destination registers is SP then the base register must +be SP, and it's not SP in the test case. + +The test case fails on armv5t but doesn't fail on armv6t2 or armv7-a because +peephole doesn't trigger there (because there is a different epilogue +sequence). It looks like a latent problem for other architecture or CPUs. + +This patch adds this condition to the peephole optimizer. + +No regression on qemu for arm-none-eabi and fixes the test reported in the +PR. I couldn't minimize the test sufficiently to include it in the +testsuite. + +Ok for trunk? + +Thanks, +Greta + +gcc/ + +2013-04-18 Greta Yorsh <Greta.Yorsh@arm.com> + + PR target/56797 + * config/arm/arm.c (load_multiple_sequence): Require SP + as base register for loads if SP is in the register list. + + +diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c +index d00849c..60fef78 100644 +--- a/gcc/config/arm/arm.c ++++ b/gcc/config/arm/arm.c +@@ -10347,6 +10347,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, + || (i != nops - 1 && unsorted_regs[i] == base_reg)) + return 0; + ++ /* Don't allow SP to be loaded unless it is also the base ++ register. It guarantees that SP is reset correctly when ++ an LDM instruction is interruptted. Otherwise, we might ++ end up with a corrupt stack. */ ++ if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) ++ return 0; ++ + unsorted_offsets[i] = INTVAL (offset); + if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) + order[0] = i; diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch deleted file mode 100644 index f6958b32..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch +++ /dev/null @@ -1,138 +0,0 @@ -From d626297e87e19251a284ea1e9360e831b48999ca Mon Sep 17 00:00:00 2001 -From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Thu, 4 Sep 2014 08:32:05 +0000 -Subject: [PATCH] Add target hook to override DWARF2 frame register size - -gcc/ - - * target.def (TARGET_DWARF_FRAME_REG_MODE): New target hook. - * targhooks.c (default_dwarf_frame_reg_mode): New function. - * targhooks.h (default_dwarf_frame_reg_mode): New prototype. - * doc/tm.texi.in (TARGET_DWARF_FRAME_REG_MODE): Document. - * doc/tm.texi: Regenerate. - * dwarf2cfi.c (expand_builtin_init_dwarf_reg_sizes): Abstract mode - selection logic to default_dwarf_frame_reg_mode. - - - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214898 138bc75d-0d04-0410-961f-82ee72b054a4 - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Upstream-Status: Backport [gcc 5.0] - ---- - gcc/ChangeLog | 10 ++++++++++ - gcc/doc/tm.texi | 7 +++++++ - gcc/doc/tm.texi.in | 2 ++ - gcc/dwarf2cfi.c | 4 +--- - gcc/target.def | 11 +++++++++++ - gcc/targhooks.c | 13 +++++++++++++ - gcc/targhooks.h | 1 + - 7 files changed, 45 insertions(+), 3 deletions(-) - -Index: gcc-4.9.2/gcc/doc/tm.texi -=================================================================== ---- gcc-4.9.2.orig/gcc/doc/tm.texi -+++ gcc-4.9.2/gcc/doc/tm.texi -@@ -9017,6 +9017,13 @@ register in Dwarf. Otherwise, this hook - If not defined, the default is to return @code{NULL_RTX}. - @end deftypefn - -+@deftypefn {Target Hook} {enum machine_mode} TARGET_DWARF_FRAME_REG_MODE (int @var{regno}) -+Given a register, this hook should return the mode which the -+corresponding Dwarf frame register should have. This is normally -+used to return a smaller mode than the raw mode to prevent call -+clobbered parts of a register altering the frame register size -+@end deftypefn -+ - @deftypefn {Target Hook} void TARGET_INIT_DWARF_REG_SIZES_EXTRA (tree @var{address}) - If some registers are represented in Dwarf-2 unwind information in - multiple pieces, define this hook to fill in information about the -Index: gcc-4.9.2/gcc/doc/tm.texi.in -=================================================================== ---- gcc-4.9.2.orig/gcc/doc/tm.texi.in -+++ gcc-4.9.2/gcc/doc/tm.texi.in -@@ -6745,6 +6745,8 @@ the target supports DWARF 2 frame unwind - - @hook TARGET_DWARF_REGISTER_SPAN - -+@hook TARGET_DWARF_FRAME_REG_MODE -+ - @hook TARGET_INIT_DWARF_REG_SIZES_EXTRA - - @hook TARGET_ASM_TTYPE -Index: gcc-4.9.2/gcc/dwarf2cfi.c -=================================================================== ---- gcc-4.9.2.orig/gcc/dwarf2cfi.c -+++ gcc-4.9.2/gcc/dwarf2cfi.c -@@ -271,11 +271,9 @@ expand_builtin_init_dwarf_reg_sizes (tre - if (rnum < DWARF_FRAME_REGISTERS) - { - HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode); -- enum machine_mode save_mode = reg_raw_mode[i]; - HOST_WIDE_INT size; -+ enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i); - -- if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode)) -- save_mode = choose_hard_reg_mode (i, 1, true); - if (dnum == DWARF_FRAME_RETURN_COLUMN) - { - if (save_mode == VOIDmode) -Index: gcc-4.9.2/gcc/target.def -=================================================================== ---- gcc-4.9.2.orig/gcc/target.def -+++ gcc-4.9.2/gcc/target.def -@@ -3218,6 +3218,17 @@ If not defined, the default is to return - rtx, (rtx reg), - hook_rtx_rtx_null) - -+/* Given a register return the mode of the corresponding DWARF frame -+ register. */ -+DEFHOOK -+(dwarf_frame_reg_mode, -+ "Given a register, this hook should return the mode which the\n\ -+corresponding Dwarf frame register should have. This is normally\n\ -+used to return a smaller mode than the raw mode to prevent call\n\ -+clobbered parts of a register altering the frame register size", -+ enum machine_mode, (int regno), -+ default_dwarf_frame_reg_mode) -+ - /* If expand_builtin_init_dwarf_reg_sizes needs to fill in table - entries not corresponding directly to registers below - FIRST_PSEUDO_REGISTER, this hook should generate the necessary -Index: gcc-4.9.2/gcc/targhooks.c -=================================================================== ---- gcc-4.9.2.orig/gcc/targhooks.c -+++ gcc-4.9.2/gcc/targhooks.c -@@ -1438,6 +1438,19 @@ default_debug_unwind_info (void) - return UI_NONE; - } - -+/* Determine the correct mode for a Dwarf frame register that represents -+ register REGNO. */ -+ -+enum machine_mode -+default_dwarf_frame_reg_mode (int regno) -+{ -+ enum machine_mode save_mode = reg_raw_mode[regno]; -+ -+ if (HARD_REGNO_CALL_PART_CLOBBERED (regno, save_mode)) -+ save_mode = choose_hard_reg_mode (regno, 1, true); -+ return save_mode; -+} -+ - /* To be used by targets where reg_raw_mode doesn't return the right - mode for registers used in apply_builtin_return and apply_builtin_arg. */ - -Index: gcc-4.9.2/gcc/targhooks.h -=================================================================== ---- gcc-4.9.2.orig/gcc/targhooks.h -+++ gcc-4.9.2/gcc/targhooks.h -@@ -194,6 +194,7 @@ extern int default_label_align_max_skip - extern int default_jump_align_max_skip (rtx); - extern section * default_function_section(tree decl, enum node_frequency freq, - bool startup, bool exit); -+extern enum machine_mode default_dwarf_frame_reg_mode (int); - extern enum machine_mode default_get_reg_raw_mode (int); - - extern void *default_get_pch_validity (size_t *); diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Fix-GCC-targeting-E500-SPE-errors-with-the-_Decimal64-type.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Fix-GCC-targeting-E500-SPE-errors-with-the-_Decimal64-type.patch new file mode 100644 index 00000000..b4be18e2 --- /dev/null +++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0052-Fix-GCC-targeting-E500-SPE-errors-with-the-_Decimal64-type.patch @@ -0,0 +1,98 @@ +From e44a6d438db4848c2a555be773568a3cf7994206 Mon Sep 17 00:00:00 2001 +From: Alexandru-Cezar Sardan <alexandru.sardan-KZfg59tc24xl57MIdRCFDg@public.gmane.org> +Date: Mon, 26 May 2014 12:11:13 +0300 +Subject: [PATCH] Fix E500 with SPE errors with the _Decimal64 type + +[gcc] +2014-04-21 Michael Meissner <meissner-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org> + + PR target/60735 + * config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64 case): + If mode is DDmode and TARGET_E500_DOUBLE allow move. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some + more debug information for E500 if -mdebug=reg. + +[gcc/testsuite] +2014-04-21 Michael Meissner <meissner-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org> + + PR target/60735 + * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does + not cause errors if -mspe. + +Upstream status: Accepted + +This solves upstream bug 60735 +(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60735). + +Patch taken from https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=209664 +--- + gcc/config/rs6000/rs6000.c | 18 ++++++++++++++++++ + gcc/config/rs6000/rs6000.md | 3 ++- + gcc/testsuite/gcc.target/powerpc/pr60735.c | 11 +++++++++++ + 3 files changed, 31 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/powerpc/pr60735.c + +diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c +index 494efc5..6dcf440 100644 +--- a/gcc/config/rs6000/rs6000.c ++++ b/gcc/config/rs6000/rs6000.c +@@ -2283,6 +2283,24 @@ rs6000_debug_reg_global (void) + if (rs6000_float_gprs) + fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + ++ fprintf (stderr, DEBUG_FMT_S, "fprs", ++ (TARGET_FPRS ? "true" : "false")); ++ ++ fprintf (stderr, DEBUG_FMT_S, "single_float", ++ (TARGET_SINGLE_FLOAT ? "true" : "false")); ++ ++ fprintf (stderr, DEBUG_FMT_S, "double_float", ++ (TARGET_DOUBLE_FLOAT ? "true" : "false")); ++ ++ fprintf (stderr, DEBUG_FMT_S, "soft_float", ++ (TARGET_SOFT_FLOAT ? "true" : "false")); ++ ++ fprintf (stderr, DEBUG_FMT_S, "e500_single", ++ (TARGET_E500_SINGLE ? "true" : "false")); ++ ++ fprintf (stderr, DEBUG_FMT_S, "e500_double", ++ (TARGET_E500_DOUBLE ? "true" : "false")); ++ + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + +diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md +index 64c9e7c..9cefe15 100644 +--- a/gcc/config/rs6000/rs6000.md ++++ b/gcc/config/rs6000/rs6000.md +@@ -9395,7 +9395,8 @@ + (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] + "! TARGET_POWERPC64 + && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) +- || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) ++ || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE ++ || (<MODE>mode == DDmode && TARGET_E500_DOUBLE)) + && (gpc_reg_operand (operands[0], <MODE>mode) + || gpc_reg_operand (operands[1], <MODE>mode))" + "#" +diff --git a/gcc/testsuite/gcc.target/powerpc/pr60735.c b/gcc/testsuite/gcc.target/powerpc/pr60735.c +new file mode 100644 +index 0000000..9bac30b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/powerpc/pr60735.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */ ++/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ ++ ++/* In PR60735, the type _Decimal64 generated an insn not found message. */ ++ ++void ++pr60735 (_Decimal64 *p, _Decimal64 *q) ++{ ++ *p = *q; ++} +-- +1.7.9.5 + diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-PR-rtl-optimization-61801.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-PR-rtl-optimization-61801.patch new file mode 100644 index 00000000..b27abdef --- /dev/null +++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-PR-rtl-optimization-61801.patch @@ -0,0 +1,36 @@ +From 556537c4ad0df4cbebb74197bb2bdea75cf5dd35 Mon Sep 17 00:00:00 2001 +From: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4> +Date: Thu, 17 Jul 2014 07:48:49 +0000 +Subject: [PATCH] 2014-07-17 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/61801 + * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and + ASM_INPUT don't set reg_pending_barrier if it appears in a + debug-insn. + + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212739 138bc75d-0d04-0410-961f-82ee72b054a4 + +Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801] +Signed-off-by: Peter A. Bigot <pab@pabigot.com> + +--- + gcc/sched-deps.c | 3 ++- + +diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c +index efc4223..df29bd3 100644 +--- a/gcc/sched-deps.c ++++ b/gcc/sched-deps.c +@@ -2750,7 +2750,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn) + Consider for instance a volatile asm that changes the fpu rounding + mode. An insn should not be moved across this even if it only uses + pseudo-regs because it might give an incorrectly rounded result. */ +- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) ++ if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x)) ++ && !DEBUG_INSN_P (insn)) + reg_pending_barrier = TRUE_BARRIER; + + /* For all ASM_OPERANDS, we must traverse the vector of input operands. +-- +1.8.5.5 + diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-dwarf-reg-processing-helper.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-dwarf-reg-processing-helper.patch deleted file mode 100644 index 557dab0f..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0055-dwarf-reg-processing-helper.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 4fd39f1329379e00f958394adde6be96f0caf21f Mon Sep 17 00:00:00 2001 -From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Fri, 5 Dec 2014 16:53:22 +0000 -Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com> - - * dwarf2cfi.c (init_one_dwarf_reg_size): New helper, processing - one particular reg for expand_builtin_init_dwarf_reg_sizes. - (expand_builtin_init_dwarf_reg_sizes): Rework to use helper and - account for dwarf register spans. - - - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218428 138bc75d-0d04-0410-961f-82ee72b054a4 - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Upstream-Status: Backport [gcc 5.0] - ---- - gcc/ChangeLog | 7 +++++ - gcc/dwarf2cfi.c | 98 +++++++++++++++++++++++++++++++++++++++++++++------------ - 2 files changed, 85 insertions(+), 20 deletions(-) - -Index: gcc-4.9.2/gcc/dwarf2cfi.c -=================================================================== ---- gcc-4.9.2.orig/gcc/dwarf2cfi.c -+++ gcc-4.9.2/gcc/dwarf2cfi.c -@@ -252,7 +252,59 @@ init_return_column_size (enum machine_mo - gen_int_mode (size, mode)); - } - --/* Generate code to initialize the register size table. */ -+/* Datastructure used by expand_builtin_init_dwarf_reg_sizes and -+ init_one_dwarf_reg_size to communicate on what has been done by the -+ latter. */ -+ -+typedef struct -+{ -+ /* Whether the dwarf return column was initialized. */ -+ bool wrote_return_column; -+ -+ /* For each hard register REGNO, whether init_one_dwarf_reg_size -+ was given REGNO to process already. */ -+ bool processed_regno [FIRST_PSEUDO_REGISTER]; -+ -+} init_one_dwarf_reg_state; -+ -+/* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to -+ initialize the dwarf register size table entry corresponding to register -+ REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to -+ use for the size entry to initialize, and INIT_STATE is the communication -+ datastructure conveying what we're doing to our caller. */ -+ -+static -+void init_one_dwarf_reg_size (int regno, machine_mode regmode, -+ rtx table, machine_mode slotmode, -+ init_one_dwarf_reg_state *init_state) -+{ -+ const unsigned int dnum = DWARF_FRAME_REGNUM (regno); -+ const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); -+ -+ const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode); -+ const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode); -+ -+ init_state->processed_regno[regno] = true; -+ -+ if (rnum >= DWARF_FRAME_REGISTERS) -+ return; -+ -+ if (dnum == DWARF_FRAME_RETURN_COLUMN) -+ { -+ if (regmode == VOIDmode) -+ return; -+ init_state->wrote_return_column = true; -+ } -+ -+ if (slotoffset < 0) -+ return; -+ -+ emit_move_insn (adjust_address (table, slotmode, slotoffset), -+ gen_int_mode (regsize, slotmode)); -+} -+ -+/* Generate code to initialize the dwarf register size table located -+ at the provided ADDRESS. */ - - void - expand_builtin_init_dwarf_reg_sizes (tree address) -@@ -261,35 +313,40 @@ expand_builtin_init_dwarf_reg_sizes (tre - enum machine_mode mode = TYPE_MODE (char_type_node); - rtx addr = expand_normal (address); - rtx mem = gen_rtx_MEM (BLKmode, addr); -- bool wrote_return_column = false; -+ -+ init_one_dwarf_reg_state init_state; -+ -+ memset ((char *)&init_state, 0, sizeof (init_state)); - - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - { -- unsigned int dnum = DWARF_FRAME_REGNUM (i); -- unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); -- -- if (rnum < DWARF_FRAME_REGISTERS) -- { -- HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode); -- HOST_WIDE_INT size; -- enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i); -+ machine_mode save_mode; -+ rtx span; - -- if (dnum == DWARF_FRAME_RETURN_COLUMN) -+ /* No point in processing a register multiple times. This could happen -+ with register spans, e.g. when a reg is first processed as a piece of -+ a span, then as a register on its own later on. */ -+ -+ if (init_state.processed_regno[i]) -+ continue; -+ -+ save_mode = targetm.dwarf_frame_reg_mode (i); -+ span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); -+ if (!span) -+ init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); -+ else -+ { -+ for (int si = 0; si < XVECLEN (span, 0); si++) - { -- if (save_mode == VOIDmode) -- continue; -- wrote_return_column = true; -- } -- size = GET_MODE_SIZE (save_mode); -- if (offset < 0) -- continue; -+ rtx reg = XVECEXP (span, 0, si); -+ init_one_dwarf_reg_size -+ (REGNO (reg), GET_MODE (reg), mem, mode, &init_state); -+ } - -- emit_move_insn (adjust_address (mem, mode, offset), -- gen_int_mode (size, mode)); - } - } - -- if (!wrote_return_column) -+ if (!init_state.wrote_return_column) - init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); - - #ifdef DWARF_ALT_FRAME_RETURN_COLUMN diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-define-default-cfa-register-mapping.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-define-default-cfa-register-mapping.patch deleted file mode 100644 index 3b6c94c4..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-define-default-cfa-register-mapping.patch +++ /dev/null @@ -1,75 +0,0 @@ -From c0235a33de8c4f78cce35b2a8c2035c83fe1bd14 Mon Sep 17 00:00:00 2001 -From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Fri, 5 Dec 2014 17:01:42 +0000 -Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com> - - gcc/ - * defaults.h: (DWARF_REG_TO_UNWIND_COLUMN): Define default. - * dwarf2cfi.c (init_one_dwarf_reg_size): Honor - DWARF_REG_TO_UNWIND_COLUMN. - - libgcc/ - * unwind-dw2.c (DWARF_REG_TO_UNWIND_COLUMN): Remove default def, - now provided by defaults.h. - - - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218429 138bc75d-0d04-0410-961f-82ee72b054a4 - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Upstream-Status: Backport [gcc 5.0] - ---- - gcc/ChangeLog | 6 ++++++ - gcc/defaults.h | 5 +++++ - gcc/dwarf2cfi.c | 3 ++- - libgcc/ChangeLog | 5 +++++ - libgcc/unwind-dw2.c | 4 ---- - 5 files changed, 18 insertions(+), 5 deletions(-) - -Index: gcc-4.9.2/gcc/defaults.h -=================================================================== ---- gcc-4.9.2.orig/gcc/defaults.h -+++ gcc-4.9.2/gcc/defaults.h -@@ -438,6 +438,11 @@ see the files COPYING3 and COPYING.RUNTI - #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG) - #endif - -+/* The mapping from dwarf CFA reg number to internal dwarf reg numbers. */ -+#ifndef DWARF_REG_TO_UNWIND_COLUMN -+#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO) -+#endif -+ - /* Map register numbers held in the call frame info that gcc has - collected using DWARF_FRAME_REGNUM to those that should be output in - .debug_frame and .eh_frame. */ -Index: gcc-4.9.2/gcc/dwarf2cfi.c -=================================================================== ---- gcc-4.9.2.orig/gcc/dwarf2cfi.c -+++ gcc-4.9.2/gcc/dwarf2cfi.c -@@ -280,8 +280,9 @@ void init_one_dwarf_reg_size (int regno, - { - const unsigned int dnum = DWARF_FRAME_REGNUM (regno); - const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); -+ const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum); - -- const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode); -+ const HOST_WIDE_INT slotoffset = dcol * GET_MODE_SIZE (slotmode); - const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode); - - init_state->processed_regno[regno] = true; -Index: gcc-4.9.2/libgcc/unwind-dw2.c -=================================================================== ---- gcc-4.9.2.orig/libgcc/unwind-dw2.c -+++ gcc-4.9.2/libgcc/unwind-dw2.c -@@ -55,10 +55,6 @@ - #define PRE_GCC3_DWARF_FRAME_REGISTERS DWARF_FRAME_REGISTERS - #endif - --#ifndef DWARF_REG_TO_UNWIND_COLUMN --#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO) --#endif -- - /* ??? For the public function interfaces, we tend to gcc_assert that the - column numbers are in range. For the dwarf2 unwind info this does happen, - although so far in a case that doesn't actually matter. diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-top-level-reorder_gcc-bug-61144.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-top-level-reorder_gcc-bug-61144.patch new file mode 100644 index 00000000..f4489325 --- /dev/null +++ b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0056-top-level-reorder_gcc-bug-61144.patch @@ -0,0 +1,31 @@ + +Upstream-Status: Backport + +Originally-submitted-by: Peter Urbanec <openembedded-devel@urbanec.net> +Signed-off-by: Saul Wold <sgw@linux.intel.com> + +--- /dev/null ++++ b/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch +@@ -0,0 +1,21 @@ ++--- a/gcc/varpool.c 2014/10/05 02:50:01 215895 +++++ b/gcc/varpool.c 2014/10/05 04:52:19 215896 ++@@ -329,8 +329,16 @@ ++ ++ /* Variables declared 'const' without an initializer ++ have zero as the initializer if they may not be ++- overridden at link or run time. */ ++- if (!DECL_INITIAL (real_decl) +++ overridden at link or run time. +++ +++ It is actually requirement for C++ compiler to optimize const variables +++ consistently. As a GNU extension, do not enfore this rule for user defined +++ weak variables, so we support interposition on: +++ static const int dummy = 0; +++ extern const int foo __attribute__((__weak__, __alias__("dummy"))); +++ */ +++ if ((!DECL_INITIAL (real_decl) +++ || (DECL_WEAK (decl) && !DECL_COMDAT (decl))) ++ && (DECL_EXTERNAL (decl) || decl_replaceable_p (decl))) ++ return error_mark_node; ++ + diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0057-aarch64-config.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0057-aarch64-config.patch deleted file mode 100644 index f2955969..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0057-aarch64-config.patch +++ /dev/null @@ -1,32 +0,0 @@ -Disable the MULTILIB_OSDIRNAMES and other multilib options. - -Hard coding the MULTILIB_OSDIRNAMES with ../lib64 is causing problems on -systems where the libdir is NOT set to /lib64. This is allowed by the ABI, as -long as the dynamic loader is present in /lib. - -We simply want to use the default rules in gcc to find and configure the -normal libdir. - -Signed-off-by: Mark Hatle <mark.hatle@windriver.com> - -Index: gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux -=================================================================== ---- gcc-4.9.1.orig/gcc/config/aarch64/t-aarch64-linux -+++ gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux -@@ -21,11 +21,11 @@ - LIB1ASMSRC = aarch64/lib1funcs.asm - LIB1ASMFUNCS = _aarch64_sync_cache_range - --AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be) --MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu) --MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu) -+#AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be) -+#MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu) -+#MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu) - - # Disable the multilib for linux-gnu targets for the time being; focus - # on the baremetal targets. --MULTILIB_OPTIONS = --MULTILIB_DIRNAMES = -+#MULTILIB_OPTIONS = -+#MULTILIB_DIRNAMES = diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch deleted file mode 100644 index 75a9fdd4..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 5c0092070253113cf0d9c45eacc884b3ecc34d81 Mon Sep 17 00:00:00 2001 -From: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Sat, 25 Oct 2014 00:23:17 +0000 -Subject: [PATCH] Only allow e500 double in SPE_SIMD_REGNO_P registers. - -rs6000_hard_regno_nregs_internal allows SPE vectors in single -registers satisfying SPE_SIMD_REGNO_P (i.e. register numbers 0 to -31). However, the corresponding test for e500 double treats all -registers as being able to store a 64-bit value, rather than just -those GPRs. - -Logically this inconsistency is wrong; in addition, it causes problems -unwinding from signal handlers. linux-unwind.h uses -ARG_POINTER_REGNUM as a place to store the return address from a -signal handler, but this logic in rs6000_hard_regno_nregs_internal -results in that being considered an 8-byte register, resulting in -assertion failures. -(<https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02625.html> first -needs to be applied for unwinding to work in general on e500.) This -patch makes rs6000_hard_regno_nregs_internal handle the e500 double -case consistently with SPE vectors. - -Tested with no regressions with cross to powerpc-linux-gnuspe (given -the aforementioned patch applied). Failures of signal handling -unwinding tests such as gcc.dg/cleanup-{8,9,10,11}.c are fixed by this -patch. - - * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Do - not allow e500 double in registers not satisyfing - SPE_SIMD_REGNO_P. - - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216688 138bc75d-0d04-0410-961f-82ee72b054a4 - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Upstream-Status: Backport [gcc 5.0] - ---- - gcc/ChangeLog | 6 ++++++ - gcc/config/rs6000/rs6000.c | 2 +- - 2 files changed, 7 insertions(+), 1 deletion(-) - -Index: gcc-4.9.2/gcc/config/rs6000/rs6000.c -=================================================================== ---- gcc-4.9.2.orig/gcc/config/rs6000/rs6000.c -+++ gcc-4.9.2/gcc/config/rs6000/rs6000.c -@@ -1703,7 +1703,7 @@ rs6000_hard_regno_nregs_internal (int re - SCmode so as to pass the value correctly in a pair of - registers. */ - else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode -- && !DECIMAL_FLOAT_MODE_P (mode)) -+ && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno)) - reg_size = UNITS_PER_FP_WORD; - - else diff --git a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0061-target-gcc-includedir.patch b/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0061-target-gcc-includedir.patch deleted file mode 100644 index f48c66dc..00000000 --- a/meta-linaro-toolchain/recipes-devtools/gcc/gcc-linaro-4.9/0061-target-gcc-includedir.patch +++ /dev/null @@ -1,81 +0,0 @@ -Ensure target gcc headers can be included - -There are a few headers installed as part of the OpenEmbedded -gcc-runtime target (omp.h, ssp/*.h). Being installed from a recipe -built for the target architecture, these are within the target -sysroot and not cross/nativesdk; thus they weren't able to be -found by gcc with the existing search paths. Add support for -picking up these headers under the sysroot supplied on the gcc -command line in order to resolve this. - -Signed-off-by: Paul Eggleton <paul.eggleton@linux.intel.com> - -Upstream-Status: Pending - ---- a/gcc/Makefile.in 2014-12-23 11:57:33.327873331 +0000 -+++ b/gcc/Makefile.in 2015-01-21 11:32:35.447305394 +0000 -@@ -587,6 +587,7 @@ - - # Directory in which the compiler finds libraries etc. - libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(version) -+libsubdir_target = gcc/$(target_noncanonical)/$(version) - # Directory in which the compiler finds executables - libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(version) - # Directory in which all plugin resources are installed -@@ -2534,6 +2535,7 @@ - - PREPROCESSOR_DEFINES = \ - -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ -+ -DGCC_INCLUDE_SUBDIR_TARGET=\"$(libsubdir_target)/include\" \ - -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ - -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ - -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ ---- a/gcc/cppdefault.c 2015-01-13 17:40:26.131012725 +0000 -+++ b/gcc/cppdefault.c 2015-01-21 11:30:08.928426492 +0000 -@@ -59,6 +59,10 @@ - /* This is the dir for gcc's private headers. */ - { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 }, - #endif -+#ifdef GCC_INCLUDE_SUBDIR_TARGET -+ /* This is the dir for gcc's private headers under the specified sysroot. */ -+ { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0 }, -+#endif - #ifdef LOCAL_INCLUDE_DIR - /* /usr/local/include comes before the fixincluded header files. */ - { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, -diff --git a/gcc/defaults.h b/gcc/defaults.h -index f94ae17..d98b40b 100644 ---- a/gcc/defaults.h -+++ b/gcc/defaults.h -@@ -1390,4 +1390,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - - #endif /* GCC_INSN_FLAGS_H */ - -+/* Default prefixes to attach to command names. */ -+ -+#ifndef STANDARD_STARTFILE_PREFIX_1 -+#define STANDARD_STARTFILE_PREFIX_1 "/lib/" -+#endif -+#ifndef STANDARD_STARTFILE_PREFIX_2 -+#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib/" -+#endif -+ - #endif /* ! GCC_DEFAULTS_H */ -diff --git a/gcc/gcc.c b/gcc/gcc.c -index 9f0b781..174fca8 100644 ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -1189,13 +1189,6 @@ static const char *gcc_libexec_prefix; - - /* Default prefixes to attach to command names. */ - --#ifndef STANDARD_STARTFILE_PREFIX_1 --#define STANDARD_STARTFILE_PREFIX_1 "/lib/" --#endif --#ifndef STANDARD_STARTFILE_PREFIX_2 --#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib/" --#endif -- - #ifdef CROSS_DIRECTORY_STRUCTURE /* Don't use these prefixes for a cross compiler. */ - #undef MD_EXEC_PREFIX - #undef MD_STARTFILE_PREFIX |