From d2a2d3f4f3d5ebc4c29598b4beac01abd8c4c55e Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 3 Feb 2016 13:13:16 +0800 Subject: clk: hi6220: Add RTC clock for pl031 Adds clk support for the pl031 RTC on hi6220 Signed-off-by: John Stultz --- drivers/clk/hisilicon/clk-hi6220.c | 1 + include/dt-bindings/clock/hi6220-clock.h | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 4563343b6420..a886e46f7b4c 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -68,6 +68,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, }, { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, }, { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, + { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, }, }; static void __init hi6220_clk_ao_init(struct device_node *np) diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 70ee3833a7a0..8df5a24b6f9a 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -55,8 +55,8 @@ #define HI6220_TIMER7_PCLK 34 #define HI6220_TIMER8_PCLK 35 #define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 +#define HI6220_RTC0_PCLK 41 +#define HI6220_AO_NR_CLKS 48 /* clk in Hi6220 systrl */ /* gate clock */ -- cgit v1.2.3 From ac71dbb1da65894b9578d2e5578efafb065c71ee Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 12 Mar 2015 21:38:52 -0400 Subject: drivers/clk: hi6220: initialize UART1 clock to 150MHz Early at boot, during the sys_clk initialization, make sure UART1 uses the higher frequency clock. This enables support for higher baud rates (up to 3Mbps) required to support faster bluetooth transfers. Signed-off-by: Jorge Ramirez-Ortiz Conflicts: drivers/clk/hisilicon/clk-hi6220.c --- drivers/clk/hisilicon/clk-hi6220.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index a886e46f7b4c..4593bd706c97 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -71,22 +72,25 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, }, }; +static struct hisi_clock_data *clk_data_ao; + static void __init hi6220_clk_ao_init(struct device_node *np) { - struct hisi_clock_data *clk_data_ao; - clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, - ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); + ARRAY_SIZE(hi6220_fixed_rate_clks), + clk_data_ao); hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks, - ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao); + ARRAY_SIZE(hi6220_fixed_factor_clks), + clk_data_ao); hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, - ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); + ARRAY_SIZE(hi6220_separated_gate_clks_ao), + clk_data_ao); } CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); @@ -193,6 +197,13 @@ static void __init hi6220_clk_sys_init(struct device_node *np) hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); + + if (!clk_data_ao) + return; + + /* enable high speed clock on UART1 mux */ + clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], + clk_data_ao->clk_data.clks[HI6220_150M]); } CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init); -- cgit v1.2.3 From 796d7889a93b6a2414bccdba3563deb343ce6a43 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 25 Jul 2015 21:06:39 +0800 Subject: clk: hi6220: change syspll and med_syspll to what PERIPH_STAT1 returns To major changes: 1. The way to read PERI_SC_PERIPH_STAT1 should be split into two word (2-byte) parts. 2. msleep(1) is required between PERI_SC_PERIPH_CTRL14 write and PERI_SC_PERIPH_STAT1 read. 3. syspll and med_syspll need to be changed together. 4. ddrpll doesn't need to be changed. Keep it at 1.2G. Tests are done using a LG TV on all four settings. Model no.: LG 37LK460-CC ATF/UEFI w/ syspll @ 1.2G ATF/UEFI w/ syspll @ 1.19G fastboot w/ syspll @ 1.2G fastboot w/ syspll @ 1.19G Signed-off-by: Guodong Xu Signed-off-by: John Stultz --- drivers/clk/hisilicon/clk-hi6220.c | 50 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 4593bd706c97..30acdf5a50f3 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -14,7 +14,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -35,8 +37,8 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 245760000, }, { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 1000000000,}, { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 1066000000,}, - { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1200000000,}, - { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1200000000,}, + { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1190494208,}, + { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1190494208,}, { HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1200000000,}, { HI6220_PLL_MEDIA, "media_pll", NULL, CLK_IS_ROOT, 1440000000,}, { HI6220_PLL_DDR, "ddrpll0", NULL, CLK_IS_ROOT, 1600000000,}, @@ -72,14 +74,58 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, }, }; +#define SOC_PERI_SCTRL_BASE_ADDR 0xF7030000 /* peri ctrl base addr */ +#define SC_PERIPH_CTRL14 0x02C +#define SC_PERIPH_STAT1 0x094 +#define SOC_PMCTRL_BASE_ADDR 0xF7032000 /* pm ctrl base addr*/ +#define SC_PM_DDRPLL_STAT 0x18 +#define SC_PM_SYSPLL_STAT 0x28 +#define SC_PM_MEDPLL_STAT 0x38 + static struct hisi_clock_data *clk_data_ao; static void __init hi6220_clk_ao_init(struct device_node *np) { + void __iomem *peri_base, *pm_base; + unsigned int freq_u, freq_l, freq, pll_stat; + int i; + clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; + peri_base = ioremap(SOC_PERI_SCTRL_BASE_ADDR, 0x1000); + pm_base = ioremap(SOC_PMCTRL_BASE_ADDR, 0x1000); + /* SYSPLL is set by bootloader. Read it */ + /* check syspll enablement status */ + pll_stat = readl(pm_base + SC_PM_SYSPLL_STAT); + pr_info("SYSPLL: syspll PM status: 0x%x\n", pll_stat); + /* 0x2101 means to calculate clk_sys_pll */ + writew(0x2101, peri_base + SC_PERIPH_CTRL14); + mdelay(1); + /* read back the calculated value */ + freq_l = readw(peri_base + SC_PERIPH_STAT1); + freq_u = readw(peri_base + SC_PERIPH_STAT1 + 2); + mdelay(1); + freq = freq_u << 16 | freq_l; + pr_info("SYSPLL: syspll is read: l: 0x%04X, u: 0x%04X\n", + freq_l, freq_u); + pr_info("SYSPLL: syspll is read: 0x%X, %d\n", freq, freq); + if (freq == 0x00020000 || freq == 0) { + pr_info("SYSPLL: ERROR: read returns misterious value.\n"); + freq = 1200000000; + } + pr_info("SYSPLL: set syspll medpll: %d\n", freq); + + for (i = 0; i < ARRAY_SIZE(hi6220_fixed_rate_clks); i++) { + if (hi6220_fixed_rate_clks[i].id == HI6220_PLL_SYS || + hi6220_fixed_rate_clks[i].id == HI6220_PLL_SYS_MEDIA) { + hi6220_fixed_rate_clks[i].fixed_rate = freq; + pr_info("SYSPLL: modified fix_rate[%d], id=%d, f=%d\n", + i, hi6220_fixed_rate_clks[i].id, freq); + } + } + hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); -- cgit v1.2.3 From 70e64ffbd629d9aa5f75c63f94b3614fe2c2d058 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 12 Sep 2015 08:14:14 +0800 Subject: clk: hi6220: mark off lower five decimal number of SYSPLL Signed-off-by: Guodong Xu Signed-off-by: John Stultz --- drivers/clk/hisilicon/clk-hi6220.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 30acdf5a50f3..fe5ec1d0a11b 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -115,6 +115,9 @@ static void __init hi6220_clk_ao_init(struct device_node *np) pr_info("SYSPLL: ERROR: read returns misterious value.\n"); freq = 1200000000; } + + /* mask off freq */ + freq -= (freq % 100000); pr_info("SYSPLL: set syspll medpll: %d\n", freq); for (i = 0; i < ARRAY_SIZE(hi6220_fixed_rate_clks); i++) { -- cgit v1.2.3 From 90187ddd3ec77641da822cc4fe59818d5e4f39dd Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sat, 21 Jan 2017 10:26:31 +0800 Subject: clk: hisilicon: fix lock assignment In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/clkgate-separated.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index a47812f56a17..7908bc3c9ec7 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->bit_idx = bit_idx; sclk->flags = clk_gate_flags; sclk->hw.init = &init; + sclk->lock = lock; clk = clk_register(dev, &sclk->hw); if (IS_ERR(clk)) -- cgit v1.2.3 From 112ddbfac9eb61174824c5f9acb94873ed617f7c Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 21 Jan 2016 18:53:47 +0800 Subject: arm64: dts: Reserve memory regions for hi6220 On Hi6220, below memory regions in DDR have specific purpose: 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime; 0x06df,f000 - 0x06df,ffff: For mailbox message data; 0x0740,f000 - 0x0740,ffff: For MCU firmware's section; 0x3e00,0000 - 0x3fff,ffff: For OP-TEE. This patch reserves these memory regions in DT. Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 8d43a0fce522..1997e4df3ffe 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -7,9 +7,6 @@ /dts-v1/; -/*Reserved 1MB memory for MCU*/ -/memreserve/ 0x05e00000 0x00100000; - #include "hi6220.dtsi" / { @@ -27,8 +24,19 @@ stdout-path = "serial3:115200n8"; }; + /* + * Reserve below regions from memory node: + * + * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using + * 0x06df,f000 - 0x06df,ffff: Mailbox message data + * 0x0740,f000 - 0x0740,ffff: MCU firmware section + * 0x3e00,0000 - 0x3fff,ffff: OP-TEE + */ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, + <0x00000000 0x05f00000 0x00000000 0x00eff000>, + <0x00000000 0x06e00000 0x00000000 0x0060f000>, + <0x00000000 0x07410000 0x00000000 0x36bf0000>; }; }; -- cgit v1.2.3 From fdf48938232e3edf19f76c144ce25efb63eee2f3 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 21 Jan 2016 18:53:49 +0800 Subject: arm64: dts: add sp804 timer node for Hi6220 Add sp804 timer for hi6220, so it can be used as broadcast timer. Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 82d2488a0e86..781681aa7a90 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -208,5 +208,14 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + dual_timer0: dual_timer@f8008000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xf8008000 0x0 0x1000>; + interrupts = , + ; + clocks = <&ao_ctrl 27>; + clock-names = "apb_pclk"; + }; }; }; -- cgit v1.2.3 From 9555656855fcce6864a395c045619a17460b4e55 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 21 Jan 2016 18:53:50 +0800 Subject: arm64: dts: enable idle states for Hi6220 Add cpu and cluster level's low power state for Hi6220. Acked-by: Sudeep Holla Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 781681aa7a90..6fb16974b072 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -53,11 +53,35 @@ }; }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu1: cpu@1 { @@ -65,6 +89,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu2: cpu@2 { @@ -72,6 +97,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu3: cpu@3 { @@ -79,6 +105,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu4: cpu@100 { @@ -86,6 +113,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu5: cpu@101 { @@ -93,6 +121,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu6: cpu@102 { @@ -100,6 +129,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu7: cpu@103 { @@ -107,6 +137,7 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; }; -- cgit v1.2.3 From 5fd0e5c1c01be39e377f4df2758d0e8f3af55d4d Mon Sep 17 00:00:00 2001 From: Zhong Kaihua Date: Thu, 28 Jan 2016 19:27:41 +0800 Subject: arm64: dts: Add Hi6220 gpio configuration nodes Add Hi6220 gpio configuration nodes Signed-off-by: Zhong Kaihua Signed-off-by: Kong Xinwei Acked-by: Rob Herring Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 259 ++++++++++++++++++++++++++++++ 1 file changed, 259 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 6fb16974b072..439462864023 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -248,5 +248,264 @@ clocks = <&ao_ctrl 27>; clock-names = "apb_pclk"; }; + + gpio0: gpio@f8011000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8011000 0x0 0x1000>; + interrupts = <0 52 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio1: gpio@f8012000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8012000 0x0 0x1000>; + interrupts = <0 53 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio2: gpio@f8013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8013000 0x0 0x1000>; + interrupts = <0 54 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio3: gpio@f8014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8014000 0x0 0x1000>; + interrupts = <0 55 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio4: gpio@f7020000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7020000 0x0 0x1000>; + interrupts = <0 56 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio5: gpio@f7021000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7021000 0x0 0x1000>; + interrupts = <0 57 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio6: gpio@f7022000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7022000 0x0 0x1000>; + interrupts = <0 58 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio7: gpio@f7023000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7023000 0x0 0x1000>; + interrupts = <0 59 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio8: gpio@f7024000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7024000 0x0 0x1000>; + interrupts = <0 60 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio9: gpio@f7025000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7025000 0x0 0x1000>; + interrupts = <0 61 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio10: gpio@f7026000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7026000 0x0 0x1000>; + interrupts = <0 62 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio11: gpio@f7027000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7027000 0x0 0x1000>; + interrupts = <0 63 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio12: gpio@f7028000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7028000 0x0 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio13: gpio@f7029000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7029000 0x0 0x1000>; + interrupts = <0 65 0x4>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio14: gpio@f702a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702a000 0x0 0x1000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio15: gpio@f702b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702b000 0x0 0x1000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio16: gpio@f702c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702c000 0x0 0x1000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio17: gpio@f702d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702d000 0x0 0x1000>; + interrupts = <0 69 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio18: gpio@f702e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702e000 0x0 0x1000>; + interrupts = <0 70 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; + + gpio19: gpio@f702f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702f000 0x0 0x1000>; + interrupts = <0 71 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + status = "ok"; + }; }; }; -- cgit v1.2.3 From 577e347e3a576a892380ea346faf20b997fe3070 Mon Sep 17 00:00:00 2001 From: Zhong Kaihua Date: Wed, 9 Dec 2015 16:47:01 +0800 Subject: arm64: dts: add Hi6220 pinctrl configuration nodes Add Hi6220 pinctrl configuration nodes Signed-off-by: Zhong Kaihua --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 + arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 77 +++ arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi | 684 +++++++++++++++++++++++ include/dt-bindings/pinctrl/hisi.h | 59 ++ 4 files changed, 821 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi create mode 100755 include/dt-bindings/pinctrl/hisi.h diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 1997e4df3ffe..b290dff8d7b4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "hi6220.dtsi" +#include "hikey-pinctrl.dtsi" / { model = "HiKey Development Board"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 439462864023..c9af87f588e1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "hisilicon,hi6220"; @@ -249,6 +250,60 @@ clock-names = "apb_pclk"; }; + pmx0: pinmux@f7010000 { + compatible = "pinctrl-single"; + reg = <0x0 0xf7010000 0x0 0x27c>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-range = < + &range 80 8 MUX_M0 /* gpio 3: [0..7] */ + &range 88 8 MUX_M0 /* gpio 4: [0..7] */ + &range 96 8 MUX_M0 /* gpio 5: [0..7] */ + &range 104 8 MUX_M0 /* gpio 6: [0..7] */ + &range 112 8 MUX_M0 /* gpio 7: [0..7] */ + &range 120 2 MUX_M0 /* gpio 8: [0..1] */ + &range 2 6 MUX_M1 /* gpio 8: [2..7] */ + &range 8 8 MUX_M1 /* gpio 9: [0..7] */ + &range 0 1 MUX_M1 /* gpio 10: [0] */ + &range 16 7 MUX_M1 /* gpio 10: [1..7] */ + &range 23 3 MUX_M1 /* gpio 11: [0..2] */ + &range 28 5 MUX_M1 /* gpio 11: [3..7] */ + &range 33 3 MUX_M1 /* gpio 12: [0..2] */ + &range 43 5 MUX_M1 /* gpio 12: [3..7] */ + &range 48 8 MUX_M1 /* gpio 13: [0..7] */ + &range 56 8 MUX_M1 /* gpio 14: [0..7] */ + &range 74 6 MUX_M1 /* gpio 15: [0..5] */ + &range 122 1 MUX_M1 /* gpio 15: [6] */ + &range 126 1 MUX_M1 /* gpio 15: [7] */ + &range 127 8 MUX_M1 /* gpio 16: [0..7] */ + &range 135 8 MUX_M1 /* gpio 17: [0..7] */ + &range 143 8 MUX_M1 /* gpio 18: [0..7] */ + &range 151 8 MUX_M1 /* gpio 19: [0..7] */ + >; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmx1: pinmux@f7010800 { + compatible = "pinconf-single"; + reg = <0x0 0xf7010800 0x0 0x28c>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + }; + + pmx2: pinmux@f8001800 { + compatible = "pinconf-single"; + reg = <0x0 0xf8001800 0x0 0x78>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + }; + gpio0: gpio@f8011000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x0 0xf8011000 0x0 0x1000>; @@ -294,6 +349,7 @@ interrupts = <0 55 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 80 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -307,6 +363,7 @@ interrupts = <0 56 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 88 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -320,6 +377,7 @@ interrupts = <0 57 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 96 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -333,6 +391,7 @@ interrupts = <0 58 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 104 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -346,6 +405,7 @@ interrupts = <0 59 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 112 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -359,6 +419,7 @@ interrupts = <0 60 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -372,6 +433,7 @@ interrupts = <0 61 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 8 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -385,6 +447,7 @@ interrupts = <0 62 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -398,6 +461,7 @@ interrupts = <0 63 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -411,6 +475,7 @@ interrupts = <0 64 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -423,6 +488,8 @@ reg = <0x0 0xf7029000 0x0 0x1000>; interrupts = <0 65 0x4>; gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 48 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -436,6 +503,7 @@ interrupts = <0 66 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 56 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -449,6 +517,11 @@ interrupts = <0 67 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = < + &pmx0 0 74 6 + &pmx0 6 122 1 + &pmx0 7 126 1 + >; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -462,6 +535,7 @@ interrupts = <0 68 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 127 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -475,6 +549,7 @@ interrupts = <0 69 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 135 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -488,6 +563,7 @@ interrupts = <0 70 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 143 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; @@ -501,6 +577,7 @@ interrupts = <0 71 0x4>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 151 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&ao_ctrl 2>; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi new file mode 100644 index 000000000000..28806df214d7 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -0,0 +1,684 @@ +/* + * pinctrl dts fils for Hislicon HiKey development board + * + */ +#include + +/ { + soc { + pmx0: pinmux@f7010000 { + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_pmx_func + &hkadc_ssi_pmx_func + &codec_clk_pmx_func + &pwm_in_pmx_func + &bl_pwm_pmx_func + >; + + boot_sel_pmx_func: boot_sel_pmx_func { + pinctrl-single,pins = < + 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ + >; + }; + + emmc_pmx_func: emmc_pmx_func { + pinctrl-single,pins = < + 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ + 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ + 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ + 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ + 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ + 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ + 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ + 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ + 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ + 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ + >; + }; + + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0xc MUX_M0 /* SD_CLK (IOMG003) */ + 0x10 MUX_M0 /* SD_CMD (IOMG004) */ + 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ + >; + }; + sd_pmx_idle: sd_pmx_idle { + pinctrl-single,pins = < + 0xc MUX_M1 /* SD_CLK (IOMG003) */ + 0x10 MUX_M1 /* SD_CMD (IOMG004) */ + 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ + >; + }; + + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ + >; + }; + sdio_pmx_idle: sdio_pmx_idle { + pinctrl-single,pins = < + 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ + >; + }; + + isp_pmx_func: isp_pmx_func { + pinctrl-single,pins = < + 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ + 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ + 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ + 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ + 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ + 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ + 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ + 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ + 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ + 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ + 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ + 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ + 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ + 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ + 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ + 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ + >; + }; + + hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { + pinctrl-single,pins = < + 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ + >; + }; + + codec_clk_pmx_func: codec_clk_pmx_func { + pinctrl-single,pins = < + 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ + >; + }; + + codec_pmx_func: codec_pmx_func { + pinctrl-single,pins = < + 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ + 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ + 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ + 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ + >; + }; + + fm_pmx_func: fm_pmx_func { + pinctrl-single,pins = < + 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ + 0x84 MUX_M1 /* FM_XFS (IOMG033) */ + 0x88 MUX_M1 /* FM_DI (IOMG034) */ + 0x8c MUX_M1 /* FM_DO (IOMG035) */ + >; + }; + + bt_pmx_func: bt_pmx_func { + pinctrl-single,pins = < + 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ + 0x94 MUX_M0 /* BT_XFS (IOMG037) */ + 0x98 MUX_M0 /* BT_DI (IOMG038) */ + 0x9c MUX_M0 /* BT_DO (IOMG039) */ + >; + }; + + pwm_in_pmx_func: pwm_in_pmx_func { + pinctrl-single,pins = < + 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ + >; + }; + + bl_pwm_pmx_func: bl_pwm_pmx_func { + pinctrl-single,pins = < + 0xbc MUX_M1 /* BL_PWM (IOMG047) */ + >; + }; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ + 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ + >; + }; + + uart1_pmx_func: uart1_pmx_func { + pinctrl-single,pins = < + 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ + 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ + 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ + 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ + 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ + 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ + 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ + 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ + 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ + 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ + 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ + 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ + 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ + >; + }; + + uart5_pmx_func: uart5_pmx_func { + pinctrl-single,pins = < + 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ + 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ + 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ + 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ + >; + }; + + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ + 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ + >; + }; + }; + + pmx1: pinmux@f7010800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_cfg_func + &hkadc_ssi_cfg_func + &codec_clk_cfg_func + &pwm_in_cfg_func + &bl_pwm_cfg_func + >; + + boot_sel_cfg_func: boot_sel_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* BOOT_SEL (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { + pinctrl-single,pins = < + 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_clk_cfg_func: emmc_clk_cfg_func { + pinctrl-single,pins = < + 0x104 0x0 /* EMMC_CLK (IOCFG065) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_cfg_func: emmc_cfg_func { + pinctrl-single,pins = < + 0x108 0x0 /* EMMC_CMD (IOCFG066) */ + 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ + 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ + 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ + 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ + 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ + 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ + 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ + 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_rst_cfg_func: emmc_rst_cfg_func { + pinctrl-single,pins = < + 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sd_clk_cfg_idle: sd_clk_cfg_idle { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sd_cfg_idle: sd_cfg_idle { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sdio_clk_cfg_idle: sdio_clk_cfg_idle { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sdio_cfg_idle: sdio_cfg_idle { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp_cfg_func1: isp_cfg_func1 { + pinctrl-single,pins = < + 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ + 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ + 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + 0x3c 0x0 /* ISP_PWM (IOCFG015) */ + 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ + 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ + 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ + 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ + 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ + 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ + 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ + 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ + 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + isp_cfg_idle1: isp_cfg_idle1 { + pinctrl-single,pins = < + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp_cfg_func2: isp_cfg_func2 { + pinctrl-single,pins = < + 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_clk_cfg_func: codec_clk_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + codec_clk_cfg_idle: codec_clk_cfg_idle { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_cfg_func1: codec_cfg_func1 { + pinctrl-single,pins = < + 0x74 0x0 /* DMIC_CLK (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_cfg_func2: codec_cfg_func2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + codec_cfg_idle2: codec_cfg_idle2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + fm_cfg_func: fm_cfg_func { + pinctrl-single,pins = < + 0x84 0x0 /* FM_XCLK (IOCFG033) */ + 0x88 0x0 /* FM_XFS (IOCFG034) */ + 0x8c 0x0 /* FM_DI (IOCFG035) */ + 0x90 0x0 /* FM_DO (IOCFG036) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + bt_cfg_func: bt_cfg_func { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + bt_cfg_idle: bt_cfg_idle { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + pwm_in_cfg_func: pwm_in_cfg_func { + pinctrl-single,pins = < + 0xbc 0x0 /* PWM_IN (IOCFG047) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + bl_pwm_cfg_func: bl_pwm_cfg_func { + pinctrl-single,pins = < + 0xc0 0x0 /* BL_PWM (IOCFG048) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart0_cfg_func1: uart0_cfg_func1 { + pinctrl-single,pins = < + 0xc4 0x0 /* UART0_RXD (IOCFG049) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart0_cfg_func2: uart0_cfg_func2 { + pinctrl-single,pins = < + 0xc8 0x0 /* UART0_TXD (IOCFG050) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart1_cfg_func1: uart1_cfg_func1 { + pinctrl-single,pins = < + 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ + 0xd4 0x0 /* UART1_RXD (IOCFG053) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart1_cfg_func2: uart1_cfg_func2 { + pinctrl-single,pins = < + 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ + 0xd8 0x0 /* UART1_TXD (IOCFG054) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ + 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ + 0xe4 0x0 /* UART2_RXD (IOCFG057) */ + 0xe8 0x0 /* UART2_TXD (IOCFG058) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ + 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ + 0x198 0x0 /* UART3_RXD (IOCFG102) */ + 0x19c 0x0 /* UART3_TXD (IOCFG103) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ + 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ + 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ + 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ + 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0xec 0x0 /* I2C0_SCL (IOCFG059) */ + 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ + 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ + 0x100 0x0 /* I2C2_SDA (IOCFG064) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + }; + + pmx2: pinmux@f8001800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &rstout_n_cfg_func + >; + + rstout_n_cfg_func: rstout_n_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* RSTOUT_N (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { + pinctrl-single,pins = < + 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sysclk0_en_cfg_func: sysclk0_en_cfg_func { + pinctrl-single,pins = < + 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + jtag_tdo_cfg_func: jtag_tdo_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* JTAG_TDO (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + rf_reset_cfg_func: rf_reset_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* RF_RESET0 (IOCFG028) */ + 0x74 0x0 /* RF_RESET1 (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + }; + }; +}; diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h new file mode 100755 index 000000000000..38f1ea879ea1 --- /dev/null +++ b/include/dt-bindings/pinctrl/hisi.h @@ -0,0 +1,59 @@ +/* + * This header provides constants for hisilicon pinctrl bindings. + * + * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_HISI_H +#define _DT_BINDINGS_PINCTRL_HISI_H + +/* iomg bit definition */ +#define MUX_M0 0 +#define MUX_M1 1 +#define MUX_M2 2 +#define MUX_M3 3 +#define MUX_M4 4 +#define MUX_M5 5 +#define MUX_M6 6 +#define MUX_M7 7 + +/* iocg bit definition */ +#define PULL_MASK (3) +#define PULL_DIS (0) +#define PULL_UP (1 << 0) +#define PULL_DOWN (1 << 1) + +/* drive strength definition */ +#define DRIVE_MASK (7 << 4) +#define DRIVE1_02MA (0 << 4) +#define DRIVE1_04MA (1 << 4) +#define DRIVE1_08MA (2 << 4) +#define DRIVE1_10MA (3 << 4) +#define DRIVE2_02MA (0 << 4) +#define DRIVE2_04MA (1 << 4) +#define DRIVE2_08MA (2 << 4) +#define DRIVE2_10MA (3 << 4) +#define DRIVE3_04MA (0 << 4) +#define DRIVE3_08MA (1 << 4) +#define DRIVE3_12MA (2 << 4) +#define DRIVE3_16MA (3 << 4) +#define DRIVE3_20MA (4 << 4) +#define DRIVE3_24MA (5 << 4) +#define DRIVE3_32MA (6 << 4) +#define DRIVE3_40MA (7 << 4) +#define DRIVE4_02MA (0 << 4) +#define DRIVE4_04MA (2 << 4) +#define DRIVE4_08MA (4 << 4) +#define DRIVE4_10MA (6 << 4) + +#endif -- cgit v1.2.3 From d44ad96510ab4e22dc972ab2175a4463bda4c49f Mon Sep 17 00:00:00 2001 From: Zhong Kaihua Date: Thu, 28 Jan 2016 19:27:43 +0800 Subject: arm64: dts: add Hi6220 spi configuration nodes Add Hi6220 spi configuration nodes Signed-off-by: Zhong Kaihua Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index c9af87f588e1..8c8f8f1a1288 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -584,5 +584,20 @@ clock-names = "apb_pclk"; status = "ok"; }; + + spi0: spi@f7106000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xf7106000 0x0 0x1000>; + interrupts = <0 50 4>; + bus-id = <0>; + enable-dma = <0>; + clocks = <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; + num-cs = <1>; + cs-gpios = <&gpio6 2 0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi index 28806df214d7..0916e8459d6b 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -221,6 +221,15 @@ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ >; }; + + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ + 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ + 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ + 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ + >; + }; }; pmx1: pinmux@f7010800 { @@ -625,6 +634,18 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; + + spi0_cfg_func: spi0_cfg_func { + pinctrl-single,pins = < + 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ + 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ + 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ + 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; }; pmx2: pinmux@f8001800 { -- cgit v1.2.3 From 8300a4a63d37257f43ffbdd1a5e0ac9d815dd649 Mon Sep 17 00:00:00 2001 From: Xinwei Kong Date: Wed, 2 Dec 2015 18:13:21 +0800 Subject: arm64: dts: add all hi6220 i2c nodes This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc use this I2C IP of Synopsys Designware for HiKey board. Signed-off-by: Xinwei Kong Signed-off-by: Chen Feng Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 8c8f8f1a1288..2c1580d14990 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -599,5 +599,38 @@ cs-gpios = <&gpio6 2 0>; status = "disabled"; }; + + i2c0: i2c@f7100000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7100000 0x0 0x1000>; + interrupts = <0 44 4>; + clocks = <&sys_ctrl HI6220_I2C0_CLK>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@f7101000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7101000 0x0 0x1000>; + clocks = <&sys_ctrl HI6220_I2C1_CLK>; + interrupts = <0 45 4>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@f7102000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7102000 0x0 0x1000>; + clocks = <&sys_ctrl HI6220_I2C2_CLK>; + interrupts = <0 46 4>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 51038b9f98a8939263632be89dbd75f438a7fb86 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 3 Feb 2016 20:03:39 +0800 Subject: arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards Signed-off-by: Guodong Xu Conflicts: arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index b290dff8d7b4..f0eb7b3c9fb5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -40,4 +40,13 @@ <0x00000000 0x06e00000 0x00000000 0x0060f000>, <0x00000000 0x07410000 0x00000000 0x36bf0000>; }; + + soc { + i2c0: i2c@f7100000 { + status = "ok"; + }; + i2c1: i2c@f7101000 { + status = "ok"; + }; + }; }; -- cgit v1.2.3 From 7fdda3a5ef4a00924fa88eedbc2d2e8b10e6455c Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Mon, 30 Nov 2015 12:35:43 +0800 Subject: arm64: dts: add hi6220 usb node Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2c1580d14990..cdee25367e3d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -632,5 +632,37 @@ pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; status = "disabled"; }; + + fixed_5v_hub: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed_5v_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio0 7 0>; + regulator-always-on; + }; + + usb_phy: usbphy { + compatible = "hisilicon,hi6220-usb-phy"; + #phy-cells = <0>; + phy-supply = <&fixed_5v_hub>; + hisilicon,peripheral-syscon = <&sys_ctrl>; + }; + + usb: usb@f72c0000 { + compatible = "hisilicon,hi6220-usb"; + reg = <0x0 0xf72c0000 0x0 0x40000>; + phys = <&usb_phy>; + phy-names = "usb2-phy"; + clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; + clock-names = "otg"; + dr_mode = "otg"; + g-use-dma; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 128 128 128 128>; + interrupts = <0 77 0x4>; + }; }; }; -- cgit v1.2.3 From 333aedda18de82f3f70e300dcbcae0cf312f31d7 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 15 Feb 2016 21:50:25 +0800 Subject: arm64: dts: add mailbox node for Hi6220 This patch add device mailbox node for Hi6220 in DT. Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index cdee25367e3d..3a991307eb7d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -664,5 +664,13 @@ g-tx-fifo-size = <128 128 128 128 128 128>; interrupts = <0 77 0x4>; }; + + mailbox: mailbox@f7510000 { + compatible = "hisilicon,hi6220-mbox"; + reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ + <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ + interrupts = ; + #mbox-cells = <3>; + }; }; }; -- cgit v1.2.3 From 6e77940918449adaf2cd458874077034559dc284 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 15 Feb 2016 21:50:26 +0800 Subject: arm64: dts: add Hi6220's stub clock node Enable SRAM node and stub clock node for Hi6220, which uses mailbox channel 1 for CPU's frequency change. Furthermore, add the CPU clock phandle in CPU's node and using operating-points-v2 to register operating points. So can be used by cpufreq-dt driver. Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3a991307eb7d..40ed70fe4881 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -82,6 +82,11 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&stub_clock 0>; + operating-points-v2 = <&cpu_opp_table>; + cooling-min-level = <4>; + cooling-max-level = <0>; + #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -90,6 +95,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -98,6 +104,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -106,6 +113,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -114,6 +122,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -122,6 +131,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -130,6 +140,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -138,10 +149,42 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <729000000>; + opp-microvolt = <1090000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1180000>; + clock-latency-ns = <500000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1330000>; + clock-latency-ns = <500000>; + }; + }; + gic: interrupt-controller@f6801000 { compatible = "arm,gic-400"; reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ @@ -169,6 +212,11 @@ #size-cells = <2>; ranges; + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; + ao_ctrl: ao_ctrl@f7800000 { compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; @@ -193,6 +241,14 @@ #clock-cells = <1>; }; + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mbox-names = "mbox-tx"; + mboxes = <&mailbox 1 0 11>; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; -- cgit v1.2.3 From c44005e1980439c7ff248445909722489a2c4a64 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 29 Dec 2015 18:09:08 +0800 Subject: arm64: dts: hi6220: add pinctrl for uarts and enable them Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 12 ++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index f0eb7b3c9fb5..00cb3fb0be66 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -48,5 +48,17 @@ i2c1: i2c@f7101000 { status = "ok"; }; + + uart1: uart@f7111000 { + status = "ok"; + }; + + uart2: uart@f7112000 { + status = "ok"; + }; + + uart3: uart@f7113000 { + status = "ok"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 40ed70fe4881..fe02e6e7aade 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -265,6 +265,8 @@ clocks = <&sys_ctrl HI6220_UART1_PCLK>, <&sys_ctrl HI6220_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; status = "disabled"; }; @@ -275,6 +277,8 @@ clocks = <&sys_ctrl HI6220_UART2_PCLK>, <&sys_ctrl HI6220_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; status = "disabled"; }; @@ -285,6 +289,9 @@ clocks = <&sys_ctrl HI6220_UART3_PCLK>, <&sys_ctrl HI6220_UART3_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; }; uart4: uart@f7114000 { @@ -294,6 +301,8 @@ clocks = <&sys_ctrl HI6220_UART4_PCLK>, <&sys_ctrl HI6220_UART4_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; status = "disabled"; }; -- cgit v1.2.3 From 3520ad852a0664a1a5f77519bde994afe75dea9c Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 2 Feb 2016 16:33:16 +0800 Subject: arm64: dts: add LED nodes for hi6220-hikey Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 00cb3fb0be66..a34a6286177b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -61,4 +61,45 @@ status = "ok"; }; }; + + leds { + compatible = "gpio-leds"; + user_led1 { + label = "user_led4"; + gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "user_led3"; + gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "user_led2"; + gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ + linux,default-trigger = "mmc1"; + }; + + user_led4 { + label = "user_led1"; + gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ + linux,default-trigger = "cpu0"; + }; + + wlan_active_led { + label = "wifi_active"; + gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "bt_active"; + gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ + linux,default-trigger = "hci0rx"; + default-state = "off"; + }; + }; }; -- cgit v1.2.3 From 0c98320cd994c6216e26f1fb1b2a012f686453ec Mon Sep 17 00:00:00 2001 From: Xinwei Kong Date: Fri, 11 Dec 2015 17:11:10 +0800 Subject: arm64: dts: add dwmmc nodes for hi6220 Add all three dwmmc nodes description for hi6220 Signed-off-by: Guodong Xu Signed-off-by: Xinwei Kong --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index fe02e6e7aade..2d451d08743b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -737,5 +737,58 @@ interrupts = ; #mbox-cells = <3>; }; + + dwmmc_0: dwmmc0@f723d000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + cap-mmc-highspeed; + non-removable; + reg = <0x0 0xf723d000 0x0 0x1000>; + interrupts = <0x0 0x48 0x4>; + clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; + clock-names = "ciu", "biu"; + bus-width = <0x8>; + vmmc-supply = <&ldo19>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func + &emmc_cfg_func &emmc_rst_cfg_func>; + }; + + dwmmc_1: dwmmc1@f723e000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + card-detect-delay = <200>; + hisilicon,peripheral-syscon = <&ao_ctrl>; + cap-sd-highspeed; + reg = <0x0 0xf723e000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; + clock-names = "ciu", "biu"; + vqmmc-supply = <&ldo7>; + vmmc-supply = <&ldo10>; + bus-width = <0x4>; + disable-wp; + cd-gpios = <&gpio1 0 1>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; + }; + + dwmmc_2: dwmmc2@f723f000 { + compatible = "hisilicon,hi6220-dw-mshc"; + status = "okay"; + num-slots = <0x1>; + reg = <0x0 0xf723f000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; + clock-names = "ciu", "biu"; + bus-width = <0x4>; + broken-cd; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; + pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; + }; }; }; -- cgit v1.2.3 From a694b30814f12902a076b80a954fb636c9bc6e3c Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sun, 14 Feb 2016 21:48:47 +0800 Subject: arm64: dts: hi6220: add resets property into dwmmc nodes Add resets property into dwmmc_0, dwmmc_1 and dwmmc_2 for hi6220 Signed-off-by: Guodong Xu arm64: dts: hi6220: add resets in dwmmc_2 Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2d451d08743b..2d8012a18d37 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "hisilicon,hi6220"; @@ -747,6 +748,7 @@ interrupts = <0x0 0x48 0x4>; clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; bus-width = <0x8>; vmmc-supply = <&ldo19>; pinctrl-names = "default"; @@ -766,6 +768,7 @@ #size-cells = <0x0>; clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; vqmmc-supply = <&ldo7>; vmmc-supply = <&ldo10>; bus-width = <0x4>; @@ -784,6 +787,7 @@ interrupts = <0x0 0x4a 0x4>; clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; bus-width = <0x4>; broken-cd; pinctrl-names = "default", "idle"; -- cgit v1.2.3 From a60a1d47b0a5ef1f69f7ec789bd01eda263218bf Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 17 Aug 2015 17:39:44 +0800 Subject: arm64: dts: add wifi nodes support for hi6220-hikey Add wifi nodes support for hi6220-hikey Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index a34a6286177b..1ea43469d8c8 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -45,6 +45,7 @@ i2c0: i2c@f7100000 { status = "ok"; }; + i2c1: i2c@f7101000 { status = "ok"; }; @@ -60,6 +61,33 @@ uart3: uart@f7113000 { status = "ok"; }; + + dwmmc_2: dwmmc2@f723f000 { + /* WL_EN */ + vmmc-supply = <&wlan_en_reg>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + }; + + wlan_en_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* WLAN_EN GPIO */ + gpio = <&gpio0 5 0>; + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; }; leds { -- cgit v1.2.3 From 105a6977334ac42ef820f69e883c0d7a88f5b339 Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Mon, 1 Feb 2016 17:16:06 +0800 Subject: arm64: dts: hisilicon: Add hi655x pmic dts node Add the mfd hi655x dts node and regulator support on hi6220 platform. Signed-off-by: Chen Feng Signed-off-by: Fei Wang Signed-off-by: Xinwei Kong Signed-off-by: Guodong Xu Reviewed-by: Haojian Zhuang --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 87 ++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 1ea43469d8c8..eda16cfa1af4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "hi6220.dtsi" #include "hikey-pinctrl.dtsi" @@ -130,4 +131,90 @@ default-state = "off"; }; }; + + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0x0 0xf8000000 0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + + regulators { + ldo2: LDO2 { + regulator-name = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo7: LDO7 { + regulator-name = "LDO7_SDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo10: LDO10 { + regulator-name = "LDO10_2V85"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + + ldo13: LDO13 { + regulator-name = "LDO13_1V8"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo14: LDO14 { + regulator-name = "LDO14_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo15: LDO15 { + regulator-name = "LDO15_1V8"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo17: LDO17 { + regulator-name = "LDO17_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo19: LDO19 { + regulator-name = "LDO19_3V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + + ldo21: LDO21 { + regulator-name = "LDO21_1V8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo22: LDO22 { + regulator-name = "LDO22_1V2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + }; + }; }; -- cgit v1.2.3 From 62a1dfc713e1e8118bcb6fdcc08923a08aeef1ee Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 20 Jan 2016 15:25:40 +0800 Subject: arm64: dts: add node for mtcmos regulators Signed-off-by: Guodong Xu bugfix Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2d8012a18d37..f209154f7e72 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -794,5 +794,26 @@ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; }; + + mtcmos { + compatible = "hisilicon,hi6220-mtcmos-driver"; + hisilicon,mtcmos-steady-us = <10>; + hisilicon,mtcmos-sc-on-base = <0xf7800000>; + hisilicon,mtcmos-acpu-on-base = <0xf65a0000>; + + g3d_vdd: regulator@a1{ + regulator-name = "G3D_PD_VDD"; + regulator-compatible = "mtcmos1"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <1 0x1>; + }; + + soc_med: regulator@a2{ + regulator-name = "SOC_MED"; + regulator-compatible = "mtcmos2"; + hisilicon,ctrl-regs = <0x830 0x834 0x83c>; + hisilicon,ctrl-data = <2 0x1>; + }; + }; }; }; -- cgit v1.2.3 From 8c7a9a13841343918849d27350042414d43d6c9b Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 7 Jul 2015 20:45:35 +0800 Subject: arm64: dts: add thermal zone and sensor for Hi6220 Add thermal sensor node for Hi6220; and also bind thermal sensor 2 with CPU cooling device. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f209154f7e72..e7c6c9053e0f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include / { @@ -795,6 +796,125 @@ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; }; + tsensor: tsensor@0,f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0x0 0xf7030700 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl 22>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + local: local { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 0>; + + trips { + local_alert: local_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + local_crit: local_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + cluster1: cluster1 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 1>; + + trips { + cluster1_alert: cluster1_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cluster1_crit: cluster1_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + cluster0: cluster0 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 2>; + + trips { + cluster0_alert: cluster0_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cluster0_crit: cluster0_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cluster0_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu: gpu { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsensor 3>; + + trips { + gpu_alert: gpu_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + }; + mtcmos { compatible = "hisilicon,hi6220-mtcmos-driver"; hisilicon,mtcmos-steady-us = <10>; -- cgit v1.2.3 From 3f407b13a7df47916e52e45ad72e2a1601af7271 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Sat, 6 Feb 2016 10:49:41 +0800 Subject: arm64: dts: Add display subsystem DT nodes for hi6220-hikey Add ade and dsi DT nodes for hikey board. Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 8 ++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 55 ++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index eda16cfa1af4..87976ae65a79 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -218,3 +218,11 @@ }; }; }; + +&ade { + status = "ok"; +}; + +&dsi { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index e7c6c9053e0f..d2c3422f6c8d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -251,6 +251,11 @@ mboxes = <&mailbox 1 0 11>; }; + medianoc_ade: medianoc_ade@f4520000 { + compatible = "syscon"; + reg = <0x0 0xf4520000 0x0 0x4000>; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; @@ -935,5 +940,55 @@ hisilicon,ctrl-data = <2 0x1>; }; }; + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + status = "disabled"; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; }; }; -- cgit v1.2.3 From 46e47376794350a374d24dfe0bd9cc1e6d463d63 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Sun, 10 Apr 2016 17:09:47 +0800 Subject: arm64: dts: Add HDMI node for hi6220-hikey Add adv7533 HDMI DT node for HiKey board. Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 87976ae65a79..844678a4897e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -225,4 +225,37 @@ &dsi { status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; }; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + adv7533: adv7533@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <1 2>; + pd-gpio = <&gpio0 4 0>; + adi,dsi-lanes = <4>; + adi,disable-timing-generator; + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; + }; -- cgit v1.2.3 From 6b6fbc30e49bd6be42921b1d443db43ac4b686fd Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Fri, 29 Apr 2016 14:35:47 +0800 Subject: arm64: dts: hikey: Add lcd panel dt node Add innolux n070icn-pb1 HC070I635023 LCD panel. Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 844678a4897e..3761aad580a8 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -224,16 +224,46 @@ }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "ok"; ports { /* 1 for output port */ port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; dsi_out0: endpoint@0 { + reg = <0>; remote-endpoint = <&adv7533_in>; }; + + dsi_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel0_in>; + }; + }; + }; + + /* For panel reg's value should >= 1 */ + panel@1 { + compatible = "innolux,n070icn-pb1"; + reg = <1>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + panel-width-mm = <58>; + panel-height-mm = <103>; + pwr-en-gpio = <&gpio2 1 0>; + bl-en-gpio = <&gpio2 3 0>; + pwm-gpio = <&gpio12 7 0>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi_out1>; + }; }; }; }; -- cgit v1.2.3 From d8691f8732131bf9ea7e18ad822e930f6a844ec6 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Fri, 29 Apr 2016 15:41:23 +0800 Subject: arm64: dts: hikey: Add dsi mux gpio Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 3761aad580a8..ab5b2d377015 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -226,6 +226,7 @@ &dsi { #address-cells = <1>; #size-cells = <0>; + mux-gpio = <&gpio0 1 0>; status = "ok"; ports { -- cgit v1.2.3 From 0889a4556142813ffd1d60d50db336f1fd021147 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Wed, 17 Feb 2016 19:08:01 +0800 Subject: arm64: dts: hi6220: Add media subsystem reset dts Add media subsystem reset support. Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index d2c3422f6c8d..c30efe982106 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -235,6 +235,7 @@ compatible = "hisilicon,hi6220-mediactrl", "syscon"; reg = <0x0 0xf4410000 0x0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pm_ctrl: pm_ctrl@f7032000 { -- cgit v1.2.3 From 8aaa0d7a67592a57e8a00a6981ab3bbd40e52b12 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Mon, 28 Dec 2015 17:40:48 +0800 Subject: arm64: dts: Add mali gpu node Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index c30efe982106..9aec403793a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -991,5 +991,44 @@ }; }; }; + + mali:mali@f4080000 { + compatible = "arm,mali-450", "arm,mali-utgard"; + reg = <0x0 0x3f100000 0x0 0x00708000>; + clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + clock-names = "clk_g3d", "pclk_g3d"; + G3D_PD_VDD-supply = <&g3d_vdd>; + mali_def_freq = <500>; + pclk_freq = <144>; + dfs_steps = <2>; + dfs_lockprf = <1>; + dfs_limit_max_prf = <1>; + dfs_profile_num = <2>; + dfs_profiles = <250 3 0>, <500 1 0>; + mali_type = <2>; + + interrupt-parent = <&gic>; + interrupts = <1 126 4>, /*gp*/ + <1 126 4>, /*gp mmu*/ + <1 126 4>, /*pp bc*/ + <1 126 4>, /*pmu*/ + <1 126 4>, /*pp0*/ + <1 126 4>, + <1 126 4>, /*pp1*/ + <1 126 4>, + <1 126 4>, /*pp2*/ + <1 126 4>, + <1 126 4>, /*pp4*/ + <1 126 4>, + <1 126 4>, /*pp5*/ + <1 126 4>, + <1 126 4>, /*pp6*/ + <1 126 4>; + interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU", + "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", + "IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4", + "IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6"; + }; }; }; -- cgit v1.2.3 From 4e43ce2cbab7eded3aec2b022d50da70a6faf4da Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 22 Dec 2014 15:26:06 -0600 Subject: arm64: dts: hikey: add description for bluetooth and set baudrate to 3Mbps Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index ab5b2d377015..180e5f8b98cc 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -132,6 +132,27 @@ }; }; + kim { + compatible = "kim"; + pinctrl-names = "default"; + pinctrl-0 = <>; /* FIXME: add BT PCM pinctrl here */ + /* + * FIXME: The following is complete CRAP since + * the vendor driver doesn't follow the gpio + * binding. Passing in a magic Linux gpio number + * here until we fix the vendor driver. + */ + /* BT_EN: BT_REG_ON_GPIO1_7 */ + nshutdown_gpio = <503>; + dev_name = "/dev/ttyAMA1"; + flow_cntrl = <1>; + baud_rate = <3000000>; + }; + + btwilink { + compatible = "btwilink"; + }; + pmic: pmic@f8000000 { compatible = "hisilicon,hi655x-pmic"; reg = <0x0 0xf8000000 0x0 0x1000>; -- cgit v1.2.3 From bdbe328b1c9760fd6addf6ed0441d540fcdf04c5 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 22 Jan 2016 11:02:10 -0800 Subject: arm64: dts: hikey: Add ION entries to hikey dts This patch adds ion entries to the hikey dts. This was based off of the entries used in the 4.1 kernel Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 180e5f8b98cc..77821449e33b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -89,6 +89,28 @@ startup-delay-us = <70000>; enable-active-high; }; + + hisi-ion@0 { + compatible = "hisilicon,ion"; + + heap_sys_user@0 { + heap-name = "sys_user"; + heap-range = <0x0 0x0>; + heap-type = "ion_system"; + }; + + heap_sys_contig@0 { + heap-name = "sys_contig"; + heap-range = <0x0 0x0>; + heap-type = "ion_system_contig"; + }; + + heap_cma@0 { + heap-name = "cma"; + heap-range = <0x0 0x0>; + heap-type = "ion_cma"; + }; + }; }; leds { -- cgit v1.2.3 From 54385183eb4a5c4dfa13311117b00c4ed13ef799 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 3 Feb 2016 13:06:09 +0800 Subject: arm64: dts: hi6220: Add pl031 RTC support Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 9aec403793a7..0c811986e4f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -323,6 +323,14 @@ clock-names = "apb_pclk"; }; + rtc0: rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8003000 0x0 0x1000>; + interrupts = <0 12 4>; + clocks = <&ao_ctrl HI6220_RTC0_PCLK>; + clock-names = "apb_pclk"; + }; + pmx0: pinmux@f7010000 { compatible = "pinctrl-single"; reg = <0x0 0xf7010000 0x0 0x27c>; -- cgit v1.2.3 From a387f2b9134d6b4bb850197fd8f01f3049c709e2 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Mon, 14 Dec 2015 21:57:41 -0800 Subject: dts: hikey: Add reboot reason support Add support in the DT to enable the reboot reason support for "adb reboot bootloader" functionality. Cc: Vishal Bhoj Cc: haojian.zhuang@linaro.org Cc: guodong.xu@linaro.org Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 77821449e33b..7c823a419794 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -30,6 +30,7 @@ * Reserve below regions from memory node: * * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using + * 0x05f0,1000 - 0x05f0,1fff: Reboot reason * 0x06df,f000 - 0x06df,ffff: Mailbox message data * 0x0740,f000 - 0x0740,ffff: MCU firmware section * 0x3e00,0000 - 0x3fff,ffff: OP-TEE @@ -37,11 +38,21 @@ memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, - <0x00000000 0x05f00000 0x00000000 0x00eff000>, + <0x00000000 0x05f00000 0x00000000 0x00001000>, + <0x00000000 0x05f02000 0x00000000 0x00efd000>, <0x00000000 0x06e00000 0x00000000 0x0060f000>, <0x00000000 0x07410000 0x00000000 0x36bf0000>; }; + reboot_reason: reboot-reason@05f01000 { + compatible = "linux,reboot-reason-sram"; + reg = <0x0 0x05F01000 0x0 0x4>; + reason,none = <0x77665501>; + reason,bootloader = <0x77665500>; + reason,recovery = <0x77665502>; + reason,oem = <0x6f656d00>; + }; + soc { i2c0: i2c@f7100000 { status = "ok"; -- cgit v1.2.3 From 999d3c67fd01f3617928dfe67ae6a552939b2409 Mon Sep 17 00:00:00 2001 From: Xinwei Kong Date: Fri, 11 Dec 2015 17:21:54 +0800 Subject: arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Add reset controller for hi6220 hikey-board. Signed-off-by: Chen Feng Signed-off-by: Xinwei Kong --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 0c811986e4f0..544c28eda334 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -229,6 +229,7 @@ compatible = "hisilicon,hi6220-sysctrl", "syscon"; reg = <0x0 0xf7030000 0x0 0x2000>; #clock-cells = <1>; + #reset-cells = <1>; }; media_ctrl: media_ctrl@f4410000 { -- cgit v1.2.3 From bb6600112a1205f219264517d6bdee2216308318 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 23 Feb 2016 10:56:53 +0800 Subject: arm64: dts: register Hi6220's thermal zone for power allocator With profiling Hi6220's power modeling so get dynamic coefficient and sustainable power. So pass these parameters from DT. Now enable power allocator wit only one actor for CPU part, so directly use cluster0's thermal sensor for monitoring temperature. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 107 +++++------------------------- 1 file changed, 16 insertions(+), 91 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 544c28eda334..0ffe62092ed4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -90,6 +90,7 @@ cooling-max-level = <0>; #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <311>; }; cpu1: cpu@1 { @@ -821,111 +822,35 @@ }; thermal-zones { - local: local { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - /* sensor ID */ - thermal-sensors = <&tsensor 0>; + cls0: cls0 { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <3326>; - trips { - local_alert: local_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - local_crit: local_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ - }; - }; - - cluster1: cluster1 { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsensor 1>; + /* sensor ID */ + thermal-sensors = <&tsensor 2>; trips { - cluster1_alert: cluster1_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ + threshold: trip-point@0 { + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; - cluster1_crit: cluster1_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ - }; - }; - - cluster0: cluster0 { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsensor 2>; - - trips { - cluster0_alert: cluster0_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ + target: trip-point@1 { + temperature = <75000>; + hysteresis = <1000>; type = "passive"; }; - - cluster0_crit: cluster0_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; }; cooling-maps { map0 { - trip = <&cluster0_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu: gpu { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsensor 3>; - - trips { - gpu_alert: gpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; + trip = <&target>; + contribution = <1024>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; - - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* There are currently no cooling maps because there are no cooling devices */ }; }; }; -- cgit v1.2.3 From dc83d3b26b0170cf1dc90e595a7efe9ca59600a6 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 5 Jan 2016 16:26:58 -0800 Subject: hikey: dts: Add pstore support for HiKey This patch reserves some memory in the DTS and sets up a pstore device tree node to enable pstore support on HiKey. Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 7c823a419794..50ddaf698292 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -33,6 +33,7 @@ * 0x05f0,1000 - 0x05f0,1fff: Reboot reason * 0x06df,f000 - 0x06df,ffff: Mailbox message data * 0x0740,f000 - 0x0740,ffff: MCU firmware section + * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ memory@0 { @@ -41,7 +42,21 @@ <0x00000000 0x05f00000 0x00000000 0x00001000>, <0x00000000 0x05f02000 0x00000000 0x00efd000>, <0x00000000 0x06e00000 0x00000000 0x0060f000>, - <0x00000000 0x07410000 0x00000000 0x36bf0000>; + <0x00000000 0x07410000 0x00000000 0x1aaf0000>, + <0x00000000 0x22000000 0x00000000 0x1c000000>; + }; + + pstore: pstore@0x21f00000 { + no-map; + reg = <0x0 0x21f00000 0x0 0x00100000>; /* pstore/ramoops buffer */ + }; + + ramoops { + compatible = "ramoops"; + memory-region = <&pstore>; + record-size = <0x0 0x00020000>; + console-size = <0x0 0x00020000>; + ftrace-size = <0x0 0x00020000>; }; reboot_reason: reboot-reason@05f01000 { -- cgit v1.2.3 From 87cfe19467bd869584163c3f9e8011e703258650 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 26 Feb 2016 13:14:51 +0800 Subject: arm64: dts: Add L2 cache topology to Hi6220 This patch adds the L2 cache topology on Hi6220. Hi6220 has two clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways). Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 0ffe62092ed4..4dd77d4b8aee 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -84,6 +84,7 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; cooling-min-level = <4>; @@ -98,6 +99,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -107,6 +109,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -116,6 +119,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -125,6 +129,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -134,6 +139,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -143,6 +149,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -152,9 +159,18 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; + + CLUSTER0_L2: l2-cache0 { + compatible = "cache"; + }; + + CLUSTER1_L2: l2-cache1 { + compatible = "cache"; + }; }; cpu_opp_table: cpu_opp_table { -- cgit v1.2.3 From 8d7e7ec76abf1684b82f4bebc4d293ac3cfd0f97 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 3 Mar 2016 11:54:39 +0800 Subject: arm64: dts: Add powerkey info to pmic for hi6220-hikey Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 50ddaf698292..2762085df5d2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -209,6 +209,13 @@ pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; status = "okay"; + ponkey:ponkey@b1{ + compatible = "hisilicon,hi6552-powerkey"; + interrupt-parent = <&pmic>; + interrupts = <6 0>, <5 0>, <4 0>; + interrupt-names = "down", "up", "hold 4s"; + }; + regulators { ldo2: LDO2 { regulator-name = "LDO2_2V8"; -- cgit v1.2.3 From b83745856932c0e410eaff6a797c773f9077970f Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 15 Mar 2016 14:02:49 -0700 Subject: dts: Readd ti wifi options on mmc2 Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 2762085df5d2..e8adf5c4f5bc 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -90,6 +90,8 @@ }; dwmmc_2: dwmmc2@f723f000 { + ti,non-removable; + non-removable; /* WL_EN */ vmmc-supply = <&wlan_en_reg>; -- cgit v1.2.3 From 5f012dcfd09f108ae2f9f008b0d7747929ded664 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 6 Feb 2016 19:55:49 +0800 Subject: arm64: dts: hi6220: add sd-uhs- properties into dwmmc_1 With these properties added, sd cards inserted into hikey can work at UHS mode if they have such capability. Due to some silicon defect in hi6220, a UHS support patch must be applied into drivers/mmc/host/dw_mmc to enable UHS mode. If you didn't add this patch, but added sd-uhs- properties into dwmmc_1, then sd cards cannot work. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 4dd77d4b8aee..312dcf63fd6f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -795,6 +795,9 @@ card-detect-delay = <200>; hisilicon,peripheral-syscon = <&ao_ctrl>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; reg = <0x0 0xf723e000 0x0 0x1000>; interrupts = <0x0 0x49 0x4>; #address-cells = <0x1>; -- cgit v1.2.3 From 79dca55a06c9c9b68692f814db7b9c684f946bc7 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 27 Apr 2016 16:56:46 +0800 Subject: arm64: dts: hikey: add i2s0 and hi6210_hdmi_card Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 312dcf63fd6f..2920241bd063 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -229,6 +229,8 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; + #sound-dai-cells = <0>; + interrupt-parent = <&gic>; ranges; sram: sram@fff80000 { @@ -983,5 +985,26 @@ "IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4", "IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6"; }; + + i2s0: hi6210_i2s { + compatible = "hisilicon,hi6210-i2s"; + reg = <0x0 0xf7118000 0x0 0x8000>, /* i2s unit */ + <0x0 0xf7030000 0x0 0x400>, /* syscon */ + <0x0 0xf7032000 0x0 0x400>; /* pmctrl */ + interrupts = <0 123 0x4>; /* 155 "DigACodec_intr" - 32 */ + pinctrl-names = "default"; + pinctrl-0 = <&bt_pmx_func &bt_cfg_func>; + clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, + <&sys_ctrl HI6220_BBPPLL0_DIV>; + clock-names = "dacodec", "i2s-base"; + dmas = <&dma0 15 &dma0 14>; + dma-names = "rx", "tx"; + }; + + hi6210_hdmi_card: hi6210_hdmi_card { + compatible = "hisilicon,hi6210-hdmi-audio-card"; + reg = <0 0 0 0>; + sound-dai = <&i2s0>; + }; }; }; -- cgit v1.2.3 From ab32fe8163588fbcf9bc5fda519d6f06386b47e0 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Mon, 21 Mar 2016 17:24:36 -0700 Subject: dts: hi6220: Add k3-dma entry Add entry for k3-dma driver Signed-off-by: John Stultz --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2920241bd063..d34039d56276 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -334,6 +334,19 @@ status = "disabled"; }; + dma0: dma@f7370000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0x0 0xf7370000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <15>; + dma-requests = <32>; + interrupts = <0 84 4>; + clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; + dma-no-cci; + dma-type = "hi6220_dma"; + status = "ok"; + }; + dual_timer0: dual_timer@f8008000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xf8008000 0x0 0x1000>; -- cgit v1.2.3 From 9142957af5fc594c2f3290654f50bc3fc9fd1cf1 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Tue, 22 Mar 2016 16:38:45 +0100 Subject: arm64: dt: hikey: Add optee node Signed-off-by: Jerome Forissier Reviewed-by: Jens Wiklander Reviewed-by: Pascal Brand --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e8adf5c4f5bc..9df44c849a15 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -46,6 +46,13 @@ <0x00000000 0x22000000 0x00000000 0x1c000000>; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + pstore: pstore@0x21f00000 { no-map; reg = <0x0 0x21f00000 0x0 0x00100000>; /* pstore/ramoops buffer */ -- cgit v1.2.3 From c9ee5398be5351a76a403791539c3c8df799adde Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 29 Apr 2016 01:34:04 +0800 Subject: arm64: dts: add Hi6220's EAS Energy model Add energy model for the CPUs and cluster states into Hi6220's DTS. Signed-off-by: Leo Yan --- .../boot/dts/hisilicon/hi6220-sched-energy.dtsi | 69 ++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 10 ++++ 2 files changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi new file mode 100644 index 000000000000..6dfc49332b4f --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi6220-sched-energy.dtsi @@ -0,0 +1,69 @@ +/* + * Hikey specific energy cost model data. + */ + +/* static struct idle_state idle_states_cluster_a53[] = { */ +/* { .power = 47 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */ +/* { .power = 47 }, /\* WFI *\/ */ +/* { .power = 47 }, /\* cpu-sleep-0 *\/ */ +/* { .power = 0 }, /\* cluster-sleep-0 *\/ */ +/* }; */ + +/* static struct capacity_state cap_states_cluster_a53[] = { */ +/* /\* Power per cluster *\/ */ +/* { .cap = 178, .power = 16, }, /\* 200 MHz *\/ */ +/* { .cap = 369, .power = 29, }, /\* 432 MHz *\/ */ +/* { .cap = 622, .power = 47, }, /\* 729 MHz *\/ */ +/* { .cap = 819, .power = 75, }, /\* 960 MHz *\/ */ +/* { .cap = 1024, .power = 112, }, /\* 1200 Mhz *\/ */ +/* }; */ + +/* static struct idle_state idle_states_core_a53[] = { */ +/* { .power = 15 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */ +/* { .power = 15 }, /\* WFI *\/ */ +/* { .power = 0 }, /\* cpu-sleep-0 *\/ */ +/* { .power = 0 }, /\* cluster-sleep-0 *\/ */ +/* }; */ + +/* static struct capacity_state cap_states_core_a53[] = { */ +/* /\* Power per cpu *\/ */ +/* { .cap = 178, .power = 69, }, /\* 200 MHz *\/ */ +/* { .cap = 369, .power = 124, }, /\* 432 MHz *\/ */ +/* { .cap = 622, .power = 224, }, /\* 729 MHz *\/ */ +/* { .cap = 819, .power = 367, }, /\* 960 MHz *\/ */ +/* { .cap = 1024, .power = 670, }, /\* 1200 Mhz *\/ */ +/* }; */ + +energy-costs { + CPU_COST: core-cost { + busy-cost-data = < + 178 69 + 369 124 + 622 224 + 819 367 + 1024 670 + >; + idle-cost-data = < + 15 + 15 + 0 + 0 + >; + }; + + CLUSTER_COST: cluster-cost { + busy-cost-data = < + 178 16 + 369 29 + 622 47 + 819 75 + 1024 112 + >; + idle-cost-data = < + 47 + 47 + 47 + 0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index d34039d56276..78d0a9fe1e17 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -91,6 +91,7 @@ cooling-max-level = <0>; #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; dynamic-power-coefficient = <311>; }; @@ -102,6 +103,7 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu2: cpu@2 { @@ -112,6 +114,7 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu3: cpu@3 { @@ -122,6 +125,7 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu4: cpu@100 { @@ -132,6 +136,7 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu5: cpu@101 { @@ -142,6 +147,7 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu6: cpu@102 { @@ -152,6 +158,7 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; cpu7: cpu@103 { @@ -162,6 +169,7 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + sched-energy-costs = <&CPU_COST &CLUSTER_COST>; }; CLUSTER0_L2: l2-cache0 { @@ -171,6 +179,8 @@ CLUSTER1_L2: l2-cache1 { compatible = "cache"; }; + + /include/ "hi6220-sched-energy.dtsi" }; cpu_opp_table: cpu_opp_table { -- cgit v1.2.3 From 29a7414d87ebcdc4d30283ed1b35e2e7d267fe46 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 23 May 2016 16:55:55 +0800 Subject: arm64: dts: hi6220: add pinmux for MODEM_PCM/I2S Add pinmux and cfg nodes for MODEM_PCM/I2S module. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi index 0916e8459d6b..d103cf10f0fa 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -230,6 +230,16 @@ 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ >; }; + + modem_pcm_pmx_func: modem_pcm_pmx_func { + pinctrl-single,pins = < + 0x198 MUX_M3 /* MODEM_PCM_XCLK (IOMG102) */ + 0x19c MUX_M3 /* MODEM_PCM_XFS (IOMG103) */ + 0x1d0 MUX_M3 /* MODEM_PCM_DI (IOMG116) */ + 0x1d4 MUX_M3 /* MODEM_PCM_DO (IOMG117) */ + >; + }; + }; pmx1: pinmux@f7010800 { @@ -646,6 +656,18 @@ pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; + + modem_pcm_cfg_func: modem_pcm_cfg_func { + pinctrl-single,pins = < + 0x1a8 0x0 /* MODEM_PCM_XCLK (IOCFG106) */ + 0x1ac 0x0 /* MODEM_PCM_XFS (IOCFG107) */ + 0x1e0 0x0 /* MODEM_PCM_DI (IOCFG120) */ + 0x1e4 0x0 /* MODEM_PCM_DO (IOCFG121) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; }; pmx2: pinmux@f8001800 { -- cgit v1.2.3 From e44caf1cf9a8267e9f858ccde9a4f4f136d29811 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Mon, 6 Jun 2016 09:37:00 +0800 Subject: arm64: dts: hi6220: Fix dma buffer coherent problem ADE module is not DMA coherent, so remove the 'dma-coherent;' property. This fix the display content corrupted issue. Signed-off-by: Xinliang Liu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 78d0a9fe1e17..18c92b3daf5b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -939,7 +939,6 @@ assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, <&media_ctrl HI6220_CODEC_JPEG>; assigned-clock-rates = <360000000>, <288000000>; - dma-coherent; status = "disabled"; port { -- cgit v1.2.3 From c60000cdf592eb661f573591468d6f18b1f3efc7 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 17 Jun 2016 19:59:57 +0800 Subject: arm64: dts: hikey: enable i2c0 to support touch panel ft5506 FT6606 is used on HiKey LCD panel mezzanine as touch input. Signed-off-by: oldpam Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 9df44c849a15..40eaa9ae4836 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -375,3 +375,17 @@ }; }; }; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + tp: tp@8{ + compatible = "FocalTech,ft5506"; + reg = <0x38>; + interrupt-parent = <&gpio2>; + interrupts = <7 2>; + rst-gpio = <&gpio9 1 1>; + }; +}; -- cgit v1.2.3 From 54e4eedb6952310fa7ec00b3d68ff19e9287cbf5 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 17 Jun 2016 20:02:35 +0800 Subject: arm64: dts: hikey: enable i2c1 to support MIPI-LVDS converter icn6201 ICN6201 is used by HiKey Mezzanine as MIPI-LVDS converter to support LVDS display panel. Signed-off-by: oldpam Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 40eaa9ae4836..727a0cee2316 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -389,3 +389,14 @@ rst-gpio = <&gpio9 1 1>; }; }; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + icn6201: icn6201@5a{ + compatible = "ChipOne,icn6201"; + reg = <0x2d>; + }; +}; -- cgit v1.2.3 From f32a7b398a5b44032f25516e37bca487db0b4b3e Mon Sep 17 00:00:00 2001 From: Akira Tsukamoto Date: Thu, 31 Dec 2015 15:55:24 +0900 Subject: arm64: dts: hikey: listing spidev Listing spidev for Low-Speed expansion port on HiKey Signed-off-by: Akira Tsukamoto Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 727a0cee2316..c36bd3aeea82 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -400,3 +400,15 @@ reg = <0x2d>; }; }; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + spidev@0 { + compatible = "linux,spidev"; + spi-max-frequency = <500000>; + reg = <0>; + }; +}; -- cgit v1.2.3 From d09fbe55a4470887ccde9a87538087625cac808e Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Mon, 1 Feb 2016 17:16:02 +0800 Subject: mfd: hi655x: Add document for mfd hi665x PMIC DT bindings for hisilicon hi655x MFD PMIC chip. Signed-off-by: Chen Feng Signed-off-by: Fei Wang Signed-off-by: Xinwei Kong Reviewed-by: Haojian Zhuang --- .../devicetree/bindings/mfd/hisilicon,hi655x.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt new file mode 100644 index 000000000000..5edc310470b6 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt @@ -0,0 +1,27 @@ +Hisilicon hi655x Power Management Integrated Circuit (PMIC) + +The hardware layout for access PMIC Hi655x from AP SoC Hi6220. +Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. +We can use memory-mapped I/O to communicate. + ++----------------+ +-------------+ +| | | | +| Hi6220 | SSI bus | Hi655x | +| |-------------| | +| |(REGMAP_MMIO)| | ++----------------+ +-------------+ + +Required properties: +- compatible: Should be "hisilicon,hi655x-pmic" +- reg: Base address of PMIC on hi6220 soc +- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). +- pmic-gpios: The gpio used by PMIC irq. + +Example: + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0x0 0xf8000000 0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + } -- cgit v1.2.3 From 823143e294343ac9dfef966c16675e5ffec5d2b8 Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Mon, 1 Feb 2016 17:16:03 +0800 Subject: regulator: hi655x: Document for hi655x regulator This patch adds the device tree binding documentation for hi655x PMIC regulator. Signed-off-by: Chen Feng Signed-off-by: Fei Wang Signed-off-by: Xinwei Kong Reviewed-by: Haojian Zhuang --- .../regulator/hisilicon,hi655x-regulator.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt diff --git a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt new file mode 100644 index 000000000000..09d3884e7cc2 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt @@ -0,0 +1,28 @@ +Hisilicon Hi655x Voltage regulators + +Note: +The hi655x regulator control is managed by hi655x Power IC. +So the node of this regulator must be child node of hi655x +PMIC node. + +The driver uses the regulator core framework, so please also +take the bindings of regulator.txt for reference. + +The valid names for regulators are: + +LDO2 LDO7 LDO10 LDO13 LDO14 LDO15 LDO17 LDO19 LDO21 LDO22 + +Example: + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + ... + regulators { + ldo2: LDO2@a21 { + regulator-compatible = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + ... + } + } -- cgit v1.2.3 From aba1a8453d97ac301be77dd0f98764d712a9b47b Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Mon, 1 Feb 2016 17:16:04 +0800 Subject: mfd: hi655x: Add MFD driver for hi655x Add PMIC MFD driver to support hisilicon hi665x. Signed-off-by: Chen Feng Signed-off-by: Fei Wang Signed-off-by: Xinwei Kong Reviewed-by: Haojian Zhuang --- drivers/mfd/Kconfig | 10 +++ drivers/mfd/Makefile | 1 + drivers/mfd/hi655x-pmic.c | 162 ++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/hi655x-pmic.h | 55 ++++++++++++++ 4 files changed, 228 insertions(+) create mode 100644 drivers/mfd/hi655x-pmic.c create mode 100644 include/linux/mfd/hi655x-pmic.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7398262a2fab..0226aacb2f0c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -284,6 +284,16 @@ config MFD_HI6421_PMIC menus in order to enable them. We communicate with the Hi6421 via memory-mapped I/O. +config MFD_HI655X_PMIC + tristate "HiSilicon Hi655X series PMU/Codec IC" + depends on ARCH_HISI || COMPILE_TEST + depends on OF + select MFD_CORE + select REGMAP_MMIO + select REGMAP_IRQ + help + Select this option to enable Hisilicon hi655x series pmic driver. + config HTC_EGPIO bool "HTC EGPIO support" depends on GPIOLIB && ARM diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index a8b76b81b467..6a7b0e1fe6ba 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -186,6 +186,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o +obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o obj-$(CONFIG_MFD_DLN2) += dln2.o obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c new file mode 100644 index 000000000000..05ddc7882362 --- /dev/null +++ b/drivers/mfd/hi655x-pmic.c @@ -0,0 +1,162 @@ +/* + * Device driver for MFD hi655x PMIC + * + * Copyright (c) 2016 Hisilicon. + * + * Authors: + * Chen Feng + * Fei Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell hi655x_pmic_devs[] = { + { .name = "hi655x-regulator", }, +}; + +static const struct regmap_irq hi655x_irqs[] = { + { .reg_offset = 0, .mask = OTMP_D1R_INT }, + { .reg_offset = 0, .mask = VSYS_2P5_R_INT }, + { .reg_offset = 0, .mask = VSYS_UV_D3R_INT }, + { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT }, + { .reg_offset = 0, .mask = PWRON_D4SR_INT }, + { .reg_offset = 0, .mask = PWRON_D20F_INT }, + { .reg_offset = 0, .mask = PWRON_D20R_INT }, + { .reg_offset = 0, .mask = RESERVE_INT }, +}; + +static const struct regmap_irq_chip hi655x_irq_chip = { + .name = "hi655x-pmic", + .irqs = hi655x_irqs, + .num_regs = 1, + .num_irqs = ARRAY_SIZE(hi655x_irqs), + .status_base = HI655X_IRQ_STAT_BASE, + .mask_base = HI655X_IRQ_MASK_BASE, +}; + +static struct regmap_config hi655x_regmap_config = { + .reg_bits = 32, + .reg_stride = HI655X_STRIDE, + .val_bits = 8, + .max_register = HI655X_BUS_ADDR(0xFFF), +}; + +static void hi655x_local_irq_clear(struct regmap *map) +{ + int i; + + regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR); + for (i = 0; i < HI655X_IRQ_ARRAY; i++) { + regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE, + HI655X_IRQ_CLR); + } +} + +static int hi655x_pmic_probe(struct platform_device *pdev) +{ + int ret; + struct hi655x_pmic *pmic; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + + pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); + if (!pmic) + return -ENOMEM; + pmic->dev = dev; + + pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!pmic->res) + return -ENOENT; + + base = devm_ioremap_resource(dev, pmic->res); + if (!base) + return -ENOMEM; + + pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base, + &hi655x_regmap_config); + + regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver); + if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) { + dev_warn(dev, "PMU version %d unsupported\n", pmic->ver); + return -EINVAL; + } + + hi655x_local_irq_clear(pmic->regmap); + + pmic->gpio = of_get_named_gpio(np, "pmic-gpios", 0); + if (!gpio_is_valid(pmic->gpio)) { + dev_err(dev, "Failed to get the pmic-gpios\n"); + return -ENODEV; + } + + ret = devm_gpio_request_one(dev, pmic->gpio, GPIOF_IN, + "hi655x_pmic_irq"); + if (ret < 0) { + dev_err(dev, "Failed to request gpio %d ret = %d\n", + pmic->gpio, ret); + return ret; + } + + ret = regmap_add_irq_chip(pmic->regmap, gpio_to_irq(pmic->gpio), + IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, 0, + &hi655x_irq_chip, &pmic->irq_data); + if (ret) { + dev_err(dev, "Failed to obtain 'hi655x_pmic_irq' %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, pmic); + + ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs, + ARRAY_SIZE(hi655x_pmic_devs), NULL, 0, NULL); + if (ret) { + dev_err(dev, "Failed to register device %d\n", ret); + regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data); + return ret; + } + + return 0; +} + +static int hi655x_pmic_remove(struct platform_device *pdev) +{ + struct hi655x_pmic *pmic = platform_get_drvdata(pdev); + + regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data); + mfd_remove_devices(&pdev->dev); + return 0; +} + +static const struct of_device_id hi655x_pmic_match[] = { + { .compatible = "hisilicon,hi655x-pmic", }, + {}, +}; + +static struct platform_driver hi655x_pmic_driver = { + .driver = { + .name = "hi655x-pmic", + .of_match_table = of_match_ptr(hi655x_pmic_match), + }, + .probe = hi655x_pmic_probe, + .remove = hi655x_pmic_remove, +}; +module_platform_driver(hi655x_pmic_driver); + +MODULE_AUTHOR("Chen Feng "); +MODULE_DESCRIPTION("Hisilicon hi655x PMIC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/hi655x-pmic.h b/include/linux/mfd/hi655x-pmic.h new file mode 100644 index 000000000000..dbbe9a644622 --- /dev/null +++ b/include/linux/mfd/hi655x-pmic.h @@ -0,0 +1,55 @@ +/* + * Device driver for regulators in hi655x IC + * + * Copyright (c) 2016 Hisilicon. + * + * Authors: + * Chen Feng + * Fei Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __HI655X_PMIC_H +#define __HI655X_PMIC_H + +/* Hi655x registers are mapped to memory bus in 4 bytes stride */ +#define HI655X_STRIDE 4 +#define HI655X_BUS_ADDR(x) ((x) << 2) + +#define HI655X_BITS 8 + +#define HI655X_NR_IRQ 32 + +#define HI655X_IRQ_STAT_BASE (0x003 << 2) +#define HI655X_IRQ_MASK_BASE (0x007 << 2) +#define HI655X_ANA_IRQM_BASE (0x1b5 << 2) +#define HI655X_IRQ_ARRAY 4 +#define HI655X_IRQ_MASK 0xFF +#define HI655X_IRQ_CLR 0xFF +#define HI655X_VER_REG 0x00 + +#define PMU_VER_START 0x10 +#define PMU_VER_END 0x38 + +#define RESERVE_INT BIT(7) +#define PWRON_D20R_INT BIT(6) +#define PWRON_D20F_INT BIT(5) +#define PWRON_D4SR_INT BIT(4) +#define VSYS_6P0_D200UR_INT BIT(3) +#define VSYS_UV_D3R_INT BIT(2) +#define VSYS_2P5_R_INT BIT(1) +#define OTMP_D1R_INT BIT(0) + +struct hi655x_pmic { + struct resource *res; + struct device *dev; + struct regmap *regmap; + int gpio; + unsigned int ver; + struct regmap_irq_chip_data *irq_data; +}; + +#endif -- cgit v1.2.3 From b730359fcfa970742185d79afc609b7cce803ad4 Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Mon, 1 Feb 2016 17:16:05 +0800 Subject: regulator: hi655x: enable regulator for hi655x PMIC Add the regulator driver for hi655x PMIC. Signed-off-by: Chen Feng Signed-off-by: Fei Wang Signed-off-by: Xinwei Kong Reviewed-by: Haojian Zhuang --- drivers/regulator/Kconfig | 8 ++ drivers/regulator/Makefile | 1 + drivers/regulator/hi655x-regulator.c | 228 +++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/regulator/hi655x-regulator.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 00676208080e..5b9140caf681 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -261,6 +261,14 @@ config REGULATOR_HI6421 21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All of them come with support to either ECO (idle) or sleep mode. +config REGULATOR_HI655X + tristate "Hisilicon HI655X PMIC regulators support" + depends on ARCH_HISI || COMPILE_TEST + depends on MFD_HI655X_PMIC && OF + help + This driver provides support for the voltage regulators of the + Hisilicon Hi655x PMIC device. + config REGULATOR_ISL9305 tristate "Intersil ISL9305 regulator" depends on I2C diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 0f8174913c17..8e4db96fd45b 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o +obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o diff --git a/drivers/regulator/hi655x-regulator.c b/drivers/regulator/hi655x-regulator.c new file mode 100644 index 000000000000..bca15edad512 --- /dev/null +++ b/drivers/regulator/hi655x-regulator.c @@ -0,0 +1,228 @@ +/* + * Device driver for regulators in hi655x IC + * + * Copyright (c) 2016 Hisilicon. + * + * Authors: + * Chen Feng + * Fei Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct hi655x_regulator { + unsigned int disable_reg; + unsigned int status_reg; + unsigned int ctrl_regs; + unsigned int ctrl_mask; + struct regulator_desc rdesc; +}; + +/* LDO7 & LDO10 */ +static const unsigned int ldo7_voltages[] = { + 1800000, 1850000, 2850000, 2900000, + 3000000, 3100000, 3200000, 3300000, +}; + +static const unsigned int ldo19_voltages[] = { + 1800000, 1850000, 1900000, 1750000, + 2800000, 2850000, 2900000, 3000000, +}; + +static const unsigned int ldo22_voltages[] = { + 900000, 1000000, 1050000, 1100000, + 1150000, 1175000, 1185000, 1200000, +}; + +enum hi655x_regulator_id { + HI655X_LDO0, + HI655X_LDO1, + HI655X_LDO2, + HI655X_LDO3, + HI655X_LDO4, + HI655X_LDO5, + HI655X_LDO6, + HI655X_LDO7, + HI655X_LDO8, + HI655X_LDO9, + HI655X_LDO10, + HI655X_LDO11, + HI655X_LDO12, + HI655X_LDO13, + HI655X_LDO14, + HI655X_LDO15, + HI655X_LDO16, + HI655X_LDO17, + HI655X_LDO18, + HI655X_LDO19, + HI655X_LDO20, + HI655X_LDO21, + HI655X_LDO22, +}; + +static int hi655x_is_enabled(struct regulator_dev *rdev) +{ + unsigned int value = 0; + + struct hi655x_regulator *regulator = rdev_get_drvdata(rdev); + + regmap_read(rdev->regmap, regulator->status_reg, &value); + return (value & BIT(regulator->ctrl_mask)); +} + +static int hi655x_disable(struct regulator_dev *rdev) +{ + int ret = 0; + + struct hi655x_regulator *regulator = rdev_get_drvdata(rdev); + + ret = regmap_write(rdev->regmap, regulator->disable_reg, + BIT(regulator->ctrl_mask)); + return ret; +} + +static struct regulator_ops hi655x_regulator_ops = { + .enable = regulator_enable_regmap, + .disable = hi655x_disable, + .is_enabled = hi655x_is_enabled, + .list_voltage = regulator_list_voltage_table, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, +}; + +static struct regulator_ops hi655x_ldo_linear_ops = { + .enable = regulator_enable_regmap, + .disable = hi655x_disable, + .is_enabled = hi655x_is_enabled, + .list_voltage = regulator_list_voltage_linear, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, +}; + +#define HI655X_LDO(_ID, vreg, vmask, ereg, dreg, \ + sreg, cmask, vtable) { \ + .rdesc = { \ + .name = #_ID, \ + .of_match = of_match_ptr(#_ID), \ + .ops = &hi655x_regulator_ops, \ + .regulators_node = of_match_ptr("regulators"), \ + .type = REGULATOR_VOLTAGE, \ + .id = HI655X_##_ID, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(vtable), \ + .volt_table = vtable, \ + .vsel_reg = HI655X_BUS_ADDR(vreg), \ + .vsel_mask = vmask, \ + .enable_reg = HI655X_BUS_ADDR(ereg), \ + .enable_mask = cmask, \ + }, \ + .disable_reg = HI655X_BUS_ADDR(dreg), \ + .status_reg = HI655X_BUS_ADDR(sreg), \ + .ctrl_mask = cmask, \ +} + +#define HI655X_LDO_LINEAR(_ID, vreg, vmask, ereg, dreg, \ + sreg, cmask, minv, nvolt, vstep) { \ + .rdesc = { \ + .name = #_ID, \ + .of_match = of_match_ptr(#_ID), \ + .ops = &hi655x_ldo_linear_ops, \ + .regulators_node = of_match_ptr("regulators"), \ + .type = REGULATOR_VOLTAGE, \ + .id = HI655X_##_ID, \ + .owner = THIS_MODULE, \ + .min_uV = minv, \ + .n_voltages = nvolt, \ + .uV_step = vstep, \ + .uV_step = vstep, \ + .vsel_reg = HI655X_BUS_ADDR(vreg), \ + .vsel_mask = vmask, \ + .enable_reg = HI655X_BUS_ADDR(ereg), \ + .enable_mask = cmask, \ + }, \ + .disable_reg = HI655X_BUS_ADDR(dreg), \ + .status_reg = HI655X_BUS_ADDR(sreg), \ + .ctrl_mask = cmask, \ +} + +static struct hi655x_regulator regulators[] = { + HI655X_LDO_LINEAR(LDO2, 0x72, 0x07, 0x29, 0x2a, 0x2b, 0x01, + 2500000, 8, 100000), + HI655X_LDO(LDO7, 0x78, 0x07, 0x29, 0x2a, 0x2b, 0x06, ldo7_voltages), + HI655X_LDO(LDO10, 0x78, 0x07, 0x29, 0x2a, 0x2b, 0x01, ldo7_voltages), + HI655X_LDO_LINEAR(LDO13, 0x7e, 0x07, 0x2c, 0x2d, 0x2e, 0x04, + 1600000, 8, 50000), + HI655X_LDO_LINEAR(LDO14, 0x7f, 0x07, 0x2c, 0x2d, 0x2e, 0x05, + 2500000, 8, 100000), + HI655X_LDO_LINEAR(LDO15, 0x80, 0x07, 0x2c, 0x2d, 0x2e, 0x06, + 1600000, 8, 50000), + HI655X_LDO_LINEAR(LDO17, 0x82, 0x07, 0x2f, 0x30, 0x31, 0x00, + 2500000, 8, 100000), + HI655X_LDO(LDO19, 0x84, 0x07, 0x2f, 0x30, 0x31, 0x02, ldo19_voltages), + HI655X_LDO_LINEAR(LDO21, 0x86, 0x07, 0x2f, 0x30, 0x31, 0x04, + 1650000, 8, 50000), + HI655X_LDO(LDO22, 0x87, 0x07, 0x2f, 0x30, 0x31, 0x05, ldo22_voltages), +}; + +static int hi655x_regulator_probe(struct platform_device *pdev) +{ + unsigned int i; + struct hi655x_regulator *regulator; + struct hi655x_pmic *pmic; + struct regulator_config config = { }; + struct regulator_dev *rdev; + + pmic = dev_get_drvdata(pdev->dev.parent); + if (!pmic) { + dev_err(&pdev->dev, "no pmic in the regulator parent node\n"); + return -ENODEV; + } + + regulator = devm_kzalloc(&pdev->dev, sizeof(*regulator), GFP_KERNEL); + if (!regulator) + return -ENOMEM; + + platform_set_drvdata(pdev, regulator); + + config.dev = pdev->dev.parent; + config.regmap = pmic->regmap; + config.driver_data = regulator; + for (i = 0; i < ARRAY_SIZE(regulators); i++) { + rdev = devm_regulator_register(&pdev->dev, + ®ulators[i].rdesc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register regulator %s\n", + regulator->rdesc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static struct platform_driver hi655x_regulator_driver = { + .driver = { + .name = "hi655x-regulator", + }, + .probe = hi655x_regulator_probe, +}; +module_platform_driver(hi655x_regulator_driver); + +MODULE_AUTHOR("Chen Feng "); +MODULE_DESCRIPTION("Hisilicon hi655x regulator driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From a6ef0ab7b30f6918ec4ea7ed7bbfcd23079b1dbd Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 4 Feb 2016 21:05:30 +0800 Subject: regulator: hi655x: bug fix, cmask should be BIT mask Signed-off-by: Guodong Xu --- drivers/regulator/hi655x-regulator.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/hi655x-regulator.c b/drivers/regulator/hi655x-regulator.c index bca15edad512..9074355791a2 100644 --- a/drivers/regulator/hi655x-regulator.c +++ b/drivers/regulator/hi655x-regulator.c @@ -33,7 +33,6 @@ struct hi655x_regulator { struct regulator_desc rdesc; }; -/* LDO7 & LDO10 */ static const unsigned int ldo7_voltages[] = { 1800000, 1850000, 2850000, 2900000, 3000000, 3100000, 3200000, 3300000, @@ -129,7 +128,7 @@ static struct regulator_ops hi655x_ldo_linear_ops = { .vsel_reg = HI655X_BUS_ADDR(vreg), \ .vsel_mask = vmask, \ .enable_reg = HI655X_BUS_ADDR(ereg), \ - .enable_mask = cmask, \ + .enable_mask = BIT(cmask), \ }, \ .disable_reg = HI655X_BUS_ADDR(dreg), \ .status_reg = HI655X_BUS_ADDR(sreg), \ @@ -149,11 +148,10 @@ static struct regulator_ops hi655x_ldo_linear_ops = { .min_uV = minv, \ .n_voltages = nvolt, \ .uV_step = vstep, \ - .uV_step = vstep, \ .vsel_reg = HI655X_BUS_ADDR(vreg), \ .vsel_mask = vmask, \ .enable_reg = HI655X_BUS_ADDR(ereg), \ - .enable_mask = cmask, \ + .enable_mask = BIT(cmask), \ }, \ .disable_reg = HI655X_BUS_ADDR(dreg), \ .status_reg = HI655X_BUS_ADDR(sreg), \ -- cgit v1.2.3 From e55e2581e3e6dff6f20cc5b71f3f6719025c6625 Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Wed, 9 Dec 2015 11:46:02 +0800 Subject: regulator: add driver for mtcmos voltage regulator on hi6220 SoC Add driver to support mtcmos on hi6220 Signed-off-by: Chen Feng Signed-off-by: Fei Wang --- drivers/regulator/Kconfig | 7 ++ drivers/regulator/Makefile | 1 + drivers/regulator/hi6220-mtcmos.c | 245 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 drivers/regulator/hi6220-mtcmos.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 5b9140caf681..10c46e236e8b 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -261,6 +261,13 @@ config REGULATOR_HI6421 21 general purpose LDOs, 3 dedicated LDOs, and 5 BUCKs. All of them come with support to either ECO (idle) or sleep mode. +config REGULATOR_HI6220_MTCMOS + bool "Hisilicon Hi6220 mtcmos support" + depends on ARCH_HISI + help + This driver provides support for the mtcmos regulators of Hi6220 Soc. + + config REGULATOR_HI655X tristate "Hisilicon HI655X PMIC regulators support" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 8e4db96fd45b..7345d43551ee 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o +obj-$(CONFIG_REGULATOR_HI6220_MTCMOS) += hi6220-mtcmos.o obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o diff --git a/drivers/regulator/hi6220-mtcmos.c b/drivers/regulator/hi6220-mtcmos.c new file mode 100644 index 000000000000..eabbc48f6921 --- /dev/null +++ b/drivers/regulator/hi6220-mtcmos.c @@ -0,0 +1,245 @@ +/* + * Device driver for regulators in hi6220 mtcmos + * + * Copyright (c) 2015 Hisilicon. + * + * Fei Wang + * Chen Feng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + HI6220_MTCMOS1, + HI6220_MTCMOS2, + HI6220_RG_MAX, +}; + +struct hi6220_mtcmos_ctrl_regs { + unsigned int enable_reg; + unsigned int disable_reg; + unsigned int status_reg; +}; + +struct hi6220_mtcmos_ctrl_data { + int shift; + unsigned int mask; +}; + +struct hi6220_mtcmos_info { + struct regulator_desc rdesc; + struct hi6220_mtcmos_ctrl_regs ctrl_regs; + struct hi6220_mtcmos_ctrl_data ctrl_data; +}; + +struct hi6220_mtcmos { + struct regulator_dev *rdev[HI6220_RG_MAX]; + void __iomem *sc_on_regs; +}; + +static int hi6220_mtcmos_is_on(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned int ret; + + ret = readl(mtcmos->sc_on_regs + regs); + ret &= (mask << shift); + + return ret; +} + +static int hi6220_mtcmos_is_enabled(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; + struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; + + ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, + ctrl_data->mask, ctrl_data->shift); + return ret; +} + +static int hi6220_mtcmos_op(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + writel(mask << shift, mtcmos->sc_on_regs + regs); + + return 0; +} + +static int hi6220_mtcmos_enable(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; + struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; + + hi6220_mtcmos_op(mtcmos, ctrl_regs->enable_reg, + ctrl_data->mask, ctrl_data->shift); + ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, + ctrl_data->mask, ctrl_data->shift); + return ret; +} + +static int hi6220_mtcmos_disable(struct regulator_dev *rdev) +{ + int ret; + struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); + struct platform_device *pdev = + container_of(rdev->dev.parent, struct platform_device, dev); + struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; + struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; + + ret = hi6220_mtcmos_op(mtcmos, ctrl_regs->disable_reg, + ctrl_data->mask, ctrl_data->shift); + + return ret; +} + +static struct regulator_ops hi6220_mtcmos_mtcmos_rops = { + .is_enabled = hi6220_mtcmos_is_enabled, + .enable = hi6220_mtcmos_enable, + .disable = hi6220_mtcmos_disable, +}; + +#define HI6220_MTCMOS(vreg) \ +{ \ + .rdesc = { \ + .name = #vreg, \ + .ops = &hi6220_mtcmos_mtcmos_rops, \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + }, \ +} + +static struct hi6220_mtcmos_info hi6220_mtcmos_info[] = { + HI6220_MTCMOS(MTCMOS1), + HI6220_MTCMOS(MTCMOS2), +}; + +static struct of_regulator_match hi6220_mtcmos_matches[] = { + { .name = "mtcmos1", + .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS1], }, + { .name = "mtcmos2", + .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS2], }, +}; + +static int hi6220_mtcmos_probe(struct platform_device *pdev) +{ + int ret; + struct hi6220_mtcmos *mtcmos; + const __be32 *sc_on_regs = NULL; + void __iomem *regs; + struct device *dev; + struct device_node *np, *child; + int i; + struct regulator_config config = { }; + struct regulator_init_data *init_data; + struct hi6220_mtcmos_info *sreg; + u32 off_on_delay = 0; + + dev = &pdev->dev; + np = dev->of_node; + mtcmos = devm_kzalloc(dev, sizeof(struct hi6220_mtcmos), GFP_KERNEL); + if (!mtcmos) + return -ENOMEM; + + sc_on_regs = of_get_property(np, "hisilicon,mtcmos-sc-on-base", NULL); + if (sc_on_regs) { + regs = ioremap(be32_to_cpu(*sc_on_regs), SZ_4K); + mtcmos->sc_on_regs = regs; + } else + return -ENODEV; + of_property_read_u32(np, "hisilicon,mtcmos-steady-us", &off_on_delay); + + for (i = 0; i < HI6220_RG_MAX; i++) { + init_data = hi6220_mtcmos_matches[i].init_data; + if (!init_data) + continue; + sreg = hi6220_mtcmos_matches[i].driver_data; + sreg->rdesc.off_on_delay = off_on_delay; + config.dev = &pdev->dev; + config.init_data = init_data; + config.driver_data = sreg; + config.of_node = hi6220_mtcmos_matches[i].of_node; + child = config.of_node; + + ret = of_property_read_u32_array(child, "hisilicon,ctrl-regs", + (u32 *)(&sreg->ctrl_regs), + 0x3); + ret = of_property_read_u32_array(child, "hisilicon,ctrl-data", + (u32 *)(&sreg->ctrl_data), + 0x2); + + mtcmos->rdev[i] = regulator_register(&sreg->rdesc, &config); + if (IS_ERR(mtcmos->rdev[i])) { + ret = PTR_ERR(mtcmos->rdev[i]); + dev_err(&pdev->dev, "failed to register mtcmos %s\n", + sreg->rdesc.name); + while (--i >= 0) + regulator_unregister(mtcmos->rdev[i]); + + return ret; + } + } + + platform_set_drvdata(pdev, mtcmos); + + return 0; +} + +static const struct of_device_id of_hi6220_mtcmos_match_tbl[] = { + { .compatible = "hisilicon,hi6220-mtcmos-driver", }, + {} +}; + +static struct platform_driver mtcmos_driver = { + .driver = { + .name = "hisi_hi6220_mtcmos", + .owner = THIS_MODULE, + .of_match_table = of_hi6220_mtcmos_match_tbl, + }, + .probe = hi6220_mtcmos_probe, +}; + +static int __init hi6220_mtcmos_init(void) +{ + return platform_driver_register(&mtcmos_driver); +} + +static void __exit hi6220_mtcmos_exit(void) +{ + platform_driver_unregister(&mtcmos_driver); +} + +fs_initcall(hi6220_mtcmos_init); +module_exit(hi6220_mtcmos_exit); + +MODULE_AUTHOR("Fei Wang "); +MODULE_DESCRIPTION("Hi6220 mtcmos interface driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From b61befdeea8e41a9847779efb3a6d6033a385574 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Thu, 21 Jan 2016 15:05:16 +0800 Subject: regulator: hi6220: Revert to 4.1 kernel mtcmos driver This is temporary. 4.4 kernel mtcmos driver is not working and need to be fixed. Signed-off-by: Xinliang Liu Signed-off-by: John Stultz --- drivers/regulator/hi6220-mtcmos.c | 140 ++++++++++++++++++++++---------------- 1 file changed, 82 insertions(+), 58 deletions(-) diff --git a/drivers/regulator/hi6220-mtcmos.c b/drivers/regulator/hi6220-mtcmos.c index eabbc48f6921..492be7adfaa2 100644 --- a/drivers/regulator/hi6220-mtcmos.c +++ b/drivers/regulator/hi6220-mtcmos.c @@ -1,16 +1,9 @@ /* - * Device driver for regulators in hi6220 mtcmos + * Device driver for MTCMOS DRIVER in HI6220 SOC * - * Copyright (c) 2015 Hisilicon. + * Copyright (c) 2011 Hisilicon Co. Ltd * - * Fei Wang - * Chen Feng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ - #include #include #include @@ -24,7 +17,8 @@ #include #include #include -#include +#include +#include enum { HI6220_MTCMOS1, @@ -52,79 +46,105 @@ struct hi6220_mtcmos_info { struct hi6220_mtcmos { struct regulator_dev *rdev[HI6220_RG_MAX]; void __iomem *sc_on_regs; + int mtcmos_steady_time; + spinlock_t mtcmos_spin_lock; }; static int hi6220_mtcmos_is_on(struct hi6220_mtcmos *mtcmos, - unsigned int regs, unsigned int mask, int shift) + unsigned int regs, unsigned int mask, int shift) { unsigned int ret; + unsigned long mtcmos_spin_flag = 0; + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); ret = readl(mtcmos->sc_on_regs + regs); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + ret &= (mask << shift); + return !!ret; +} - return ret; +int hi6220_mtcmos_on(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned long mtcmos_spin_flag = 0; + + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + writel(mask << shift, mtcmos->sc_on_regs + regs); + udelay(mtcmos->mtcmos_steady_time); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + + return 0; +} + +int hi6220_mtcmos_off(struct hi6220_mtcmos *mtcmos, + unsigned int regs, unsigned int mask, int shift) +{ + unsigned long mtcmos_spin_flag = 0; + + spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag); + writel(mask << shift, mtcmos->sc_on_regs + regs); + udelay(mtcmos->mtcmos_steady_time); + spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, + mtcmos_spin_flag); + + return 0; } -static int hi6220_mtcmos_is_enabled(struct regulator_dev *rdev) +static int hi6220_regulator_mtcmos_is_enabled(struct regulator_dev *rdev) { int ret; struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); struct platform_device *pdev = container_of(rdev->dev.parent, struct platform_device, dev); struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); - struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; - struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, - ctrl_data->mask, ctrl_data->shift); + ctrl_data->mask, ctrl_data->shift); return ret; } -static int hi6220_mtcmos_op(struct hi6220_mtcmos *mtcmos, - unsigned int regs, unsigned int mask, int shift) -{ - writel(mask << shift, mtcmos->sc_on_regs + regs); - - return 0; -} - -static int hi6220_mtcmos_enable(struct regulator_dev *rdev) +static int hi6220_regulator_mtcmos_enabled(struct regulator_dev *rdev) { int ret; struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); struct platform_device *pdev = container_of(rdev->dev.parent, struct platform_device, dev); struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); - struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; - struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; - - hi6220_mtcmos_op(mtcmos, ctrl_regs->enable_reg, - ctrl_data->mask, ctrl_data->shift); - ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, - ctrl_data->mask, ctrl_data->shift); + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); + + ret = hi6220_mtcmos_on(mtcmos, ctrl_regs->enable_reg, + ctrl_data->mask, ctrl_data->shift); + if (0 == hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg, + ctrl_data->mask, ctrl_data->shift)) { + return -1; + } return ret; } -static int hi6220_mtcmos_disable(struct regulator_dev *rdev) +static int hi6220_regulator_mtcmos_disabled(struct regulator_dev *rdev) { int ret; struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev); struct platform_device *pdev = container_of(rdev->dev.parent, struct platform_device, dev); struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev); - struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &sreg->ctrl_regs; - struct hi6220_mtcmos_ctrl_data *ctrl_data = &sreg->ctrl_data; + struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs); + struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data); - ret = hi6220_mtcmos_op(mtcmos, ctrl_regs->disable_reg, - ctrl_data->mask, ctrl_data->shift); + ret = hi6220_mtcmos_off(mtcmos, ctrl_regs->disable_reg, + ctrl_data->mask, ctrl_data->shift); return ret; } static struct regulator_ops hi6220_mtcmos_mtcmos_rops = { - .is_enabled = hi6220_mtcmos_is_enabled, - .enable = hi6220_mtcmos_enable, - .disable = hi6220_mtcmos_disable, + .is_enabled = hi6220_regulator_mtcmos_is_enabled, + .enable = hi6220_regulator_mtcmos_enabled, + .disable = hi6220_regulator_mtcmos_disabled, }; #define HI6220_MTCMOS(vreg) \ @@ -157,32 +177,38 @@ static int hi6220_mtcmos_probe(struct platform_device *pdev) void __iomem *regs; struct device *dev; struct device_node *np, *child; - int i; + int count, i; struct regulator_config config = { }; struct regulator_init_data *init_data; struct hi6220_mtcmos_info *sreg; - u32 off_on_delay = 0; dev = &pdev->dev; np = dev->of_node; - mtcmos = devm_kzalloc(dev, sizeof(struct hi6220_mtcmos), GFP_KERNEL); - if (!mtcmos) + mtcmos = devm_kzalloc(dev, + sizeof(struct hi6220_mtcmos), GFP_KERNEL); + if (!mtcmos) { + dev_err(dev, "cannot allocate hi6220_mtcmos device info\n"); return -ENOMEM; + } + spin_lock_init((spinlock_t *)&mtcmos->mtcmos_spin_lock); sc_on_regs = of_get_property(np, "hisilicon,mtcmos-sc-on-base", NULL); if (sc_on_regs) { - regs = ioremap(be32_to_cpu(*sc_on_regs), SZ_4K); + regs = ioremap(be32_to_cpu(*sc_on_regs), 0x1000); mtcmos->sc_on_regs = regs; - } else - return -ENODEV; - of_property_read_u32(np, "hisilicon,mtcmos-steady-us", &off_on_delay); + } + ret = of_property_read_u32(np, "hisilicon,mtcmos-steady-us", + &mtcmos->mtcmos_steady_time); + + count = of_regulator_match(&pdev->dev, np, + hi6220_mtcmos_matches, + ARRAY_SIZE(hi6220_mtcmos_matches)); for (i = 0; i < HI6220_RG_MAX; i++) { init_data = hi6220_mtcmos_matches[i].init_data; if (!init_data) continue; sreg = hi6220_mtcmos_matches[i].driver_data; - sreg->rdesc.off_on_delay = off_on_delay; config.dev = &pdev->dev; config.init_data = init_data; config.driver_data = sreg; @@ -190,17 +216,15 @@ static int hi6220_mtcmos_probe(struct platform_device *pdev) child = config.of_node; ret = of_property_read_u32_array(child, "hisilicon,ctrl-regs", - (u32 *)(&sreg->ctrl_regs), - 0x3); + (unsigned int *)(&sreg->ctrl_regs), 0x3); ret = of_property_read_u32_array(child, "hisilicon,ctrl-data", - (u32 *)(&sreg->ctrl_data), - 0x2); + (unsigned int *)(&sreg->ctrl_data), 0x2); mtcmos->rdev[i] = regulator_register(&sreg->rdesc, &config); if (IS_ERR(mtcmos->rdev[i])) { ret = PTR_ERR(mtcmos->rdev[i]); dev_err(&pdev->dev, "failed to register mtcmos %s\n", - sreg->rdesc.name); + sreg->rdesc.name); while (--i >= 0) regulator_unregister(mtcmos->rdev[i]); @@ -213,7 +237,7 @@ static int hi6220_mtcmos_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id of_hi6220_mtcmos_match_tbl[] = { +static struct of_device_id of_hi6220_mtcmos_match_tbl[] = { { .compatible = "hisilicon,hi6220-mtcmos-driver", }, {} }; @@ -240,6 +264,6 @@ static void __exit hi6220_mtcmos_exit(void) fs_initcall(hi6220_mtcmos_init); module_exit(hi6220_mtcmos_exit); -MODULE_AUTHOR("Fei Wang "); -MODULE_DESCRIPTION("Hi6220 mtcmos interface driver"); -MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Baixing Quan"); +MODULE_DESCRIPTION("HI6220 MTCMOS interface driver"); +MODULE_LICENSE("GPL V2"); -- cgit v1.2.3 From 3b69c65e095438ef6dc9972630916a62bd46fdd4 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 9 Feb 2016 10:57:28 -0800 Subject: hi655x-pmic: Make hi655x pmic logic probe child nodes in the dt In trying to wire up the powerkey driver, I found I needed to add this to get the pmic logic to probe child nodes in the dt data. With this patch, child nodes get properly probed. Signed-off-by: John Stultz --- drivers/mfd/hi655x-pmic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c index 05ddc7882362..ae169f1aa8d0 100644 --- a/drivers/mfd/hi655x-pmic.c +++ b/drivers/mfd/hi655x-pmic.c @@ -39,6 +39,16 @@ static const struct regmap_irq hi655x_irqs[] = { { .reg_offset = 0, .mask = RESERVE_INT }, }; +static struct of_device_id of_hi655x_pmic_child_match_tbl[] = { + { .compatible = "hisilicon,hi6552-regulator-pmic", }, + { .compatible = "hisilicon,hi6552-powerkey", }, + { .compatible = "hisilicon,hi6552-usbvbus", }, + { .compatible = "hisilicon,hi6552-coul", }, + { .compatible = "hisilicon,hi6552-pmu-rtc", }, + { .compatible = "hisilicon,hi6552-pmic-mntn", }, + { /* end */ } +}; + static const struct regmap_irq_chip hi655x_irq_chip = { .name = "hi655x-pmic", .irqs = hi655x_irqs, @@ -122,6 +132,9 @@ static int hi655x_pmic_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmic); + /* populate sub nodes */ + of_platform_populate(np, of_hi655x_pmic_child_match_tbl, NULL, dev); + ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs, ARRAY_SIZE(hi655x_pmic_devs), NULL, 0, NULL); if (ret) { -- cgit v1.2.3 From df5138f92bfacb6ef00648ce9327a47b6caae7af Mon Sep 17 00:00:00 2001 From: John Stultz Date: Wed, 10 Feb 2016 22:04:33 -0800 Subject: hi655x-pmic: Fixup issue with un-acked interrupts While trying to get the powerkey to funciton, I found when pressing the key, I would get infinitely repeating interrupts. After digging around a bit, it seems we didn't set the ack_base value for the regmap irqchip logic, so nothing was acking the interrupt. This patch adds the ack_base, which seems to make things work. Signed-off-by: John Stultz --- drivers/mfd/hi655x-pmic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c index ae169f1aa8d0..20607af75927 100644 --- a/drivers/mfd/hi655x-pmic.c +++ b/drivers/mfd/hi655x-pmic.c @@ -55,6 +55,7 @@ static const struct regmap_irq_chip hi655x_irq_chip = { .num_regs = 1, .num_irqs = ARRAY_SIZE(hi655x_irqs), .status_base = HI655X_IRQ_STAT_BASE, + .ack_base = HI655X_IRQ_STAT_BASE, .mask_base = HI655X_IRQ_MASK_BASE, }; -- cgit v1.2.3 From e4d2976aaf8ded51a70e9e640bb44e989c125d5b Mon Sep 17 00:00:00 2001 From: Fei Wang Date: Thu, 5 Feb 2015 23:55:05 +0800 Subject: misc: hi6220: Add driver to config chips at kernel boot, enable CK32B for wifi This driver is used to configure the hi6220 SoC to control some device hosts(e.g. pmic clock output CK32B), reset the host or disable the reset. CK32B is a 32K clock output from PMIC Hi6553. This clock is used by TI WL1835MOD on HiKey board. Signed-off-by: Bintian Wang Signed-off-by: Guodong Xu --- drivers/misc/Kconfig | 8 ++++++++ drivers/misc/Makefile | 1 + drivers/misc/hi6220-sysconfig.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) create mode 100644 drivers/misc/hi6220-sysconfig.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 4bf7d50b1bc7..c4bbd7280e9d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -466,6 +466,14 @@ config BMP085_SPI To compile this driver as a module, choose M here: the module will be called bmp085-spi. +config HI6220_SYSCFG + bool "Hisilicon HI6220 System Configuration driver" + depends on ARCH_HISI + default y + help + Hisilicon HI6220 uses some registers to configure some chip hosts to + work or not, e.g. disable the UART hosts reset and let's them work. + config PCH_PHUB tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) PHUB" select GENERIC_NET_UTILS diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 537d7f3b78da..b84697a9010b 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o obj-$(CONFIG_BMP085) += bmp085.o obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o +obj-$(CONFIG_HI6220_SYSCFG) += hi6220-sysconfig.o obj-$(CONFIG_DUMMY_IRQ) += dummy-irq.o obj-$(CONFIG_ICS932S401) += ics932s401.o obj-$(CONFIG_LKDTM) += lkdtm.o diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c new file mode 100644 index 000000000000..fa83941df375 --- /dev/null +++ b/drivers/misc/hi6220-sysconfig.c @@ -0,0 +1,40 @@ +/* + * For Hisilicon Hi6220 SoC, the reset of some hosts (e.g. UART) should be disabled + * before using them, this driver will handle the host chip reset disable. + * + * Copyright (C) 2015 Hisilicon Ltd. + * Author: Bintian Wang + * + */ + +#include +#include +#include + +#define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base) + +static int __init hi6220_sysconf(void) +{ + static void __iomem *base1 = NULL; + struct device_node *node1; + unsigned char ret; + + node1 = of_find_compatible_node(NULL, NULL, "hisilicon,hi655x-pmic"); + if (!node1) + return -ENOENT; + + base1 = of_iomap(node1, 0); + if (base1 == NULL) { + printk(KERN_ERR "hi6220: pmic reg iomap failed!\n"); + return -ENOMEM; + } + + /*enable clk for BT/WIFI*/ + ret = *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c); + ret |= 0x40; + *(volatile unsigned char*)PMUSSI_REG_EX(base1, 0x1c) = ret; + + iounmap(base1); + return 0; +} +postcore_initcall(hi6220_sysconf); -- cgit v1.2.3 From 4e59d54296a7a4a79c902ffed85493e3cf09c72e Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 5 Jan 2016 11:35:57 +0800 Subject: misc: hi6220: reset uart1 at booting for bluetooth Signed-off-by: Guodong Xu --- drivers/misc/hi6220-sysconfig.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c index fa83941df375..7e9915d7b197 100644 --- a/drivers/misc/hi6220-sysconfig.c +++ b/drivers/misc/hi6220-sysconfig.c @@ -11,14 +11,34 @@ #include #include +#define reset_offset 0x334 +#define pclk_offset 0x230 #define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base) static int __init hi6220_sysconf(void) { + static void __iomem *base = NULL; + struct device_node *node; static void __iomem *base1 = NULL; struct device_node *node1; unsigned char ret; + node = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220-sysctrl"); + if (!node) + return -ENOENT; + + base = of_iomap(node, 0); + if (base == NULL) { + printk(KERN_ERR "hi6220: sysctrl reg iomap failed!\n"); + return -ENOMEM; + } + + /*Disable UART1 reset and set pclk*/ + writel(BIT(5), base + reset_offset); + writel(BIT(5), base + pclk_offset); + + iounmap(base); + node1 = of_find_compatible_node(NULL, NULL, "hisilicon,hi655x-pmic"); if (!node1) return -ENOENT; -- cgit v1.2.3 From 4693d73e76ce5438cfa9daa8b9dfe493b2899056 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 17 Feb 2016 22:15:27 +0800 Subject: misc: hi6220: reset uart2, uart3, and uart4 upon kernel boots Signed-off-by: Guodong Xu --- drivers/misc/hi6220-sysconfig.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c index 7e9915d7b197..9b9d5d8bff19 100644 --- a/drivers/misc/hi6220-sysconfig.c +++ b/drivers/misc/hi6220-sysconfig.c @@ -37,6 +37,18 @@ static int __init hi6220_sysconf(void) writel(BIT(5), base + reset_offset); writel(BIT(5), base + pclk_offset); + /*Disable UART2 reset and set pclk*/ + writel(BIT(6), base + reset_offset); + writel(BIT(6), base + pclk_offset); + + /*Disable UART3 reset and set pclk*/ + writel(BIT(7), base + reset_offset); + writel(BIT(7), base + pclk_offset); + + /*Disable UART4 reset and set pclk*/ + writel(BIT(8), base + reset_offset); + writel(BIT(8), base + pclk_offset); + iounmap(base); node1 = of_find_compatible_node(NULL, NULL, "hisilicon,hi655x-pmic"); -- cgit v1.2.3 From 6f51031e88b21475692cc04a9cc2b04d198f6c48 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Wed, 2 Mar 2016 19:21:24 +0800 Subject: Documentation: synopsys-dw-mshc: add binding for resets Add resets property to synopsys-dw-mshc bindings. It is intended to represent the hardware reset signal present internally in some host controller IC designs. See Documentation/devicetree/bindings/reset/reset.txt for details. Signed-off-by: Guodong Xu --- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 8636f5ae97e5..9b4896c11716 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -39,6 +39,10 @@ Required Properties: Optional properties: +* resets: phandle + reset specifier pair, intended to represent hardware + reset signal present internally in some host controller IC designs. + See Documentation/devicetree/bindings/reset/reset.txt for details. + * clocks: from common clock binding: handle to biu and ciu clocks for the bus interface unit clock and the card interface unit clock. @@ -48,7 +52,7 @@ Optional properties: clock-frequency. It is an error to omit both the ciu clock and the clock-frequency. -* clock-frequency: should be the frequency (in Hz) of the ciu clock. If this +* clock-frequency: should be tke frequency (in Hz) of the ciu clock. If this is specified and the ciu clock is specified then we'll try to set the ciu clock to this at probe time. -- cgit v1.2.3 From 612400d82c7c0b08280eb34071b484fcd458763f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 16 Feb 2016 10:45:11 +0800 Subject: mmc: dw_mmc: add resets support to dw_mci_parse_dt() With this, user can add a 'resets' property into dw_mmc dts node, and when driver probe and parse_dt, it will call reset APIs to reset dw_mmc host controller. Please also refer to Documentation/devicetree/bindings/reset/reset.txt Signed-off-by: Guodong Xu Signed-off-by: Xinwei Kong Signed-off-by: Zhangfei Gao --- drivers/mmc/host/dw_mmc.c | 7 +++++++ include/linux/mmc/dw_mmc.h | 6 ++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index fb204ee6ff89..5039be13be2b 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2879,6 +2879,13 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) if (!pdata) return ERR_PTR(-ENOMEM); + /* find reset controller when exist */ + pdata->rstc = devm_reset_control_get_optional(dev, NULL); + if (IS_ERR(pdata->rstc)) + pdata->rstc = NULL; + else + reset_control_deassert(pdata->rstc); + /* find out number of slots supported */ if (of_property_read_u32(dev->of_node, "num-slots", &pdata->num_slots)) { diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 7776afb0ffa5..b4295be358ec 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -14,9 +14,10 @@ #ifndef LINUX_MMC_DW_MMC_H #define LINUX_MMC_DW_MMC_H -#include -#include #include +#include +#include +#include #define MAX_MCI_SLOTS 2 @@ -276,6 +277,7 @@ struct dw_mci_board { /* delay in mS before detecting cards after interrupt */ u32 detect_delay_ms; + struct reset_control *rstc; struct dw_mci_dma_ops *dma_ops; struct dma_pdata *data; }; -- cgit v1.2.3 From 9e4f844ba4f0c0fe02d605f19ba0d4accaeff79d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 4 Mar 2016 15:54:26 +0800 Subject: dwmmc: hikey: fix and improvement about reset Signed-off-by: Guodong Xu --- drivers/mmc/host/dw_mmc.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 5039be13be2b..d6310942c5a9 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2881,10 +2881,12 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) /* find reset controller when exist */ pdata->rstc = devm_reset_control_get_optional(dev, NULL); - if (IS_ERR(pdata->rstc)) - pdata->rstc = NULL; - else - reset_control_deassert(pdata->rstc); + if (IS_ERR(pdata->rstc)) { + if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) + return ERR_PTR(-EPROBE_DEFER); + else + pdata->rstc = NULL; + } /* find out number of slots supported */ if (of_property_read_u32(dev->of_node, "num-slots", @@ -2966,7 +2968,9 @@ int dw_mci_probe(struct dw_mci *host) if (!host->pdata) { host->pdata = dw_mci_parse_dt(host); - if (IS_ERR(host->pdata)) { + if (PTR_ERR(host->pdata) == -EPROBE_DEFER) + return -EPROBE_DEFER; + else if (IS_ERR(host->pdata)) { dev_err(host->dev, "platform data not available\n"); return -EINVAL; } @@ -3035,6 +3039,9 @@ int dw_mci_probe(struct dw_mci *host) } } + if (host->pdata->rstc != NULL) + reset_control_deassert(host->pdata->rstc); + setup_timer(&host->cmd11_timer, dw_mci_cmd11_timer, (unsigned long)host); @@ -3181,6 +3188,9 @@ err_dmaunmap: if (host->use_dma && host->dma_ops->exit) host->dma_ops->exit(host); + if (host->pdata->rstc != NULL) + reset_control_assert(host->pdata->rstc); + err_clk_ciu: if (!IS_ERR(host->ciu_clk)) clk_disable_unprepare(host->ciu_clk); @@ -3213,11 +3223,15 @@ void dw_mci_remove(struct dw_mci *host) if (host->use_dma && host->dma_ops->exit) host->dma_ops->exit(host); + if (host->pdata->rstc != NULL) + reset_control_assert(host->pdata->rstc); + if (!IS_ERR(host->ciu_clk)) clk_disable_unprepare(host->ciu_clk); if (!IS_ERR(host->biu_clk)) clk_disable_unprepare(host->biu_clk); + } EXPORT_SYMBOL(dw_mci_remove); -- cgit v1.2.3 From 5c68ed902d9bb985e28f465bad4300ff469ba94f Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Wed, 10 Feb 2016 14:48:00 +0100 Subject: mmc: dw_mmc: hikey: add MMC_CAP_CMD23 Enables RPMB support for the on-board eMMC as well as for eMMC modules connected to the microSD slot. Signed-off-by: Jerome Forissier --- drivers/mmc/host/dw_mmc-k3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c index 63c2e2ed1288..8e9d886bfcda 100644 --- a/drivers/mmc/host/dw_mmc-k3.c +++ b/drivers/mmc/host/dw_mmc-k3.c @@ -32,6 +32,12 @@ struct k3_priv { struct regmap *reg; }; +static unsigned long dw_mci_hi6220_caps[] = { + MMC_CAP_CMD23, + MMC_CAP_CMD23, + 0 +}; + static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) { int ret; @@ -126,6 +132,7 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) } static const struct dw_mci_drv_data hi6220_data = { + .caps = dw_mci_hi6220_caps, .switch_voltage = dw_mci_hi6220_switch_voltage, .set_ios = dw_mci_hi6220_set_ios, .parse_dt = dw_mci_hi6220_parse_dt, -- cgit v1.2.3 From d6ecd4d6783b055bfc0f9ac818afaba296dac8fb Mon Sep 17 00:00:00 2001 From: Xinwei Kong Date: Sat, 16 Jan 2016 16:34:30 +0800 Subject: mmc: dw_mmc: hikey: add this to support uhs mode sd card With this, dwmmc_1 (SD card slot) can support cards working at UHS speed mod. Signed-off-by: Xinwei Kong --- drivers/mmc/host/dw_mmc-k3.c | 6 ++++++ drivers/mmc/host/dw_mmc.c | 18 +++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c index 8e9d886bfcda..6aa6d0d63f7f 100644 --- a/drivers/mmc/host/dw_mmc-k3.c +++ b/drivers/mmc/host/dw_mmc-k3.c @@ -131,11 +131,17 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios) host->bus_hz = clk_get_rate(host->biu_clk); } +static void dw_mci_hi6220_prepare_command(struct dw_mci *host, u32 *cmdr) +{ + *cmdr |= SDMMC_CMD_USE_HOLD_REG; +} + static const struct dw_mci_drv_data hi6220_data = { .caps = dw_mci_hi6220_caps, .switch_voltage = dw_mci_hi6220_switch_voltage, .set_ios = dw_mci_hi6220_set_ios, .parse_dt = dw_mci_hi6220_parse_dt, + .prepare_command = dw_mci_hi6220_prepare_command, }; static const struct of_device_id dw_mci_k3_match[] = { diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index d6310942c5a9..900a4941eab5 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -250,7 +250,7 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) cmdr |= SDMMC_CMD_PRV_DAT_WAIT; if (cmd->opcode == SD_SWITCH_VOLTAGE) { - u32 clk_en_a; + /*u32 clk_en_a;*/ /* Special bit makes CMD11 not die */ cmdr |= SDMMC_CMD_VOLT_SWITCH; @@ -270,11 +270,11 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) * ever called with a non-zero clock. That shouldn't happen * until the voltage change is all done. */ - clk_en_a = mci_readl(host, CLKENA); - clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); - mci_writel(host, CLKENA, clk_en_a); - mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | - SDMMC_CMD_PRV_DAT_WAIT, 0); + /*clk_en_a = mci_readl(host, CLKENA);*/ + /*clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);*/ + /*mci_writel(host, CLKENA, clk_en_a);*/ + /*mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |*/ + /*SDMMC_CMD_PRV_DAT_WAIT, 0);*/ } if (cmd->flags & MMC_RSP_PRESENT) { @@ -1124,7 +1124,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) /* enable clock; only low power if no SDIO */ clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; - if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) + if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags) && (slot->mmc->index != 1)) clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; mci_writel(host, CLKENA, clk_en_a); @@ -1298,6 +1298,8 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) regs |= ((0x1 << slot->id) << 16); else regs &= ~((0x1 << slot->id) << 16); + if (mmc->index == 1) + regs |= (0x1 << slot->id); mci_writel(slot->host, UHS_REG, regs); slot->host->timing = ios->timing; @@ -1540,6 +1542,8 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) if (drv_data && drv_data->execute_tuning) err = drv_data->execute_tuning(slot, opcode); + else + err = 0; return err; } -- cgit v1.2.3 From f1123fab8ff46c825ba1436ab25defa826847313 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 18 Nov 2015 15:39:47 +0800 Subject: usb: dwc2: add support of hi6220 Support hisilicon,hi6220-usb for HiKey board Acked-by: Rob Herring Acked-by: John Youn Signed-off-by: Zhangfei Gao Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc2.txt | 1 + drivers/usb/dwc2/platform.c | 32 ++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index fd132cbee70e..221368207ca4 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -4,6 +4,7 @@ Platform DesignWare HS OTG USB 2.0 controller Required properties: - compatible : One of: - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. + - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index 39c1cbf0e75d..912590c3bd74 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2/platform.c @@ -54,6 +54,37 @@ static const char dwc2_driver_name[] = "dwc2"; +static const struct dwc2_core_params params_hi6220 = { + .otg_cap = 2, /* No HNP/SRP capable */ + .otg_ver = 0, /* 1.3 */ + .dma_enable = 1, + .dma_desc_enable = 0, + .speed = 0, /* High Speed */ + .enable_dynamic_fifo = 1, + .en_multiple_tx_fifo = 1, + .host_rx_fifo_size = 512, + .host_nperio_tx_fifo_size = 512, + .host_perio_tx_fifo_size = 512, + .max_transfer_size = 65535, + .max_packet_count = 511, + .host_channels = 16, + .phy_type = 1, /* UTMI */ + .phy_utmi_width = 8, + .phy_ulpi_ddr = 0, /* Single */ + .phy_ulpi_ext_vbus = 0, + .i2c_enable = 0, + .ulpi_fs_ls = 0, + .host_support_fs_ls_low_power = 0, + .host_ls_low_power_phy_clk = 0, /* 48 MHz */ + .ts_dline = 0, + .reload_ctl = 0, + .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT, + .uframe_sched = 0, + .external_id_pin_ctl = -1, + .hibernation = -1, +}; + static const struct dwc2_core_params params_bcm2835 = { .otg_cap = 0, /* HNP/SRP capable */ .otg_ver = 0, /* 1.3 */ @@ -308,6 +339,7 @@ static int dwc2_driver_remove(struct platform_device *dev) static const struct of_device_id dwc2_of_match_table[] = { { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, + { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, { .compatible = "snps,dwc2", .data = NULL }, { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, -- cgit v1.2.3 From c098901b4e555e7b6d7773d6bac18008a711ba8e Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Mon, 23 Nov 2015 10:44:04 +0800 Subject: phy: add phy-hi6220-usb Support hi6220 use phy for HiKey board Acked-by: Rob Herring Signed-off-by: Zhangfei Gao --- .../devicetree/bindings/phy/phy-hi6220-usb.txt | 16 ++ drivers/phy/Kconfig | 9 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-hi6220-usb.c | 168 +++++++++++++++++++++ 4 files changed, 194 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt create mode 100644 drivers/phy/phy-hi6220-usb.c diff --git a/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt new file mode 100644 index 000000000000..f17a56e2152f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt @@ -0,0 +1,16 @@ +Hisilicon hi6220 usb PHY +----------------------- + +Required properties: +- compatible: should be "hisilicon,hi6220-usb-phy" +- #phy-cells: must be 0 +- hisilicon,peripheral-syscon: phandle of syscon used to control phy. +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: + usb_phy: usbphy { + compatible = "hisilicon,hi6220-usb-phy"; + #phy-cells = <0>; + phy-supply = <&fixed_5v_hub>; + hisilicon,peripheral-syscon = <&sys_ctrl>; + }; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index b5679fb67591..1f08800a6473 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -215,6 +215,15 @@ config PHY_MT65XX_USB3 for mt65xx SoCs. it supports two usb2.0 ports and one usb3.0 port. +config PHY_HI6220_USB + tristate "hi6220 USB PHY support" + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON HI6220 USB PHY. + + To compile this driver as a module, choose M here. + config PHY_SUN4I_USB tristate "Allwinner sunxi SoC USB PHY driver" depends on ARCH_SUNXI && HAS_IOMEM && OF diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 075db1a81aa5..faccda1f237f 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o +obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o diff --git a/drivers/phy/phy-hi6220-usb.c b/drivers/phy/phy-hi6220-usb.c new file mode 100644 index 000000000000..b2141cbd4cf6 --- /dev/null +++ b/drivers/phy/phy-hi6220-usb.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2015 Linaro Ltd. + * Copyright (c) 2015 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#define SC_PERIPH_CTRL4 0x00c + +#define CTRL4_PICO_SIDDQ BIT(6) +#define CTRL4_PICO_OGDISABLE BIT(8) +#define CTRL4_PICO_VBUSVLDEXT BIT(10) +#define CTRL4_PICO_VBUSVLDEXTSEL BIT(11) +#define CTRL4_OTG_PHY_SEL BIT(21) + +#define SC_PERIPH_CTRL5 0x010 + +#define CTRL5_USBOTG_RES_SEL BIT(3) +#define CTRL5_PICOPHY_ACAENB BIT(4) +#define CTRL5_PICOPHY_BC_MODE BIT(5) +#define CTRL5_PICOPHY_CHRGSEL BIT(6) +#define CTRL5_PICOPHY_VDATSRCEND BIT(7) +#define CTRL5_PICOPHY_VDATDETENB BIT(8) +#define CTRL5_PICOPHY_DCDENB BIT(9) +#define CTRL5_PICOPHY_IDDIG BIT(10) + +#define SC_PERIPH_CTRL8 0x018 +#define SC_PERIPH_RSTEN0 0x300 +#define SC_PERIPH_RSTDIS0 0x304 + +#define RST0_USBOTG_BUS BIT(4) +#define RST0_POR_PICOPHY BIT(5) +#define RST0_USBOTG BIT(6) +#define RST0_USBOTG_32K BIT(7) + +#define EYE_PATTERN_PARA 0x7053348c + +struct hi6220_priv { + struct regmap *reg; + struct device *dev; +}; + +static void hi6220_phy_init(struct hi6220_priv *priv) +{ + struct regmap *reg = priv->reg; + u32 val, mask; + + val = RST0_USBOTG_BUS | RST0_POR_PICOPHY | + RST0_USBOTG | RST0_USBOTG_32K; + mask = val; + regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val); + regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val); +} + +static int hi6220_phy_setup(struct hi6220_priv *priv, bool on) +{ + struct regmap *reg = priv->reg; + u32 val, mask; + int ret; + + if (on) { + val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB; + mask = val | CTRL5_PICOPHY_BC_MODE; + ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val); + if (ret) + goto out; + + val = CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL | + CTRL4_OTG_PHY_SEL; + mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE; + ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); + if (ret) + goto out; + + ret = regmap_write(reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA); + if (ret) + goto out; + } else { + val = CTRL4_PICO_SIDDQ; + mask = val; + ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); + if (ret) + goto out; + } + + return 0; +out: + dev_err(priv->dev, "failed to setup phy ret: %d\n", ret); + return ret; +} + +static int hi6220_phy_start(struct phy *phy) +{ + struct hi6220_priv *priv = phy_get_drvdata(phy); + + return hi6220_phy_setup(priv, true); +} + +static int hi6220_phy_exit(struct phy *phy) +{ + struct hi6220_priv *priv = phy_get_drvdata(phy); + + return hi6220_phy_setup(priv, false); +} + +static struct phy_ops hi6220_phy_ops = { + .init = hi6220_phy_start, + .exit = hi6220_phy_exit, + .owner = THIS_MODULE, +}; + +static int hi6220_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct phy *phy; + struct hi6220_priv *priv; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->reg = syscon_regmap_lookup_by_phandle(dev->of_node, + "hisilicon,peripheral-syscon"); + if (IS_ERR(priv->reg)) { + dev_err(dev, "no hisilicon,peripheral-syscon\n"); + return PTR_ERR(priv->reg); + } + + hi6220_phy_init(priv); + + phy = devm_phy_create(dev, NULL, &hi6220_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id hi6220_phy_of_match[] = { + {.compatible = "hisilicon,hi6220-usb-phy",}, + { }, +}; +MODULE_DEVICE_TABLE(of, hi6220_phy_of_match); + +static struct platform_driver hi6220_phy_driver = { + .probe = hi6220_phy_probe, + .driver = { + .name = "hi6220-usb-phy", + .of_match_table = hi6220_phy_of_match, + } +}; +module_platform_driver(hi6220_phy_driver); + +MODULE_DESCRIPTION("HISILICON HI6220 USB PHY driver"); +MODULE_ALIAS("platform:hi6220-usb-phy"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From b1f2d8b33dcc7a216d3b86478ec2fe64980870c5 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Thu, 17 Dec 2015 16:43:31 -0800 Subject: usb: HACK: Disable usb autosuspend, as the dwc2 usb driver can't handle it Currently the usb autosuspend is causing problems with the dwc2 usb driver. This can be easily seen by removing all devices from the host port, then remove the OTG plug, and then replug the OTG cable. The gadget device will then fail to re-initialize with the error: dwc2 f72c0000.usb: s3c_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430) Since I could find no obovious solution to fix the suspend/resume logic on the device, this patch sets the default usbcore.autosuspend to -1 which avoids the problem. Once a proper fix has been found, we can remove this hack. Signed-off-by: John Stultz --- drivers/usb/core/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index f8bbd0b6d9fe..a717ddc3eae3 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -66,7 +66,7 @@ int usb_disabled(void) EXPORT_SYMBOL_GPL(usb_disabled); #ifdef CONFIG_PM -static int usb_autosuspend_delay = 2; /* Default delay value, +static int usb_autosuspend_delay = -1; /* Default delay value, * in seconds */ module_param_named(autosuspend, usb_autosuspend_delay, int, 0644); MODULE_PARM_DESC(autosuspend, "default autosuspend delay"); -- cgit v1.2.3 From 09bd30894a5009d6ef82d43be9a956dc26dec7b9 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 29 Jan 2016 15:23:22 -0800 Subject: hikey: hack: handle usb bus speed switch HiKey usb host ports can unfortunately can only support one usb speed at a time. This patch adds usb speed auto-negotiation to Hikey, so by default, the ports will run at highspeed, but when low-speed devices are plugged in, the host ports will downgrade to low-speed. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: John Stultz --- drivers/usb/core/hub.c | 20 ++++++++++++++++++-- drivers/usb/dwc2/hcd.c | 45 ++++++++++++++++++++++++++++++++------------- include/linux/usb/hcd.h | 1 + 3 files changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index b627392ad52a..4a9a96056fa9 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -2086,6 +2086,12 @@ void usb_disconnect(struct usb_device **pdev) */ pm_runtime_barrier(&udev->dev); + if (udev->speed < USB_SPEED_HIGH ) { + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + if (hcd->driver->change_bus_speed) + hcd->driver->change_bus_speed(hcd, 0); + } + usb_lock_device(udev); hub_disconnect_children(udev); @@ -4852,9 +4858,19 @@ loop: if (hub->hdev->parent || !hcd->driver->port_handed_over || !(hcd->driver->port_handed_over)(hcd, port1)) { - if (status != -ENOTCONN && status != -ENODEV) + if (status != -ENOTCONN && status != -ENODEV) { dev_err(&port_dev->dev, - "unable to enumerate USB device\n"); + "unable to enumerate USB device" + " at %s while bus at %s \n", + usb_speed_string(udev->speed), + hdev->descriptor.bDeviceProtocol == USB_HUB_PR_FS ? + "FULL_SPEED" : "HIGH_SPEED"); + + if (udev->speed < USB_SPEED_HIGH && + hdev->descriptor.bDeviceProtocol > USB_HUB_PR_FS && + hcd->driver->change_bus_speed) + hcd->driver->change_bus_speed(hcd, 1); + } } done: diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 571c21727ff9..f4823c4856c5 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -54,6 +54,19 @@ #include "core.h" #include "hcd.h" +struct wrapper_priv_data { + struct dwc2_hsotg *hsotg; +}; + +/* Gets the dwc2_hsotg from a usb_hcd */ +static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) +{ + struct wrapper_priv_data *p; + + p = (struct wrapper_priv_data *) &hcd->hcd_priv; + return p->hsotg; +} + /** * dwc2_dump_channel_info() - Prints the state of a host channel * @@ -1350,6 +1363,24 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, } } +/* + * 0: high speed + * 1: full speed + */ +static void dwc2_change_bus_speed(struct usb_hcd* hcd, int speed) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + static int last_speed = 0; + + if (speed == last_speed) + return; + + hsotg->core_params->speed = speed; + queue_work(hsotg->wq_otg, &hsotg->wf_otg); + + last_speed = speed; +} + static void dwc2_conn_id_status_change(struct work_struct *work) { struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, @@ -2121,19 +2152,6 @@ void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) #endif } -struct wrapper_priv_data { - struct dwc2_hsotg *hsotg; -}; - -/* Gets the dwc2_hsotg from a usb_hcd */ -static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) -{ - struct wrapper_priv_data *p; - - p = (struct wrapper_priv_data *) &hcd->hcd_priv; - return p->hsotg; -} - static int _dwc2_hcd_start(struct usb_hcd *hcd); void dwc2_host_start(struct dwc2_hsotg *hsotg) @@ -2905,6 +2923,7 @@ static struct hc_driver dwc2_hc_driver = { .bus_suspend = _dwc2_hcd_suspend, .bus_resume = _dwc2_hcd_resume, + .change_bus_speed = dwc2_change_bus_speed, }; /* diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 3993b21f3d11..3ada32f24310 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -396,6 +396,7 @@ struct hc_driver { int (*find_raw_port_number)(struct usb_hcd *, int); /* Call for power on/off the port if necessary */ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable); + void (*change_bus_speed)(struct usb_hcd*, int); }; -- cgit v1.2.3 From 2803e9e641e3d33b0450c77b9cf0a4bb7b1b1e24 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Mon, 14 Sep 2015 17:55:04 +0800 Subject: drm/cma-helper: Add multi buffer support for cma fbdev This patch add a config to support to create multi buffer for cma fbdev. Such as double buffer and triple buffer. Cma fbdev is convient to add a legency fbdev. And still many Android devices use fbdev now and at least double buffer is needed for these Android devices, so that a buffer flip can be operated. It will need some time for Android device vendors to abondon legency fbdev. So multi buffer for fbdev is needed. Signed-off-by: Xinliang Liu --- drivers/gpu/drm/Kconfig | 8 ++++++++ drivers/gpu/drm/drm_fb_cma_helper.c | 8 +++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4bf9a1cf4a6..8773fadfc792 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -97,6 +97,14 @@ config DRM_KMS_CMA_HELPER help Choose this if you need the KMS CMA helper functions +config DRM_CMA_FBDEV_BUFFER_NUM + int "Cma Fbdev Buffer Number" + depends on DRM_KMS_CMA_HELPER + default 1 + help + Defines the buffer number of cma fbdev. Default is one buffer. + For double buffer please set to 2 and 3 for triple buffer. + source "drivers/gpu/drm/i2c/Kconfig" config DRM_TDFX diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index c19a62561183..26051b849e93 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -25,6 +25,12 @@ #include #include +#ifdef CONFIG_DRM_CMA_FBDEV_BUFFER_NUM +#define FBDEV_BUFFER_NUM CONFIG_DRM_CMA_FBDEV_BUFFER_NUM +#else +#define FBDEV_BUFFER_NUM 1 +#endif + struct drm_fb_cma { struct drm_framebuffer fb; struct drm_gem_cma_object *obj[4]; @@ -253,7 +259,7 @@ static int drm_fbdev_cma_create(struct drm_fb_helper *helper, bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8); mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; + mode_cmd.height = sizes->surface_height * FBDEV_BUFFER_NUM; mode_cmd.pitches[0] = sizes->surface_width * bytes_per_pixel; mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); -- cgit v1.2.3 From d673dcf271d2bee722451014c7c6b7de8f1dc3b2 Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Fri, 9 Oct 2015 17:00:29 +0800 Subject: drm/hisilicon: Add device tree binding for hi6220 display subsystem Add ADE display controller binding doc. Add DesignWare DSI Host Controller v1.20a binding doc. v8: None. v7: Acked by Rob Herring. v6: - Cleanup values part of reg and clocks properties. - Change "pclk_dsi" clock name to "pclk". v5: - Remove endpoint unit address of dsi output port. - Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon. - Add "resets" property for ADE reset. v4: - Describe more specific of clocks and ports. - Fix indentation. v3: - Make ade as the drm master node. - Use assigned-clocks to set clock rate. - Use ports to connect display relavant nodes. v2: - Move dt binding docs to bindings/display/hisilicon directory. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong Acked-by: Rob Herring --- .../bindings/display/hisilicon/dw-dsi.txt | 72 ++++++++++++++++++++++ .../bindings/display/hisilicon/hisi-ade.txt | 64 +++++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt new file mode 100644 index 000000000000..d270bfe4e4e0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt @@ -0,0 +1,72 @@ +Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver + +A DSI Host Controller resides in the middle of display controller and external +HDMI converter or panel. + +Required properties: +- compatible: value should be "hisilicon,hi6220-dsi". +- reg: physical base address and length of dsi controller's registers. +- clocks: contains APB clock phandle + clock-specifier pair. +- clock-names: should be "pclk". +- ports: contains DSI controller input and output sub port. + The input port connects to ADE output port with the reg value "0". + The output port with the reg value "1", it could connect to panel or + any other bridge endpoints. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +A example of HiKey board hi6220 SoC and board specific DT entry: +Example: + +SoC specific: + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; + + +Board specific: + &dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; + }; + + &i2c2 { + ... + + adv7533: adv7533@39 { + ... + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt new file mode 100644 index 000000000000..38dc9d60eef8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt @@ -0,0 +1,64 @@ +Device-Tree bindings for hisilicon ADE display controller driver + +ADE (Advanced Display Engine) is the display controller which grab image +data from memory, do composition, do post image processing, generate RGB +timing stream and transfer to DSI. + +Required properties: +- compatible: value should be "hisilicon,hi6220-ade". +- reg: physical base address and length of the ADE controller's registers. +- hisilicon,noc-syscon: ADE NOC QoS syscon. +- resets: The ADE reset controller node. +- interrupt: the ldi vblank interrupt number used. +- clocks: a list of phandle + clock-specifier pairs, one for each entry + in clock-names. +- clock-names: should contain: + "clk_ade_core" for the ADE core clock. + "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with + jpeg codec. + "clk_ade_pix" for the ADE pixel clok. +- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' + phandle + clock-specifier pairs. +- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. + The rate of "clk_ade_core" could be "360000000" or "180000000"; + The rate of "clk_codec_jpeg" could be or less than "1440000000". + These rate values could be configured according to performance and power + consumption. +- port: the output port. This contains one endpoint subnode, with its + remote-endpoint set to the phandle of the connected DSI input endpoint. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +Optional properties: +- dma-coherent: Present if dma operations are coherent. + + +A example of HiKey board hi6220 SoC specific DT entry: +Example: + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; -- cgit v1.2.3 From 4fc4eb07b5ad0a046d23a9b256ea27445e96663b Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Fri, 9 Oct 2015 18:00:56 +0800 Subject: drm/hisilicon: Add hisilicon kirin drm master driver Add kirin DRM master driver for hi6220 SoC which used in HiKey board. Add dumb buffer feature. Add prime dmabuf feature. v9: Add OF and ARM64 depends on in Kconfig v8: None. v7: - Add config.mutex protection when accessing mode_config.connector_list. - Clean up match data getting. v6: None. v5: None. v4: None. v3: - Move and rename all the files to kirin sub-directory. So that we could separate different seires SoCs' driver. - Replace drm_platform_init, load, unload implementation. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/hisilicon/Kconfig | 5 + drivers/gpu/drm/hisilicon/Makefile | 5 + drivers/gpu/drm/hisilicon/kirin/Kconfig | 9 + drivers/gpu/drm/hisilicon/kirin/Makefile | 3 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 309 ++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 20 ++ 8 files changed, 354 insertions(+) create mode 100644 drivers/gpu/drm/hisilicon/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/Kconfig create mode 100644 drivers/gpu/drm/hisilicon/kirin/Makefile create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 8773fadfc792..038aae8c7c66 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -274,3 +274,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" + +source "drivers/gpu/drm/hisilicon/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 1e9ff4c3e3db..95ba48234f3e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -75,3 +75,4 @@ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/ +obj-y += hisilicon/ diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig new file mode 100644 index 000000000000..558c61b1b8e8 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/Kconfig @@ -0,0 +1,5 @@ +# +# hisilicon drm device configuration. +# Please keep this list sorted alphabetically + +source "drivers/gpu/drm/hisilicon/kirin/Kconfig" diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile new file mode 100644 index 000000000000..e3f6d493c996 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for hisilicon drm drivers. +# Please keep this list sorted alphabetically + +obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/ diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig new file mode 100644 index 000000000000..a45bf54eb080 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -0,0 +1,9 @@ +config DRM_HISI_KIRIN + tristate "DRM Support for Hisilicon Kirin series SoCs Platform" + depends on DRM && OF && ARM64 + select DRM_KMS_HELPER + select DRM_GEM_CMA_HELPER + select DRM_KMS_CMA_HELPER + help + Choose this option if you have a hisilicon Kirin chipsets(hi6220). + If M is selected the module will be called kirin-drm. diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile new file mode 100644 index 000000000000..cb346de47d48 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -0,0 +1,3 @@ +kirin-drm-y := kirin_drm_drv.o + +obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c new file mode 100644 index 000000000000..976c9b1a3fd3 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -0,0 +1,309 @@ +/* + * Hisilicon Kirin SoCs drm master driver + * + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * Author: + * Xinliang Liu + * Xinliang Liu + * Xinwei Kong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "kirin_drm_drv.h" + +static struct kirin_dc_ops *dc_ops; + +static int kirin_drm_kms_cleanup(struct drm_device *dev) +{ + dc_ops->cleanup(dev); + drm_mode_config_cleanup(dev); + + return 0; +} + +static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = { + .fb_create = drm_fb_cma_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static void kirin_drm_mode_config_init(struct drm_device *dev) +{ + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + + dev->mode_config.max_width = 2048; + dev->mode_config.max_height = 2048; + + dev->mode_config.funcs = &kirin_drm_mode_config_funcs; +} + +static int kirin_drm_kms_init(struct drm_device *dev) +{ + int ret; + + dev_set_drvdata(dev->dev, dev); + + /* dev->mode_config initialization */ + drm_mode_config_init(dev); + kirin_drm_mode_config_init(dev); + + /* display controller init */ + ret = dc_ops->init(dev); + if (ret) + goto err_mode_config_cleanup; + + /* bind and init sub drivers */ + ret = component_bind_all(dev->dev, dev); + if (ret) { + DRM_ERROR("failed to bind all component.\n"); + goto err_dc_cleanup; + } + + /* reset all the states of crtc/plane/encoder/connector */ + drm_mode_config_reset(dev); + + return 0; + +err_dc_cleanup: + dc_ops->cleanup(dev); +err_mode_config_cleanup: + drm_mode_config_cleanup(dev); + + return ret; +} + +static const struct file_operations kirin_drm_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = drm_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .poll = drm_poll, + .read = drm_read, + .llseek = no_llseek, + .mmap = drm_gem_cma_mmap, +}; + +static int kirin_gem_cma_dumb_create(struct drm_file *file, + struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + return drm_gem_cma_dumb_create_internal(file, dev, args); +} + +static struct drm_driver kirin_drm_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | + DRIVER_ATOMIC, + .fops = &kirin_drm_fops, + .set_busid = drm_platform_set_busid, + + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .dumb_create = kirin_gem_cma_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, + + .name = "kirin", + .desc = "Hisilicon Kirin SoCs' DRM Driver", + .date = "20150718", + .major = 1, + .minor = 0, +}; + +static int compare_of(struct device *dev, void *data) +{ + return dev->of_node == data; +} + +static int kirin_drm_connectors_register(struct drm_device *dev) +{ + struct drm_connector *connector; + struct drm_connector *failed_connector; + int ret; + + mutex_lock(&dev->mode_config.mutex); + drm_for_each_connector(connector, dev) { + ret = drm_connector_register(connector); + if (ret) { + failed_connector = connector; + goto err; + } + } + mutex_unlock(&dev->mode_config.mutex); + + return 0; + +err: + drm_for_each_connector(connector, dev) { + if (failed_connector == connector) + break; + drm_connector_unregister(connector); + } + mutex_unlock(&dev->mode_config.mutex); + + return ret; +} + +static int kirin_drm_bind(struct device *dev) +{ + struct drm_driver *driver = &kirin_drm_driver; + struct drm_device *drm_dev; + int ret; + + drm_dev = drm_dev_alloc(driver, dev); + if (!drm_dev) + return -ENOMEM; + + drm_dev->platformdev = to_platform_device(dev); + + ret = kirin_drm_kms_init(drm_dev); + if (ret) + goto err_drm_dev_unref; + + ret = drm_dev_register(drm_dev, 0); + if (ret) + goto err_kms_cleanup; + + /* connectors should be registered after drm device register */ + ret = kirin_drm_connectors_register(drm_dev); + if (ret) + goto err_drm_dev_unregister; + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + driver->name, driver->major, driver->minor, driver->patchlevel, + driver->date, drm_dev->primary->index); + + return 0; + +err_drm_dev_unregister: + drm_dev_unregister(drm_dev); +err_kms_cleanup: + kirin_drm_kms_cleanup(drm_dev); +err_drm_dev_unref: + drm_dev_unref(drm_dev); + + return ret; +} + +static void kirin_drm_unbind(struct device *dev) +{ + drm_put_dev(dev_get_drvdata(dev)); +} + +static const struct component_master_ops kirin_drm_ops = { + .bind = kirin_drm_bind, + .unbind = kirin_drm_unbind, +}; + +static struct device_node *kirin_get_remote_node(struct device_node *np) +{ + struct device_node *endpoint, *remote; + + /* get the first endpoint, in our case only one remote node + * is connected to display controller. + */ + endpoint = of_graph_get_next_endpoint(np, NULL); + if (!endpoint) { + DRM_ERROR("no valid endpoint node\n"); + return ERR_PTR(-ENODEV); + } + of_node_put(endpoint); + + remote = of_graph_get_remote_port_parent(endpoint); + if (!remote) { + DRM_ERROR("no valid remote node\n"); + return ERR_PTR(-ENODEV); + } + of_node_put(remote); + + if (!of_device_is_available(remote)) { + DRM_ERROR("not available for remote node\n"); + return ERR_PTR(-ENODEV); + } + + return remote; +} + +static int kirin_drm_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct component_match *match = NULL; + struct device_node *remote; + + dc_ops = (struct kirin_dc_ops *)of_device_get_match_data(dev); + if (!dc_ops) { + DRM_ERROR("failed to get dt id data\n"); + return -EINVAL; + } + + remote = kirin_get_remote_node(np); + if (IS_ERR(remote)) + return PTR_ERR(remote); + + component_match_add(dev, &match, compare_of, remote); + + return component_master_add_with_match(dev, &kirin_drm_ops, match); + + return 0; +} + +static int kirin_drm_platform_remove(struct platform_device *pdev) +{ + component_master_del(&pdev->dev, &kirin_drm_ops); + dc_ops = NULL; + return 0; +} + +static const struct of_device_id kirin_drm_dt_ids[] = { + { .compatible = "hisilicon,hi6220-ade", + .data = &ade_dc_ops, + }, + { /* end node */ }, +}; +MODULE_DEVICE_TABLE(of, kirin_drm_dt_ids); + +static struct platform_driver kirin_drm_platform_driver = { + .probe = kirin_drm_platform_probe, + .remove = kirin_drm_platform_remove, + .driver = { + .name = "kirin-drm", + .of_match_table = kirin_drm_dt_ids, + }, +}; + +module_platform_driver(kirin_drm_platform_driver); + +MODULE_AUTHOR("Xinliang Liu "); +MODULE_AUTHOR("Xinliang Liu "); +MODULE_AUTHOR("Xinwei Kong "); +MODULE_DESCRIPTION("hisilicon Kirin SoCs' DRM master driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h new file mode 100644 index 000000000000..75e9d82356d4 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __KIRIN_DRM_DRV_H__ +#define __KIRIN_DRM_DRV_H__ + +/* display controller init/cleanup ops */ +struct kirin_dc_ops { + int (*init)(struct drm_device *dev); + void (*cleanup)(struct drm_device *dev); +}; + +#endif /* __KIRIN_DRM_DRV_H__ */ -- cgit v1.2.3 From a74b9ad6c5a988893a8e2e5116950bbf088d5b5c Mon Sep 17 00:00:00 2001 From: Xinliang Liu Date: Sat, 10 Oct 2015 10:16:22 +0800 Subject: drm/hisilicon: Add crtc driver for ADE Add crtc funcs and helper funcs for ADE. v8: None. v7: - A few Regs define clean up and typo fixs. v6: - Cleanup reg-names dt parsing. v5: - Use syscon to access ADE media NOC QoS registers instread of directly writing registers. - Use reset controller to reset ADE instead of directly writing registers. v4: None. v3: - Make ade as the master driver. - Use port to connect with encoder. - A few cleanup. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong Reviewed-by: Archit Taneja --- drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +- drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 230 ++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 462 ++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 12 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + 5 files changed, 714 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index cb346de47d48..2a61ab006ddb 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,3 +1,4 @@ -kirin-drm-y := kirin_drm_drv.o +kirin-drm-y := kirin_drm_drv.o \ + kirin_drm_ade.o obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h new file mode 100644 index 000000000000..4cf281b7ed63 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __KIRIN_ADE_REG_H__ +#define __KIRIN_ADE_REG_H__ + +/* + * ADE Registers + */ +#define MASK(x) (BIT(x) - 1) + +#define ADE_CTRL 0x0004 +#define FRM_END_START_OFST 0 +#define FRM_END_START_MASK MASK(2) +#define AUTO_CLK_GATE_EN_OFST 0 +#define AUTO_CLK_GATE_EN BIT(0) +#define ADE_DISP_SRC_CFG 0x0018 +#define ADE_CTRL1 0x008C +#define ADE_EN 0x0100 +#define ADE_DISABLE 0 +#define ADE_ENABLE 1 +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4) +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) +#define RDMA_OFST 0 +#define CLIP_OFST 15 +#define SCL_OFST 21 +#define CTRAN_OFST 24 +#define OVLY_OFST 37 /* 32+5 */ +/* channel regs */ +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_EN(x) (0x1020 + (x) * 0x80) +/* overlay regs */ +#define ADE_OVLY1_TRANS_CFG 0x002C +#define ADE_OVLY_CTL 0x0098 +#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4) +#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4) +#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4) +#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8) +#define OUTPUT_XSIZE_OFST 16 +#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4) +#define CH_OVLY_SEL_OFST(x) ((x) * 4) +#define CH_OVLY_SEL_MASK MASK(2) +#define CH_OVLY_SEL_VAL(x) ((x) + 1) +#define CH_ALP_MODE_OFST 0 +#define CH_ALP_SEL_OFST 2 +#define CH_UNDER_ALP_SEL_OFST 4 +#define CH_EN_OFST 6 +#define CH_ALP_GBL_OFST 15 +#define CH_SEL_OFST 28 +/* ctran regs */ +#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100) +#define CTRAN_BYPASS_ON 1 +#define CTRAN_BYPASS_OFF 0 +#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100) +/* clip regs */ +#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) + +/* + * LDI Registers + */ +#define LDI_HRZ_CTRL0 0x7400 +#define HBP_OFST 20 +#define LDI_HRZ_CTRL1 0x7404 +#define LDI_VRT_CTRL0 0x7408 +#define VBP_OFST 20 +#define LDI_VRT_CTRL1 0x740C +#define LDI_PLR_CTRL 0x7410 +#define FLAG_NVSYNC BIT(0) +#define FLAG_NHSYNC BIT(1) +#define FLAG_NPIXCLK BIT(2) +#define FLAG_NDE BIT(3) +#define LDI_DSP_SIZE 0x7414 +#define VSIZE_OFST 20 +#define LDI_INT_EN 0x741C +#define FRAME_END_INT_EN_OFST 1 +#define LDI_CTRL 0x7420 +#define BPP_OFST 3 +#define DATA_GATE_EN BIT(2) +#define LDI_EN BIT(0) +#define LDI_MSK_INT 0x7428 +#define LDI_INT_CLR 0x742C +#define LDI_WORK_MODE 0x7430 +#define LDI_HDMI_DSI_GT 0x7434 + +/* + * ADE media bus service regs + */ +#define ADE0_QOSGENERATOR_MODE 0x010C +#define QOSGENERATOR_MODE_MASK MASK(2) +#define ADE0_QOSGENERATOR_EXTCONTROL 0x0118 +#define SOCKET_QOS_EN BIT(0) +#define ADE1_QOSGENERATOR_MODE 0x020C +#define ADE1_QOSGENERATOR_EXTCONTROL 0x0218 + +/* + * ADE regs relevant enums + */ +enum frame_end_start { + /* regs take effect in every vsync */ + REG_EFFECTIVE_IN_VSYNC = 0, + /* regs take effect in fist ade en and every frame end */ + REG_EFFECTIVE_IN_ADEEN_FRMEND, + /* regs take effect in ade en immediately */ + REG_EFFECTIVE_IN_ADEEN, + /* regs take effect in first vsync and every frame end */ + REG_EFFECTIVE_IN_VSYNC_FRMEND +}; + +enum ade_fb_format { + ADE_RGB_565 = 0, + ADE_BGR_565, + ADE_XRGB_8888, + ADE_XBGR_8888, + ADE_ARGB_8888, + ADE_ABGR_8888, + ADE_RGBA_8888, + ADE_BGRA_8888, + ADE_RGB_888, + ADE_BGR_888 = 9, + ADE_FORMAT_UNSUPPORT = 800 +}; + +enum ade_channel { + ADE_CH1 = 0, /* channel 1 for primary plane */ + ADE_CH_NUM +}; + +enum ade_scale { + ADE_SCL1 = 0, + ADE_SCL2, + ADE_SCL3, + ADE_SCL_NUM +}; + +enum ade_ctran { + ADE_CTRAN1 = 0, + ADE_CTRAN2, + ADE_CTRAN3, + ADE_CTRAN4, + ADE_CTRAN5, + ADE_CTRAN6, + ADE_CTRAN_NUM +}; + +enum ade_overlay { + ADE_OVLY1 = 0, + ADE_OVLY2, + ADE_OVLY3, + ADE_OVLY_NUM +}; + +enum ade_alpha_mode { + ADE_ALP_GLOBAL = 0, + ADE_ALP_PIXEL, + ADE_ALP_PIXEL_AND_GLB +}; + +enum ade_alpha_blending_mode { + ADE_ALP_MUL_COEFF_0 = 0, /* alpha */ + ADE_ALP_MUL_COEFF_1, /* 1-alpha */ + ADE_ALP_MUL_COEFF_2, /* 0 */ + ADE_ALP_MUL_COEFF_3 /* 1 */ +}; + +/* + * LDI regs relevant enums + */ +enum dsi_pclk_en { + DSI_PCLK_ON = 0, + DSI_PCLK_OFF +}; + +enum ldi_output_format { + LDI_OUT_RGB_565 = 0, + LDI_OUT_RGB_666, + LDI_OUT_RGB_888 +}; + +enum ldi_work_mode { + TEST_MODE = 0, + NORMAL_MODE +}; + +enum ldi_input_source { + DISP_SRC_NONE = 0, + DISP_SRC_OVLY2, + DISP_SRC_DISP, + DISP_SRC_ROT, + DISP_SRC_SCL2 +}; + +/* + * ADE media bus service relevant enums + */ +enum qos_generator_mode { + FIXED_MODE = 0, + LIMITER_MODE, + BYPASS_MODE, + REGULATOR_MODE +}; + +/* + * Register Write/Read Helper functions + */ +static inline void ade_update_bits(void __iomem *addr, u32 bit_start, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig = readl(addr); + tmp = orig & ~(mask << bit_start); + tmp |= (val & mask) << bit_start; + writel(tmp, addr); +} + +#endif diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c new file mode 100644 index 000000000000..cfbea957297b --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -0,0 +1,462 @@ +/* + * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver + * + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * Author: + * Xinliang Liu + * Xinliang Liu + * Xinwei Kong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include